Semiconductor device and chip including nanosheet field effect transistor unit architecture

Abstract

A semiconductor device and a semiconductor chip are provided. The semiconductor device includes a first and second wraparound gate field effect transistors separated by a channel spacing, and a gate contact. Each of the wraparound gate field effect transistors includes: a horizontal nanosheet conductive channel structure; a gate material completely surrounding the horizontal nanosheet conductive channel structure; a source region and a drain region located at opposite ends of the horizontal nanosheet conductive channel structure; and a source contact and a drain contact located on the source region and the drain region. The width of the horizontal nanosheet conductive channel structure of the first wraparound gate field effect transistor or the second wraparound gate field effect transistor is less than a maximum allowable width. The gate contact is spaced apart from each of the source region and the drain region of the first wraparound gate field effect transistor and the second wraparound gate field effect transistor by a distance ranging from a minimum design rule spacing to a maximum distance.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This application claims priority to and the benefits of U.S. Provisional Application No. 62 / 758,243, filed on November 9, 2018, and U.S. Non-Provisional Application No. 16 / 390,859, filed on April 22, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to gate-all-around field-effect transistors and methods of fabricating the same. Background Art

[0004] Semiconductor circuits are often formed using non-planar "fin" field effect transistors (finFETs). Conventional finFETs typically include multiple vertical fins that serve as conductive channel regions. The power required to operate a semiconductor circuit can be reduced by varying the number of fins in a finFET. However, as semiconductor circuits shrink to smaller sizes, several limitations may hinder the proper formation of finFETs, including the lateral spacing between adjacent fins and the height of the fins required to achieve the desired effective width of the fins. Summary of the Invention

[0005] The present disclosure relates to various embodiments of semiconductor devices. In one embodiment, the semiconductor device includes a first gate-all-around (GAA) field effect transistor (FET) and a second gate-all-around field effect transistor separated from the first gate-all-around field effect transistor by a channel spacing. Each of the first gate-all-around field effect transistor and the second gate-all-around field effect transistor includes: at least one horizontal nanosheet conductive channel structure; a gate material completely surrounding each of the at least one horizontal nanosheet conductive channel structure; a source region located at a first end of the at least one horizontal nanosheet conductive channel structure; a source contact located on the source region; a drain region located at a second end of the at least one horizontal nanosheet conductive channel structure opposite the first end; and a drain contact located on the drain region. The semiconductor device also includes: at least one gate contact located on the gate material in the channel spacing between the first gate-all-around field effect transistor and the second gate-all-around field effect transistor. The width of the horizontal nanosheet conductive channel structure of the first gate-all-around field effect transistor or the second gate-all-around field effect transistor is less than a maximum allowable width. The gate contact is spaced apart from each of the source region and the drain region of the first and second wrap-around gate field effect transistors by a distance ranging from a minimum design rule spacing to a maximum distance.

[0006] The gate contact may be spaced apart from one of the source region or the drain region of the first wrap-around gate field effect transistor or the second wrap-around gate field effect transistor by a distance greater than the minimum design rule spacing.

[0007] The distance may be the maximum distance from the source region or the drain region of the first wrap-around gate field effect transistor or the second wrap-around gate field effect transistor.

[0008] The gate contact can be spaced apart from the source region and the drain region of each of the first and second wrap-around gate field effect transistors by the maximum distance.

[0009] The first wrap-around gate field effect transistor may be a p-type field effect transistor and the second wrap-around gate field effect transistor may be an n-type field effect transistor. The width of the at least one horizontal nanosheet conductive channel structure of the first wrap-around gate field effect transistor may be greater than the width of the at least one horizontal nanosheet conductive channel structure of the second wrap-around gate field effect transistor.

[0010] The first wrap-around gate field effect transistor may be a p-type field effect transistor and the second wrap-around gate field effect transistor may be an n-type field effect transistor. The width of the at least one horizontal nanosheet conductive channel structure of the first wrap-around gate field effect transistor may be smaller than the width of the at least one horizontal nanosheet conductive channel structure of the second wrap-around gate field effect transistor.

[0011] The at least one horizontal nanosheet conductive channel structure may include a plurality of horizontal nanosheet conductive channel structures.

[0012] The at least one horizontal nanosheet conductive channel structure may have a width ranging from approximately 5 nm to approximately 50 nm.

[0013] According to another embodiment of the present disclosure, a semiconductor device includes: a first wraparound gate field effect transistor; a second wraparound gate field effect transistor separated from the first wraparound gate field effect transistor by a channel spacing; and a first gate contact and a second gate contact located on a gate material in the channel spacing between the first wraparound gate field effect transistor and the second wraparound gate field effect transistor. The first gate contact and the second gate contact are staggered. Each of the first wraparound gate field effect transistor and the second wraparound gate field effect transistor includes: at least one horizontal nanosheet conductive channel structure; the gate material completely surrounding each of the at least one horizontal nanosheet conductive channel structure; a source region located at a first end of the at least one horizontal nanosheet conductive channel structure; a source contact located on the source region; a drain region located at a second end of the at least one horizontal nanosheet conductive channel structure opposite the first end; and a drain contact located on the drain region.

[0014] The width of the at least one horizontal nanosheet conductive channel structure of the first wrap-around gate field effect transistor may be different from the width of the at least one horizontal nanosheet conductive channel structure of the second wrap-around gate field effect transistor.

[0015] A width of the at least one horizontal nanosheet conductive channel structure of the first wrap-around gate field effect transistor may be substantially the same as a width of the at least one horizontal nanosheet conductive channel structure of the second wrap-around gate field effect transistor.

[0016] The width of the at least one horizontal nanosheet conductive channel structure of each of the first and second wrap-around gate field effect transistors may range from approximately 5 nm to approximately 50 nm.

[0017] The present disclosure also relates to various embodiments of semiconductor chips. In one embodiment, the semiconductor chip includes: a first semiconductor device and a second semiconductor device, each including a first wraparound gate field effect transistor, a second wraparound gate field effect transistor separated from the first wraparound gate field effect transistor by a channel spacing, and at least one gate contact located in the channel spacing. Each of the first wraparound gate field effect transistor and the second wraparound gate field effect transistor includes: at least one horizontal nanosheet conductive channel structure; a gate material completely surrounding each of the at least one horizontal nanosheet conductive channel structure; a source region located at a first end of the at least one horizontal nanosheet conductive channel structure; a source contact located on the source region; a drain region located at a second end of the at least one horizontal nanosheet conductive channel structure opposite the first end; and a drain contact located on the drain region. The construction of the first semiconductor device is different from the construction of the second semiconductor device.

[0018] The first wrap-around gate field effect transistor of each of the first semiconductor device and the second semiconductor device may be one type of field effect transistor (e.g., a p-type field effect transistor or an n-type field effect transistor), and the second wrap-around gate field effect transistor of each of the first semiconductor device and the second semiconductor device may be another type of field effect transistor (e.g., an n-type field effect transistor or a p-type field effect transistor).

[0019] An effective channel width of the first wrap-around gate field effect transistor of the first semiconductor device may be different from an effective channel width of the first wrap-around gate field effect transistor of the second semiconductor device.

[0020] The width of the at least one horizontal nanosheet conductive channel structure of the first wrap-around gate field effect transistor of the first semiconductor device may be different from the width of the at least one horizontal nanosheet conductive channel structure of the first wrap-around gate field effect transistor of the second semiconductor device.

[0021] The at least one horizontal nanosheet conductive channel structure of the first wrap-around gate field effect transistor of the first semiconductor device may include a first series of horizontal nanosheet conductive channel structures, and the at least one horizontal nanosheet conductive channel structure of the first wrap-around gate field effect transistor of the second semiconductor device may include a second series of horizontal nanosheet conductive channel structures different from the first series of horizontal nanosheet conductive channel structures.

[0022] The at least one gate contact of the first semiconductor device may include a first gate contact and a second gate contact, wherein the first gate contact and the second gate contact are staggered.

[0023] The at least one gate contact of the second semiconductor device may include a single gate contact, and the single gate contact may be spaced apart a maximum distance from each of the source region and the drain region of the first and second wrap-around gate field effect transistors of the second semiconductor device.

[0024] The at least one horizontal nanosheet conductive channel structure may include a series of horizontal nanosheet conductive channel structures ranging from two horizontal nanosheet conductive channel structures to four horizontal nanosheet conductive channel structures.

[0025] The at least one horizontal nanosheet conductive channel structure may have a width ranging from approximately 5 nm to approximately 50 nm.

[0026] This summary is provided to introduce a collection of concepts that are further elaborated below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. One or more of the described features can be combined with one or more other described features to provide a workable device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The features and advantages of the embodiments of the present disclosure will be better understood by referring to the following detailed description when considered in conjunction with the accompanying drawings. In the drawings, the same reference numerals are used throughout the figures to refer to the same features and components. The figures are not necessarily drawn to scale.

[0028] Figure 1A to Figure 1B 1 and 2 are perspective and side views, respectively, of a semiconductor device including a gate-all-around (GAA) field effect transistor (FET) according to one embodiment of the present disclosure.

[0029] Figures 2A to 2D is a top view of a semiconductor device according to various embodiments of the present disclosure.

[0030] Figure 3 is a flow chart illustrating operations of a method for forming a semiconductor device according to one embodiment of the present disclosure.

[0031] [Explanation of Symbols]

[0032] 100: Semiconductor devices

[0033] 101: First gate-all-around field-effect transistor / GAA FET

[0034] 102: Second all-around gate field effect transistor / GAA FET

[0035] 103: Base

[0036] 104, 114: Horizontal nanosheet conductive channel structure

[0037] 105: Gate material

[0038] 106, 115: upper surface

[0039] 107, 116: lower surface

[0040] 108, 118: vertical side

[0041] 109, 117: Vertical side / edge

[0042] 110, 119: Source region

[0043] 111, 120: drain region

[0044] 112, 121: Source contacts

[0045] 113: Drain contact

[0046] 123: First gate contact / gate contact

[0047] 124: Second gate contact / gate contact

[0048] 200: Method

[0049] 205, 210, 215, 220, 225, 230, 235, 240, 245, 250: Homework

[0050] H: horizontal direction

[0051] H1, H2: height

[0052] L: longitudinal centerline

[0053] nFET: n-type field effect transistor

[0054] pFET: p-type field effect transistor

[0055] V: vertical direction

[0056] W1, W2: width DETAILED DESCRIPTION

[0057] The present disclosure relates to various embodiments of a semiconductor device including a wrap-around gate (GAA) field effect transistor (FET). The semiconductor device according to one or more embodiments includes: a gate contact centrally located between the GAA FETs and spaced apart from the source and drain regions of the GAA FETs and the source and drain contacts by a maximum distance, which reduces the operating power required for the semiconductor device without increasing the cell height. The semiconductor device according to various embodiments of the present disclosure may include: a pair of staggered gate contacts located between the GAA FETs, which enables a dense cell layout. In addition, the semiconductor device according to various embodiments of the present disclosure includes: a GAA FET having nanosheet channels of different widths. The GAA FET with a lower width nanosheet channel can be set in a non-timing critical path of a semiconductor circuit to reduce power, and can be used to improve circuit performance by selectively tuning the feedback path. The present disclosure also relates to various embodiments of a semiconductor chip having a series of semiconductor devices in which the construction of the semiconductor devices varies depending on the region in which the semiconductor devices are disposed, such that the semiconductor chip can be configured to achieve optimal circuit power, performance, area, and cost (PPAC).

[0058] Hereinafter, exemplary embodiments will be described in more detail with reference to the accompanying drawings, and the same reference numerals refer to the same elements in all drawings. However, the present invention can be implemented in various forms and should not be considered as being limited to the embodiments illustrated herein. Specifically, these embodiments are provided as examples to make this disclosure thorough and complete, and to fully convey the aspects and features of the present invention to those skilled in the art. Therefore, processes, elements and technologies that are not necessary for those of ordinary skill in the art to fully understand the various aspects and features of the present invention may not be described again. Unless otherwise noted, the same reference numerals in all drawings and this written description represent the same elements, and therefore, they may not be repeated.

[0059] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated and / or simplified for clarity. For ease of explanation, spatially relative terms such as "beneath," "below," "lower," "under," "above," and "upper" may be used herein to describe the relationship of one element or feature shown in the drawings to another or other elements or features. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, an element described as being "below," "beneath," or "beneath" another element or feature would now be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "beneath" may encompass both above and below orientations. The device may be in other orientations (e.g., rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0060] It should be understood that although terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are merely used to distinguish between various elements, components, regions, layers, or sections. Thus, a first element, component, region, layer, or section described below could be termed a second element, component, region, layer, or section without departing from the spirit and scope of the present invention.

[0061] It should be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element or layer can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers may be present. It should also be understood that when an element or layer is referred to as being “between” two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0062] The terms used herein are only for the purpose of illustrating specific embodiments and are not intended to limit the present invention. Unless the context clearly indicates otherwise, the singular forms "a and an" used herein are intended to also include plural forms. It should also be understood that when the terms "comprises, comprising" and "includes, including" are used in this specification, it is to indicate the presence of stated features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. The terms "and / or" used herein include any and all combinations of one or more items in the relevant listed items. For example, expressions such as "at least one of..." modify the elements of the entire series when located after a series of elements rather than modifying the individual elements in the series of elements.

[0063] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation, not as terms of degree, and are intended to take into account the inherent variations in measurements or calculations that one of ordinary skill in the art would recognize. Furthermore, the use of "may" when describing embodiments of the present invention refers to "one or more embodiments of the present invention." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively. Additionally, the term "exemplary" is intended to refer to an example or illustration.

[0064] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. It should also be understood that terms (e.g., those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted as having an idealized or overly formal meaning unless explicitly defined herein.

[0065] Now refer to Figure 1A to Figure 1BAccording to one embodiment of the present disclosure, a semiconductor device 100 includes: a first gate-all-around (GAA) field effect transistor (FET) 101; and a second GAA FET 102 spaced apart from the first GAA FET 101 in the horizontal direction by a channel spacing. The first GAA FET and the second GAA FET are located on a substrate 103. In one or more embodiments, the substrate 103 may be a bulk Si substrate, a strain relaxed buffer (SRB), or a silicon on insulator (SOI) substrate. Although the semiconductor device 100 includes two GAA FETs 101 and 102 in the illustrated embodiment, the semiconductor device 100 may include any other suitable number of GAA FETs (for example, the semiconductor device 100 may include more than two GAA FETs) in one or more embodiments. In one or more embodiments, the first GAA FET 101 may be a p-type field effect transistor, and the second GAA FET 102 may be an n-type field effect transistor. In one or more embodiments, the first GAA FET 101 may be an n-type field effect transistor, and the second GAA FET 102 may be a p-type field effect transistor. In one or more embodiments, the semiconductor device 100 may be a complementary metal-oxide-semiconductor (CMOS) device.

[0066] In the illustrated embodiment, the first GAA FET 101 includes a stack of horizontal nanosheet conductive channel structures 104. Although in the illustrated embodiment, the first GAA FET 101 includes three horizontal nanosheet conductive channel structures 104, in one or more embodiments, the first GAA FET 101 may include any other suitable number of horizontal nanosheet conductive channel structures 104, such as, for example, ranging from two to four horizontal nanosheet conductive channel structures 104. The lowermost horizontal nanosheet conductive channel structure 104 is spaced apart a vertical distance from the substrate 103, and adjacent horizontal nanosheet conductive channel structures 104 are spaced apart a vertical distance from each other. In the illustrated embodiment, the first GAA FET 101 also includes a gate material 105 that completely surrounds each of the horizontal nanosheet conductive channel structures 104 (e.g., the gate material 105 extends along the upper surface 106, lower surface 107, and vertical sides 108, 109 of each of the horizontal nanosheet conductive channel structures 104). The first GAA FET 101 further includes a source region 110 located on one side of the stack of horizontal nanosheet conductive channel structures 104, and a drain region 111 located on an opposite side of the stack of horizontal nanosheet conductive channel structures 104. In the illustrated embodiment, the first GAA FET 101 further includes a source contact 112 located on the source region 110, and a drain contact 113 located on the drain region 111. Together, the horizontal nanosheet conductive channel structures 104 provide a channel region for the first GAA FET 101 that responds to an electric potential applied to the gate material 105 between the source region 110 and the drain region 111. In one or more embodiments, the horizontal nanosheet conductive channel structure 104 may be silicon (Si), silicon-germanium (SiGe), and / or a III-V semiconductor material, such as (for example) indium gallium arsenide (InGaAs), indium arsenide (InAs), or indium antimonide (InSb).

[0067] In one or more embodiments, the gate material 105 completely surrounding each of the horizontal nanosheet conductive channel structures 104 may include a stack of materials completely surrounding each of the horizontal nanosheet conductive channel structures 104. For example, in one or more embodiments, the gate material 105 may include a gate dielectric material and a work-function material. Additionally, in one or more embodiments, the gate material 105 may include a work-function tuning metal layer located between the gate metal layer and the dielectric layer to control the work function of the gate material 105.

[0068] In the illustrated embodiment, the width W1 of each of the horizontal nanosheet conductive channel structures 104 of the first GAA FET 101 is in a range from approximately 5 nm to approximately 50 nm. In one or more embodiments, the width W1 of the horizontal nanosheet conductive channel structure 104 in the horizontal direction (H) may be in a range from approximately 10 nm to approximately 30 nm. Although in the illustrated embodiment, each of the horizontal nanosheet conductive channel structures 104 of the first GAA FET 101 has the same width W1 or substantially the same width W1, in one or more embodiments, the horizontal nanosheet conductive channel structure 104 may have two or more different widths W1. In one or more embodiments, the width W1 of the horizontal nanosheet conductive channel structure 104 may vary depending on the vertical position of the horizontal nanosheet conductive channel structure 104. For example, in one or more embodiments, the width W1 of the lowermost horizontal nanosheet conductive channel structure 104 may be wider than the width W1 of the uppermost horizontal nanosheet conductive channel structure 104.

[0069] In one or more embodiments, the height H1 of each of the horizontal nanosheet conductive channel structures 104 of the first GAA FET 101 in the vertical direction (V) is in a range from about 2 nm to about 8 nm. In one or more embodiments, the height H1 of each of the horizontal nanosheet conductive channel structures 104 of the first GAA FET 101 may be in a range from about 3 nm to about 6 nm.

[0070] The effective channel width of the first GAA FET 101 is defined by the cumulative perimeter of the horizontal nanosheet conductive channel structures 104. In the illustrated embodiment, the perimeter of each of the horizontal nanosheet conductive channel structures 104 is defined by 2×W1+2×H1. Therefore, in the illustrated embodiment in which the first GAA FET 101 includes three horizontal nanosheet conductive channel structures 104, the effective channel width of the first GAA FET 101 is 3×(2×W1+2×H1).

[0071] In the illustrated embodiment, the second GAA FET 102 includes a stack of horizontal nanosheet conductive channel structures 114. Although in the illustrated embodiment, the second GAA FET 102 includes three horizontal nanosheet conductive channel structures 114, in one or more embodiments, the second GAA FET 102 may include any other suitable number of horizontal nanosheet conductive channel structures 114, such as, for example, ranging from two horizontal nanosheet conductive channel structures 114 to four horizontal nanosheet conductive channel structures 114. Additionally, although in the illustrated embodiment, the first GAA FET 101 and the second GAA FET 102 include the same number of horizontal nanosheet conductive channel structures 104 and 114, respectively, in one or more embodiments, the number of horizontal nanosheet conductive channel structures 114 in the second GAA FET 102 may be different from the number of horizontal nanosheet conductive channel structures 104 in the first GAA FET 101. The lowermost horizontal nanosheet conductive channel structure 114 is spaced apart from the substrate 103 by a vertical distance, and adjacent horizontal nanosheet conductive channel structures 114 are spaced apart from each other by a vertical distance. In the illustrated embodiment, the gate material 105 that completely surrounds each of the horizontal nanosheet conductive channel structures 104 of the first GAA FET 101 also completely surrounds each of the horizontal nanosheet conductive channel structures 114 of the second GAA FET 102 (e.g., the gate material 105 extends along the upper surface 115, lower surface 116, and vertical sides 117, 118 of each of the horizontal nanosheet conductive channel structures 114). The second GAA FET 102 also includes a source region 119 located on one side of the stack of horizontal nanosheet conductive channel structures 114 and a drain region 120 located on an opposite side of the stack of horizontal nanosheet conductive channel structures 114. In the illustrated embodiment, the second GAA FET 102 further includes a source contact 121 located on the source region 119 and a drain contact (not shown) located on the drain region 120. Meanwhile, the horizontal nanosheet conductive channel structure 114 provides a channel region for the second GAA FET 102 that responds to an electric potential applied to the gate material 105 between the source region 119 and the drain region 120. In one or more embodiments, the horizontal nanosheet conductive channel structure 114 may be silicon (Si), silicon-germanium (SiGe), and / or a III-V semiconductor material, such as, for example, indium gallium arsenide (InGaAs), indium arsenide (InAs), or indium antimonide (InSb).

[0072] In one or more embodiments, the height H2 of each of the horizontal nanosheet conductive channel structures 114 of the second GAA FET 102 in the vertical direction (V) is in a range from approximately 2 nm to approximately 8 nm. In one or more embodiments, the height H2 of each of the horizontal nanosheet conductive channel structures 114 of the second GAA FET 102 may be in a range from approximately 3 nm to approximately 6 nm. Additionally, in the illustrated embodiment, the height H2 of each of the horizontal nanosheet conductive channel structures 114 of the second GAA FET 102 is equal to or substantially equal to the height H1 of each of the horizontal nanosheet conductive channel structures 104 of the first GAA FET 101.

[0073] In the illustrated embodiment, each of the horizontal nanosheet conductive channel structures 114 of the second GAA FET 102 has a width W2 in the horizontal direction (H) ranging from approximately 5 nm to approximately 50 nm. In one or more embodiments, the width W2 of the horizontal nanosheet conductive channel structure 114 in the horizontal direction (H) may range from approximately 10 nm to approximately 30 nm. In addition, although in the illustrated embodiment, each of the horizontal nanosheet conductive channel structures 114 of the second GAA FET 102 has the same width W2 or substantially the same width W2, in one or more embodiments, the horizontal nanosheet conductive channel structure 114 may have two or more different widths W2. In one or more embodiments, the width W2 of the horizontal nanosheet conductive channel structure 114 may vary depending on the vertical position of the horizontal nanosheet conductive channel structure 114. For example, in one or more embodiments, the width W2 of the lowermost horizontal nanosheet conductive channel structure 114 may be wider than the width W2 of the uppermost horizontal nanosheet conductive channel structure 114. In addition, in one or more embodiments, the width W2 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102 may be the same or substantially the same as the width W1 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101. Figure 2B to Figure 2C In more detail, in one or more embodiments, the width W2 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102 may be different from the width W1 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101. For example, in one or more embodiments, the width W2 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102 may be wider than the width W1 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101, or the width W1 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101 may be wider than the width W2 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102.

[0074] The effective channel width of the second GAA FET 102 is defined by the cumulative perimeter of the horizontal nanosheet conductive channel structures 114. In the illustrated embodiment, the perimeter of each of the horizontal nanosheet conductive channel structures 114 is defined by 2×W2+2×H2. Therefore, in the illustrated embodiment in which the second GAA FET 102 includes three horizontal nanosheet conductive channel structures 114, the effective channel width of the second GAA FET 102 is 3×(2×W2+2×H2). In one or more embodiments, the effective channel width of the second GAA FET 102 can be the same or substantially the same as the effective channel width of the first GAA FET 101. In one or more embodiments, the effective channel width of the second GAA FET 102 can be different from the effective channel width of the first GAA FET 101 by, for example, having horizontal nanosheet conductive channel structures 104, 114 of different widths and / or a different number of horizontal nanosheet conductive channel structures 104, 114.

[0075] Reference Figure 1B , the vertical spacing within hns is defined as the distance between each of the horizontal nanosheet conductive channel structures 104 in the vertical direction V.

[0076] In the illustrated embodiment, the semiconductor device 100 further includes at least one gate contact 123 in contact with the gate material 105 (e.g., the semiconductor device 100 includes at least one gate contact 123 in contact with the gate material 105 that completely surrounds each of the horizontal nanosheet conductive channel structures 104 and 114 in the first GAA FET 101 and the second GAA FET 102). In the illustrated embodiment, the at least one gate contact 123 is located in the channel spacing between the first GAA FET 101 and the second GAA FET 102. The channel spacing between the first GAA FET 101 and the second GAA FET 102 is defined as the distance between the corresponding edges 109, 117 of the directly adjacent horizontal nanosheet conductive channel structures 104, 114 located in different GAA FETs 101, 102 but in a shared horizontal plane of the semiconductor device 100 (i.e., the channel spacing between the first GAA FET 101 and the second GAA FET 102 is defined as the distance between the edge 109 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101 that faces the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102 and the corresponding edge 117 of the horizontal nanosheet conductive channel structure 104 of the second GAA FET 102 that faces the first GAA FET 101).

[0077] In one or more embodiments, the gate contact 123 may be located at a maximum distance from each of the source regions 110, 119 and the drain regions 111, 120 (i.e., the gate contact 123 on the gate material 105 is spaced apart a maximum distance from each of the source region 110 of the first GAA FET 101, the drain region 111 of the first GAA FET 101, the source region 119 of the second GAA FET 102, and the drain region 120 of the second GAA FET 102). The gate contact 123 located at the maximum distance from each of the source regions 110, 119 and the drain regions 111, 120 is configured to reduce the power of the semiconductor device 100 without increasing the cell height.

[0078] Figures 2A to 2D Different configurations of the first GAA FET 101 and the second GAA FET 102 and the at least one gate contact 123 according to various embodiments of the present disclosure are shown. Figure 2A In the embodiment shown in FIG, the first GAA FET 101 is a p-type field effect transistor, and the second GAA FET 102 is an n-type field effect transistor. In addition, in the embodiment shown, the width W1 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101 is equal to or substantially equal to the width W2 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102. Figure 2AIn the embodiment shown in FIG, the gate contact 123 is laterally centered between the first GAA FET 101 and the second GAA FET 102 (e.g., the gate contact 123 is centered between the first GAA FET 101 and the second GAA FET 102 in a direction that defines the channel spacing between the first GAA FET 101 and the second GAA FET 102). That is, the gate contact 123 is centered between an edge 109 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101 that faces the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102 and a corresponding edge 117 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102 that faces the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101. Additionally, in the illustrated embodiment, the gate contact 123 is longitudinally centered between the source regions 110, 119 and the drain regions 111, 120 of the first GAA FET 101 and the second GAA FET 102 (e.g., the gate contact 123 is centered between the source region 110 and the drain region 111 of the first GAA FET 101 and between the source region 119 and the drain region 120 of the second GAA FET 102 along a direction defining a channel length of each of the first GAA FET 101 and the second GAA FET 102). Figure 2A In the embodiment shown in , the gate contact 123 is located at a maximum distance from each of the source regions 110 , 119 and the drain regions 111 , 120 of the first and second GAA FETs 101 , 102 .

[0079] exist Figure 2B In the embodiment shown in FIG, the first GAA FET 101 is a p-type field effect transistor, and the second GAA FET 102 is an n-type field effect transistor. In addition, in the embodiment shown, the width W1 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101 is greater than the width W2 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102. Figure 2BIn the embodiment shown in FIG, the gate contact 123 is laterally centered between the first GAA FET 101 and the second GAA FET 102 (e.g., the gate contact 123 is centered between the first GAA FET 101 and the second GAA FET 102 in a direction that defines the channel spacing between the first GAA FET 101 and the second GAA FET 102). That is, the gate contact 123 is centered between an edge 109 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101 that faces the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102 and a corresponding edge 117 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102 that faces the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101. Additionally, in the illustrated embodiment, the gate contact 123 is longitudinally centered between the source regions 110, 119 and the drain regions 111, 120 of the first GAA FET 101 and the second GAA FET 102 (e.g., the gate contact 123 is centered between the source region 110 and the drain region 111 of the first GAA FET 101 and between the source region 119 and the drain region 120 of the second GAA FET 102 along a direction defining a channel length of each of the first GAA FET 101 and the second GAA FET 102). Figure 2B In the embodiment shown in , the gate contact 123 is located at a maximum distance from each of the source regions 110 , 119 and the drain regions 111 , 120 of the first and second GAA FETs 101 , 102 .

[0080] In one or more embodiments, Figure 2BThe gate contact 123 shown in FIG may not be located at a maximum distance from each of the source regions 110, 119 and the drain regions 111, 120 of the first and second GAA FETs 101, 102. Rather, in one or more embodiments, the gate contact 123 may be located at a maximum distance from at least one of the source regions 110, 119 and the drain regions 111, 120 of the first and second GAA FETs 101, 102 (e.g., the gate contact 123 may be located at a maximum distance from one or more of the source regions 110, 119 and the drain regions 111, 120 of the first and second GAA FETs 101, 102, and may be located at least at a minimum design rule spacing from the remaining ones of the source regions 110, 119 and the drain regions 111, 120 of the first and second GAA FETs 101, 102). In one or more embodiments, the gate contact 123 may be located at a distance greater than the minimum design rule spacing from at least one of the source regions 110, 119 and the drain regions 111, 120 of the first GAA FET 101 and the second GAA FET 102 (for example, the gate contact 123 may be located at a distance greater than the minimum design rule spacing from one or more of the source regions 110, 119 and the drain regions 111, 120 of the first GAA FET 101 and the second GAA FET 102, and may be located at least at the minimum design rule spacing from the remaining regions of the source regions 110, 119 and the drain regions 111, 120 of the first GAA FET 101 and the second GAA FET 102).

[0081] exist Figure 2C In the embodiment shown in , the first GAA FET 101 is a p-type field effect transistor, and the second GAA FET 102 is an n-type field effect transistor. In addition, in the embodiment shown, the width W2 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102 is greater than the width W1 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101 (that is, the width W1 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101 is less than the width W2 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102). Figure 2CIn the embodiment shown in FIG, the gate contact 123 is laterally centered between the first GAA FET 101 and the second GAA FET 102 (e.g., the gate contact 123 is centered between the first GAA FET 101 and the second GAA FET 102 in a direction that defines the channel spacing between the first GAA FET 101 and the second GAA FET 102). That is, the gate contact 123 is centered between an edge 109 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101 that faces the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102 and a corresponding edge 117 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102 that faces the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101. Additionally, in the illustrated embodiment, the gate contact 123 is longitudinally centered between the source regions 110, 119 and the drain regions 111, 120 of the first GAA FET 101 and the second GAA FET 102 (e.g., the gate contact 123 is centered between the source region 110 and the drain region 111 of the first GAA FET 101 and between the source region 119 and the drain region 120 of the second GAA FET 102 along a direction defining a channel length of each of the first GAA FET 110 and the second GAA FET 102). Figure 2C In the embodiment shown in , the gate contact 123 is located at a maximum distance from each of the source regions 110 , 119 and the drain regions 111 , 120 of the first and second GAA FETs 101 , 102 .

[0082] In one or more embodiments, Figure 2CThe gate contact 123 shown in FIG may not be located at a maximum distance from each of the source regions 110, 119 and the drain regions 111, 120 of the first and second GAA FETs 101, 102. Rather, in one or more embodiments, the gate contact 123 may be located at a maximum distance from at least one of the source regions 110, 119 and the drain regions 111, 120 of the first and second GAA FETs 101, 102 (e.g., the gate contact 123 may be located at a maximum distance from one or more of the source regions 110, 119 and the drain regions 111, 120 of the first and second GAA FETs 101, 102, and may be located at least at a minimum design rule spacing from the remaining ones of the source regions 110, 119 and the drain regions 111, 120 of the first and second GAA FETs 101, 102). In one or more embodiments, the gate contact 123 may be located at a distance greater than the minimum design rule spacing from at least one of the source regions 110, 119 and the drain regions 111, 120 of the first GAA FET 101 and the second GAA FET 102 (for example, the gate contact 123 may be located at a distance greater than the minimum design rule spacing from one or more of the source regions 110, 119 and the drain regions 111, 120 of the first GAA FET 101 and the second GAA FET 102, and may be located at least at the minimum design rule spacing from the remaining regions of the source regions 110, 119 and the drain regions 111, 120 of the first GAA FET 101 and the second GAA FET 102).

[0083] exist Figure 2D In the embodiment shown in , the first GAA FET 101 is a p-type field effect transistor, and the second GAA FET 102 is an n-type field effect transistor, and the semiconductor device 100 includes two gate contacts 123, 124 located on the gate material 105 of each of the horizontal nanosheet conductive channel structures 104, 114 surrounding the first GAA FET 101 and the second GAA FET 102. Figure 2D In the embodiment shown in FIG, the gate contacts 123, 124 are staggered in the channel spacing between the first GAA FET 101 and the second GAA FET 102. Figure 2A Compared to the channel spacing between the GAA FETs 101, 102 in the embodiment shown, Figure 2DIn the embodiment shown in FIG, the width of the channel spacing between the GAA FETs is increased by reducing the widths W1, W2 of the horizontal nanosheet conductive channel structures 104, 114. In the embodiment shown, the first gate contact 123 is laterally offset relative to the longitudinal centerline L of the channel spacing toward the first GAA FET 101, and the second gate contact 124 is laterally offset relative to the centerline of the channel spacing toward the second GAA FET 102. That is, the first gate contact 123 is laterally spaced apart from the edge 109 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101 by a first distance and laterally spaced apart from the edge 117 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102 by a second distance greater than the first distance, and the second gate contact 124 is laterally spaced apart from the edge 117 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102 by a first distance and laterally spaced apart from the edge 109 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101 by a second distance greater than the first distance. Additionally, in the illustrated embodiment, the first gate contact 123 is longitudinally offset relative to a lateral centerline perpendicular to the longitudinal centerline of the channel spacing toward the source regions 110, 119 of the first and second GAA FETs 101, 102, and the second gate contact 124 is longitudinally offset relative to the lateral centerline toward the drain regions 111, 120 of the first and second GAA FETs 101, 102. In one or more embodiments, the first gate contact 123 may be longitudinally offset toward the drain regions 111, 120 of the first and second GAA FETs 101, 102, and the second gate contact 124 may be longitudinally offset toward the source regions 110, 119 of the first and second GAA FETs 101, 102. That is, the first and second gate contacts 123, 124 are longitudinally offset in opposite directions along an axis defining the channel length of each of the first and second GAA FETs 101, 102. Therefore, in Figure 2D In the embodiment shown in , the spacing between the first gate contact 123 and each of the source region 110 of the first GAA FET 101, the drain region 111 of the first GAA FET 101, the source region 119 of the second GAA FET 102, and the drain region 120 of the second GAA FET 102 is different. Figure 2D In the embodiment shown in , the spacing between the second gate contact 124 and each of the source region 110 of the first GAA FET 101, the drain region 111 of the first GAA FET 101, the source region 119 of the second GAA FET 102, and the drain region 120 of the second GAA FET 102 is different.

[0084] In addition, Figure 2D In the embodiment shown in , the width W1 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101 is equal to or substantially equal to the width W2 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102. In one or more embodiments, the width W1 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101 may be different from the width W2 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102 (i.e., the width W1 of the horizontal nanosheet conductive channel structure 104 of the first GAA FET 101 may be smaller than or larger than the width W2 of the horizontal nanosheet conductive channel structure 114 of the second GAA FET 102).

[0085] The present disclosure also relates to various embodiments of a system on chip (SoC) including a series of semiconductor devices, each of which has a first GAA FET and a second GAA FET. In one or more embodiments, the SoC may include Figures 2A to 2D . Thus, in one or more embodiments, the SoC may include a semiconductor device having GAA FETs having different channel widths in different regions or portions of the SoC. For example, in one or more embodiments, the SoC may include a first semiconductor device, a second semiconductor device, a third semiconductor device, a fourth semiconductor device, or any desired combination thereof, the first semiconductor device including a pFET and an nFET each having the same or substantially the same channel width, and a gate contact (e.g., a gate contact) centrally located between the pFET and the nFET. Figure 2A ), the second semiconductor device includes a pFET with a larger channel width than the nFET, and a gate contact (eg, Figure 2B ), the third semiconductor device includes a pFET with a smaller channel width than the nFET, and a gate contact (eg, Figure 2C ), the fourth semiconductor device includes a pFET and an nFET having the same channel width, and a pair of staggered gate contacts (eg, Figure 2D). Furthermore, in one or more embodiments, a SoC may include semiconductor devices including GAA FETs having different numbers of horizontal nanosheet conductive channel structures (e.g., the SoC may include a first semiconductor device and a second semiconductor device, the first semiconductor device including a p-type GAA FET and an n-type GAA FET, each having two horizontal nanosheet conductive channel structures, and the second semiconductor device including a p-type GAA FET and an n-type GAA FET, each having three horizontal nanosheet conductive channel structures). In one or more embodiments, depending on the desired effective channel width of the GAA FETs in the semiconductor devices, both the number of horizontal nanosheet conductive channel structures and the width of the horizontal nanosheet conductive channel structures may vary between the semiconductor devices in the SoC. Consequently, the effective widths of the channel regions of nFETs and pFETs may vary in different regions or portions of the SoC, and semiconductor devices having pFETs and / or nFETs with reduced effective channel widths may be provided only in those portions or regions of the SoC that are in non-timing critical paths and operate at lower power (e.g., the effective channel widths of the GAA FETs of the semiconductor devices may vary depending on the region or portion of the SoC in which the semiconductor devices are located). In this way, the SoC can be configured to achieve the optimal circuit power, performance, area and cost (PPAC).

[0086] Figure 3 The method 200 of forming a semiconductor device according to one embodiment of the present disclosure is shown, wherein the semiconductor device includes a first gate-all-around (GAA) field-effect transistor (FET) (e.g., a p-type GAA FET) and a second GAA FET (e.g., an n-type GAA FET). In the illustrated embodiment, the method 200 includes an operation 205 of forming or obtaining a stack of alternating conductive channel layers and sacrificial material layers on a substrate. In one or more embodiments, the substrate 103 may be a bulk silicon substrate, a strain relaxation buffer (SRB), or a silicon-on-insulator (SOI) substrate. In one or more embodiments, the conductive material of the conductive channel layer may be silicon (Si), and the sacrificial material of the sacrificial layer may be silicon germanium (SiGe). In one or more embodiments, the conductive material of the conductive channel layer may be SiGe, and the sacrificial material of the sacrificial layer may be Si. The sacrificial layer may have any suitable thickness depending on the desired vertical spacing between the horizontal nanosheet conductive channel structure of the first GAA FET and the horizontal nanosheet conductive channel structure of the second GAA FET. In one or more embodiments, the number of channel layers in the stack may be from two channel layers to six channel layers (e.g., three channel layers), although in one or more embodiments, the initial stack may include any other suitable number of channel layers depending on the desired size of the first GAA FET and the second GAA FET.

[0087] In the illustrated embodiment, method 200 further includes an operation 210 of masking and etching the stack of alternating conductive channel layers and sacrificial layers to form a first stack of alternating conductive channel layers and sacrificial layers for the first GAA FET and a second stack of alternating conductive channel layers and sacrificial layers for the second GAA FET. After masking and etching the initial stack 210, the first stack of the first GAA FET and the second stack of the second GAA FET are spaced apart from each other by a channel pitch. In one or more embodiments, masking and etching the stack of alternating conductive channel layers and sacrificial layers can be performed by any suitable one or more processes, including, for example, extreme ultraviolet (EUV) lithography, EUV litho-etch-litho-etch (LELE), or self-aligned patterning techniques (e.g., self-aligned double patterning (SADP)). In one or more embodiments, after the masking and etching operation 210 of the initial stack, the conductive channel layer in the first stack of the first GAA FET has a different width than the conductive channel layer in the second stack of the second GAA FET. In one or more embodiments, the operation may include performing LELE EUV or 193i, and using one LE for n-type GAA FETs and another LE for p-type GAA FETs to obtain a conductive channel layer having a different width in the first stack of the first GAA FETs (e.g., n-type GAA FETs) than in the second stack of the second GAA FETs (e.g., p-type GAA FETs). In addition, in one or more embodiments, the operation 210 may include a single masking step or multiple masking steps to define the width of the conductive channel layer in the first stack and the width of the conductive channel layer in the second stack.

[0088] In the illustrated embodiment, method 200 further includes an operation 215 of forming a dummy gate stack (e.g., a dummy gate formed of oxide / polysilicon / nitride) and gate spacers on each of the first and second stacks formed in operation 210. The gate spacers may be formed on opposite sides of the dummy gate stacks by any process known in the art (e.g., nitride deposition). In one or more embodiments, the gate spacers may be made of silicon oxide, silicon nitride, silicon carbon oxide, silicon boron carbon nitride, silicon carbon nitride, or a combination thereof.

[0089] In the illustrated embodiment, method 200 further includes forming source and drain electrodes on opposite sides of each of the first and second stacks 220. Forming the source and drain electrodes may include epitaxially regrowing the source and drain electrodes.

[0090] In the illustrated embodiment, the method 200 further includes an operation 225 of depositing an interlayer dielectric (ILD) on the source and drain electrodes, performing chemical mechanical planarization (CMP) on the top of the dummy gate stack, and then removing the dummy gate stack.

[0091] In the illustrated embodiment, the method 200 further includes an operation 230 of removing a sacrificial layer between adjacent conductive channel layers in each of the first and second stacks. The sacrificial layer removal operation 230 can be performed by wet etching, dry etching, or a combination of wet etching and dry etching that is selective to the conductive channel layers. After the sacrificial layer removal operation 230, the conductive channel layers are supported by the gate spacers formed in operation 215.

[0092] In the illustrated embodiment, method 200 further includes an operation 235 of depositing a gate material in the gate stack cavity formed by the operation of removing the dummy gate stack and in the vertical separation region between the conductive channel layers formed by the operation of removing the sacrificial layer. After the operation 235 of depositing the gate material, the gate material completely surrounds each of the conductive channel layers in each of the first stack and the second stack. The operation of depositing the gate material can be performed by an atomic layer deposition process. In addition, in one or more embodiments, the operation 235 of depositing the gate material can also include depositing components such as gate dielectric, gate metal, gate work function metal, work function tuning metal, and / or low resistance capping metal and dielectric capping material.

[0093] In the illustrated embodiment, the method 200 further includes an operation 240 of forming source and drain regions. Operation 240 may include etching the ILD and depositing and etching metal to form the source and drain regions on opposite sides of the gate material.

[0094] In the illustrated embodiment, method 200 further includes an operation 245 of forming at least one gate contact on the gate material deposited in operation 235 in a channel spacing between the conductive channel layer in the first GAA FET and the conductive channel layer in the second GAA FET. In one or more embodiments, operation 245 of forming the at least one gate contact may include forming a single gate contact centrally located between the first GAA FET and the second GAA FET such that the single gate contact is spaced apart a maximum distance (e.g., as shown in FIG. 1 ) from the source and drain regions of the first and second GAA FETs. Figures 2A to 2C ), or forming two staggered gate contacts (e.g., as Figure 2D ).

[0095] Method 200 also includes an operation 250 of completing the formation of GAA FETs and circuits including one or more GAA FETs by operations known in the art, including source and drain contact formation operations, and back-end-of-line (BEOL) formation operations. Furthermore, in one or more embodiments, method 200 may include forming a partial-all-around gate field effect transistor, a conventional full-all-around gate field effect transistor, and / or a conventional fin field effect transistor on the same chip / circuit as the GAA FET formed according to the operations described above.

Claims

1. A semiconductor device comprising: a first wraparound gate field effect transistor; as well as a second wraparound gate field effect transistor spaced apart from the first wraparound gate field effect transistor by a channel spacing, each of the first wraparound gate field effect transistor and the second wraparound gate field effect transistor comprising: at least one horizontal nanosheet conductive channel structure; a gate material completely surrounding each of the at least one horizontal nanosheet conductive channel structure; a source region located at a first end of the at least one horizontal nanosheet conductive channel structure; a source contact located on the source region; a drain region located at a second end of the at least one horizontal nanosheet conductive channel structure opposite to the first end; and a drain contact located on the drain region, wherein a width of the at least one horizontal nanosheet conductive channel structure of at least one of the first wrap-around gate field effect transistor or the second wrap-around gate field effect transistor is less than a maximum allowed width; and At least one gate contact is located on the gate material in the channel spacing between the first and second wrap-around gate field effect transistors, the at least one gate contact being spaced apart from each of the source and drain regions of the first and second wrap-around gate field effect transistors by a distance ranging from a minimum design rule spacing to a maximum distance.

2. The semiconductor device of claim 1 , wherein the at least one gate contact is spaced apart from at least one of the source region or the drain region of at least one of the first and second wraparound gate field effect transistors by a distance greater than the minimum design rule spacing.

3. The semiconductor device of claim 2, wherein the distance is the maximum distance from the at least one of the source region or the drain region of the at least one of the first and second wrap-around-gate field-effect transistors.

4. The semiconductor device of claim 1 , wherein the at least one gate contact is spaced apart from each of the source region and the drain region of each of the first and second wrap-around gate field effect transistors by the maximum distance.

5. The semiconductor device of claim 1 , wherein the first wrap-around gate field effect transistor is a p-type field effect transistor and the second wrap-around gate field effect transistor is an n-type field effect transistor, and wherein a width of the at least one horizontal nanosheet conductive channel structure of the first wrap-around gate field effect transistor is greater than a width of the at least one horizontal nanosheet conductive channel structure of the second wrap-around gate field effect transistor.

6. The semiconductor device of claim 1 , wherein the first wraparound gate field effect transistor is a p-type field effect transistor and the second wraparound gate field effect transistor is an n-type field effect transistor, and wherein a width of the at least one horizontal nanosheet conductive channel structure of the first wraparound gate field effect transistor is smaller than a width of the at least one horizontal nanosheet conductive channel structure of the second wraparound gate field effect transistor. 7 . The semiconductor device of claim 1 , wherein the at least one horizontal nanosheet conductive channel structure comprises a plurality of horizontal nanosheet conductive channel structures. 8 . The semiconductor device according to claim 1 , wherein a width of the at least one horizontal nanosheet conductive channel structure is in a range from 5 nm to 50 nm.

9. A semiconductor device comprising: a first wraparound gate field effect transistor; as well as a second wraparound gate field effect transistor spaced apart from the first wraparound gate field effect transistor by a channel spacing, each of the first wraparound gate field effect transistor and the second wraparound gate field effect transistor comprising: at least one horizontal nanosheet conductive channel structure; a gate material completely surrounding each of the at least one horizontal nanosheet conductive channel structure; a source region located at a first end of the at least one horizontal nanosheet conductive channel structure; a source contact located on the source region; a drain region located at a second end of the at least one horizontal nanosheet conductive channel structure opposite to the first end; and a drain contact located on the drain region; and A first gate contact and a second gate contact are located on the gate material in the channel spacing between the first and second wrap-around gate field effect transistors, the first and second gate contacts being staggered and spaced apart from each of the source and drain regions of the first and second wrap-around gate field effect transistors by a distance ranging from a minimum design rule spacing to a maximum distance.

10. The semiconductor device of claim 9, wherein a width of the at least one horizontal nanosheet conductive channel structure of the first wrap-around gate field effect transistor is different from a width of the at least one horizontal nanosheet conductive channel structure of the second wrap-around gate field effect transistor.

11. The semiconductor device of claim 9, wherein a width of the at least one horizontal nanosheet conductive channel structure of the first wrap-around gate field effect transistor is the same as a width of the at least one horizontal nanosheet conductive channel structure of the second wrap-around gate field effect transistor.

12. The semiconductor device of claim 9, wherein a width of the at least one horizontal nanosheet conductive channel structure of each of the first and second wrap-around gate field effect transistors is in a range from 5 nm to 50 nm.

13. A semiconductor chip comprising: a first semiconductor device comprising a first wraparound gate field effect transistor, a second wraparound gate field effect transistor spaced apart from the first wraparound gate field effect transistor by a channel spacing, and at least one gate contact located in the channel spacing; a second semiconductor device comprising a third wraparound gate field effect transistor, a fourth wraparound gate field effect transistor spaced apart from the third wraparound gate field effect transistor by a channel spacing, and at least one gate contact located in the channel spacing, wherein each of the first wraparound gate field effect transistor, the second wraparound gate field effect transistor, the third wraparound gate field effect transistor, and the fourth wraparound gate field effect transistor comprises: at least one horizontal nanosheet conductive channel structure; a gate material completely surrounding each of the at least one horizontal nanosheet conductive channel structure; a source region located at a first end of the at least one horizontal nanosheet conductive channel structure; a source contact located on the source region; a drain region located at a second end of the at least one horizontal nanosheet conductive channel structure opposite to the first end; and a drain contact located on the drain region, wherein a configuration of the first semiconductor device is different from a configuration of the second semiconductor device, and The at least one gate contact of the second semiconductor device is spaced apart from each of the source and drain regions of the third and fourth wrap-around gate field effect transistors by a distance ranging from a minimum design rule spacing to a maximum distance.

14. A semiconductor chip according to claim 13, wherein the first wrap-around gate field effect transistor of the first semiconductor device is a p-type field effect transistor and the second wrap-around gate field effect transistor of the first semiconductor device is an n-type field effect transistor, and wherein the third wrap-around gate field effect transistor of the second semiconductor device is a p-type field effect transistor and the fourth wrap-around gate field effect transistor of the second semiconductor device is an n-type field effect transistor. 15 . The semiconductor chip of claim 13 , wherein an effective channel width of the first wrap-around gate field effect transistor of the first semiconductor device is different from an effective channel width of the third wrap-around gate field effect transistor of the second semiconductor device.

16. A semiconductor chip according to claim 15, wherein the width of the at least one horizontal nanosheet conductive channel structure of the first wrap-around gate field effect transistor of the first semiconductor device is different from the width of the at least one horizontal nanosheet conductive channel structure of the third wrap-around gate field effect transistor of the second semiconductor device.

17. A semiconductor chip according to claim 15, wherein the at least one horizontal nanosheet conductive channel structure of the first wrap-around gate field effect transistor of the first semiconductor device includes a first plurality of horizontal nanosheet conductive channel structures, and the at least one horizontal nanosheet conductive channel structure of the third wrap-around gate field effect transistor of the second semiconductor device includes a second plurality of horizontal nanosheet conductive channel structures different from the first plurality of horizontal nanosheet conductive channel structures. 18 . The semiconductor chip according to claim 13 , wherein the at least one gate contact of the first semiconductor device comprises a first gate contact and a second gate contact, and the first gate contact and the second gate contact are staggered.

19. A semiconductor chip according to claim 18, wherein the at least one gate contact of the second semiconductor device includes a single gate contact, and the single gate contact is separated from each of the source region and the drain region of the third wrap-around gate field effect transistor and the fourth wrap-around gate field effect transistor of the second semiconductor device by a maximum distance. 20 . The semiconductor chip of claim 13 , wherein the at least one horizontal nanosheet conductive channel structure comprises a plurality of horizontal nanosheet conductive channel structures ranging from two horizontal nanosheet conductive channel structures to four horizontal nanosheet conductive channel structures.

Images