Display device and method for manufacturing the same

Abstract

A display device and a method for manufacturing the display device are provided. The display device includes a pixel circuit, an insulating layer covering the pixel circuit, an etch stop layer arranged on the insulating layer, a first guide layer, a second guide layer, a first electrode, a second electrode and a light-emitting element. The first guide layer and the second guide layer may be arranged on the etch stop layer and spaced apart from each other. The first electrode may be arranged on the first guide layer and electrically connected to the pixel circuit. The second electrode may be arranged on the second guide layer and insulated from the first electrode. The light-emitting element may be in contact with the top surface of the etch stop layer, arranged between the first guide layer and the second guide layer on a plane, and electrically connected to the first electrode and the second electrode.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0140929, filed on November 15, 2018, which is hereby incorporated by reference for all purposes as if set forth herein. Technical Field

[0002] Exemplary embodiments of the present invention relate to a display device having improved reliability and manufacturing yield and a method for manufacturing the display device. Background Art

[0003] The display device may include a light-emitting element electrically connected to an electrode, and may emit light according to a voltage applied to the electrode. The light-emitting element may be formed directly on the electrode, or a light-emitting element formed separately from the electrode may be connected to the electrode. When the light-emitting element is formed separately and then connected to the electrode, a process for aligning the light-emitting element on the electrode is required. When the light-emitting element is not properly aligned on the electrode, the light-emitting element does not emit light.

[0004] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0005] Exemplary embodiments of the present invention provide a display device having improved reliability and manufacturing yield and a method for manufacturing the display device.

[0006] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0007] Exemplary embodiments of the inventive concept provide a display device including a pixel circuit, an insulating layer, an etch stopper layer, a first guide layer, a second guide layer, a first electrode, a second electrode, and a light emitting element.

[0008] An insulating layer may cover the pixel circuit, and an etch stop layer may be disposed on the insulating layer.

[0009] The first guide layer may be disposed on the etch stop layer.The second guide layer may be disposed on the etch stop layer and spaced apart from the first guide layer.

[0010] The first electrode may be disposed on the first guide layer and electrically connected to the pixel circuit. The second electrode may be disposed on the second guide layer and insulated from the first electrode.

[0011] The light emitting element may be in contact with a top surface of the etch stop layer, disposed between the first guide layer and the second guide layer on a plane, and electrically connected to the first electrode and the second electrode.

[0012] The material constituting the etch stop layer and the material forming each of the first guide layer and the second guide layer may have an etching selection ratio of 1:N, and N may be 2 or more.

[0013] The etch stop layer may include silicon oxide, and the first guide layer and the second guide layer may include silicon nitride.

[0014] On a plane, the first guide layer may be covered by the first electrode, and the second guide layer may be covered by the second electrode.

[0015] On a plane, an outer edge of the first electrode may have a shape substantially the same as or similar to that of an outer edge of the first guide layer. On a plane, an outer edge of the second electrode may have a shape substantially the same as or similar to that of an outer edge of the second guide layer.

[0016] The display device may further include a first wall and a second wall. In an embodiment, the first wall may be disposed between the first guide layer and the first electrode. The second wall may be disposed between the second guide layer and the second electrode.

[0017] The first electrode and the second electrode may extend in the first direction and be spaced apart from each other in a second direction intersecting the first direction. The first wall may have a width smaller than that of the first guide layer in the second direction. The second wall may have a width smaller than that of the second guide layer in the second direction.

[0018] The first electrode and the second electrode may extend in a first direction and be spaced apart from each other in a second direction crossing the first direction, respectively. A length of the light emitting element may be smaller than a distance between the first electrode and the second electrode in the second direction.

[0019] The thickness of each of the first guide layer and the second guide layer may be equal to or smaller than the thickness of the light emitting element.

[0020] Another exemplary embodiment of the inventive concept provides a method for manufacturing a display device, the method comprising: forming a pixel circuit on a base layer; forming an insulating layer covering the pixel circuit; forming an etch stop layer on the insulating layer; forming a guide insulating layer on the etch stop layer; forming a first electrode and a second electrode spaced apart from each other on the guide insulating layer through an etching process using a photoresist pattern as a mask;

[0021] a second electrode; forming a first guide layer and a second guide layer by etching the guide insulating layer using the photoresist pattern as a mask; disposing a light emitting element between the first guide layer and the second guide layer; and aligning the light emitting element.

[0022] The steps of forming the first electrode and the second electrode may include: forming a first reflective electrode and a second reflective electrode spaced apart from each other on the guide insulating layer; forming a capping layer on the first reflective electrode and the second reflective electrode; forming a photoresist pattern on the capping layer; and forming a first capping electrode covering the first reflective electrode and a second capping electrode covering the second reflective electrode by patterning the capping layer using the photoresist pattern as a mask.

[0023] The material constituting the etch stop layer and the material constituting the guide insulating layer may have an etching selection ratio of 1:N, where N may be 2 or more.

[0024] The etch stop layer may include silicon oxide, and the guide insulating layer may include silicon nitride.

[0025] The first electrode and the second electrode may be formed through a wet etching process, and the first guide layer and the second guide layer may be formed through a dry etching process.

[0026] In the step of forming the first guide layer and the second guide layer, the etch stop layer may not be etched.

[0027] The method may further include forming a first wall and a second wall spaced apart from each other on the guide insulating layer after forming the guide insulating layer.

[0028] The first electrode and the second electrode may extend in the first direction and be spaced apart from each other in a second direction intersecting the first direction. The first wall may have a width smaller than that of the first guide layer in the second direction. The second wall may have a width smaller than that of the second guide layer in the second direction.

[0029] Another exemplary embodiment of the inventive concept provides a display device, which includes a pixel circuit, an insulating layer covering the pixel circuit, a first guide layer arranged on the insulating layer, a second guide layer arranged on the insulating layer and separated from the first guide layer, a first electrode arranged on the first guide layer and electrically connected to the pixel circuit, a second electrode arranged on the second guide layer and insulated from the first electrode, and a light-emitting element electrically connected to the first electrode and the second electrode.

[0030] The first electrode and the second electrode may extend in a first direction and be spaced apart from each other in a second direction crossing the first direction, respectively. The light emitting element may be disposed between ends of the first electrode and the second electrode facing each other in the second direction.

[0031] The light emitting element may not overlap with the end portion of the first electrode and the end portion of the second electrode on a plane.

[0032] The display device may further include an etch stop layer disposed between the insulating layer and the first guide layer and between the insulating layer and the second guide layer. The light emitting element may contact a top surface of the etch stop layer.

[0033] On a plane, an outer edge of the first electrode may have a shape substantially the same as or similar to a shape of an outer edge of the first guide layer.

[0034] On a plane, an outer edge of the second electrode may have a shape substantially the same as or similar to a shape of an outer edge of the second guide layer.

[0035] The thickness of each of the first guide layer and the second guide layer may be equal to or smaller than the thickness of the light emitting element.

[0036] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept.

[0038] Figure 1 is a perspective view of a display device according to an exemplary embodiment of the inventive concept.

[0039] Figure 2 is a block diagram of a display device according to an exemplary embodiment of the inventive concept.

[0040] Figure 3 is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the inventive concept.

[0041] Figure 4A is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept.

[0042] Figure 4B is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept.

[0043] Figure 4C is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept.

[0044] Figure 4D is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept.

[0045] Figure 5 is a cross-sectional view of a display panel according to an exemplary embodiment of the inventive concept.

[0046] Figure 6is a plan view illustrating a partial configuration of a display panel according to an exemplary embodiment of the inventive concept.

[0047] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F and Figure 7G are cross-sectional views sequentially illustrating steps of manufacturing a display device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0048] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various exemplary embodiments of the invention. As used herein, an "embodiment" is a non-limiting example of a device or method using one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other examples, well-known structures and devices are shown in block diagram form to avoid unnecessary obscurity of various exemplary embodiments. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, construction and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment.

[0049] Unless otherwise specified, the exemplary embodiments shown will be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0050] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or demand for the specific material, material properties, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or two processes described in succession may be performed in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0051] When an element or layer is referred to as being "on" another element or layer, "connected to" or "bonded to" another element or layer, it may be directly on, directly connected to or directly bonded to the other element or layer, or there may be an intermediate element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly bonded to" another element or layer, there is no intermediate element or layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intermediate element. In addition, the D1-axis, the D2-axis and the D3-axis are not limited to three axes such as the x-axis, the y-axis and the z-axis of a rectangular coordinate system, but may be interpreted in a broader sense. For example, the D1-axis, the D2-axis and the D3-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ for example. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0052] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the disclosure, the first element discussed below may be referred to as the second element.

[0053] For descriptive purposes, spatially relative terms such as "under," "below," "below," "down," "above," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein to describe the relationship of one element to another (other) element as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" other elements or features would subsequently be positioned as "above" the other elements or features. Thus, the exemplary term "under" can include both above and below orientations. In addition, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), with the spatially relative descriptors used herein interpreted accordingly.

[0054] The terms used herein are for the purpose of describing specific embodiments, and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "one (kind / person)" and "the (described)" are also intended to include plural forms. In addition, the terms "include" and its variations and / or "comprise" and its variations when used in this specification sheet indicate the presence of stated features, integral bodies, steps, operations, elements, components and / or their groups, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It is also noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, and are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0055] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations, such as those caused by manufacturing techniques and / or tolerances, are expected. Therefore, the exemplary embodiments disclosed herein should not necessarily be interpreted as being limited to the specific illustrated shapes of the regions, but rather include deviations in shapes, such as those caused by manufacturing. In this manner, the regions shown in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and thus need not be intended to be limiting.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0057] Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0058] Figure 1 is a perspective view of a display device according to an exemplary embodiment of the inventive concept.

[0059] Reference Figure 1 , the display device DD can display an image through the display area DA. Figure 1 , the display area DA is exemplarily shown as being disposed on a surface defined by a first direction DR1 and a second direction DR2 crossing the first direction DR1. However, in another exemplary embodiment, the display area of ​​the display device may be disposed on a curved surface.

[0060] The thickness direction of the display device DD is indicated by the third direction DR3. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and can be converted into different directions. In the present disclosure, "when viewed on a plane" may mean when viewed from the third direction DR3. In addition, "thickness direction" may mean the third direction DR3.

[0061] exist Figure 1 In the embodiment, the display device DD is exemplarily shown as a television. However, the display device DD can be used for large electronic devices such as monitors or external billboards, and can also be used for small and medium-sized electronic devices such as personal computers, notebook computers, personal digital terminals, car navigation system units, game consoles, smart phones, tablets, and cameras. It should be understood that these are only examples, and the display device DD can be used in other electronic devices without departing from the inventive concept.

[0062] Figure 2 is a block diagram of a display device according to an exemplary embodiment of the inventive concept.

[0063] Reference Figure 2 , the display device DD may include a display panel DP, a signal control unit TC (or a timing controller), a data driving unit DDV, and a scan driving unit GDV. Each of the signal control unit TC, the data driving unit DDV, and the scan driving unit GDV may include an electronic circuit.

[0064] The display panel DP may be a micro-light emitting element display panel DP including micro-light emitting elements. For example, the display panel DP may be a micro-LED display panel DP.

[0065] The display panel DP may include a plurality of data lines DL1 to DLm, a plurality of scan lines SL1 to SLn, and a plurality of pixels PX.

[0066] The plurality of data lines DL1 to DLm extend in a first direction DR1 and may be arranged in a second direction DR2 crossing the first direction DR1. The plurality of scan lines SL1 to SLn extend in a second direction DR2 and may be arranged in the first direction DR1.

[0067] Each of the pixels PX may include a light emitting element and a pixel circuit electrically connected to the light emitting element. The pixel circuit may include a plurality of transistors. A first power supply voltage ELVDD and a second power supply voltage ELVSS may be provided to each of the pixels PX.

[0068] The pixels may be arranged on the plane of the display panel DP according to a predetermined rule. Each of the pixels PX may display one of the primary colors or one of the mixed colors of the primary colors. The primary colors may include red, green, and blue, and the mixed colors may include various colors such as yellow, cyan, magenta, and white. However, the colors displayed by the pixels PX are not limited thereto.

[0069] The signal control unit TC receives image data RGB provided from the outside, converts the image data RGB to comply with the operation of the display panel DP, generates converted image data R'G'B', and then outputs the converted image data R'G'B' to the data driving unit DDV.

[0070] In addition, the signal control unit TC may receive a control signal CS provided from the outside. Examples of the control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a main clock signal, a data enable signal, etc. The signal control unit TC provides a first control signal CONT1 to the data driving unit DDV, and provides a second control signal CONT2 to the scan driving unit GDV. The first control signal CONT1 is a signal for controlling the data driving unit DDV, and the second control signal CONT2 is a signal for controlling the scan driving unit GDV.

[0071] The data driving unit DDV may provide an electrical signal to the plurality of data lines DL1 to DLm in response to a first control signal CONT1 received from the signal control unit TC. The data driving unit DDV may be implemented as an independent integrated circuit and electrically connected to one side of the display panel DP, or may be directly mounted on the display panel DP. In addition, the data driving unit DDV may be implemented as a single chip, or may include a plurality of chips.

[0072] The scan driving unit GDV may provide an electrical signal to the plurality of scan lines SL1 to SLn in response to a second control signal CONT2 received from the signal control unit TC. The scan driving unit GDV may be integrated in a predetermined area of ​​the display panel DP. For example, the scan driving unit GDV may include a plurality of thin film transistors formed by the same process (e.g., a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process) of the driving circuit of the pixel PX. In another exemplary embodiment of the inventive concept, the scan driving unit GDV may be implemented as an independent integrated circuit and electrically connected to one side of the display panel DP.

[0073] When the gate-on voltage is applied to one of the plurality of scan lines SL1 to SLn, the switching transistor of each pixel in a row connected to the one scan line is turned on. At this time, the data driving unit DDV provides a data driving signal to the data lines DL1 to DLm. The data driving signal provided to the data lines DL1 to DLm is applied to the corresponding pixel through the turned-on switching transistor. The data driving signal may be an analog voltage corresponding to the grayscale value of the image data RGB.

[0074] Figure 3 is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the inventive concept. Figure 3 Show Figure 2 2 is an equivalent circuit diagram of one pixel PX (hereinafter, referred to as a pixel) among a plurality of pixels PX shown in FIG.

[0075] Reference Figure 3 , the pixel PX can be electrically connected to a plurality of signal lines. In the present exemplary embodiment, among the signal lines, the scan line SL, the data line DL, the first power line PL1 and the second power line PL2 are exemplarily shown. However, this is merely exemplary, and the pixel PX according to the inventive concept can be additionally connected to various signal lines and is not limited to any specific exemplary embodiment.

[0076] The pixel PX may include a light emitting element ED, a first electrode E1, a second electrode E2, and a pixel circuit PXC. The pixel circuit PXC may include a first thin film transistor TR1, a capacitor CAP, and a second thin film transistor TR2. However, this is only an example, and the number of thin film transistors and the number of capacitors included in the pixel circuit PXC are not limited to Figure 3 For example, in another exemplary embodiment of the inventive concept, the pixel circuit PXC may include 7 thin film transistors and one capacitor.

[0077] The first thin film transistor TR1 may be a switching transistor for controlling on / off of the pixel PX. The first thin film transistor TR1 may transmit or block a data signal transmitted through the data line DL in response to a scan signal transmitted through the scan line SL.

[0078] The capacitor CAP is connected to the first thin film transistor TR1 and the first power line PL1. The capacitor CAP charges an amount of charge corresponding to a difference between a data signal transmitted from the first thin film transistor TR1 and a first power voltage ELVDD applied to the first power line PL1.

[0079] The second thin film transistor TR2 is connected to the first thin film transistor TR1, the capacitor CAP and the light emitting element ED. The second thin film transistor TR2 controls the driving current flowing in the light emitting element ED according to the amount of charge stored in the capacitor CAP. The on time of the second thin film transistor TR2 can be determined according to the amount of charge charged in the capacitor CAP.

[0080] The first thin film transistor TR1 and the second thin film transistor TR2 may be an N-type thin film transistor or a P-type thin film transistor. In addition, in another exemplary embodiment of the inventive concept, at least one of the first thin film transistor TR1 and the second thin film transistor TR2 may be an N-type thin film transistor, and the other of the first thin film transistor TR1 and the second thin film transistor TR2 may be a P-type thin film transistor.

[0081] The light emitting element ED is connected to the second thin film transistor TR2 and the second power line PL2. For example, the light emitting element ED may be connected to the first electrode E1 electrically connected to the second thin film transistor TR2 and the second electrode E2 connected to the second power line PL2. The first electrode E1 is electrically connected to the pixel circuit PXC, and the second electrode E2 may receive a power voltage, for example, a second power voltage ELVSS, through the second power line PL2.

[0082] The light emitting element ED emits light at a voltage corresponding to a difference between a signal transmitted through the second thin film transistor TR2 and a second power voltage ELVSS received through the second power line PL2 .

[0083] The light emitting element ED may be a micro-LED element. The micro-LED element may be an LED element having a length of several nanometers to several hundred micrometers. However, the length of the micro-LED element is only exemplary, and the length of the micro-LED element is not limited to the above numerical range.

[0084] exist Figure 3 In the embodiment, one light emitting element ED is exemplarily shown to be connected between the second thin film transistor TR2 and the second power line PL2. However, the light emitting element ED may be provided in plurality. The plurality of light emitting elements ED may be connected in parallel to each other.

[0085] Figure 4A is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept.

[0086] The light emitting element ED may have various shapes such as a cylindrical shape or a polygonal column shape. Figure 4A A cross section of the light emitting element ED is shown.

[0087] Reference Figure 4AThe light emitting element ED may include an n-type semiconductor layer SCN, a p-type semiconductor layer SCP, and an active layer AL. The active layer AL may be disposed between the n-type semiconductor layer SCN and the p-type semiconductor layer SCP.

[0088] The n-type semiconductor layer SCN can be provided by doping the semiconductor layer with an n-type dopant, and the p-type semiconductor layer SCP can be provided by doping the semiconductor layer with a p-type dopant. The semiconductor layers SCN and SCP can contain semiconductor materials, and the semiconductor material can be any one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN and AlInN, but not limited thereto. The n-type dopant can be any one of silicon (Si), germanium (Ge), tin (Sn), selenium (Se), tellurium (Te) and combinations thereof, but not limited thereto. The p-type dopant can be any one of magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba) and combinations thereof, but not limited thereto.

[0089] The active layer AL may be formed as at least one of a single quantum well structure, a multi-quantum well structure, a quantum wire structure, and a quantum dot structure. The active layer AL may be a region where electrons injected through the n-type semiconductor layer SCN and holes injected through the p-type semiconductor layer SCP recombine. The active layer AL is a layer that emits light having energy determined by a material-specific energy band. The position of the active layer AL may vary depending on the type of diode.

[0090] The n-type semiconductor layer SCN is connected to the first electrode E1 (see Figure 5 ) and the second electrode E2 (see Figure 5 ), the p-type semiconductor layer SCP is connected to the other of the first electrode E1 and the second electrode E2.

[0091] The length LT of the light emitting element ED may be several nanometers to several hundred micrometers, for example, 1 micrometer to 100 micrometers.

[0092] Figure 4B is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept.

[0093] Reference Figure 4B , when Figure 4A Compared with the light emitting element ED, the light emitting element EDa may further include a first electrode layer ECL1 and a second electrode layer ECL2.

[0094] The first electrode layer ECL1 may be adjacent to the n-type semiconductor layer SCN, and the second electrode layer ECL2 may be adjacent to the p-type semiconductor layer SCP. For example, the first electrode layer ECL1, the n-type semiconductor layer SCN, the active layer AL, the p-type semiconductor layer SCP, and the second electrode layer ECL2 may be sequentially stacked.

[0095] Each of the first electrode layer ECL1 and the second electrode layer ECL2 may be formed of a metal or an alloy of a metal. For example, each of the first electrode layer ECL1 and the second electrode layer ECL2 may be formed of any one metal selected from molybdenum (Mo), chromium (Cr), nickel (Ni), gold (Au), aluminum (Al), titanium (Ti), platinum (Pt), vanadium (V), tungsten (W), lead (Pd), copper (Cu), rhodium (Rh) and iridium (Ir), or an alloy thereof. The first electrode layer ECL1 and the second electrode layer ECL2 may include the same material, or may include materials different from each other.

[0096] Figure 4C is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept.

[0097] Reference Figure 4C , when Figure 4A Compared with the light emitting element EDb, the light emitting element EDb may further include an insulating film IL. For example, the light emitting element EDb may have a core-shell structure.

[0098] The insulating film IL covers the n-type semiconductor layer SCN, the p-type semiconductor layer SCP, and the active layer AL and may protect outer surfaces of the n-type semiconductor layer SCN, the p-type semiconductor layer SCP, and the active layer AL. In another exemplary embodiment of the inventive concept, the insulating film IL may cover only the active layer AL.

[0099] Figure 4D is a cross-sectional view of a light emitting element according to an exemplary embodiment of the inventive concept.

[0100] Reference Figure 4D , when Figure 4B Compared with the light emitting element EDa, the light emitting element EDc may further include an insulating film ILa.

[0101] The insulating film ILa covers the n-type semiconductor layer SCN, the p-type semiconductor layer SCP, and the active layer AL, and may not cover the first electrode layer ECL1 and the second electrode layer ECL2. However, in another exemplary embodiment of the inventive concept, the insulating film ILa may cover at least a portion of the first electrode layer ECL1 and the second electrode layer ECL2, or may completely cover the first electrode layer ECL1 and the second electrode layer ECL2.

[0102] Figure 5is a cross-sectional view of a display panel according to an exemplary embodiment of the inventive concept, Figure 6 is a plan view of a partial configuration of a display panel according to an exemplary embodiment of the inventive concept. For ease of description, Figure 5 and Figure 6 An area corresponding to one pixel is shown, and some configurations are not shown.

[0103] Reference Figure 5 and Figure 6 , the first base layer BL1 and the second base layer BL2 may face each other. Each of the first base layer BL1 and the second base layer BL2 may be a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a stacked structure including a plurality of insulating layers.

[0104] The buffer layer BFL may be disposed on the first base layer BL1. The first thin film transistor TR1 and the second thin film transistor TR2 may be disposed on the buffer layer BFL.

[0105] The first thin film transistor TR1 may include a first control electrode CE1, a first input electrode IE1, a first output electrode OE1, and a first semiconductor pattern SP1. The second thin film transistor TR2 may include a second control electrode CE2, a second input electrode IE2, a second output electrode OE2, and a second semiconductor pattern SP2.

[0106] The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be disposed on the buffer layer BFL. The buffer layer BFL may provide a modified surface for the first semiconductor pattern SP1 and the second semiconductor pattern SP2. In this case, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may have greater adhesion to the buffer layer BFL than when they are directly formed on the first base layer BL1. Alternatively, the buffer layer BFL may be a barrier layer for protecting the bottom surface of each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2. In this case, the buffer layer BFL may block contaminants or moisture introduced through the first base layer BL1 from penetrating into the first semiconductor pattern SP1 and the second semiconductor pattern SP2.

[0107] The first insulating layer L1 is disposed on the buffer layer BFL and may cover the first and second semiconductor patterns SP1 and SP2. The first insulating layer L1 may include an inorganic material. The inorganic material may be, for example, any one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide, but is not limited thereto.

[0108] The first and second control electrodes CE1 and CE2 may be disposed on the first insulating layer L1. The second insulating layer L2 is disposed on the first insulating layer L1 and may cover the first and second control electrodes CE1 and CE2. The second insulating layer L2 may include an inorganic material.

[0109] Capacitor CAP (see Figure 3 ) may include a first capacitor electrode (not shown) and a second capacitor electrode CPa. For example, the first capacitor electrode may be branched from the second control electrode CE2, and the second capacitor electrode CPa may be disposed on the second insulating layer L2.

[0110] The third insulating layer L3 is disposed on the second insulating layer L2 and covers the second capacitor electrode CPa. The first input electrode IE1, the first output electrode OE1, the second input electrode IE2, and the second output electrode OE2 may be disposed on the third insulating layer L3. The first input electrode IE1 and the first output electrode OE1 may be connected to the first semiconductor pattern SP1 through a through hole passing through the first insulating layer L1, the second insulating layer L2, and the third insulating layer L3. The second input electrode IE2 and the second output electrode OE2 may be connected to the second semiconductor pattern SP2 through a through hole passing through the first insulating layer L1, the second insulating layer L2, and the third insulating layer L3. Not only the first input electrode IE1, the first output electrode OE1, the second input electrode IE2, and the second output electrode OE2, but also a signal line (e.g., at least a portion of each of a scan line or a data line) may be disposed on the third insulating layer L3.

[0111] The fourth insulating layer L4 is disposed on the third insulating layer L3 and may cover the first input electrode IE1, the first output electrode OE1, the second input electrode IE2, and the second output electrode OE2. The fourth insulating layer L4 may be composed of a single layer or multiple layers, and the fourth insulating layer L4 may include organic material and / or inorganic material.

[0112] The connection electrode CNE may be disposed on the fourth insulating layer L4. Not only the connection electrode CNE but also the signal line (eg, at least another portion of each of the scan line or the data line) may be disposed on the fourth insulating layer L4. The connection electrode CNE may be connected to the second output electrode OE2.

[0113] The fifth insulating layer L5 is disposed on the fourth insulating layer L4 and may cover the connection electrode CNE. The fifth insulating layer L5 may include an inorganic material. The fifth insulating layer L5 covers the pixel circuit PXC disposed thereunder (see Figure 3 ), and can provide a flat surface.

[0114] The etch stop layer ES is disposed on the fifth insulating layer L5. The etch stop layer ES may be disposed on the entire first base layer BL1 on which the fifth insulating layer L5 is formed, except for a region in which the contact hole is formed.

[0115] The etch stop layer ES may provide a flat surface for the light emitting element ED disposed thereover. The etch stop layer ES may include various insulating materials, and in an exemplary embodiment of the inventive concept, may include silicon oxide.

[0116] The guide layer GC may be disposed on the etch stop layer ES. The guide layer GC may include a first guide layer GC1 and a second guide layer GC2. Each of the first guide layer GC1 and the second guide layer GC2 may extend in the first direction DR1. The first guide layer GC1 and the second guide layer GC2 may be spaced apart from each other in the second direction DR2.

[0117] A seating groove RV may be defined between the first guide layer GC1 and the second guide layer GC2 .

[0118] The first guide layer GC1 and the second guide layer GC2 may include the same material. The first guide layer GC1 and the second guide layer GC2 may include various insulating materials, and in an exemplary embodiment of the inventive concept, may include silicon nitride.

[0119] In an exemplary embodiment of the inventive concept, the etching rate of the material forming each of the first guide layer GC1 and the second guide layer GC2 is faster than the etching rate of the material constituting the etch stop layer ES. The material constituting the etch stop layer ES and the material forming each of the first guide layer GC1 and the second guide layer GC2 may have an etching selectivity ratio of 1:N. At this time, N may be 2 or more.

[0120] The first wall BR1 and the second wall BR2 are disposed on the guide layer GC. Each of the first wall BR1 and the second wall BR2 may extend in the first direction DR1. The second wall BR2 may be spaced apart from the first wall BR1 in the second direction DR2. The first wall BR1 and the second wall BR2 may include the same material. For example, the first wall BR1 and the second wall BR2 may include an organic material.

[0121] The first wall BR1 may have a width smaller than that of the first guide layer GC1 in the second direction DR2. In addition, the second wall BR2 may have a width smaller than that of the second guide layer GC2 in the second direction DR2.

[0122] The first electrode E1 may be disposed on the first guide layer GC1 and the first wall BR1, and the second electrode E2 may be disposed on the second guide layer GC2 and the second wall BR2. The first electrode E1 extends in the first direction DR1 and may cover the first guide layer GC1 and the first wall BR1, and the second electrode E2 extends in the first direction DR1 and may cover the second guide layer GC2 and the second wall BR2. The etch stop layer ES, the first guide layer GC1, and the first wall BR1 may be disposed between the first electrode E1 and the fifth insulating layer L5, and the etch stop layer ES, the second guide layer GC2, and the second wall BR2 may be disposed between the second electrode E2 and the fifth insulating layer L5.

[0123] The etching stopper layer ES, the first guide layer GC1, and the fifth insulating layer L5 are provided with through holes, and the connection electrode CNE may be exposed through the through holes. The first electrode E1 may be electrically connected to the exposed connection electrode CNE. Although not shown, the second electrode E2 may be electrically connected to the second power line PL2 (see FIG. Figure 3 That is, the second electrode E2 may be supplied with the second power supply voltage ELVSS (see Figure 3 ).

[0124] The first electrode E1 may include a first reflective electrode RFE1 and a first cover electrode CPE1, and the second electrode E2 may include a second reflective electrode RFE2 and a second cover electrode CPE2.

[0125] Each of the first reflective electrode RFE1 and the second reflective electrode RFE2 may include a reflective material. Each of the first reflective electrode RFE1 and the second reflective electrode RFE2 may have a single-layer structure or a multi-layer stacked structure. For example, each of the first reflective electrode RFE1 and the second reflective electrode RFE2 may have a structure in which indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) are sequentially stacked.

[0126] The first cover electrode CPE1 may cover the first reflective electrode RFE1, and the second cover electrode CPE2 may cover the second reflective electrode RFE2. For example, each of the first cover electrode CPE1 and the second cover electrode CPE2 may include at least one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), and a mixture thereof.

[0127] On a plane, the first cover electrode CPE1 may cover the first guide layer GC1, and the second cover electrode CPE2 may cover the second guide layer GC2. The first cover electrode CPE1 and the first guide layer GC1 may be formed using the same photosensitive pattern, and the second cover electrode CPE2 and the second guide layer GC2 may be formed using the same photosensitive pattern. On a plane, the outer edge of the first cover electrode CPE1 and the outer edge of the first guide layer GC1 may be substantially the same. At this time, "substantially the same" means that the shape of the outer edge is approximately the same, and includes a case where the boundary of the outer edge is partially changed due to a process error in the etching process.

[0128] However, the inventive concept is not limited thereto. When the material constituting the first cover electrode CPE1 and the material constituting the first guide layer GC1 are different from each other, the etching degrees of the first cover electrode CPE1 and the first guide layer GC1 may be different, and on a plane, the outer edge of the first cover electrode CPE1 and the outer edge of the first guide layer GC1 may have geometrically similar shapes with a predetermined margin. In the same manner, the outer edge of the second cover electrode CPE2 and the outer edge of the second guide layer GC2 may be substantially the same or have geometrically similar shapes with a predetermined margin.

[0129] The light emitting element ED may be disposed on the etching stopper layer ES. The light emitting element ED may be in contact with the top surface of the etching stopper layer ES. A plurality of light emitting elements ED may be disposed, and the plurality of light emitting elements ED may be connected to each other in parallel.

[0130] The light emitting element ED may be disposed in the seat groove RV defined between the first guide layer GC1 and the second guide layer GC2. Therefore, the light emitting element ED may be stably disposed in the region between the first electrode E1 and the second electrode E2. Therefore, the possibility of effective alignment of the light emitting element ED may be increased, thereby improving product yield and product reliability.

[0131] In addition, since the light emitting element ED is aligned by the electric field applied in the seating groove RV, the light emitting element ED is not disposed outside the seating groove RV. Therefore, the problem of wiring short-circuiting due to the light emitting element ED in an unintended area other than the area between the first electrode E1 and the second electrode E2 can be prevented in advance.

[0132] The light emitting element ED may be disposed between the first electrode E1 and the second electrode E2 in the second direction DR2. That is, when viewed from the third direction DR3, the light emitting element ED may not overlap the first electrode E1 and the second electrode E2. In other words, the length W2 of the light emitting element ED may be less than the distance W1 between the first electrode E1 and the second electrode E2 in the second direction DR2.

[0133] The thickness H1 of each of the first guide layer GC1 and the second guide layer GC2 may be equal to or less than the thickness H2 of the light emitting element ED. The thickness of each of the first guide layer GC1 and the second guide layer GC2 may be 1.5 μm or less.

[0134] Therefore, the light emitting element ED may be disposed between the end EG1 of the first electrode E1 and the end EG2 of the second electrode E2 facing each other in the second direction DR2. In addition, the light emitting element ED may overlap the end EG1 of the first electrode E1 and the end EG2 of the second electrode E2 in the second direction DR2. In addition, when viewed from the third direction DR3, the light emitting element ED may not overlap the end EG1 of the first electrode E1 and the end EG2 of the second electrode E2.

[0135] A sixth insulating layer L6 (or insulating pattern) may be disposed on the light emitting element ED. The sixth insulating layer L6 may cover at least a portion of a top surface of the light emitting element ED.

[0136] The light emitting element ED may be electrically connected to the first electrode E1 through the first connection electrode CNE1 , and may be electrically connected to the second electrode E2 through the second connection electrode CNE2 .

[0137] The second connection electrode CNE2 may be disposed on the light emitting element ED and the second electrode E2. The seventh insulating layer L7 may be disposed on the second connection electrode CNE2. The first connection electrode CNE1 may be disposed on the light emitting element ED and the first electrode E1. Even when the length of the light emitting element ED is several hundred micrometers or less, the second connection electrode CNE2 and the first connection electrode CNE1 do not directly contact each other due to the seventh insulating layer L7. However, this is only an example of the inventive concept. In another exemplary embodiment of the inventive concept, the first connection electrode CNE1 and the second connection electrode CNE2 may be formed simultaneously by the same process. In this exemplary embodiment, the seventh insulating layer L7 may be omitted.

[0138] The first connection electrode CNE1 and the second connection electrode CNE2 may include a conductive material. For example, the conductive material may include at least one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), and a mixture thereof. However, the inventive concept is not limited thereto. For example, the conductive material may be a metal material, and the metal material may include, for example, molybdenum, silver, titanium, copper, aluminum, or an alloy thereof.

[0139] An eighth insulating layer L8 may be disposed on the first connection electrode CNE1 and the seventh insulating layer L7. The eighth insulating layer L8 may be an encapsulation layer.

[0140] The light blocking layer BM may be disposed on one surface of the second base layer BL2 facing the first base layer BL1. The light blocking layer BM is provided with an opening, and the wavelength conversion unit CL may cover the opening. The region exposed by the opening may correspond to the pixel light emitting region PXA.

[0141] The wavelength conversion unit CL may include a light-emitting body. For example, the light-emitting body absorbs the first light provided from the light-emitting element ED, and converts the wavelength of the first light to emit a second light of a color different from the color of the first light. The light-emitting body may be, for example, a quantum dot. The first light may be blue light, and the second light may be green light or red light. However, this is merely exemplary, and the inventive concept is not limited thereto. In addition, in another exemplary embodiment of the inventive concept, the wavelength conversion unit CL may be replaced with a color filter. The color filter may absorb light of a specific wavelength to achieve a color. In yet another exemplary embodiment of the inventive concept, the wavelength conversion unit CL may be omitted. In this case, the light-emitting element ED may emit blue light, green light, or red light.

[0142] The ninth insulating layer L9 may be disposed between the wavelength conversion unit CL and the eighth insulating layer L8. For example, the ninth insulating layer L9 may be combined with the pixel circuit PXC disposed thereon (see Figure 3 ) and a first base layer BL1 of the light emitting element ED and a second base layer BL2 on which the wavelength conversion unit CL and the light blocking layer BM are disposed. For example, the ninth insulating layer L9 may be an optically transparent adhesive film, an optically transparent resin, or a pressure-sensitive adhesive film. However, this is only an example, and in another exemplary embodiment of the inventive concept, the ninth insulating layer L9 may be omitted.

[0143] FIG. 7A to FIG. 7G is a cross-sectional view sequentially showing steps of manufacturing a display device according to an exemplary embodiment of the inventive concept. FIG. 7A to FIG. 7G , a method for manufacturing a display device according to an embodiment of the inventive concept will be described.

[0144] Reference Fig. 7A , prepare a first base layer BL1. Although not shown separately, in the manufacturing process, the first base layer BL1 may be disposed on a working substrate (not shown). After manufacturing the display panel, the working substrate may be removed.

[0145] A pixel circuit PXC including a first thin film transistor TR1 and a second thin film transistor TR2 is formed on the first base layer BL1 (see Figure 3 ). A fifth insulating layer L5 covering the pixel circuit PXC is formed. The fifth insulating layer L5 may include an inorganic material. The fifth insulating layer L5 may provide a flat surface.

[0146] An etch stopper layer ES is formed on the fifth insulating layer L5. Thereafter, a guide insulating layer GCL is formed on the etch stopper layer ES.

[0147] The etching rate of the material constituting the guide insulating layer GCL is faster than that of the material constituting the etch stop layer ES. The material constituting the etch stop layer ES and the material constituting the guide insulating layer GCL may have an etching selection ratio of 1:N. At this time, N may be 2 or more.

[0148] In an exemplary embodiment of the inventive concept, the etch stop layer ES may be formed of silicon oxide, and the guide insulation layer GCL may be formed of silicon nitride.

[0149] Thereafter, a first wall BR1 and a second wall BR2 are formed on the guide insulating layer GCL. The first wall BR1 and the second wall BR2 may be formed by forming an insulating material on the guide insulating layer GCL and then patterning the insulating material.

[0150] Afterwards, refer to Figure 7B , a first reflective electrode RFE1 and a second reflective electrode RFE2 are formed on the guide insulating layer GCL, the first wall BR1 and the second wall BR2. The first reflective electrode RFE1 and the second reflective electrode RFE2 may be formed by depositing a conductive material on the guide insulating layer GCL, the first wall BR1 and the second wall BR2, and then patterning. Each of the first reflective electrode RFE1 and the second reflective electrode RFE2 may have a structure in which indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) are sequentially stacked.

[0151] Afterwards, refer to Figure 7C , a cap layer CFL is formed on the first reflective electrode RFE1 and the second reflective electrode RFE2. The cap layer CFL may be formed on the entire guide insulating layer GCL on which the first reflective electrode RFE1 and the second reflective electrode RFE2 are formed. The cap layer CFL may include at least one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), and a mixture thereof.

[0152] Thereafter, a photoresist pattern PRT is formed on the cap layer CFL. The photoresist pattern PRT may be formed to overlap a region where a first cap electrode CPE1 and a second cap electrode CPE2 to be described later are to be formed. The photoresist pattern PRT may be formed by applying a photoresist material to the cap layer CFL and then patterning it.

[0153] Afterwards, refer to Fig.7D, using the photoresist pattern PRT as a mask, the cap layer CFL is patterned to form the first cap electrode CPE1 and the second cap electrode CPE2. At this time, the cap layer CFL may be patterned by a wet etching process. Fig.7D According to the process shown in , the first electrode E1 including the first reflective electrode RFE1 and the first cover electrode CPE1 can be formed, and the second electrode E2 including the second reflective electrode RFE2 and the second cover electrode CPE2 can be formed.

[0154] Afterwards, refer to Fig. 7E , using the photoresist pattern PRT as a mask, the guide insulating layer GCL is patterned to form the first guide layer GC1 and the second guide layer GC2. At this time, the guide insulating layer GCL may be patterned through a dry etching process.

[0155] Since the guide insulating layer GCL and the etch stop layer ES have different etching selectivities, only the guide insulating layer GCL may be etched without etching the etch stop layer ES. When forming the first and second guide layers GC1 and GC2, a seating groove RV may be defined between the first and second guide layers GC1 and GC2.

[0156] Reference Fig.7D and Fig. 7E The cap layer CFL and the guide insulating layer GCL described above can both be patterned using the photoresist pattern PRT as a mask. Therefore, since two photoresist patterns do not need to be formed to pattern the cap layer CFL and the guide insulating layer GCL, the process can be simplified and the manufacturing time and cost can be reduced.

[0157] Thereafter, the photoresist pattern PRT may be removed.

[0158] Afterwards, refer to Figure 7F A solvent SLT such as ink or paste containing a light emitting element ED is disposed on the first electrode E1 and the second electrode E2. The solvent SLT may be a material that can evaporate at room temperature or by heating. The light emitting element ED may be disposed in the seat groove RV between the first guide layer GC1 and the second guide layer GC2.

[0159] When the light emitting element ED is not disposed between the first electrode E1 and the second electrode E2, but is disposed in an unintended region other than the region between the first electrode E1 and the second electrode E2, the light emitting element ED may be used as a conductor, so that wirings designed to be separated from each other may be short-circuited. According to an exemplary embodiment of the inventive concept, the light emitting element ED is disposed in the seat groove RV through the first guide layer GC1 and the second guide layer GC2, and thus may be stably disposed in the region between the first electrode E1 and the second electrode E2. Therefore, the possibility of effective alignment of the light emitting element ED may be increased, and thus the product yield and product reliability may be improved. In addition, the problem of wirings being short-circuited due to the light emitting element ED in unintended regions other than the region between the first electrode E1 and the second electrode E2 may be prevented in advance.

[0160] Power is applied to the first electrode E1 and the second electrode E2 to form an electric field between the first electrode E1 and the second electrode E2. Bipolarity is induced in the light emitting element ED by the electric field, and the light emitting element ED can be aligned between the first electrode E1 and the second electrode E2 by the electrophoretic force. According to an exemplary embodiment of the inventive concept, the light emitting element ED is disposed in the seat groove RV. Therefore, when compared with the comparative example in which the light emitting element is disposed above the first electrode and the second electrode, the light emitting element ED according to the exemplary embodiment of the inventive concept can be more strongly affected by the electric field formed between the first electrode E1 and the second electrode E2 in the second direction DR2. Therefore, according to the exemplary embodiment of the inventive concept, the electrophoretic force generated in the light emitting element ED can be increased, and the alignment of the light emitting element ED can be more facilitated. Therefore, the possibility of effective alignment of the light emitting element ED can be increased, and thus the product yield and product reliability can be improved.

[0161] Afterwards, refer to Figure 7G , a sixth insulating layer L6 , a first connection electrode CNE1 , a second connection electrode CNE2 , a seventh insulating layer L7 , and an eighth insulating layer L8 are sequentially formed on the light emitting element ED. Thus, the first substrate may be manufactured.

[0162] Next, a light blocking layer BM and a wavelength conversion unit CL are formed on one surface of the second base layer BL2. Thus, the second substrate may be manufactured.

[0163] The first and second substrates may be combined using the ninth insulating layer L9. However, embodiments of the inventive concept are not limited thereto, and the ninth insulating layer L9 and the second base layer BL2 may be omitted, and the light blocking layer BM and the wavelength conversion unit CL may be formed to be included in the first substrate.

[0164] According to the display device of the exemplary embodiment of the inventive concept, the light emitting element can be disposed in the seat groove defined between the first guide layer and the second guide layer. Therefore, the light emitting element can be stably disposed in the region between the first electrode and the second electrode. Therefore, the possibility of effective alignment of the light emitting element can be increased, and thus the product yield and product reliability can be improved.

[0165] In addition, since the light emitting element is aligned by the electric field applied in the recess, the light emitting element is not disposed outside the recess. Therefore, the problem of wiring short-circuiting due to the light emitting element in an unintended area other than the area between the first electrode and the second electrode can be prevented in advance.

[0166] Although certain exemplary embodiments have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as are apparent to those of ordinary skill in the art.

Claims

1. A display device, comprising: Pixel circuit; an insulating layer, covering the pixel circuit; An etch stop layer, disposed on the insulating layer; a first guide layer disposed on the etch stop layer; a second guide layer disposed on the etch stop layer and spaced apart from the first guide layer; a first electrode disposed on the first guide layer and electrically connected to the pixel circuit; a second electrode disposed on the second guide layer and insulated from the first electrode; as well as A light emitting element is in contact with a top surface of the etching stopper layer, is provided between the first guide layer and the second guide layer on a plane, and is electrically connected to the first electrode and the second electrode.

2. The display device according to claim 1, wherein: A material constituting the etch stop layer and a material constituting each of the first guide layer and the second guide layer have an etching selection ratio of 1:N, where N is 2 or more.

3. The display device according to claim 2, wherein: The etch stop layer includes silicon oxide, and the first guide layer and the second guide layer each include silicon nitride.

4. The display device according to claim 1, wherein: On a plane, the first guide layer is covered by the first electrode, and the second guide layer is covered by the second electrode.

5. The display device according to claim 4, wherein: On a plane, an outer edge of the first electrode has the same shape as that of an outer edge of the first guide layer; and On a plane, an outer edge of the second electrode has the same shape as that of an outer edge of the second guide layer.

6. The display device according to claim 1, further comprising: a first wall disposed between the first guide layer and the first electrode; as well as a second wall disposed between the second guide layer and the second electrode, in: The first electrode and the second electrode extend in a first direction and are spaced apart from each other in a second direction crossing the first direction; the first wall having a width in the second direction that is smaller than a width of the first guide layer; and The second wall has a width in the second direction that is smaller than a width of the second guide layer.

7. The display device according to claim 1, wherein: The first electrode and the second electrode extend in a first direction and are spaced apart from each other in a second direction crossing the first direction; as well as The length of the light emitting element is smaller than the distance between the first electrode and the second electrode in the second direction.

8. The display device according to claim 1, wherein: The thickness of each of the first guide layer and the second guide layer is equal to or smaller than the thickness of the light emitting element.

9. A method for manufacturing a display device, the method comprising: forming a pixel circuit on the substrate layer; forming an insulating layer covering the pixel circuit; forming an etch stop layer on the insulating layer; forming a guide insulating layer on the etch stop layer; forming a first electrode and a second electrode spaced apart from each other on the guide insulating layer through an etching process using a photoresist pattern as a mask; forming a first guide layer and a second guide layer by etching the guide insulating layer using the photoresist pattern as a mask; Disposing a light emitting element between the first guide layer and the second guide layer; as well as The light emitting elements are aligned.

10. The method according to claim 9, wherein: The steps of forming the first electrode and the second electrode include: forming a first reflective electrode and a second reflective electrode spaced apart from each other on the guide insulating layer; forming a cap layer on the first reflective electrode and the second reflective electrode; forming the photoresist pattern on the capping layer; and The capping layer is patterned by using the photoresist pattern as a mask to form a first capping electrode covering the first reflective electrode and a second capping electrode covering the second reflective electrode.

11. The method according to claim 9, wherein: A material constituting the etch stop layer and a material constituting the guide insulating layer have an etching selection ratio of 1:N, where N is 2 or more.

12. The method according to claim 11, wherein: The etch stop layer includes silicon oxide, and the guide insulating layer includes silicon nitride.

13. The method according to claim 9, wherein: forming the first electrode and the second electrode by a wet etching process; and The first guide layer and the second guide layer are formed by a dry etching process.

14. The method according to claim 9, wherein: In the forming steps of the first guide layer and the second guide layer, the etch stop layer is not etched.

15. The method according to claim 9, further comprising, after forming the guide insulating layer, forming a first wall and a second wall spaced apart from each other on the guide insulating layer, in: The first electrode and the second electrode extend in a first direction and are spaced apart from each other in a second direction crossing the first direction; the first wall having a width in the second direction that is smaller than a width of the first guide layer; as well as The second wall has a width in the second direction that is smaller than a width of the second guide layer.

16. A display device, comprising: Pixel circuit; an insulating layer, covering the pixel circuit; A first guide layer, disposed on the insulating layer; a second guide layer disposed on the insulating layer and spaced apart from the first guide layer; a first electrode disposed on the first guide layer and electrically connected to the pixel circuit; a second electrode disposed on the second guide layer and insulated from the first electrode; a first wall disposed between the first guide layer and the first electrode; a second wall disposed between the second guide layer and the second electrode; as well as a light emitting element electrically connected to the first electrode and the second electrode, in: The first electrode and the second electrode extend in a first direction and are spaced apart from each other in a second direction crossing the first direction; as well as The light emitting element is provided between an end portion of the first electrode and an end portion of the second electrode facing each other in the second direction.

17. The display device according to claim 16, wherein: The light emitting element does not overlap the end portion of the first electrode and the end portion of the second electrode on a plane.

18. The display device according to claim 16, further comprising an etch stop layer provided between the insulating layer and the first guide layer and between the insulating layer and the second guide layer, wherein The light emitting element is in contact with a top surface of the etch stop layer.

19. The display device according to claim 16, wherein: On a plane, an outer edge of the first electrode has a shape that is the same as or similar to a shape of an outer edge of the first guide layer; as well as On a plane, an outer edge of the second electrode has a shape that is the same as or similar to a shape of an outer edge of the second guide layer.

20. The display device according to claim 16, wherein: The thickness of each of the first guide layer and the second guide layer is equal to or smaller than the thickness of the light emitting element.

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