Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a first substrate, an active region defined by an isolation film in the first substrate, an oxide semiconductor layer on the first substrate in the active region and not including silicon, a recess inside the oxide semiconductor layer, and a gate structure filling the recess, including a gate electrode and a cap film on the gate electrode, and having an upper surface that is in the same plane as an upper surface of the active region.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0141232, filed on November 16, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device. Background Technology

[0004] As the integration density of semiconductor devices continues to increase, individual circuit patterns are becoming increasingly miniaturized to accommodate more semiconductor devices within the same area. In other words, the increased integration density of semiconductor devices leads to a reduction in the design rules relative to the constituent elements of the semiconductor device.

[0005] Research is underway on improving leakage characteristics in buried word line array transistor (BCAT) structures where multiple word lines are buried. Summary of the Invention

[0006] One aspect of this disclosure is to provide a semiconductor device that improves reliability by forming an oxide semiconductor layer comprising a material having a higher bandgap on a channel region of an active region (ACT) to enhance leakage characteristics.

[0007] According to some example embodiments of the present disclosure, a semiconductor device is provided, comprising: a first substrate; an active region defined by an isolation film in the first substrate; an oxide semiconductor layer on the first substrate in the active region and not including silicon, the oxide semiconductor layer including a recess; and a gate structure filling the recess, including a gate electrode and a capping film on the gate electrode, the upper surface of the gate structure being coplanar with the upper surface of the active region.

[0008] According to some example embodiments of this disclosure, a semiconductor device is provided, comprising: a substrate; an active region defined by an isolation film in the substrate; a gate structure in the isolation film and the active region, having an upper surface coplanar with the upper surface of the active region; an oxide semiconductor layer in the active region, contacting at least a portion of the sidewalls of the gate structure, and not including silicon; and a capacitor electrically connected to the active region and extending in the thickness direction of the substrate.

[0009] According to some example embodiments of this disclosure, a semiconductor device is provided, comprising: a substrate; an active region defined by an isolation film in the substrate and extending in a first direction; an oxide semiconductor layer extending in the active region on the substrate in the first direction and excluding silicon; a word line extending in the isolation film and the active region in a second direction different from the first direction; and a bit line extending upward in the isolation film and the active region in a third direction different from the first and second directions, wherein the upper surface of the oxide semiconductor layer is coplanar with the upper surface of the active region.

[0010] The aspects that this disclosure is intended to address are not limited to those mentioned above, and other aspects not mentioned above will be clearly understood by those skilled in the art based on the description provided below. Attached Figure Description

[0011] The above and other aspects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0012] Figure 1 These are schematic layout diagrams of semiconductor devices according to some exemplary embodiments of the present disclosure;

[0013] Figure 2 It is along Figure 1 A cross-sectional view taken from line II;

[0014] Figures 3 to 12 This is a diagram illustrating an intermediate manufacturing stage of a method for manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0015] Figure 13 These are diagrams provided to illustrate semiconductor devices according to some other exemplary embodiments of the present disclosure;

[0016] Figure 14 These are diagrams provided to illustrate semiconductor devices according to some other exemplary embodiments of the present disclosure;

[0017] Figure 15 These are diagrams provided to illustrate semiconductor devices according to some other exemplary embodiments of the present disclosure; and

[0018] Figure 16 This is a diagram provided to illustrate a semiconductor device according to some other example embodiments of the present disclosure. Detailed Implementation

[0019] Below, we will refer to Figure 1 and Figure 2 This disclosure describes semiconductor devices according to some example embodiments.

[0020] Figure 1 This is a schematic layout diagram of a semiconductor device according to some example embodiments. Figure 2 It is along Figure 1 The cross-sectional view taken from line II.

[0021] Although dynamic random access memory (DRAM) is illustrated in the accompanying drawings of semiconductor devices according to some example embodiments, this disclosure is not limited thereto.

[0022] Reference Figure 1 A semiconductor device according to some example embodiments may include a plurality of active regions ACT. The active regions ACT may be disposed on a substrate 100 ( Figure 2 ) and the isolation film 105 in the oxide semiconductor layer 102 Figure 2 )limited.

[0023] As design rules for semiconductor devices become less restrictive, active regions (ACTs) can be arranged in diagonal or oblique stripe patterns, such as... Figure 1 As shown. The active region ACT can be arranged to extend in the first direction DR1.

[0024] On and across the active region ACT, multiple gate electrodes can be arranged in the second direction DR2. These gate electrodes can extend parallel to each other. For example, the multiple gate electrodes can be multiple word lines WL.

[0025] The letter lines (WL) can be arranged at uniform intervals. The width of the letter lines (WL) or the spacing between them can be determined according to design rules.

[0026] Multiple bit lines BL can be arranged on and orthogonal to the word line WL, extending in the third direction DR3. These multiple bit lines BL can extend parallel to each other.

[0027] Bit lines BL can be arranged at uniform intervals. The width of bit lines BL or the spacing between bit lines BL can be determined according to design rules.

[0028] In some example embodiments, bit lines BL can be arranged parallel to each other with a spacing of 3F. Furthermore, word lines WL can be arranged parallel to each other with a spacing of 2F.

[0029] As used herein, "F" can indicate "minimum lithographic feature size". When the bit line BL and word line WL are arranged according to the above spacing, the semiconductor device may include a 6F-sized feature. 2 A memory cell with a unit cell size.

[0030] The semiconductor device according to some example embodiments may include various contact arrangements formed on an active region ACT. For example, various contact arrangements may include direct contacts DC and buried contacts BC.

[0031] In this document, the direct contact DC indicates the contact used to electrically connect the active region ACT to the bit line BL. The buried contact BC indicates the contact used to connect the active region ACT to the lower electrode 191 of the capacitor. Figure 2 ) contacts.

[0032] In a semiconductor device according to some example embodiments, a direct contact DC may be arranged at the center of the active region ACT. Buried contacts BC may be arranged at both ends of the active region ACT.

[0033] In other words, the buried contact BC can be arranged as the active region ACT and the isolation membrane 105 between the adjacent word line WL and the adjacent bit line BL. Figure 2 )overlap.

[0034] The word line WL can be formed according to the structure buried in the active area ACT. The word line WL can be arranged across the active area ACT between the direct contact DC or the buried contact BC.

[0035] like Figure 1 As shown, two word lines WL can be arranged across an active region ACT. When the active region ACT is arranged diagonally, the word line WL can have an angle of less than 90 degrees with the active region ACT. The direct contact DC and the buried contact BC can be arranged symmetrically on the active region ACT.

[0036] Reference Figure 1 and Figure 2 A semiconductor device according to some example embodiments may include a substrate 100, an active region ACT, an isolation film 105, a plurality of gate structures 110, storage contacts 120, a plurality of conductive films 140, bit line contacts 146, and / or a capacitor 190.

[0037] Substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, substrate 100 may be a silicon substrate, or may include other materials such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but this disclosure is not limited thereto. In the following description, it is assumed that substrate 100 is a silicon substrate.

[0038] An isolation film 105 may be formed in the substrate 100 and the oxide semiconductor layer 102. Although Figure 2 An isolation film 105 is depicted forming in a first substrate 101 disposed on a substrate 100, but this is only for illustrative purposes. That is, the substrate 100 and the first substrate 101 comprise the same material, and for illustrative purposes, the portion of the substrate 100 included in the active region ACT is shown as the first substrate 101.

[0039] The isolation film 105 may have a shallow trench isolation structure, which has device isolation characteristics. The isolation film 105 may define an active region ACT in the first substrate 101 and the oxide semiconductor layer 102.

[0040] The separator 105 may include at least one of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, but this disclosure is not limited thereto. In semiconductor devices according to some example embodiments, the separator 105 is described as including a silicon oxide film.

[0041] although Figure 2 The separator 105 is depicted as forming an insulating film, but this is only for illustrative purposes and the present disclosure is not limited thereto.

[0042] The active region ACT can have a long island form including a short axis and a long axis, such as... Figure 1 As shown. The active region ACT may have a diagonal form with an angle of less than 90 degrees relative to the word line WL formed in the isolation film 105. Furthermore, the active region ACT may have a diagonal form with an angle of less than 90 degrees relative to the bit line BL formed on the isolation film 105. That is, the active region ACT may extend in a first direction DR1, which has a specific angle relative to the second direction DR2 and the third direction DR3.

[0043] An active region ACT may be disposed on a substrate 100. The active region ACT may include a first substrate 101 protruding from the substrate 100 in a fourth direction DR4 and an oxide semiconductor layer 102 disposed on the first substrate 101. The active region ACT may be isolated from adjacent active regions ACT by an isolation film 105.

[0044] The oxide semiconductor layer 102 may include a material that does not contain silicon and / or has a higher band gap. For example, the oxide semiconductor layer 102 may include indium gallium zinc oxide (IGZO). However, this disclosure is not limited thereto. That is, in some other example embodiments, the oxide semiconductor layer 102 may include another material that does not contain silicon and / or has a higher band gap.

[0045] The oxide semiconductor layer 102 may be disposed on the uppermost portion of the active region ACT. That is, the upper surface 102a of the oxide semiconductor layer 102 may be formed on the same plane as the upper surface ACTa of the active region ACT. However, this disclosure is not limited thereto.

[0046] The gate structure 110 may be disposed in the oxide semiconductor layer 102 and the isolation film 105. The gate structure 110 may be disposed across the isolation film 105 and the active region ACT defined by the isolation film 105. The gate structure 110 may be formed in the oxide semiconductor layer 102 and the isolation film 105 positioned on a second direction DR2 extending from the gate structure 110.

[0047] Two gate structures 110 can be arranged across an active region ACT on a single active region ACT. The two gate structures 110 can be spaced apart from each other on a third-direction DR3. This is in Figure 2 The diagram shows a first gate structure 110_1 and a second gate structure 110_2 spaced apart from each other in the first direction DR1 in the active region ACT.

[0048] The gate structure 110 may include a recess 114 formed in the oxide semiconductor layer 102 and the isolation film 105, a gate insulating film 111, a gate electrode 112, and / or a capping film 113. In this document, the gate electrode 112 may correspond to a word line WL.

[0049] The gate structure 110 may be disposed within the oxide semiconductor layer 102 in the active region ACT. That is, the recess 114 may be formed within the oxide semiconductor layer 102 in the active region ACT, and the bottom surface of the recess 114 may be spaced apart from the first substrate 101. However, this disclosure is not limited thereto.

[0050] The gate insulating film 111 may extend along the sidewalls and bottom surface of the recess 114. The gate insulating film 111 may be disposed along the inner wall of the recess 114 between the inner wall of the recess 114 and the gate electrode 112.

[0051] The gate insulating film 111 may not be disposed between the inner wall of the recess 114 and the capping film 113. However, this disclosure is not limited thereto.

[0052] The gate insulating film 111 may comprise silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material with a dielectric constant higher than that of silicon oxide. For example, the high-k dielectric material may comprise at least one of the following: hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0053] Although the above-described high-k dielectric materials are primarily described with reference to oxides, alternatively, high-k dielectric materials may include one or more of the above-described metallic materials (e.g., hafnium nitride) or oxynitrides (e.g., hafnium oxynitride) nitrides, but this disclosure is not limited thereto.

[0054] The gate electrode 112 may be disposed on the gate insulating film 111. The gate electrode 112 may fill a portion of the recess 114. The upper surface 112a of the gate electrode 112 may be formed on the same plane as the upper surface of the gate insulating film 111, but this disclosure is not limited thereto.

[0055] The gate electrode 112 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), and tungsten. At least one of the following: (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof.

[0056] The gate electrode 112 may include conductive metal oxides, conductive metal nitrides, or the oxidation form of a metal material derived from the above materials.

[0057] The upper surface 112a of the gate electrode 112 may be formed closer to the upper surface 102a of the oxide semiconductor layer 102 than the upper surface 101a of the first substrate 101. That is, the upper surface 112a of the gate electrode 112 may be formed between the upper surface 101a of the first substrate 101 and the upper surface 102a of the oxide semiconductor layer 102.

[0058] A capping film 113 may be disposed on the gate electrode 112. The capping film 113 may fill another portion of the interior of the recess 114 where the gate insulating film 111 and the gate electrode 112 are disposed. The capping film 113 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and combinations thereof.

[0059] Figure 2 The upper surface of the capping film 113 can indicate the upper surface 110a of the gate structure 110. The upper surface of the capping film 113 can be formed on the same plane as the upper surface 102a of the oxide semiconductor layer 102. That is, the upper surface 110a of the gate structure 110 can be formed on the same plane as the upper surface 102a of the oxide semiconductor layer 102.

[0060] although Figure 2 As not shown, a doped region may be formed on at least one side of the gate structure 110. The doped region may be the source / drain region of the transistor.

[0061] The conductive wire film 140 may be disposed on the oxide semiconductor layer 102 and the isolation film 105 on which the gate structure 110 is formed. The conductive wire film 140 may intersect with the isolation film 105 and the active region ACT defined by the isolation film 105.

[0062] In other words, a conductive wire 140 may be disposed on an oxide semiconductor layer 102 and an isolation film 105 positioned on a third-direction DR3 extending from the conductive wire 140. The conductive wire 140 may be formed to intersect with the gate structure 110. In this document, the conductive wire 140 may correspond to a bit line BL.

[0063] The conductive film 140 can be a single-layer film, but as shown, it can be a multilayer film. When the conductive film 140 is a multilayer film, it may include, for example, a first conductive film 142 and a second conductive film 143, but this disclosure is not limited thereto. The first conductive film 142 and the second conductive film 143 may be sequentially stacked on the oxide semiconductor layer 102 and the isolation film 105.

[0064] The first conductive film 142 and the second conductive film 143 may each comprise at least one of, for example, a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, and a metal. For example, the first conductive film 142 may comprise a conductive silicide compound, and the second conductive film 143 may comprise at least one of a conductive metal nitride and a metal. However, this disclosure is not limited thereto.

[0065] Bit line contacts 146 can be disposed between conductive wire film 140 and oxide semiconductor layer 102. That is, conductive wire film 140 can be disposed on bit line contacts 146.

[0066] For example, bit line contacts 146 may be disposed at the intersection between the conductive film 140 and the center of the active region ACT having an island shape. Bit line contacts 146 may also be disposed between the oxide semiconductor layer 102 and the conductive film 140 at the center of the active region ACT.

[0067] Bit line contact 146 can electrically connect the conductive film 140 and the oxide semiconductor layer 102. For example, bit line contact 146 can electrically connect a doped region of the oxide semiconductor layer 102 between adjacent gate structures 110 to the conductive film 140. In this document, bit line contact 146 may correspond to direct contact DC.

[0068] The depth from the upper surface 110a of the gate structure 110 to the bottom surface of the line contact 146 may be less than the depth from the upper surface 110a of the gate structure 110 to the lower surface of the capping film 113. However, this disclosure is not limited thereto.

[0069] Bit line contact 146 may include, for example, at least one of a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. However, this disclosure is not limited thereto.

[0070] The conductor capping film 144 may be disposed on the conductor conductive film 140 and extend toward the third direction DR3. For example, the conductor capping film 144 may include a silicon nitride film, but this disclosure is not limited thereto.

[0071] The conductive film 140 and the capping film 144 may be included in the bit line structure 145. The space between adjacent bit line structures 145 may overlap perpendicularly with the oxide semiconductor layer 102 and the isolation film 105.

[0072] The conductor spacer 150 may be disposed on the sidewalls of the bit contact 146, the conductor conductive film 140, and the conductor capping film 144. The conductor spacer 150 may extend in the third direction DR3 on the sidewalls of the bit contact 146, the conductor conductive film 140, and the conductor capping film 144.

[0073] The conductor spacer 150 can be a single-layer film, or as... Figure 2 As shown, the conductor spacer 150 may be a multilayer film including a first spacer 151 and a second spacer 152. For example, the first spacer 151 and the second spacer 152 may include one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon carbonitride film, air, and combinations thereof. However, this disclosure is not limited thereto.

[0074] The first interlayer insulating film 170 may be disposed on the oxide semiconductor layer 102 and the isolation film 105. The first interlayer insulating film 170 may be disposed to overlap with the gate structure 110 formed in the oxide semiconductor layer 102 and the isolation film 105.

[0075] The first interlayer insulating film 170 may be disposed on the gate structure 110 and may extend in the second direction DR2. The first interlayer insulating film 170 may intersect with the bit line structure 145 extending in the third direction DR3. The space between adjacent first interlayer insulating films 170 may overlap with the oxide semiconductor layer 102 and the isolation film 105 in the fourth direction DR4.

[0076] The first interlayer insulating film 170 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. It is shown that the first interlayer insulating film 170 is a single-layer film, but this is for illustrative purposes only, and the present disclosure is not limited thereto.

[0077] Storage contacts 120 may be arranged between adjacent gate structures 110 and between adjacent conductive films 140. A portion of storage contacts 120 may be arranged to extend into the interior of oxide semiconductor layer 102 and isolation film 105.

[0078] Storage contacts 120 may be disposed between adjacent gate structures 110 and between adjacent conductive films 140. Storage contacts 120 may overlap with oxide semiconductor layers 102 and isolation films 105 between adjacent gate structures 110 and adjacent conductive films 140. Gate structures 110 may be positioned between storage contacts 120 and bit line contacts 146. In this document, storage contacts 120 may correspond to buried contacts BC.

[0079] The upper surface of the storage contact 120 may be closer to the substrate 100 than the upper surface of the first interlayer insulating film 170 and the upper surface of the bit line structure 145. However, this disclosure is not limited thereto.

[0080] although Figure 2 The lower surface of the contact oxide semiconductor layer 102 of the storage contact 120 and the lower surface of the contact isolation film 105 of the storage contact 120 are depicted without stepped portions, but this disclosure is not limited thereto. That is, in some other example embodiments, stepped portions may be formed between the lower surface of the contact oxide semiconductor layer 102 of the storage contact 120 and the lower surface of the contact isolation film 105 of the storage contact 120.

[0081] The storage contact 120 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, and a metal.

[0082] Storage pad 160 may be arranged on storage contact 120. Storage pad 160 may be electrically connected to storage contact 120.

[0083] The storage pad 160 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, and a metal.

[0084] A second interlayer insulating film 180 may be disposed on the storage pad 160, the bit line structure 145, and the first interlayer insulating film 170. The second interlayer insulating film 180 may define the area of ​​the storage pad 160 that forms multiple isolation regions. In addition, the second interlayer insulating film 180 may be patterned to expose a portion of the upper surface of the storage pad 160.

[0085] The second interlayer insulating film 180 may include an insulating material to electrically isolate the plurality of storage pads 160 from each other. For example, the second interlayer insulating film 180 may include one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and combinations thereof, but this disclosure is not limited thereto.

[0086] Capacitor 190 may be formed on the second interlayer insulating film 180. Capacitor 190 may be electrically connected to storage pad 160. That is, capacitor 190 may be electrically connected to storage contact 120.

[0087] The capacitor 190 may include a lower electrode 191, a capacitor insulating film 192, and / or an upper electrode 193.

[0088] For example, the lower electrode 191 may have a pillar shape. For example, the lower electrode 191 may extend in a fourth direction DR4 (which is the thickness direction of the first substrate 101).

[0089] For example, the lower electrode 191 may include doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, or tungsten nitride), metals (e.g., ruthenium, iridium, titanium, or tantalum), conductive metal oxides (e.g., iridium oxide), etc., but this disclosure is not limited thereto.

[0090] A capacitor insulating film 192 may be disposed on the lower electrode 191. The capacitor insulating film 192 may be disposed along the contour of the lower electrode 191. That is, the capacitor insulating film 192 may be formed along the sidewall and upper surface of the lower electrode 191.

[0091] For example, the capacitor insulating film 192 may include one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof, but this disclosure is not limited thereto.

[0092] The upper electrode 193 may be disposed on the capacitor insulating film 192. The upper electrode 193 may surround the lower electrode 191.

[0093] The upper electrode 193 may include at least one of, for example, doped semiconductor material, metal, conductive metal nitride and metal silicide.

[0094] The semiconductor device according to some example embodiments has an oxide semiconductor layer comprising a material that does not contain silicon and has a higher bandgap, formed on the channel region of the active region ACT, thereby enhancing leakage characteristics and thus improving reliability.

[0095] The following will refer to Figures 1 to 12 A method for manufacturing a semiconductor device according to some example embodiments is described.

[0096] Figures 3 to 12 This is a diagram illustrating an intermediate manufacturing stage of a method for manufacturing a semiconductor device according to some example embodiments.

[0097] Reference Figure 3 An oxide semiconductor layer 102 can be formed on the substrate 100.

[0098] For example, substrate 100 may be a silicon substrate. The oxide semiconductor layer 102 may include a material that does not contain silicon and has a higher bandgap, such as indium gallium zinc oxide (IGZO).

[0099] Reference Figure 4 An isolation film 105 can be formed by filling an insulating material inside a trench formed by etching a portion of the substrate 100 and the oxide semiconductor layer 102.

[0100] The first substrate 101 and the oxide semiconductor layer 102 can be included on the substrate 100 by means of the isolation film 105, and an active region ACT extending in the first direction DR1 can be defined.

[0101] Reference Figure 1 and Figure 5 Multiple gate structures 110 extending in the second direction DR2 can be formed in the oxide semiconductor layer 102 and the isolation film 105.

[0102] Multiple gate structures 110 can be respectively located in a third-direction DR3 ( Figure 1 They are spaced apart from each other. Figure 5 The first gate structure 110_1 and the second gate structure 110_2 are depicted being spaced apart from each other in the first direction DR1 inside the oxide semiconductor layer 102.

[0103] For example, a recess 114 extending in the second direction DR2 can be formed in the oxide semiconductor layer 102 and the isolation film 105. Since the etching rates of the oxide semiconductor layer 102 and the isolation film 105 may be different, the depth of the recess 114 in the oxide semiconductor layer 102 may be different from the depth of the recess 114 in the isolation film 105.

[0104] A gate insulating film 111 may be formed along the sidewalls and bottom surface of the recess 114. The gate insulating film 111 may extend along the upper surface of the oxide semiconductor layer 102 and the upper surface of the isolation film 105, but this disclosure is not limited thereto.

[0105] A gate conductive film for filling the recess 114 can be formed on the gate insulating film 111. The gate conductive film can also be formed on the upper surface of the oxide semiconductor layer 102 and the upper surface of the isolation film 105.

[0106] Then, by removing a portion of the gate conductive film filling the recess 114, a gate electrode 112 for filling a portion of the recess 114 can be formed. The gate conductive film on the upper surface of the oxide semiconductor layer 102 and the upper surface of the isolation film 105 can also be removed.

[0107] In addition, a portion of the gate insulating film 111 extending along the upper surface of the oxide semiconductor layer 102 and the upper surface of the isolation film 105, as well as a portion of the gate insulating film 111 formed on the sidewall of the recess 114, can be removed.

[0108] A capping film 113, filling a portion of the recess 114, can then be formed on the gate electrode 112. In some example embodiments, the upper surface of the capping film 113 may be formed on the same plane as the upper surface of the oxide semiconductor layer 102.

[0109] Reference Figure 6 On the oxide semiconductor layer 102 on which multiple gate structures 110 are formed, a pre-cell insulating film 130p, a pre-wire conductive film 140p including a pre-position line contact 146p connected to the oxide semiconductor layer 102 and / or a pre-wire capping film 144p may be formed sequentially.

[0110] For example, a pre-cell insulating film 130p may be formed on the oxide semiconductor layer 102, the isolation film 105, and the gate structure 110. A first pre-conductive film 141p may be formed on the pre-cell insulating film 130p.

[0111] The pre-unit insulating film 130p may include a first pre-unit insulating film 131p and a second pre-unit insulating film 132p, but this disclosure is not limited thereto.

[0112] Then, in the area where the bit line contact 146 is formed, the bit line contact hole 146h can be formed by removing the first pre-conductive film 141p and the pre-unit insulating film 130p. A pre-positioning contact 146p for filling the bit line contact hole 146h can be formed.

[0113] A second pre-conductive film 142p and a third pre-conductive film 143p can be sequentially formed on the pre-positioning contact 146p and the first pre-conductive film 141p. As a result, a pre-conductive conductive film 140p, including the first to third pre-conductive films 141p, 142p, and 143p, can be formed on the pre-unit insulating film 130p.

[0114] Then, a pre-conductor capping film 144p can be formed on the pre-conductor conductive film 140p.

[0115] Reference Figure 7 The pre-conducting conductive film 140p and the pre-conducting capping film 144p can be patterned and formed on the oxide semiconductor layer 102 in a third-direction DR3 ( Figure 1 Multiple conductive wire films 140 and / or wire capping films 144 extending on the oxide semiconductor layer 102. That is, bit line structures 145 can be formed on the oxide semiconductor layer 102.

[0116] Furthermore, the bit line contact 146 can be formed between the conductive film 140 and the oxide semiconductor layer 102 by patterning the bit line contact 146p.

[0117] The gate structure 110 formed in the oxide semiconductor layer 102 and the isolation film 105 may be covered by the pre-cell insulating film 130p.

[0118] Reference Figure 8 Conductor spacers 150 can be formed on the sidewall of the bit line structure 145.

[0119] For example, a wire spacer 150 may be formed on the oxide semiconductor layer 102 and the isolation film 105 at the portion of the conductive film 140 where the bit contact 146 is formed. The wire spacer 150 may be formed on the third-party DR3 ( Figure 1 It extends along the sidewall of bit line structure 145.

[0120] Additionally, conductor spacers 150 can be formed on the pre-unit insulating film 130p at the remaining portion of the bit line structure 145 where the bit line contacts 146 are not formed.

[0121] The conductor spacer 150 may include a first spacer 151 and a second spacer 152, but this disclosure is not limited thereto. The first spacer 151 of the conductor spacer 150 may be formed along the upper surface of the pre-unit insulating film 130p.

[0122] Reference Figure 9 In the bit line structure 145 and the conductor spacer 150, the pre-unit insulating film 130p that does not overlap with the second spacer 152 and the first spacer 151 can be removed.

[0123] As a result, the upper surfaces of the oxide semiconductor layer 102 and the isolation film 105 are exposed. In addition, the upper surface of the gate structure 110 is also exposed.

[0124] Reference Figure 10 DR2 in the second direction can be formed on the oxide semiconductor layer 102 and the isolation film 105. Figure 1 The first interlayer insulating film 170 extends on the top. The first interlayer insulating film 170 may intersect with the bit line structure 145.

[0125] The first interlayer insulating film 170 may be formed to overlap with the gate structure 110 formed in the oxide semiconductor layer 102 and the isolation film 105.

[0126] As a result, the oxide semiconductor layer 102 and the isolation film 105, which are not covered by the first interlayer insulating film 170 and the bit line structure 145, can be exposed. That is, the oxide semiconductor layer 102 and the isolation film 105 between adjacent gate structures 110 and between adjacent conductive films 140 can be exposed.

[0127] Reference Figure 11 Storage contact recesses 125p can be formed in oxide semiconductor layers 102 and isolation films 105 by removing oxide semiconductor layers 102 and isolation films 105 between adjacent gate structures 110 and between adjacent conductive films 140.

[0128] It can be used in the second direction DR2 ( Figure 1 The first interlayer insulating film 170 extending on the third-party DR3 () and the third-party DR3 () Figure 1 The bit line structure 145 and the conductor spacer 150 extending on the top serve as a mask to form the storage contact recess 125p.

[0129] Reference Figure 12 Storage contacts 120 for filling storage contact recesses 125p can be formed on oxide semiconductor layers 102 and isolation films 105 between adjacent gate structures 110 and between adjacent conductive films 140.

[0130] Storage contacts 120 may be formed along a portion of the sidewall of the first interlayer insulating film 170.

[0131] Reference Figure 2 After the storage pad 160 is formed on the storage contact 120, a second interlayer insulating film 180 is formed on the storage pad 160, the first interlayer insulating film 170 and the bit line structure 145.

[0132] Then, a capacitor 190 electrically connected to the storage pad 160 can be formed on the second interlayer insulating film 180. By the above manufacturing method, a device can be manufactured. Figure 2 The semiconductor device shown.

[0133] Below, we will refer to Figure 13 Describes a semiconductor device according to some other example embodiments. Highlights will be given. Figure 2 The differences shown are in the semiconductor devices.

[0134] Figure 13 These are diagrams provided to illustrate semiconductor devices according to some other example embodiments.

[0135] Reference Figure 13 In a semiconductor device according to some other example embodiments, the active region ACT disposed on the substrate 200 includes a first substrate 201 and an oxide semiconductor layer 202 disposed on the first substrate 201.

[0136] The recess 114 on which the gate structure 110 is formed can extend through the oxide semiconductor layer 202 into the interior of the first substrate 201. That is, the gate structure 110 can be disposed inside the first substrate 201 and the oxide semiconductor layer 202.

[0137] The upper surface 201a of the first substrate 201 may be formed closer to the upper surface 202a of the oxide semiconductor layer 202 than the upper surface 112a of the gate electrode 112. That is, the upper surface 201a of the first substrate 201 may be formed between the upper surface 112a of the gate electrode 112 and the upper surface 202a of the oxide semiconductor layer 202.

[0138] In some example embodiments, the lower portion of the bit line structure 145 may be disposed inside the oxide semiconductor layer 202.

[0139] Below, we will refer to Figure 14 Describes a semiconductor device according to some other example embodiments. Highlights will be given. Figure 2 The differences shown are in the semiconductor devices.

[0140] Figure 14 These are diagrams provided to illustrate semiconductor devices according to some other example embodiments.

[0141] Reference Figure 14 In a semiconductor device according to some other example embodiments, the active region ACT disposed on the substrate 300 includes a first substrate 301, an oxide semiconductor layer 302 disposed on the first substrate 301 and / or a second substrate 303 disposed on the oxide semiconductor layer 302.

[0142] The second substrate 303 can be disposed on the uppermost part of the active region ACT. That is, the upper surface 303a of the second substrate 303 can be formed on the same plane as the upper surface ACTa of the active region ACT and the upper surface 110a of the gate structure 110.

[0143] The recess 114 on which the gate structure 110 is formed can extend through the second substrate 303 into the interior of the oxide semiconductor layer 202. That is, the gate structure 110 can be disposed inside the oxide semiconductor layer 302 and the second substrate 303.

[0144] The upper surface 302a of the oxide semiconductor layer 302 may be formed closer to the upper surface 303a of the second substrate 303 than the upper surface 112a of the gate electrode 112. That is, the upper surface 302a of the oxide semiconductor layer 302 may be formed between the upper surface 112a of the gate electrode 112 and the upper surface 303a of the second substrate 303.

[0145] In some example embodiments, the lower portion of the bit line structure 145 may be disposed inside the second substrate 303.

[0146] Below, we will refer to Figure 15 Describes a semiconductor device according to some other example embodiments. Highlights will be given. Figure 2 The differences shown are in the semiconductor devices.

[0147] Figure 15 These are diagrams provided to illustrate semiconductor devices according to some other example embodiments.

[0148] Reference Figure 15 In a semiconductor device according to some other example embodiments, a plurality of gate structures 410 may include a recess 114, a gate insulating film 411, a gate electrode 112 and / or a capping film 413 formed in an oxide semiconductor layer 102 and an isolation film 105.

[0149] Two gate structures 410 can be arranged across an active region ACT on a single active region ACT. The two gate structures 410 can be arranged in a third-direction DR3 ( Figure 1 They are spaced apart from each other. This is on Figure 15 The diagram shows a first gate structure 410_1 and a second gate structure 410_2 spaced apart from each other in the first direction DR1 in the active region ACT.

[0150] The gate insulating film 411 may extend along the sidewalls and bottom surface of the recess 114 to the upper surface 410a of the gate structure 410. The capping film 413 may fill the recess 114 on the gate insulating film 411 and the gate electrode 112.

[0151] Below, we will refer to Figure 16 Describes a semiconductor device according to some other example embodiments. Highlights will be given. Figure 2 The differences shown are in the semiconductor devices.

[0152] Figure 16 These are diagrams provided to illustrate semiconductor devices according to some other example embodiments.

[0153] Reference Figure 16 The semiconductor device according to some other example embodiments may have a capacitor 590 formed in a cylindrical shape.

[0154] For example, the lower electrode 591 of the capacitor 590 may include a sidewall extending in a fourth direction (DR4) of the substrate 100 and a bottom parallel to the upper surface 101a of the first substrate 101. The bottom of the lower electrode 591 may be connected to the sidewall of the lower electrode 591.

[0155] The capacitor insulating film 592 can be disposed on the lower electrode 591. The capacitor insulating film 592 can be disposed along the contour of the lower electrode 591. The capacitor insulating film 592 can be disposed along the outer sidewall and the inner sidewall of the lower electrode 591.

[0156] The upper electrode 593 may be disposed on the capacitor insulating film 592. The upper electrode 593 may surround the outer wall of the lower electrode 591. In addition, a portion of the upper electrode 593 may be disposed between the sidewalls of the lower electrode 591.

[0157] Exemplary embodiments according to the present disclosure have been described above with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to the above-described exemplary embodiments, but can be made in various different forms and can be implemented in other specific forms by those skilled in the art without changing the technical concept or essential characteristics of the present disclosure. Therefore, it will be understood that the above-described exemplary embodiments are merely illustrative and should not be construed as limiting.

Claims

1. A semiconductor device, comprising: First substrate; The active region is defined by an isolation film in the first substrate; An oxide semiconductor layer on the first substrate in the active region and not including silicon, the oxide semiconductor layer including a recess; A gate structure that fills the recess includes a gate electrode and a capping film on the gate electrode, the upper surface of the gate structure being coplanar with the upper surface of the active region, the active region including a portion of the first substrate defined by the isolation film and the oxide semiconductor layer; Bit lines extend in a first direction over the isolation membrane and the active region; Bit line contacts are arranged between the bit line and the oxide semiconductor layer; as well as A wire spacer is disposed on the sidewalls of the bit line contacts and the sidewalls of the bit lines, extends along the thickness direction of the first substrate, and contacts the oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein, The upper surface of the oxide semiconductor layer is on the same plane as the upper surface of the gate structure.

3. The semiconductor device according to claim 1, wherein, The upper surface of the gate electrode is located between the upper surface of the first substrate and the upper surface of the oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein, The upper surface of the first substrate is located between the upper surface of the gate electrode and the upper surface of the oxide semiconductor layer.

5. The semiconductor device according to claim 1, wherein, The recess extends through the oxide semiconductor layer into the interior of the first substrate.

6. The semiconductor device according to claim 1, wherein, The gate structure further includes a gate insulating film, which is located between the inner wall of the recess and the gate electrode along the inner wall of the recess.

7. The semiconductor device according to claim 6, wherein, The gate insulating film is located between the inner wall of the recess and the capping film along the inner wall of the recess.

8. The semiconductor device according to claim 1, wherein, The oxide semiconductor layer includes indium gallium zinc oxide.

9. A semiconductor device, comprising: Substrate; The active region is defined by an isolation film in the substrate; A gate structure is provided in the isolation film and the active region, and has an upper surface that is coplanar with the upper surface of the active region. An oxide semiconductor layer, which contacts at least a portion of the sidewall of the gate structure in the active region, and does not include silicon, the active region comprising a portion of the substrate defined by the isolation film and the oxide semiconductor layer; A capacitor, which is electrically connected to the active region and extends in the thickness direction of the substrate, Bit lines extend in a first direction over the isolation membrane and the active region; Bit line contacts are arranged between the bit line and the oxide semiconductor layer; as well as A wire spacer is disposed on the sidewalls of the bit line contacts and the sidewalls of the bit lines, extends along the thickness direction of the substrate, and contacts the oxide semiconductor layer.

10. The semiconductor device according to claim 9, wherein, The gate structure in the active region is inside the oxide semiconductor layer.

11. The semiconductor device according to claim 9, wherein, The gate structure in the active region is located within the substrate and the oxide semiconductor layer.

12. The semiconductor device according to claim 9, wherein, The capacitor includes a lower electrode, a capacitor insulating film on the lower electrode, and an upper electrode on the capacitor insulating film. The lower electrode has a columnar shape.

13. The semiconductor device according to claim 9, wherein, The capacitor includes a lower electrode, a capacitor insulating film on the lower electrode, and an upper electrode on the capacitor insulating film. The lower electrode has a cylindrical shape.

14. A semiconductor device, comprising: Substrate; An active region, defined by an isolation film in the substrate, and extending in a first direction; An oxide semiconductor layer extending in the first direction on the substrate in the active region, and excluding silicon; The word line extends in the isolation membrane and the active region in a second direction different from the first direction; Bit lines extend upward on the isolation membrane and the active region in a third direction different from the first and second directions. Bit line contacts are arranged between the bit line and the oxide semiconductor layer; as well as A wire spacer, disposed on the sidewalls of the bit line contacts and the sidewalls of the bit lines, extends along the thickness direction of the substrate and contacts the oxide semiconductor layer. The upper surface of the oxide semiconductor layer is on the same plane as the upper surface of the active region, and the active region includes the portion of the substrate defined by the isolation film and the oxide semiconductor layer.

15. The semiconductor device of claim 14, further comprising: The sealing film is on the upper surface of the letter lines. The upper surface of the sealing film and the upper surface of the active region are on the same plane.

16. The semiconductor device according to claim 14, wherein, The upper surface of the word line is located between the upper surface of the substrate and the upper surface of the oxide semiconductor layer.

17. The semiconductor device according to claim 14, wherein, The oxide semiconductor layer includes indium gallium zinc oxide.

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