Magnetic storage devices

Abstract

The magnetic memory device may include: a magnetic tunnel junction pattern on a substrate; a wire extending between the substrate and the magnetic tunnel junction pattern and contacting the bottom surface of the magnetic tunnel junction pattern; and a bottom pattern located between the wire and the substrate and contacting the bottom surface of the wire. The material of the wire may have a first lattice constant, and the material of the bottom pattern may have a second lattice constant less than the first lattice constant of the wire. Alternatively or additionally, the bottom pattern includes a metal nitride, and the nitrogen content of the bottom pattern is higher than the metal element content of the bottom pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0142748 filed in the Korean Intellectual Property Office on November 19, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor devices, and more particularly, to a magnetic memory device including a magnetic tunnel junction. Background Art

[0004] The magnetic memory device can work as a high-speed and / or low-voltage semiconductor memory device, which can be included in a high-speed and / or low-power electronic device. The magnetic memory device may include a magnetic tunnel junction (MTJ). The magnetic tunnel junction may include two magnetic layers and an insulating layer located between the two magnetic layers. The resistance value of the magnetic tunnel junction may be changed according to the magnetization directions of the two magnetic layers. For example, if the magnetization directions of the two magnetic layers are oriented antiparallel to each other, the magnetic tunnel junction may have a relatively high resistance value. If the magnetization directions of the two magnetic layers are oriented parallel to each other, the magnetic tunnel junction may have a relatively low resistance value. The magnetic memory device may facilitate read / write operations based on the difference in resistance values ​​of the magnetic tunnel junction. Summary of the invention

[0005] In some example embodiments, a magnetic memory device may include: a magnetic tunnel junction pattern on a substrate; a conductive line extending between the substrate and the magnetic tunnel junction pattern and contacting a bottom surface of the magnetic tunnel junction pattern, the conductive line having a first lattice constant; and a bottom pattern located between the conductive line and the substrate and contacting a bottom surface of the conductive line, the bottom pattern having a second lattice constant smaller than the first lattice constant of the conductive line.

[0006] In some example embodiments, a magnetic memory device may include: a magnetic tunnel junction pattern on a substrate; a conductive line extending between the substrate and the magnetic tunnel junction pattern and contacting a bottom surface of the magnetic tunnel junction pattern; and a bottom pattern located between the conductive line and the substrate, wherein the bottom pattern is in contact with the bottom surface of the conductive line, wherein the bottom pattern includes a metal nitride, and wherein a nitrogen content of the bottom pattern is higher than a metal element content of the bottom pattern.

[0007] Some example embodiments of some inventive concepts may provide a magnetic memory device in which a switching property is improved due to improved efficiency of a spin orbit torque. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1is a plan view illustrating a magnetic memory device according to some example embodiments of some inventive concepts.

[0009] Figure 2 is along Figure 1 A cross-sectional view taken along line AA′ or line BB′.

[0010] Figure 3 and Figure 4 According to some example embodiments of some inventive concepts Figure 2 Magnified view of region 'AQ'.

[0011] Figures 5 to 8 According to some example embodiments of some inventive concepts Figure 2 FIG. 1 is an enlarged view of area 'AQ', which is used to illustrate the bottom pattern.

[0012] Fig. 9 , Fig.11 and Fig.13 is a plan view illustrating a method of manufacturing a magnetic memory device according to some example embodiments of some inventive concepts.

[0013] Fig.10 , Fig.12 and Fig.14 According to some exemplary embodiments of some inventive concepts, Fig. 9 , Fig.11 and Fig.13 A cross-sectional view taken along line AA′ or line BB′. DETAILED DESCRIPTION

[0014] Figure 1 is a plan view illustrating a magnetic memory device according to some example embodiments of some inventive concepts. Figure 2 is along Figure 1 A cross-sectional view taken along line AA′ or line BB′. Figure 3 and Figure 4 According to some example embodiments of some inventive concepts Figure 2 Magnified view of region 'AQ'.

[0015] refer to Figures 1 to 3 , the magnetic tunnel junction pattern MTJ may be disposed on a substrate 100. The substrate 100 may include a semiconductor substrate. For example, the semiconductor substrate may include silicon (Si), silicon on insulator (SOI), silicon germanium (SiGe), germanium (Ge), or gallium-arsenic (GaAs). The substrate 100 may include a selection element formed on the semiconductor substrate. The selection element may be electrically connected to the magnetic tunnel junction pattern MTJ. The selection element may be a field effect transistor or a diode.

[0016] As described herein, a magnetic tunnel junction pattern MTJ may be disposed on a substrate 100. For example, the magnetic tunnel junction pattern MTJ may be located in an upper interlayer insulating layer 170. The upper interlayer insulating layer 170 may cover a sidewall of the magnetic tunnel junction pattern MTJ. The upper interlayer insulating layer 170 may include at least one of an oxide, a nitride, or an oxynitride.

[0017] In some example embodiments, the magnetic tunnel junction pattern MTJ may be two-dimensionally arranged on the substrate 100. For example, the magnetic tunnel junction pattern MTJ may be arranged along the first direction D1 and / or the third direction D3. The first direction D1 and the third direction D3 may represent axes oriented parallel to the top surface of the substrate 100 and may intersect each other, such as a horizontal axis and / or a vertical axis in a plan view of the substrate 100. As used herein, a "height axis" refers to an axis substantially perpendicular to the top surface of the substrate 100, such as Figure 1 The second direction D2 in the.

[0018] In some example embodiments, one or more magnetic tunnel junction patterns MTJ may include a group of layers sequentially stacked along a height axis, wherein the group of layers includes a first magnetic pattern MP1, a tunnel barrier pattern TBP, and / or a second magnetic pattern MP2. The tunnel barrier pattern 220 may be disposed between the first magnetic pattern MP1 and the second magnetic pattern MP2. For example, the tunnel barrier pattern TBP may include at least one of a magnesium oxide (MgO) layer, a titanium oxide (TiO) layer, an aluminum oxide (AlO) layer, a magnesium oxide-zinc (MgZnO) layer, or a magnesium oxide-boron (MgBO) layer. The first magnetic pattern MP1 and / or the second magnetic pattern MP2 may include at least one magnetic layer. Reference may be made to Figure 3 and Figure 4 To understand the magnetic tunnel junction pattern MTJ.

[0019] In some example embodiments, the electrode patterns 160 may be respectively located on the magnetic tunnel junction patterns MTJ. The first magnetic pattern MP1 may be located between the substrate 100 and the tunnel barrier pattern TBP, and / or the second magnetic pattern MP2 may be located between the tunnel barrier pattern TBP and each electrode pattern 160. For example, the electrode pattern 160 may include at least one of a metal (e.g., Ta, W, Ru, or Ir) or a conductive metal nitride (e.g., TiN).

[0020] In some example embodiments, the upper conductive wire 200 may be located on the upper interlayer insulating layer 170. The upper conductive wire 200 may be connected to the magnetic tunnel junction pattern MTJ. Each upper conductive wire 200 may be electrically connected to a corresponding magnetic tunnel junction pattern MTJ through a corresponding electrode pattern 160. For example, the upper conductive wire 200 may extend in the third direction D3 and / or may be spaced apart from each other in the first direction D1. The upper conductive wire 200 may include at least one of a metal (e.g., copper) or a conductive metal nitride. The upper conductive wire 200 may be used as a bit line.

[0021] In some example embodiments, the wire SOL may be located between the substrate 100 and the magnetic tunnel junction pattern MTJ. A plurality of wires SOL may be provided, wherein each of the plurality of wires SOL may extend in the first direction D1 and / or may be connected to the bottom surface of the plurality of magnetic tunnel junction patterns MTJ. For example, the top surface of the wire SOL may contact the bottom surface of the first magnetic pattern MP1. The wire SOL may be located in the lower interlayer insulating layer 110. The lower interlayer insulating layer 110 may include at least one of an oxide, a nitride, or an oxynitride. The wires SOL may be insulated from each other by the lower interlayer insulating layer 110.

[0022] In some example embodiments, the bottom pattern BOL may be located between the conductor SOL and the substrate 100. In some example embodiments, a plurality of bottom patterns BOL may be provided, wherein each bottom pattern BOL may be disposed below the conductor SOL. For example, a group of bottom patterns BOL may be formed together with the conductor SOL (e.g., by the same patterning process), and / or the sidewalls of the bottom pattern BOL may be aligned with the sidewalls of the corresponding conductor SOL. In some example embodiments, the bottom pattern BOL may have a substantially similar planar shape to the conductor SOL. Alternatively, some example embodiments of the present invention are not limited thereto. For example, in some other example embodiments, the width and / or length of the bottom pattern BOL may be different from the width and / or length of the corresponding conductor SOL observed in the plan view.

[0023] You can refer to Figure 3 and Figure 4Understand the wire SOL and the bottom pattern BOL. In some example embodiments, the wire SOL may be configured to apply a spin-orbit torque to the magnetic tunnel junction pattern MTJ connected thereto. For example, a current J may flow through the wire SOL. The current J may be an in-plane current flowing through the wire SOL. The wire SOL may be configured to have a strong spin-orbit interaction. The current J flowing through the wire SOL may cause an accumulation of spin-polarized charge carriers (e.g., electrons) near the magnetic tunnel junction pattern MTJ through the spin-orbit interaction in the wire SOL. A spin-orbit field may be generated by the accumulated charge carriers. The spin-orbit field may be in the plane of the wire SOL and / or may be perpendicular to the direction of the in-plane current J flowing through the wire SOL. For example, the in-plane current J may flow in the wire SOL along a first direction D1, and / or the spin-orbit field may be parallel to a third direction D3. The spin-orbit field generated in the wire SOL may apply a spin-orbit torque to the magnetic tunnel junction pattern MTJ. Each magnetic tunnel junction pattern MTJ may be configured such that a magnetization direction of a free layer in each magnetic tunnel junction pattern MTJ is switched using a spin-orbit torque.

[0024] In some example embodiments, the wire SOL may include a heavy metal or a material doped with a heavy metal. For example, the wire SOL may include at least one of 'A' or 'M' doped with 'B'. In some example embodiments, 'A' may include yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), cadmium (Cd), indium (In), antimony (Sb), tellurium (Te), hafnium (Hf), tantalum (Ta, including high-resistance amorphous β-Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), mercury (Hg), thallium (T1), lead (Pb), bismuth (Bi), polonium (Po), astatine (At), and / or any combination thereof. In some example embodiments, 'B' may include vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), phosphorus (P), sulfur (S), zinc (Zn), gallium (Ga), germanium (Ge), arsenic (As), selenium (Se), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), cadmium (Cd), indium (In), antimony (Sb), tellurium (Te), iodine (I), lutetium (Tc), ruthenium (Ru), tantalum (Th), tantalum (Tc ...c), tantalum (Tc), tantalum (Tc), tantalum (Tc), tantalum (Tc), tantalum (Tc), tantalum (Tc), tantalum (Tc), tantalum (Tc), tantalum (Tc), tantalum (Tc), tantalum (Tc), tantalum (Tc), tantalum (Tc), tantalum (Tc), tantalum (Tc), tantalum (Tc), tanta At least one of tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), mercury (Hg), thallium (Tl), lead (Pb), bismuth (Bi), polonium (Po), astatine (At), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm) and ytterbium (Yb). In some example embodiments, 'M' may include at least one of aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), copper (Cu), zinc (Zn), silver (Ag), hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), platinum (Pt), gold (Au), mercury (Hg), lead (Pb), silicon (Si), gallium (Ga), gallium-manganese (GaMn), or gallium-arsenic (GaAs). For example, the conductive line SOL may include copper (Cu) doped with iridium (Ir) and / or copper (Cu) doped with bismuth (Bi).

[0025] Reference Figure 4 According to some example embodiments, the conductive line SOL may include a first conductive pattern 151 and a second conductive pattern 152 on the first conductive pattern 151. For example, the first conductive pattern 151 may be a magnetic layer, and the second conductive pattern 152 may be a non-magnetic layer.

[0026] In some example embodiments, a portion of the in-plane current J flowing through the conductive line SOL may be spin-polarized by the first conductive pattern 151. For example, the charge carriers (e.g., electrons) in the first conductive pattern 151 may be spin-polarized along the magnetic moment direction of the first conductive pattern 151. The spin-polarized charge carriers may flow from the first conductive pattern 151 into the second conductive pattern 152, and / or may accumulate in the second conductive pattern 152 near the magnetic tunnel junction pattern MTJ. By the accumulation of spin-polarized charge carriers, a spin-orbit torque may be applied to the magnetic tunnel junction pattern MTJ. Each magnetic tunnel junction pattern MTJ may be configured such that: the magnetization direction of the free layer in each magnetic tunnel junction pattern MTJ is switched using a spin-orbit torque.

[0027] In some example embodiments, the first conductive pattern 151 may include at least one of iron (Fe), cobalt (Co), or nickel (Ni), and / or may include at least one of platinum (Pt), palladium (Pd), manganese (Mn), yttrium (Y), chromium (Cr), ruthenium (Ru), rhodium (Rh), tungsten (W), tantalum (Ta), boron (B), bismuth (Bi), iridium (Ir), lead (Pb), nitrogen (N), or oxygen (O). The second conductive pattern 152 may include at least one of copper (Cu), silver (Ag), gold (Au), tantalum (Ta), tungsten (W), or nitrogen (N). The materials of the first conductive pattern 151 and the second conductive pattern 152 are not limited to the materials described herein.

[0028] In some example embodiments, the top surface of the bottom pattern BOL may contact the bottom surface of the conductive wire SOL. In some example embodiments, the bottom pattern BOL may apply compressive stress to the conductive wire SOL. For example, the material of the conductive wire SOL may have a first lattice constant, and the material of the bottom pattern BOL may have a second lattice constant, and the second lattice constant may be smaller than the first lattice constant of the material of the conductive wire SOL. In other words, the conductive wire SOL may be formed using a first lattice constant that is smaller than the intrinsic lattice constant of the material of the conductive wire SOL.

[0029] Grain density can be defined as the number of grains per unit area. Compared with an alternative semiconductor device in which the bottom pattern BOL is not present, the grain size of the conductor SOL can be reduced by the bottom pattern BOL. In other words, the bottom pattern BOL can increase the grain density of the conductor SOL. A structure that exhibits an increased grain density of the conductor SOL can also exhibit an increased resistivity of the conductor SOL.

[0030] In some example embodiments, the grain density of the top surface of the bottom pattern BOL may be equal to that of the bottom surface of the bottom pattern BOL. In some other example embodiments, the grain density of the top surface of the bottom pattern BOL may be greater than that of the bottom surface of the bottom pattern BOL.

[0031] In some example embodiments, the grain density of the top surface of the conductive line SOL may be equal to the grain density of the bottom surface of the conductive line SOL. In some other example embodiments, the grain density of the top surface of the conductive line SOL may be different from the grain density of the bottom surface of the conductive line SOL.

[0032] In some example embodiments, the grain density of the bottom surface of the conductive line SOL in contact with the bottom pattern BOL may be greater than the grain density of the top surface of the conductive line SOL. For example, the grain density of the conductive line SOL may gradually decrease from the bottom surface to the top surface of the conductive line SOL. That is, the grain density at a vertical position within the conductive line SOL may be inversely proportional to the distance between the vertical position and the bottom surface of the conductive line SOL in contact with the bottom pattern BOL.

[0033] In some example embodiments, a reduction in the lattice constant of the wire SOL and / or a change in the grain size of the wire SOL may increase the efficiency of the spin-orbit torque applied by the wire SOL to the magnetic tunnel junction pattern MTJ. In some example embodiments, even if the same current J flows through the wire SOL, such spin-orbit torque may be increased, which may improve the switching efficiency of a memory element such as the magnetic tunnel junction pattern MTJ.

[0034] In some example embodiments, the thickness T2 of the bottom pattern BOL along the height axis may be less than the thickness T1 of the conductive wire SOL along the height axis. For example, the thickness T1 of the conductive wire SOL along the height axis may range from about 2 times to about 5 times the thickness T2 of the bottom pattern BOL along the height axis. For example, the thickness T1 of the conductive wire SOL along the height axis may range from about 300 angstroms to about 700 angstroms. For example, the thickness T2 of the bottom pattern BOL along the height axis may range from about 80 angstroms to about 300 angstroms. However, in some other example embodiments, the thickness T1 of the conductive wire SOL along the height axis may be similar to or less than the thickness T2 of the bottom pattern BOL along the height axis.

[0035] In some example embodiments, the bottom pattern BOL may be a non-magnetic layer. For example, the bottom pattern BOL may be formed of a material having a resistivity greater than that of the wire SOL. Therefore, the current flowing under the magnetic tunnel junction pattern MTJ may selectively flow through the wire SOL. As a result, the bottom pattern BOL may not affect (e.g., reduce) the spin-orbit torque generated by the wire SOL.

[0036] In some example embodiments, the bottom pattern BOL may include a metal nitride, such as TiN, TaN, or WN. In some example embodiments in which the bottom pattern BOL is formed of a metal nitride, the bottom pattern BOL may be formed of a nitrogen-rich metal nitride in which the nitrogen content is higher than the metal element content. As used herein, "content" may be measured as, for example, atomic percentage, atomic density, molar concentration, number concentration, and / or volume concentration, as well as other measurements that can be understood by a person of ordinary skill in the art. In some example embodiments, the ratio of the nitrogen content in the bottom pattern BOL to the metal element content in the bottom pattern BOL may be substantially between 1.0 and 1.3. For example, a nitrogen-rich metal nitride may be formed by adjusting the source supply time and / or the cycle of the deposition process. In some example embodiments, a compressive stress may be generated in the bottom pattern BOL formed of a nitrogen-rich metal nitride compared to a metal-rich metal nitride. In some example embodiments, a compressive stress may be applied in the conductor SOL during the formation of the conductor SOL by the compressive stress in the bottom pattern BOL. Therefore, the grain density of the conductor SOL may be increased.

[0037] Reference again Figure 3 and Figure 4 , the first magnetic pattern MP1 may be located between the conductive line SOL and the tunnel barrier pattern TBP, and / or the second magnetic pattern MP2 may be located between each electrode pattern 160 and the tunnel barrier pattern TBP. The second magnetic pattern MP2 may be utilized and / or configured to operate as a reference layer having a magnetization direction M2 fixed in one direction, and the first magnetic pattern MP1 may be utilized and / or configured to operate as a free layer whose magnetization direction M1 may become parallel or antiparallel to the magnetization direction M2 of the reference layer. Figure 3 and Figure 4 Some example embodiments are shown, in which the first magnetic pattern MP1 can be utilized and / or configured to operate as a free layer and the second magnetic pattern MP2 can be utilized as a reference layer. Alternatively, some example embodiments of the present inventive concept are not limited thereto. For example, in some other example embodiments and with Figure 3 and Figure 4 Differently, the first magnetic pattern MP1 may be utilized and / or configured to operate as a reference layer, and the second magnetic pattern MP2 may be utilized and / or configured to operate as a free layer.

[0038] In some example embodiments, Figure 3 As shown, the magnetization directions M1 and M2 may be oriented along the height axis to form a perpendicular magnetic structure, and / or may form an interface between the tunnel barrier pattern TBP and the first magnetic pattern MP1. The reference layer and / or the free layer may include a perpendicular magnetic material (e.g., CoFeTb, CoFeGd, or CoFeDy), a L10 At least one of a perpendicular magnetic material having a structure, a CoPt alloy having a hexagonal close-packed (HCP) lattice structure and / or a perpendicular magnetic structure. 0 The vertical magnetic materials of the structure may include (but are not limited to) one or more of the following: 0 FePt with L1 0 FePd with L1 0 CoPd of the structure and / or with L1 0 The vertical magnetic structure may include magnetic layers and non-magnetic layers alternately and repeatedly stacked along the height axis. For example, the vertical magnetic structure may include (but is not limited to) one or more of the following: (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n and / or (CoCr / Pd)n, where "n" represents the number of double layers.

[0039] In some example embodiments, the thickness of the reference layer along the height axis may be greater than the thickness of the free layer along the height axis. In some other example embodiments, the thickness of the reference layer along the height axis may be similar to or less than the thickness of the free layer along the height axis.

[0040] In some example embodiments, the coercivity of the reference layer may be greater than the coercivity of the free layer. In some other example embodiments, the coercivity of the reference layer may be similar to or less than the coercivity of the free layer.

[0041] In some example embodiments, for example Figure 4 As shown in FIG. 1 , the magnetization directions M1 and M2 may be substantially parallel to the interface between the tunnel barrier pattern TBP and the first magnetic pattern MP1. For example, the reference layer and / or the free layer may include a ferromagnetic material. In some example embodiments, the reference layer may further include an antiferromagnetic material for fixing or pinning the magnetization direction of the ferromagnetic material. However, some example embodiments are not limited to Figure 3 and Figure 4 Such magnetization directions M1 and M2 and / or structures as described in the above. For example, in some other exemplary embodiments, Figure 3 The magnetization directions M1 and M2 can be related to Figure 4 The magnetization directions M1 and M2 are exchanged.

[0042] As reference Figure 2 , Figure 3 and Figure 4As described, the wire SOL can be configured to apply a spin-orbit torque to the magnetic tunnel junction pattern MTJ. The spin-orbit torque can be used to switch the magnetization direction of the free layer in each magnetic tunnel junction pattern MTJ. According to some example embodiments of some inventive concepts, a switching operation (e.g., a write operation) of the magnetic tunnel junction pattern MTJ can be performed based on the spin-orbit torque. A read operation of the magnetic tunnel junction pattern MTJ can be performed by a method similar to that of a spin transfer torque memory. For example, the read current Jr can be Figure 3 and Figure 4 The upper conductive line 200 flows in a direction perpendicular to the surface (or plane) of the magnetic tunnel junction pattern MTJ. The resistance state of the magnetic tunnel junction pattern MTJ can be detected by reading the current Jr. For example, the magnetic tunnel junction pattern MTJ can be detected by reading the current Jr to determine whether it is in a high resistance state or a low resistance state.

[0043] According to some embodiments of some inventive concepts, the efficiency of the spin-orbit torque applied to the magnetic tunnel junction pattern through the conductive line can be increased by the bottom pattern. Therefore, the switching efficiency of the memory element (eg, the magnetic tunnel junction pattern MTJ) can be improved.

[0044] Figures 5 to 8 According to some example embodiments of some inventive concepts Figure 2 FIG. 1 is an enlarged view of area 'AQ', which is used to illustrate the bottom pattern.

[0045] like Figure 5 and Figure 6 As shown in , the bottom pattern BOL may be composed of multiple layers. In some example embodiments, as Figure 5 As shown, the bottom pattern BOL may include a first bottom pattern SL1 and a second bottom pattern SL2 below the first bottom pattern SL1. The first bottom pattern SL1 may be a metal nitride layer, and / or the second bottom pattern SL2 may be a metal layer. For example, the first bottom pattern SL1 may be a TiN layer, a TaN layer, or a WN layer, and / or the second bottom pattern SL2 may be a Ti layer, a Ta layer, or a W layer. Alternatively, the second bottom pattern SL2 may be a silicon nitride layer.

[0046] In some example embodiments, the first bottom pattern SL1 may be thicker along the height axis than the second bottom pattern SL2 along the height axis. For example, the thickness of the first bottom pattern SL1 along the height axis may range from about 1.5 times to about 5 times the thickness of the second bottom pattern SL2 along the height axis. For example, the thickness of the first bottom pattern SL1 along the height axis may range from about 80 angstroms to about 150 angstroms, and / or the thickness of the second bottom pattern SL2 along the height axis may range from about 30 angstroms to about 80 angstroms. Alternatively, if the second bottom pattern SL2 is a silicon nitride layer, the thickness of the second bottom pattern SL2 along the height axis may range from about 2 times to about 5 times the thickness of the first bottom pattern SL1 along the height axis.

[0047] In some example embodiments, the bottom pattern BOL may include a first bottom pattern SL1 such as Figure 5 In some example embodiments, the bottom pattern BOL may include a second bottom pattern SL2 below the first bottom pattern SL1, which may be a metal layer such as a Ti layer, a Ta layer, and / or a W layer. In some example embodiments, for example Figure 6 As shown, the bottom pattern BOL may include a third bottom pattern SL3 below the second bottom pattern SL2. For example, the third bottom pattern SL3 may be Figures 9 to 14 A layer used as an etch stop layer in the described manufacturing method. For example, the third bottom pattern SL3 may include a silicon nitride-based material, such as SiN, SiON, SiCN, and / or SiOCN.

[0048] In some example embodiments, the thickness of the first bottom pattern SL1 along the height axis may be greater than the thickness of the second bottom pattern SL2 along the height axis. In some other example embodiments, the thickness of the first bottom pattern SL1 along the height axis may be substantially similar to the thickness of the second bottom pattern SL2 along the height axis.

[0049] In some example embodiments, the thickness of the third bottom pattern SL3 along the height axis may be greater than the thickness of the first bottom pattern SL1 and / or the second bottom pattern SL2 along the height axis. In some other example embodiments, the thickness of the third bottom pattern SL3 along the height axis may be substantially similar to the thickness of the first bottom pattern SL1 and / or the second bottom pattern SL2 along the height axis.

[0050] In some example embodiments (including Figure 5 and Figure 6 In the embodiment shown in ), the semiconductor device may include a bottom pattern BOL having sidewalls (e.g., sidewalls of the first bottom pattern SL1, the second bottom pattern SL2, and / or the third bottom pattern SL3) that may be substantially aligned with one or more corresponding sidewalls of the conductive line SOL along the height axis. For example, and as Figure 7 and Figure 8 As shown, the semiconductor device may include a bottom pattern BOL having a stepped shape (e.g., a stepped structure ST, which extends beyond the sidewall of the conductive line SOL along the lateral axis and / or protrudes relative to the sidewall of the conductive line SOL). For example, after the second bottom pattern SL2 and / or the third bottom pattern SL3 are used as an etching stop layer, the stepped structure ST may be the remaining shape of the second bottom pattern SL2 and / or the third bottom pattern SL3. In some example embodiments, the second bottom pattern SL2 or the third bottom pattern SL3 may extend along the lateral axis (e.g., in the direction D1) relative to the substrate 100 between the magnetic tunnel junction patterns MTJ adjacent to each other in the third direction D3. In other words, in some example embodiments, the stepped structure ST of the second bottom pattern SL2 and / or the third bottom pattern SL3 may have a plate shape, and / or may cover the substrate 100 along the lateral axis (e.g., in the direction D1) between the magnetic tunnel junction patterns MTJ arranged two-dimensionally along another lateral axis (e.g., direction D3). In some example embodiments, the stepped structure ST of the second bottom pattern SL2 and / or the third bottom pattern SL3 may extend along the lateral axis (e.g., in the direction D1) between the conductive lines SOL onto the substrate 100. In some example embodiments, the sidewalls of the bottom pattern BOL may not be substantially aligned with the sidewalls of the conductive lines SOL along the height axis.

[0051] Fig. 9 , Fig.11 and Fig.13 is a plan view illustrating an example method of manufacturing a magnetic memory device according to some example embodiments of some inventive concepts. Fig.10 , Fig.12 and Fig.14 Along Fig. 9 , Fig.11 and Fig.13 In the following, for the convenience of explanation, the cross-sectional view taken along the line AA′ or the line BB′ is omitted. Figures 1 to 8 Some parts of the description of similar features shown in .

[0052] In some example embodiments (including Fig. 9 and Fig.10 In the embodiment shown in ), the bottom layer 125 and the conductive layer 135 may be sequentially formed on the substrate 100. For example, the substrate 100 may include a semiconductor substrate and a selection element formed on the semiconductor substrate. In some example embodiments, the bottom layer 125 and / or the conductive layer 135 may be formed by various manufacturing processes (including (but not limited to) a sputtering process, a chemical vapor deposition (CVD) process, and / or an atomic layer deposition (ALD) process). In some example embodiments, the material and thickness of the bottom layer 125 and / or the conductive layer 135 may be similar to those of the reference 1. Figures 1 to 8The material and thickness of the bottom pattern BOL and / or the conductive line SOL described above. In some example embodiments, the thickness of the bottom layer 125 along the height axis may be greater than the thickness of the conductive layer 135 along the height axis. In some other example embodiments, the thickness of the bottom layer 125 along the height axis may be similar to the thickness of the conductive layer 135 along the height axis. In some example embodiments, the bottom layer 125 may apply compressive stress in the conductive layer 135 during the formation of the conductive layer 135.

[0053] In some example embodiments (including Fig.11 and Fig.12 In the embodiment shown in ), the bottom layer 125 and the conductive layer 135 may be patterned to form a bottom pattern BOL and a conductive line SOL, respectively. For example, the patterning process of the bottom layer 125 and / or the conductive layer 135 may include: forming a mask pattern on the conductive layer 135, and / or performing a dry etching process and / or a wet etching process by using the mask pattern as an etching mask. As a result of the etching process, the sidewall of the bottom pattern BOL may be aligned with the sidewall of the conductive line SOL relative to the height axis. In some example embodiments (including Figure 7 and Figure 8 In the embodiment shown in ), a portion of the bottom pattern BOL may be used as an etch stop layer, and / or a step structure may be formed at the sidewall of the bottom pattern BOL. In some other example embodiments, the sidewall of the bottom pattern BOL may not be aligned with the sidewall of the conductive line SOL with respect to the height axis.

[0054] In some example embodiments, a lower interlayer insulating layer 110 may be formed to cover the wire SOL relative to the lateral axis. A planarization process may be performed on the lower interlayer insulating layer 110 to expose the top surface of the wire SOL; that is, after planarization, the lower interlayer insulating layer 110 may not cover at least a portion of the top surface of the wire SOL. A magnetic tunnel junction layer MTJL may be formed to cover the wire SOL relative to the lateral axis. The magnetic tunnel junction layer MTJL may include a first magnetic layer ML1, a tunnel barrier layer TBL, and a second magnetic layer ML2 sequentially stacked along the height axis. Each of the first magnetic layer ML1 and the second magnetic layer ML2 may include at least one magnetic layer. The tunnel barrier layer TBL may include, but is not limited to, one or more of the following: a magnesium oxide (MgO) layer, a titanium oxide (TiO) layer, an aluminum oxide (AlO) layer, a magnesium oxide-zinc (MgZnO) layer, and / or a magnesium oxide-boron (MgBO) layer. In some example embodiments, the first magnetic layer ML1, the tunnel barrier layer TBL, and / or the second magnetic layer ML2 may be formed by a sputtering process or a CVD process. Alternatively, one of ordinary skill in the art may identify many manufacturing processes that may be used to form the first magnetic layer ML1 , the tunnel barrier layer TBL, and / or the second magnetic layer ML2 .

[0055] A conductive mask pattern 165 may be formed on the magnetic tunnel junction layer MTJL, wherein the conductive mask pattern 165 may define a region where a magnetic tunnel junction pattern is to be formed. In some example embodiments, the conductive mask pattern 165 may include, but is not limited to, one or more metals (e.g., Ta, W, Ru, or Ir) and / or one or more conductive metal nitrides (e.g., TiN).

[0056] In some example embodiments (including Fig.13 and Fig.14 In the embodiment shown in ), the magnetic tunnel junction layer MTJL may be etched to form magnetic tunnel junction patterns MTJ, wherein each magnetic tunnel junction pattern MTJ may include a first magnetic pattern MP1, a tunnel barrier pattern TBP, and a second magnetic pattern MP2 that may be sequentially stacked on the conductive line SOL along the height axis. In some example embodiments, the first magnetic pattern MP1 and the second magnetic pattern MP2 may be spaced apart from each other along the lateral axis, wherein the tunnel barrier pattern TBP is interposed between the first magnetic pattern MP1 and the second magnetic pattern MP2. That is, some example embodiments may include a first conductive line and a second conductive line, and the lowest layer of the bottom pattern may extend onto the substrate between the first conductive line and the second conductive line.

[0057] In some example embodiments, the magnetic tunnel junction layer MTJL may be etched by, for example, an ion beam etching process, which may include irradiating an ion beam onto the substrate 100, wherein the ion beam may include inert ions (eg, positive argon ions) (Ar + )). For example, the ion beam may be irradiated obliquely relative to the top surface of the substrate 100. In some example embodiments, during the ion beam etching process, the substrate 100 may be rotated by using the height axis as the rotation axis. A portion of the top surface of the conductive line SOL may be recessed toward the substrate 100 by the ion beam etching process. In some example embodiments, the ion beam etching process may use the conductive mask pattern 165 as an etching mask, so that one or more residual portions of the conductive mask pattern 165 may remain on the one or more magnetic tunnel junction patterns MTJ and form the one or more magnetic tunnel junction patterns MTJ, respectively. The remaining portion of the conductive mask pattern 165 may be used as the electrode pattern 160.

[0058] In some example embodiments (including Figure 1 and Figure 2In the embodiment shown in ), the upper interlayer insulating layer 170 may be formed on the lower interlayer insulating layer 110 with respect to the height axis, and / or may cover at least a portion of the magnetic tunnel junction pattern MTJ and the electrode pattern 160 with respect to the height axis. In some example embodiments, the upper interlayer insulating layer 170 may cover at least a portion of at least one sidewall of the magnetic tunnel junction pattern MTJ and / or the electrode pattern 160. In some example embodiments, the upper conductive line 200 may be formed on the upper interlayer insulating layer 170 with respect to the height axis. Each upper conductive line 200 may be electrically connected to a corresponding one of the magnetic tunnel junction patterns MTJ through a corresponding one of the electrode patterns 160.

[0059] Although some inventive concepts have been described with reference to some example embodiments, it will be appreciated by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of some inventive concepts included in some example embodiments. The example embodiments given herein are not intended to be restrictive, but illustrative. Therefore, the scope, variation and / or range of the example embodiments covered by this application will be determined by the broadest permissible interpretation of the attached claims and their equivalents, and should not be restricted or limited by the foregoing description.

Claims

1. A magnetic storage device, comprising: a magnetic tunnel junction pattern on a substrate; a conductive line extending between the substrate and the magnetic tunnel junction pattern and contacting a bottom surface of the magnetic tunnel junction pattern, wherein the conductive line has a first lattice constant; and a bottom pattern located between the conductive line and the substrate and in contact with a bottom surface of the conductive line, wherein the bottom pattern has a second lattice constant that is smaller than a first lattice constant of the conductive line, Wherein, the grain density of the bottom surface of the conductive line is greater than the grain density of the top surface of the conductive line.

2. The magnetic memory device according to claim 1, wherein: A sidewall of the bottom pattern is aligned with a sidewall of the conductive line with respect to a height axis.

3. The magnetic memory device according to claim 1, wherein: A thickness of the bottom pattern along a height axis is smaller than a thickness of the conductive line along the height axis.

4. The magnetic memory device according to claim 3, wherein: A thickness of the conductive line along the height axis is at least twice a thickness of the bottom pattern along the height axis.

5. The magnetic memory device according to claim 1, wherein: The resistivity of the bottom pattern is greater than the resistivity of the conductive line.

6. The magnetic memory device according to claim 1, wherein: The bottom pattern includes metal nitride.

7. The magnetic memory device according to claim 6, wherein: The nitrogen content of the bottom pattern is higher than the metal element content of the bottom pattern.

8. The magnetic memory device according to claim 1, wherein: The bottom pattern includes: a first bottom pattern; and A second bottom pattern is below the first bottom pattern.

9. The magnetic memory device according to claim 8, wherein: The first bottom pattern is a metal nitride layer, and The second bottom pattern is a metal layer.

10. The magnetic memory device according to claim 9, wherein: A thickness of the second bottom pattern along a height axis is smaller than a thickness of the first bottom pattern along the height axis.

11. The magnetic memory device according to claim 8, wherein: The bottom pattern includes a third bottom pattern below the second bottom pattern.

12. The magnetic memory device according to claim 11, wherein: A thickness of the third bottom pattern along a height axis is greater than a thickness of the first bottom pattern along the height axis.

13. The magnetic memory device according to claim 11, wherein: The third bottom pattern includes a sidewall having a stepped shape.

14. The magnetic memory device according to claim 1, wherein: The conductive line is configured to apply a spin-orbit torque to the magnetic tunnel junction pattern.

15. The magnetic memory device according to claim 1, wherein The magnetic tunnel junction pattern includes a group of layers sequentially stacked along a height axis, wherein the group of layers includes: Free layer; Tunnel barrier pattern; and Reference layers, and Wherein, the free layer is located between the tunnel barrier pattern and the conductive line.

16. A magnetic storage device comprising: a magnetic tunnel junction pattern on a substrate; a conductive line extending between the substrate and the magnetic tunnel junction pattern and contacting a bottom surface of the magnetic tunnel junction pattern; as well as a bottom pattern located between the conductive line and the substrate and in contact with the bottom surface of the conductive line, Wherein, the bottom pattern comprises metal nitride, and Wherein, the nitrogen content of the bottom pattern is higher than the metal element content of the bottom pattern, Wherein, the grain density of the bottom surface of the conductive line is greater than the grain density of the top surface of the conductive line.

17. The magnetic memory device according to claim 16, wherein: The bottom pattern is configured to apply compressive stress to the conductive line.

18. The magnetic memory device according to claim 16, wherein: The ratio of the nitrogen content to the metal element content is between 1.0 and 1.

3.

19. The magnetic memory device according to claim 16, wherein: A thickness of the bottom pattern along a height axis is smaller than a thickness of the conductive line along the height axis.

20. The magnetic memory device according to claim 16, wherein The bottom pattern includes: a first bottom pattern; and A second bottom pattern is below the first bottom pattern.

21. The magnetic memory device according to claim 20, wherein: The first bottom pattern is a metal nitride layer, and The second bottom pattern is a metal layer.

22. The magnetic memory device according to claim 20, wherein: The bottom pattern includes a third bottom pattern below the second bottom pattern, and a thickness of the third bottom pattern along a height axis is greater than a thickness of the first bottom pattern along the height axis.

23. The magnetic memory device according to claim 16, wherein: The wire includes a first wire and a second wire, and The bottom layer of the bottom pattern extends between the first conductive line and the second conductive line onto the substrate.

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