Display device and method of manufacturing the same

Abstract

A display device and a manufacturing method thereof are disclosed. The display device includes a base substrate, an active pattern and a gate electrode, the active pattern located on the base substrate includes a source region, a drain region and a channel region doped between the source region and the drain region, the channel region includes crystalline silicon, and the gate electrode overlaps the channel region of the active pattern. The channel region may include a lower portion, an upper portion and a middle portion located between the upper portion and the lower portion, and the dopant density of the lower portion may be 80% or more of the dopant density of the upper portion.

Description

Technical Field

[0001] Example embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0002] Recently, display devices with light weight and small size have been manufactured. Cathode ray tube (CRT) display devices have been used due to performance and competitive price. However, CRT display devices have weaknesses in size or portability. Therefore, display devices such as plasma display devices, liquid crystal display devices, and organic light emitting display devices have been highly praised due to small size, light weight, and low power consumption. Summary of the invention

[0003] An embodiment relates to a display device, including a base substrate, an active pattern, and a gate electrode, the active pattern located on the base substrate including a source region, a drain region, and a channel region doped between the source region and the drain region, the channel region including crystalline silicon, and the gate electrode overlapping the channel region of the active pattern. The channel region may include a lower portion, an upper portion, and a middle portion located between the upper portion and the lower portion, and a dopant density of the lower portion may be 80% or more of a dopant density of the upper portion.

[0004] The upper portion may be 1 / 3 the thickness of the active pattern, and the lower portion may be 1 / 3 the thickness of the active pattern.

[0005] The dopant of the channel region of the active pattern may include one or more of boron, phosphorus, nitrogen, nickel, and cobalt.

[0006] The average grain size of the channel region of the active pattern may be 270 nm or more.

[0007] According to electron backscatter diffraction results of the channel region of the active pattern, the fraction of the (001) direction may be 33% or more.

[0008] The display device may further include a gate insulating layer between the active pattern and the gate electrode, an interlayer insulating layer on the gate electrode, a source electrode and a drain electrode on the interlayer insulating layer and electrically connected to the active pattern.

[0009] The display device may also include a through-hole insulating layer, a first electrode, a light-emitting layer, and a second electrode, wherein the through-hole insulating layer is located on the source electrode and the drain electrode, the first electrode is located on the through-hole insulating layer and is electrically connected to the drain electrode, the light-emitting layer is located on the first electrode, and the second electrode is located on the light-emitting layer.

[0010] Embodiments also relate to a method for manufacturing a display device, the method comprising: forming an amorphous silicon layer on a base substrate; doping the amorphous silicon layer with impurities; forming a crystalline silicon layer by irradiating the doped amorphous silicon layer with an excimer laser; patterning the crystalline silicon layer; and forming a source region and a drain region in the crystalline silicon layer to form an active pattern including the source region, the drain region, and a channel region between the source region and the drain region. The channel region may include a lower portion, an upper portion, and a middle portion between the upper portion and the lower portion, and the dopant density of the lower portion may be 80% or more of the dopant density of the upper portion.

[0011] When doping the amorphous silicon layer, the dopant of the channel region of the active pattern may include one or more of boron, phosphorus, nitrogen, nickel, and cobalt.

[0012] When doping the amorphous silicon layer, the dopant dose may be 0.4E12 at / cm 2 to 1.5E12 at / cm 2 .

[0013] The crystalline silicon layer may satisfy the following formula 1:

[0014] <Formula 1>

[0015] Y=-0.075X+1.018nm

[0016] Where Y is the depth from the upper surface of the crystalline silicon layer at the maximum peak of the amount of dopant in nanometers, and X is the depth in J / cm 2 The laser density of the excimer laser.

[0017] When forming the active pattern, the source region and the drain region of the doped crystalline silicon layer may also be doped with impurities to increase the conductivity of the source region and the drain region.

[0018] A dose for forming the source region and the drain region when forming the active pattern may be greater than a dose when doping the amorphous silicon layer.

[0019] The average grain size of the channel region of the active pattern may be 270 nm or more.

[0020] According to electron backscatter diffraction results of the channel region of the active pattern, the fraction of the (001) direction may be 33% or more.

[0021] The method may further include: after patterning the crystalline silicon layer, forming a gate insulating layer on the patterned crystalline silicon layer; and forming a gate electrode on the gate insulating layer. When forming the active pattern, impurities may be doped into the crystalline silicon layer where the gate electrode is arranged to form a source region and a drain region.

[0022] The method may also include: forming an intermediate insulating layer on the gate electrode; forming a source electrode and a drain electrode electrically connected to the active pattern on the intermediate insulating layer; forming a through-hole insulating layer on the source electrode and the drain electrode; forming a first electrode electrically connected to the drain electrode on the through-hole insulating layer; forming a light-emitting layer on the first electrode; and forming a second electrode on the light-emitting layer.

[0023] The method may further include performing heat treatment on the active pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Features will become apparent to those skilled in the art by describing in detail example embodiments with reference to the accompanying drawings, in which:

[0025] Figure 1 shows a cross-sectional view of a display device according to an example embodiment;

[0026] Figure 2 A graph showing an IV curve of a thin film transistor according to a channel doping sequence and a channel doping amount;

[0027] Figure 3A and Figure 3B A graph showing hysteresis of a thin film transistor according to a channel doping sequence and a channel doping amount;

[0028] Figure 4 A graph showing a change in dopant density depending on the depth of an active pattern according to laser energy of an excimer laser annealing (ELA) process;

[0029] Figure 5 A diagram showing EBSD (electron backscatter diffraction) results according to the channel doping sequence;

[0030] 6A to 6H A cross-sectional view showing a method of manufacturing a display device according to an example embodiment;

[0031] Figure 7 shows a block diagram of an electronic device according to an example embodiment;

[0032] Fig. 8A Shows Figure 7 FIG. 1 is a diagram of an example in which the electronic device is implemented as a television; and

[0033] Figure 8B Shows Figure 7 The electronic device is implemented as an example of a smart phone. DETAILED DESCRIPTION

[0034] Now, example embodiments will be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as being limited to the embodiments described herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey example implementations to those skilled in the art. In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. Throughout the specification, the same reference numerals indicate the same elements.

[0035] Figure 1 is a cross-sectional view illustrating a display device according to example embodiments.

[0036] Reference Figure 1 The display device may include a base substrate 100, a buffer layer 110, an active pattern ACT, a gate insulating layer 120, a gate electrode GE, an interlayer insulating layer 130, a source electrode SE, a through hole insulating layer 140, a light emitting structure 180, a pixel defining layer PDL and a thin film encapsulation layer TFE.

[0037] The base substrate 100 may include a transparent or opaque insulating material. For example, the base substrate 100 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluoride-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, etc. In another implementation, the base substrate 100 may include a flexible transparent material, such as a flexible transparent resin substrate, for example, a polyimide substrate. In this case, the polyimide substrate may include a first polyimide layer, a barrier film layer, a second polyimide layer, etc. For example, the polyimide substrate may have a configuration in which a first polyimide layer, a barrier film layer, and a second polyimide layer are stacked on a rigid glass substrate.

[0038] The buffer layer 110 may be disposed on the base substrate 100. The buffer layer 110 may be disposed on the entire base substrate 100. The buffer layer 110 may prevent metal atoms and / or impurities from diffusing from the base substrate 100 into the active pattern ACT. In addition, the buffer layer 110 may control a heat transfer rate in a crystallization process for forming the active pattern ACT, which may help provide a substantially uniform active pattern ACT. In addition, when the surface of the base substrate 100 is uneven, the buffer layer 110 may improve the flatness of the surface of the base substrate 100.

[0039] The active pattern ACT may be disposed on the buffer layer 110. The active pattern ACT may include polysilicon. The active pattern ACT may include a drain region D and a source region S doped with impurities and a channel region CH between the drain region D and the source region S.

[0040] Impurities may also be doped in the channel region CH (channel doping), and the impurities may include at least one of boron (B), phosphorus (P), nitrogen (N), nickel (Ni), cobalt (Co), and fluorine (F). In this example embodiment, a case where the impurity is boron is illustrated. The channel region CH may include a lower portion 10 adjacent to the buffer layer 110, an upper portion 30 adjacent to the gate insulating layer 120, and a middle portion 20 located between the lower portion 10 and the upper portion 30.

[0041] When the dopant is boron, the density of the dopant may not change rapidly according to the depth from the top surface of the active pattern ACT, but may change relatively slowly. Therefore, the dopant may be uniformly distributed throughout the channel region CH of the active pattern ACT.

[0042] In the present example embodiment, the dopant density of the lower portion 10 may be 80% or more of the dopant density of the upper portion 30. The thickness of the upper portion 30 may be about 1 / 3 of the total thickness of the active pattern ACT. The thickness of the lower portion 10 may be about 1 / 3 of the total thickness of the active pattern ACT.

[0043] Generally, in a channel region of an active pattern where channel doping is performed, a dopant density is arranged to be concentrated adjacent to a surface of the active pattern (an upper surface of the active pattern), and the dopant density rapidly decreases as being closer to a lower surface of the active pattern.

[0044] On the other hand, according to the present exemplary embodiment, the dopant of the channel region CH is substantially uniformly distributed from the upper surface to the lower surface of the active pattern ACT according to pre-doping, which will be described below. Therefore, even with a small amount of channel doping, a sufficient positive shift of Vth can be obtained, a driving range (DR range) can be increased, and a subthreshold swing (SS) and a drain-induced barrier lowering (DIBL) can be reduced.

[0045] The gate insulating layer 120 may cover the active pattern ACT located on the buffer layer 110, and may be arranged to have substantially the same thickness along the contour of the active pattern ACT. The gate insulating layer 120 may include an inorganic insulating material such as a silicon compound or a metal oxide.

[0046] The gate electrode GE may be disposed on the gate insulating layer 120 to overlap the channel region CH of the active pattern ACT. The gate electrode GE may be formed using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, or the like.

[0047] The interlayer insulating layer 130 may be disposed on the gate insulating layer 120 on which the gate electrode GE is disposed. The interlayer insulating layer 130 may sufficiently cover the gate electrode GE on the gate insulating layer 120 and may have a substantially flat upper surface without forming a step around the gate electrode GE. The interlayer insulating layer 130 may include an inorganic insulating material such as a silicon compound or a metal oxide.

[0048] The source electrode SE and the drain electrode DE may be disposed on the interlayer insulating layer 130. The source electrode SE and the drain electrode DE may be connected to the source region S and the drain region D of the thin film transistor TFT through contact holes formed through the interlayer insulating layer 130 and the gate insulating layer 120, respectively. Figures 2 to 5 The characteristics of the thin film transistor TFT are described in detail.

[0049] The active pattern ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE may be included in a thin film transistor TFT. The thin film transistor TFT may be a driving transistor that supplies a driving current to an organic light emitting diode (OLED) as a light emitting structure.

[0050] The via insulating layer 140 may be disposed on the interlayer insulating layer 130 where the source electrode SE and the drain electrode DE are disposed. The via insulating layer 140 may have a single-layer structure, or may have a multi-layer structure including at least two insulating layers. The via insulating layer 140 may be formed using an organic material such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, or a siloxane-based resin.

[0051] The light emitting structure 180 may include a first electrode 181 , a light emitting layer 182 , and a second electrode 183 .

[0052] The first electrode 181 may be disposed on the through-hole insulating layer 140. The first electrode 181 may include a reflective material or a transmissive material according to an emission type of the display device. In example embodiments, the first electrode 181 may have a single-layer structure or a multi-layer structure that may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0053] The pixel defining layer PDL may be arranged on the through-hole insulating layer 140 on which the first electrode 181 is arranged. The pixel defining layer PDL may be formed using an organic material. For example, the pixel defining layer PDL may include a photoresist, an acrylic-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, and the like. In an example embodiment, an opening exposing the first electrode 181 may be formed by etching the pixel defining layer PDL. The emission region and the non-emission region of the display device may be defined by the opening of the pixel defining layer PDL. For example, a portion where the opening of the pixel defining layer PDL is positioned may correspond to the emission region, and the non-emission region may correspond to a portion adjacent to the opening of the pixel defining layer PDL.

[0054] The light emitting layer 182 may be arranged on the first electrode 181 exposed by the opening of the pixel defining layer PDL. In addition, the light emitting layer 182 may extend on the sidewall of the opening of the pixel defining layer PDL. In an example embodiment, the light emitting layer 182 may include an organic light emitting layer (EL), a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), an electron injection layer (EIL), etc. In an example embodiment, in addition to the organic light emitting layer, the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer may be formed in common to correspond to a plurality of pixels. In an example embodiment, a plurality of organic light emitting layers may be formed using light emitting materials that generate light of different colors (such as red light, green light, and blue light) according to the color pixels of the display device. In an example embodiment, the organic light emitting layer of the light emitting layer 182 may include a plurality of stacked light emitting materials for generating red light, green light, and blue light, thereby emitting white light. Here, the elements of the light emitting layer 182 may be formed in common to correspond to a plurality of pixels, and each pixel may be divided by a color filter layer.

[0055] The second electrode 183 may be disposed on the pixel defining layer PDL and the light emitting layer 182. The second electrode 183 may include a transmissive material or a reflective material according to the emission type of the display device. In example embodiments, the second electrode 183 may also have a single-layer structure or a multi-layer structure that may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0056] The thin film encapsulation layer TFE may be disposed on the second electrode 183. The thin film encapsulation layer TFE may prevent moisture and oxygen from penetrating from the outside. The thin film encapsulation layer TFE may include at least one organic layer and at least one inorganic layer. At least one organic layer and at least one inorganic layer may be alternately stacked with each other. For example, the thin film encapsulation layer TFE may include two inorganic layers and one organic layer located therebetween. In example embodiments, a sealing substrate for shielding external air and moisture from penetrating into the display device may be provided instead of the thin film encapsulation layer TFE.

[0057] Figure 2 is a graph showing an IV curve of a thin film transistor according to a channel doping sequence and a channel doping amount.

[0058] The horizontal axis in the drawing is the gate voltage (Vgs) input to the gate electrode of the thin film transistor, and the vertical axis is the source-drain current (Ids) flowing in the channel region of the thin film transistor.

[0059] As shown in the figure, in the region where the gate voltage Vgs is negative, the source-drain current Ids flowing through the thin film transistor is proportional to its magnitude. Therefore, by controlling the gate voltage Vgs, the current input from the power line to the first electrode or the current input to the organic light emitting diode can be controlled, and thus, the display of the image can be controlled.

[0060] exist Figure 2 1 shows IV curves of thin film transistors in six cases. When amorphous silicon is doped and crystallized (PRE, pre-doping), Vth (threshold voltage) shifts to the positive direction (right side) compared to when post-crystallization (POST, post-doping) is performed. It can be seen that as the dose of impurities increases (4E11, 1E12, 1.5E12), Vth shifts to the positive direction (right side).

[0061] Furthermore, in the case of pre-doping, the slope of the IV curve becomes gentler than in the case of post-doping and the driving range becomes wider, so that it is suitable for use as a driving transistor of an organic light emitting display device.

[0062] When a thin film transistor exhibits hysteresis, the hysteresis may cause an afterimage (ghosting) of an image. When a thin film transistor exhibits hysteresis, a curve measuring the source-drain current Ids during a change in gate voltage Vgs from a low voltage to a high voltage and a curve measuring the source-drain current Ids during a change in gate voltage Vgs from a high voltage to a low voltage are inconsistent with each other.

[0063] In this case, when a gray screen is displayed, the value of the source-drain current Ids during the period when the gate voltage Vgs changes from a low voltage to a high voltage is greater than the value of the source-drain current Ids during the period when the gate voltage Vgs changes from a high voltage to a low voltage. Accordingly, a display quality problem such as an afterimage may be caused depending on the display image of the previous frame.

[0064] For example, when a black / white pattern is applied for 10 seconds and then a 48 gray (low gray) pattern is applied, a brightness difference occurs and decreases over time. At this time, the degree of afterimage can be confirmed by measuring the time it takes for the brightness difference to reach 0.4% (unit: seconds).

[0065] Figure 3A and Figure 3B It is a graph showing the hysteresis of a thin film transistor according to the channel doping sequence and the channel doping amount.

[0066] Figure 3A and Figure 3BThe hysteresis (unit: V (voltage)) measured according to the change of dose (0.4E12, 1E12, 2E12) in the case of undoped thin film transistor channel region (skip (SKIP)) and pre-doping (PRE, i.e., doping before excimer laser annealing (ELA) process) and post-doping (POST, i.e., doping after excimer laser annealing (ELA) process) are shown.

[0067] Figure 3A A case where the thin film transistor is a PMOS transistor having a channel width of 4 μm (micrometers) and a length of 21.04 μm is shown. Figure 3B The case where the thin film transistor is a PMOS transistor having a channel width of 4 μm and a length of 4 μm is shown. In both cases, it can be seen that pre-doping can reduce hysteresis compared to post-doping of the same dose or SKIP.

[0068] Specifically, Figure 3A Compared with the post-doping case (POST1E12) with a dose of 1E12, in the pre-doping case with a dose of 0.4E12, the positive shift effect of Vth is maximized, while the dose is reduced and the hysteresis is reduced.

[0069] In addition, the hysteresis can be reduced to improve the afterimage, and this can be confirmed by the following Table 1.

[0070] [Table 1]

[0071] Doping sequence Accelerating voltage dose Vth Hysteresis(V) Instant afterimage (seconds) Post-doping 10K 1.3E12 -3.23 0.219 8.6 Pre-doping 15K 1.5E12 -3 0.187 7.0

[0072] Figure 4 is a graph showing a change in dopant density depending on the depth of an active pattern according to laser energy of an excimer laser annealing (ELA) process.

[0073] Reference Figure 4 , the horizontal axis represents the depth from the upper surface of the active pattern, and the vertical axis represents the density of boron (B) as a dopant.

[0074] As shown in the figure, according to the ELA process, the boron dopant diffuses to the lower portion of the active pattern. Therefore, boron is mainly distributed in the upper portion of the active pattern in an initial doping state, but according to the ELA process, boron diffuses to the lower portion of the active pattern.

[0075] At this time, as the laser energy of the ELA process becomes higher (i.e., injection: doping state → 1.95 J / cm 2 →2.05J / cm 2 →2.35J / cm 2 ), the diffusion becomes better and the boron density peak (maximum doping peak) becomes deeper.

[0076] When this formula is formulated, the following result [Formula 1] can be obtained.

[0077] [Formula 1]

[0078] Y=-0.075X+1.018nm

[0079] Where Y is the depth from the upper surface of the crystalline silicon layer at the maximum peak of the amount of dopant in nanometers, and X is the depth in J / cm 2 The laser density of the excimer laser.

[0080] The constants in the above equation may vary depending on the properties of the film and the characteristics of the device.

[0081] Figure 5 is a diagram showing EBSD (electron backscatter diffraction) results according to the channel doping sequence.

[0082] Reference Figure 5 , showing a color standard triangle according to electron backscatter diffraction (EBSD), a surface orientation image in the case of post-doping (b), and a surface orientation image in the case of pre-doping (a). EBSD is a known method for measuring the statistical distribution of grain sizes in a sample using a Kikuchi diffraction pattern.

[0083] Table 2 below shows the average grain size and the fraction of the (001) direction according to EBSD measurement in the case of pre-doping and post-doping, respectively.

[0084] [Table 2]

[0085] Average particle size (nm) (001) Fraction (%) Pre-doping 285 36.5 Post-doping 256 30.7

[0086] In the case of pre-doping, it was confirmed that the fraction of the (001) direction increased by 10% to 30% compared to the case of post-doping.

[0087] 6A to 6H is a cross-sectional view illustrating a method of manufacturing a display device according to example embodiments.

[0088] Reference Fig. 6A , a buffer layer 110 may be formed on the base substrate 100 . An amorphous silicon layer (a-Si layer) may be formed on the buffer layer 110 .

[0089] Reference Figure 6B , a doping process may be performed by providing impurities on an amorphous silicon layer (a-Si layer). The impurities as dopants may be any one of boron (B), phosphorus (P), nitrogen (N), nickel (Ni), cobalt (Co), and fluorine (F). The doping process may be performed by an implanter, spraying, CVD, sputtering, etc.

[0090] At this time, the dopant dose can be 0.4E12 at / cm 2 to 1.5E12 at / cm 2 When the dose is too large, hysteresis may be reduced, but the Vth shift amount may deviate from the desired range and the dispersion may become inappropriately large. On the other hand, when the dose is too small, the desired effect may not be obtained.

[0091] Reference Figure 6C , a crystalline silicon layer (eg, a polycrystalline silicon layer (p-Si layer)) can be formed by irradiating a doped amorphous silicon layer with an excimer laser.

[0092] At this time, the laser energy of the excimer laser may be within an appropriate range. When the laser energy is too low, the dopant may not be sufficiently diffused, and when the laser energy is too high, it may be difficult to obtain desired thin film transistor characteristics.

[0093] Reference Fig.6D , the polysilicon layer (p-Si layer) may be patterned into an active pattern ACT. For example, the polysilicon layer (p-Si layer) may be patterned by a photolithography process, etc. At this time, the active pattern ACT may be in a state where a source region and a drain region are not formed and only channel doping is performed.

[0094] Reference Fig. 6E , a gate insulating layer 120 may be formed on the active pattern ACT. A gate electrode GE may be formed on the gate insulating layer 120 to overlap the active pattern ACT.

[0095] Reference Fig. 6F , the source region S and the drain region D of the active pattern ACT may be formed by doping impurities into the active pattern ACT formed with the gate electrode GE. Accordingly, the channel region CH between the source region S and the drain region D may be formed to overlap the gate electrode GE.

[0096] Thereafter, a heat treatment may be performed on the active pattern ACT to activate and cure the active pattern ACT.

[0097] Reference Figure 6G , an interlayer insulating layer 130 may be formed on the gate insulating layer 120 where the gate electrode GE is arranged. A portion of the interlayer insulating layer 130 may be removed to form a contact hole exposing the source region S and the drain region D of the active pattern ACT. The source electrode SE and the drain electrode DE may be formed on the interlayer insulating layer 130 where the contact hole is formed.

[0098] Reference Figure 6H, a through-hole insulating layer 140 having a contact hole exposing the drain electrode DE may be formed on the interlayer insulating layer 130 on which the source electrode SE and the drain electrode DE are formed. A first electrode 181, a pixel defining layer PDL, a light emitting layer 182, and a second electrode 183 may be sequentially formed on the through-hole insulating layer 140. A thin film encapsulation layer TFE may be formed on the second electrode 183. Thus, a display device may be manufactured. Various suitable methods may be used as a method for forming each configuration of the display device.

[0099] According to the present exemplary embodiment, the display device includes an active pattern ACT, and the active pattern ACT includes a doped channel region CH. The active pattern ACT is formed by doping an amorphous silicon layer with impurities and then irradiating the doped amorphous silicon layer with an excimer laser, so that the characteristics of the thin film transistor can be improved. In particular, the hysteresis of the thin film transistor can be reduced, thereby reducing the afterimage problem and improving the display quality. In addition, the dose of the channel region CH can be made smaller than the dose of a general thin film transistor, so that the dispersion of the characteristics of the thin film transistor can be reduced with a small dose.

[0100] Figure 7 is a block diagram illustrating an electronic device according to an example embodiment. Fig. 8A It is shown Figure 7 The electronic device is implemented as an example of a television set. Figure 8B It is shown Figure 7 The electronic device is implemented as an example of a smart phone.

[0101] Reference Figures 7 to 8B , the electronic device 500 may include a processor 510, a storage device 520, a storage device 530, an input / output (I / O) device 540, a power supply 550, and a display device 560. Here, the display device 560 may correspond to Figure 1 In addition, the electronic device 500 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc. In an example embodiment, as Fig. 8A As shown in , the electronic device 500 may be implemented as a television. In another example embodiment, for example, Figure 8B As shown in , the electronic device 500 can be implemented as a smart phone. The electronic device 500 can also be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet computer, a car navigation system, a computer display screen, a laptop computer, a head mounted display (HMD), etc.

[0102] The processor 510 may perform various computing functions. The processor 510 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 510 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 510 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus. The storage device 520 may store data used for the operation of the electronic device 500. For example, the storage device 520 may include at least one nonvolatile storage device and / or at least one volatile storage device, at least one nonvolatile storage device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and at least one volatile storage device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc. The storage device 530 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 540 may include an input device and an output device, the input device being such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, etc., and the output device being such as a printer, a speaker, etc. The power supply 550 may provide power for the operation of the electronic device 500 .

[0103] The display device 560 may be coupled to other components via a bus or other communication link. In an example embodiment, the display device 560 may be included in the I / O device 540. As described above, the display device 560 may include a thin film transistor with reduced hysteresis and improved driving range as a driving transistor. Therefore, the display quality of the display device can be improved. However, since this has been described above, its description will not be repeated.

[0104] The exemplary embodiments may be applied to organic light-emitting display devices and various electronic devices including organic light-emitting display devices. For example, the exemplary embodiments may be applied to mobile phones, smart phones, video phones, smart tablets, smart watches, tablet computers, car navigation systems, televisions, computer displays, notebook computers, etc.

[0105] By way of summary and review, a display device may include a thin film transistor. The thin film transistor may include an active pattern, the active pattern including crystalline silicon which may be crystallized amorphous silicon. To improve the characteristics of the thin film transistor, additional channel doping of the crystalline silicon has previously been considered. In an organic light emitting display device, display quality may be affected by the characteristics of a driving transistor.

[0106] As described above, example embodiments relate to a display device and a method of manufacturing the display device that may provide improved display quality.

[0107] In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.

[0108] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art upon filing of this application, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Accordingly, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the example embodiments as set forth in the appended claims.

Claims

1. A method for manufacturing a display device, the method comprising: forming an amorphous silicon layer on a base substrate; doping the amorphous silicon layer with impurities; forming a crystalline silicon layer by irradiating the doped amorphous silicon layer with an excimer laser; patterning the crystalline silicon layer; and forming a source region and a drain region in the crystalline silicon layer to form an active pattern including the source region, the drain region and a channel region between the source region and the drain region, wherein the channel region includes a lower portion, an upper portion, and a middle portion between the upper portion and the lower portion, and a dopant density of the lower portion is 80% or more of a dopant density of the upper portion, and According to an electron backscatter diffraction result of the channel region of the active pattern, the fraction of the (001) direction is 33% or more.

2. The method of claim 1, wherein: When doping the amorphous silicon layer, a dopant of the channel region of the active pattern includes one or more of boron, phosphorus, nitrogen, nickel, and cobalt.

3. The method of claim 2, wherein: When doping the amorphous silicon layer, the dosage of the dopant is 0.4E12 at / cm 2 to 1.5E12 at / cm 2 .

4. The method of claim 2, wherein: The crystalline silicon layer satisfies the following formula 1: <Formula 1> Y=-0.075X+1.018nm Wherein, Y is the depth from the upper surface of the crystalline silicon layer at the maximum peak of the amount of the dopant in nanometers, and X is the unit of J / cm 2 The laser density of the excimer laser.

5. The method of claim 2, wherein: When forming the active pattern, the source region and the drain region of the doped crystalline silicon layer are further doped with impurities to increase conductivity of the source region and the drain region.

6. The method of claim 5, wherein: A dose used to form the source region and the drain region when forming the active pattern is greater than a dose when doping the amorphous silicon layer.

7. The method of claim 1, wherein: An average grain size of the channel region of the active pattern is 270 nm or more.

8. The method of claim 1, further comprising: After patterning the crystalline silicon layer, forming a gate insulating layer on the patterned crystalline silicon layer; as well as forming a gate electrode on the gate insulating layer, Wherein, when forming the active pattern, impurities are doped into the crystalline silicon layer where the gate electrode is arranged to form the source region and the drain region.

9. A display device, comprising: base substrate; an active pattern, the active pattern being located on the base substrate and comprising a source region, a drain region, and a channel region doped between the source region and the drain region, the channel region comprising crystalline silicon; and a gate electrode, the gate electrode overlapping the channel region of the active pattern, wherein the channel region includes a lower portion, an upper portion, and a middle portion between the upper portion and the lower portion, and a dopant density of the lower portion is 80% or more of a dopant density of the upper portion, and According to an electron backscatter diffraction result of the channel region of the active pattern, the fraction of the (001) direction is 33% or more.

Images