Semiconductor device and semiconductor chip

Abstract

A semiconductor device and a semiconductor chip are provided. The semiconductor device includes a semiconductor substrate having a scribe line defined therein. A plurality of semiconductor chips are formed on an upper surface of the semiconductor substrate. At least one conductive structure is disposed on the upper surface of the semiconductor substrate within the scribe line thereof. A fillet is disposed on at least one side surface of the conductive structure. The fillet is configured to induce a cutting line that propagates along the scribe line via a central portion of the conductive structure.

Description

[0001] Related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0145198, filed on November 22, 2018 with the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device, and more particularly to a semiconductor device, a semiconductor chip formed from the semiconductor device, and a method for dicing a semiconductor substrate containing the semiconductor device. Background Technology

[0004] Typically, multiple semiconductor chips, dies, or wafers formed on a single semiconductor substrate can be diced (“cut”) along scribe lines. For example, various conductive structures such as test element groups (TEGs) and alignment bonds can be arranged along the scribe lines.

[0005] To cleave a semiconductor substrate, a laser can be used to scribe lines to create scribe lines and conductive structures. The scribe lines can then spread along the side surfaces of each of the conductive structures located within the scribe lines.

[0006] In this case, either of the two semiconductor dies located on either side of the scribe line may contain a conductive structure without the scribe line. This conductive structure may therefore protrude from the side surface of the semiconductor die, and this protrusion could lead to short circuits, current leakage, etc., in subsequent processing steps.

[0007] While some dies may have conductive structures protruding from them, others may have grooves in which the conductive structures are positioned. These grooves can act as seed crystals for cracks in the semiconductor die. Furthermore, in the following molding processes, the grooves can serve as voids. Summary of the Invention

[0008] A semiconductor device includes a semiconductor substrate having scribe lines defined therein. A plurality of semiconductor chips are formed on an upper surface of the semiconductor substrate. At least one conductive structure is disposed on the upper surface of the semiconductor substrate within its scribe lines. Rounded corners are disposed on at least one side surface of the conductive structure. The rounded corners are configured to initiate a cleavage line that diffuses along the scribe lines through a central portion of the conductive structure.

[0009] A semiconductor chip includes internal circuitry. At least one conductive structure is disposed beside the internal circuitry. Rounded corners are disposed on at least one side surface of the conductive structure.

[0010] A method of cutting a semiconductor substrate includes forming a fillet on at least one side surface of at least one conductive structure, the at least one conductive structure being on an upper surface of a scribe line of a semiconductor substrate on which a plurality of semiconductor chips are formed. A laser is directed to the scribe line to form a cut line along the scribe line, the fillet, and a central portion of the conductive structure. BRIEF DESCRIPTION OF DRAWINGS

[0011] Exemplary embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figures 1 to 20 Various exemplary embodiments of the present disclosure are illustrated, as described herein.

[0012] Figure 1 A plan view of a semiconductor device according to an exemplary embodiment of the present disclosure is shown.

[0013] Figure 2 A cross-sectional view taken along line II-II' in Figure 1

[0014] Figure 3 A cross-sectional view taken along line III-III' in Figure 1

[0015] Figure 4 An enlarged cross-sectional view of portion "IV" in Figure 2

[0016] A perspective view showing a TEG and a fillet in Figure 5 Figure 1

[0017] Figure 6 A cross-sectional view taken along line VI-VI' in Figure 1

[0018] Figure 7 A plan view of a semiconductor device according to an exemplary embodiment of the present disclosure is shown.

[0019] Figure 8 A cross-sectional view taken along line VIII-VIII' in Figure 7

[0020] Figure 9 A cross-sectional view taken along line XI-XI' in Figure 7

[0021] Figure 10 A perspective view showing a TEG and a fillet in Figure 7

[0022] Figure 11 ​​​​​​​​FIG. 1 is a plan view to show a semiconductor device according to an exemplary embodiment of the present disclosure.

[0023] Figure 12 FIG. 2 is a cross-sectional view to show a semiconductor device according to an exemplary embodiment of the present disclosure.

[0024] Figures 13 to 16 FIG. 3 is a cross-sectional view to show a method of cutting a semiconductor substrate according to an exemplary embodiment of the present disclosure.

[0025] Figure 17 FIG. 4 is a cross-sectional view to show a method of cutting a semiconductor substrate according to an exemplary embodiment of the present disclosure.

[0026] Figure 18 FIG. 5 is a cross-sectional view to show a method of cutting a semiconductor substrate according to an exemplary embodiment of the present disclosure.

[0027] Figure 19 FIG. 6 is a cross-sectional view to show a method of cutting a semiconductor substrate according to an exemplary embodiment of the present disclosure.

[0028] Figure 20 FIG. 7 is a cross-sectional view to show a method of cutting a semiconductor substrate according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Hereinafter, exemplary embodiments of the present disclosure will be explained in detail with reference to the accompanying drawings.

[0030] Semiconductor device

[0031] Figure 1 FIG. 8 is a plan view to show a semiconductor device according to an exemplary embodiment of the present disclosure. Figure 2 FIG. 9 is a cross-sectional view taken along line II-II' of Figure 1 FIG. 10 is a cross-sectional view taken along line III-III' of Figure 3 FIG. 11 is an enlarged cross-sectional view of a portion "IV" in Figure 1 FIG. 12 is a perspective view to show a TEG and a fillet of Figure 4 FIG. 13 is a cross-sectional view taken along line VI-VI' of Figure 2 FIG. 14 is a perspective view to show a TEG and a fillet of Figure 5 FIG. 15 is a cross-sectional view taken along line VII-VII' of Figure 1 FIG. 16 is a perspective view to show a TEG and a fillet of Figure 6 FIG. 17 is a cross-sectional view taken along line VIII-VIII' of Figure 1 FIG. 18 is a cross-sectional view taken along line IX-IX' of

[0032] Referring to FIG. 1, a semiconductor device can include a semiconductor substrate 110, a plurality of semiconductor chips (or dies) 120, a conductive structure, and a fillet 140. Figures 1 to 6

[0033] ​The semiconductor chip 120 can be disposed on an upper surface of the semiconductor substrate 110. The semiconductor chip 120 can be singulated through the scribe line 112 of the semiconductor substrate 110. In an exemplary embodiment of the present disclosure, the scribe line 112 can have a cross shape.

[0034] The conductive structure can be disposed on an upper surface of the scribe line 112. In an exemplary embodiment of the present disclosure, the conductive structure can include a plurality of test element groups (TEGs) 130 and alignment keys 150. The test element groups 130 can be used to test the semiconductor chip 120. The alignment keys 150 can be used to align the semiconductor substrate 110.

[0035] Each test element group 130 can include a test pad 132 and a test line 134. The test pad 132 can be disposed on the upper surface of the scribe line 112. The test pad 132 can have a cuboid shape. Thus, the test pad 132 can have four side surfaces substantially perpendicular to the scribe line 112. The test line 134 can be electrically connected between the test pad 132 and the semiconductor chip 120. For example, the test line 134 can extend from a lower surface of the test pad 132. The test line 134 can be connected to the internal circuit 122 of the semiconductor chip 120.

[0036] A rounded corner 140 can be disposed on at least one side surface of the test element group 130. In an exemplary embodiment of the present disclosure, the rounded corner 140 can be disposed on the four side surfaces of the test pad 132. The rounded corner 140 can include an insulating material. The rounded corner 140 can be positioned in the accommodation groove 114 on the upper surface of the scribe line 112. The accommodation groove 114 can be formed in a length direction of the scribe line 112. A width of the accommodation groove 114 can be greater than a width of the test pad 132 to expose the four side surfaces of the test pad 132 through the accommodation groove 114. Here, the width of the test pad 132 can be a length measured in a direction substantially perpendicular to the length direction of the scribe line 112.

[0037] As Figure 3As seen in the cross-sectional view, the rounded corner 140 can have a lower surface 142, a side surface 144, and an inclined upper surface 146. The rounded corner 140 can be generally shaped as a right triangle, as shown, where the lower surface 142 is an adjacent side of the triangle, the side surface 144 is an opposite side of the triangle, and the inclined upper surface 146 is a hypotenuse of the triangle. The lower surface 142 of the rounded corner 140 can be configured to be in contact with the upper surface of the scribe line 112. The side surface 144 of the rounded corner 140 can extend from the lower surface 142. The side surface 144 of the rounded corner 140 can be configured to be in contact with the side surface of the test pad 132. The inclined upper surface 146 of the rounded corner 140 can be connected between the side surface 144 and the lower surface 142. The side surface 144 of the rounded corner 140 can have an upper end that can be lower than the side surface of the test pad 132. Alternatively, the side surface 144 of the rounded corner 140 can have an upper end that is generally coplanar with the side surface of the test pad 132.

[0038] The inclined upper surface 146 of the rounded corner 140 can provide a gradual inclined structure to connect the scribe line 112 and the test pad 132. Thus, when the scribe line 112 can be cut using a laser, the cutting line CL can spread along the length direction of the scribe line 112, as shown in the cross-sectional view. The cutting line CL can then be transmitted along the inclined upper surface 146 of the rounded corner 140 to the test pad 132. For example, the cutting line CL can spread along the central portion of the test pad 132. Thus, the test pad 132 can be divided into identical halves along the cutting line CL, such that each semiconductor chip 120 at both sides of the scribe line 112 can include a half of the test pad 132. Figure 5

[0039] Further, the rounded corner 140 can be disposed on at least one of the four side surfaces of the alignment key 150. In an exemplary embodiment of the present disclosure, the rounded corner 140 can be disposed on the four side surfaces of the alignment key 150. Thus, the receiving recess 114, which has a width greater than that of the scribe line 112, can expose the four side surfaces of the alignment key 150. The rounded corner 140 can be disposed in the receiving recess 114 and configured to at least partially surround the alignment key 150.

[0040] The rounded corner 140 on the alignment key 150 can have a structure and can generally function the same as the rounded corner 140 on the test element group 130. Thus, any additional description regarding the structure and function of the rounded corner 140 on the alignment key 150 can be omitted herein for brevity. It can be assumed that any omitted details are at least similar to the corresponding details already described herein.

[0041] ​The inclined upper surface 146 of the rounded corner 140 can also provide a gradual connection between the scribe line 112 and the alignment key 150. Thus, when the scribe line 112 can be used with a laser cut, a cut line CL can propagate along the length of the scribe line 112. The cut line CL can then be transmitted to the alignment key 150 via the inclined upper surface 146 of the rounded corner 140. For example, the cut line CL can propagate along a central portion of the alignment key 150. Thus, the alignment key 150 can be divided into identical halves, such that each semiconductor chip 120 at both sides of the scribe line 112 can include a half of the alignment key 150.

[0042] Figure 7 A plan view of a semiconductor device according to an exemplary embodiment of the present disclosure is shown. Figure 8 A cross-sectional view taken along line VIII-VIII' of Figure 7 A cross-sectional view taken along line XI-XI' of Figure 9 A perspective view of a TEG and rounded corners of Figure 7 A perspective view of a TEG and rounded corners of Figure 10 A perspective view of a TEG and rounded corners of Figure 7 A perspective view of a TEG and rounded corners of

[0043] The semiconductor device can include substantially the same elements as the semiconductor device shown in Figure 1 , except for the test element group. Thus, the same reference numerals can refer to the same elements, and any further description regarding the same elements can be omitted herein for brevity. It can be assumed that any omitted details are at least similar to the corresponding details already described herein.

[0044] Referring to Figures 7 to 10 , the test element group 130 can be directly connected with the semiconductor chip 120. For example, the test pads of the TEG 130 can have a first opposite surface electrically connected to the internal circuit 122 of the semiconductor chip 120. The first opposite side surface of the TEG 130 can be oriented toward the semiconductor chip 120 at both sides of the scribe line 112. Thus, an electrical connection structure can be disposed between the first opposite side surface of the TEG 130 and the semiconductor chip 120, such that the accommodation groove 114a can not be formed at the scribe line 112 between the first opposite side surface of the TEG 130 and the semiconductor chip 120. Thus, the accommodation groove 114a can be formed only along the length direction of the scribe line 112 (i.e., the direction of the cut line CL), as shown in Figure 9 . Thus, the second opposite side surface of the TEG 130 (which can be substantially perpendicular to the first opposite side surface) on the cut line CL can be exposed via the accommodation groove 114a.

[0045] Since the rounded corner 140 can be disposed in the accommodation groove 114a, the rounded corner 140 can be disposed on a second opposite side surface of the TEG 130 on the cutting line CL. Although the rounded corner 140 can be disposed on the second opposite side surface of the TEG 130, the cutting line CL diffused along the scribe line 112 can be formed along a center portion of the TEG 130.

[0046] semiconductor chip

[0047] Figure 11 A cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure is illustrated.

[0048] Referring to Figure 11 , the semiconductor chip 120 can be formed by cutting the semiconductor substrate 110 in Figure 1 along the scribe line 112. Accordingly, the semiconductor chip 120 can include the internal circuit 122, the TEG 130, the rounded corner 140, and the alignment key 150.

[0049] Since the TEG 130, the rounded corner 140, and the alignment key 150 can be cut in half by cutting the semiconductor substrate 110, the TEG 130 in the semiconductor chip 120 can have half the shape of the TEG 130 in Figure 1 . The alignment key 150 in the semiconductor chip 120 can have half the shape of the alignment key 150 in Figure 1 . The rounded corner 140 in the semiconductor chip 120 can have half the shape of the rounded corner 140 in Figure 1 . Conversely, since the rounded corner 140 on the inner surface of the TEG 130 oriented toward the internal circuit 122 can not be cut, the rounded corner 140 on the inner surface of the TEG 130 oriented toward the internal circuit 122 can have substantially the same shape as the shape of the rounded corner 140 in Figure 1 . For example, the rounded corner 140 can be disposed on three side surfaces of the TEG 130, except for the outer side surface of the TEG 130.

[0050] Figure 12 A cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure is illustrated.

[0051] Referring to Figure 12 , the semiconductor chip 120 can be formed by cutting the semiconductor substrate 110 in Figure 7 along the scribe line 112. Accordingly, the semiconductor chip 120 can include the internal circuit 122, the TEG 130, the rounded corner 140, and the alignment key 150.

[0052] Since the TEG 130, the rounded corner 140, and the alignment key 150 can be cut in half by cutting the semiconductor substrate 110, the TEG 130 in the semiconductor chip 120 can have half the shape of the TEG 130 in Figure 7half of the shape of the alignment key 150 in the semiconductor chip 120. The rounded corner 140 in the semiconductor chip 120 can have Figure 7 half of the shape of the alignment key 150 in the semiconductor chip 120. The rounded corner 140 in the semiconductor chip 120 can have Figure 7 half of the shape of the rounded corner 140 in the semiconductor chip 120. For example, the rounded corner 140 can be disposed on the opposite side surface of the TEG 130 on the scribe line CL.

[0053] A method of cutting a semiconductor substrate

[0054] Figures 13 to 16 A cross-sectional view to illustrate a method of cutting a semiconductor substrate according to an exemplary embodiment of the present disclosure. The method can be applied to Figure 1 the semiconductor substrate 110 in the semiconductor wafer 100.

[0055] Referring to Figure 13 , a die attach film 160 can be attached to the upper surface of the semiconductor substrate 110.

[0056] Referring to Figure 14 , a laser 170 can be disposed below the semiconductor substrate 110. The laser 170 can direct a laser beam to the lower surface of the scribe line 112.

[0057] Referring to Figure 15 , a cutting line CL can be formed in the scribe line 112 by the laser. The cutting line CL can spread along the length direction of the scribe line 112.

[0058] As mentioned above, the rounded corner 140 can provide a gradual inclined structure between the scribe line 112 and the TEG 130. Accordingly, the cutting line CL can spread along the central portion of the TEG 130 via the central portion of the rounded corner 140. The cutting line CL can also spread along the central portion of the alignment key 150 through the rounded corner 140.

[0059] Accordingly, the TEG 130 and the alignment key 150 can be divided into one half. Accordingly, the semiconductor chip 120 at both side surfaces of the scribe line 112 can have the half of the TEG 130 and the alignment key 150.

[0060] Referring to Figure 16 , the lower surface of the semiconductor substrate 110 can be partially removed by a grinding process to reduce the thickness of the semiconductor substrate 110. The spreading of the cutting line CL can be facilitated by the grinding process so that the semiconductor chip 120 can be separated along the scribe line 112.

[0061] The die attach film 160 can be removed to complete the semiconductor chip 120 in the semiconductor wafer 100. Figure 11

[0062] Figures 17 to 20 A cross-sectional view to illustrate a method of cutting a semiconductor substrate according to an exemplary embodiment of the present disclosure.​

[0063] Referring to Figure 17 The die attach film 160 can be attached to the upper surface of the semiconductor substrate 110.

[0064] Referring to Figure 18 The lower surface of the semiconductor substrate 110 can be partially removed by a grinding process to reduce the thickness of the semiconductor substrate 110.

[0065] Referring to Figure 19 The laser 170 can be disposed below the semiconductor substrate 110. The laser 170 can direct a laser beam to the lower surface of the scribe line 112.

[0066] Referring to Figure 20 The cut line CL can be formed in the scribe line 112 by a laser. The cut line CL can propagate along the length direction of the scribe line 112.

[0067] As mentioned above, the fillet 140 can provide a gradual slope structure between the scribe line 112 and the TEG 130. Thus, the cut line CL can propagate along the center portion of the TEG 130 via the center portion of the fillet 140. The cut line CL can also propagate along the center portion of the alignment key 150 through the fillet 140.

[0068] Thus, the TEG 130 and the alignment key 150 can be divided into halves. Thus, the semiconductor chip 120 at the two side surfaces of the scribe line 112 can have halves of the TEG 130 and the alignment key 150.

[0069] The die attach film 160 can be removed to complete the semiconductor chip 120 in Figure 12

[0070] According to exemplary embodiments of the present disclosure, a fillet can be disposed on a side surface of a conductive structure such that a cut line can propagate along a center portion of the conductive structure due to the fillet. Thus, the conductive structure can not tear towards any of the semiconductor chips. Thus, cracks, short circuits, leakage currents, etc. can not be generated in the semiconductor chips at either side of the scribe line.

[0071] The foregoing describes exemplary embodiments of the present disclosure and is not to be understood as limiting thereof. Although several exemplary embodiments of the present disclosure have been described, it will be readily apparent to those skilled in the art that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and aspects of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure.​

Claims

1. A semiconductor device, comprising: a semiconductor substrate having a scribe line defined therein; a plurality of semiconductor chips formed on an upper surface of the semiconductor substrate; at least one conductive structure disposed on an upper surface of the semiconductor substrate within the scribe line of the semiconductor substrate; and a rounded corner disposed on at least one side surface of the conductive structure, the rounded corner configured to induce a cutting line that propagates along the scribe line via a central portion of the conductive structure, wherein the rounded corner comprises an insulating material.

2. The semiconductor device of claim 1, wherein the rounded corner is disposed on the side surface of the conductive structure over the cutting line.

3. The semiconductor device of claim 1, wherein the rounded corner comprises: a lower surface in contact with the scribe line; a side surface extending from the lower surface to contact the side surface of the conductive structure; and an inclined upper surface connected between the lower surface and the side surface.

4. The semiconductor device of claim 3, wherein the side surface of the rounded corner has an upper end that is coplanar with the side surface of the conductive structure.

5. The semiconductor device of claim 3, wherein the side surface of the rounded corner has an upper end that is lower than the side surface of the conductive structure.

6. The semiconductor device of claim 1, wherein the rounded corner is disposed on a plurality of side surfaces of the conductive structure over the cutting line.

7. The semiconductor device of claim 1, wherein the rounded corner is disposed on an entire side surface of the conductive structure.

8. The semiconductor device of claim 1, wherein a receiving groove for receiving the rounded corner is formed on the scribe line.

9. The semiconductor device of claim 8, wherein the receiving groove has a width that is at least as large as a width of the scribe line.

10. The semiconductor device of claim 1, wherein the conductive structure comprises a test element group configured to test the plurality of semiconductor chips.

11. The semiconductor device of claim 10, wherein the test element group comprises a test pad having a side surface electrically connected to the plurality of semiconductor chips.

12. The semiconductor device of claim 11, wherein the rounded corner is disposed on the side surface of the test pad over the cutting line.

13. The semiconductor device of claim 10, wherein the test element group comprises: a test pad; and a test line extending from a lower surface of the test pad and connected to the plurality of semiconductor chips.

14. The semiconductor device of claim 13, wherein the rounded corner is disposed on an entire side surface of the test pad.

15. The semiconductor device of claim 1, wherein the conductive structure comprises an alignment key configured to align the semiconductor substrate.

16. The semiconductor device of claim 15, wherein the rounded corner is disposed on an entire side surface of the alignment key.

17. A semiconductor chip, comprising: an internal circuit; at least one conductive structure disposed alongside the internal circuit; and a rounded corner disposed on at least one side surface of the conductive structure, the rounded corner configured to induce a cutting line that propagates along a scribe line via a central portion of the conductive structure. ​ ​ ​ a rounded corner disposed on at least one side surface of the conductive structure, wherein the rounded corner comprises an insulating material.

18. The semiconductor chip of claim 17, wherein the rounded corner comprises: a lower surface disposed between the internal circuit and the conductive structure; a side surface extending from the lower surface and in contact with the side surface of the conductive structure; and a sloped upper surface connected between the lower surface and the side surface.

19. The semiconductor chip of claim 17, further comprising a receiving recess formed between the internal circuit and the conductive structure, the receiving recess configured to receive the rounded corner.

20. The semiconductor chip of claim 17, wherein the conductive structure comprises a portion of a test element group configured for testing the semiconductor chip.

21. The semiconductor chip of claim 20, wherein the test element group comprises a test pad having a side surface electrically connected to the internal circuit.

22. The semiconductor chip of claim 21, wherein the rounded corner is disposed on opposite side surfaces of the test pad, other than the side surface electrically connected to the internal circuit.

23. The semiconductor chip of claim 20, wherein the test element group comprises: a test pad; and a test line extending from a lower surface of the test pad and connected to the internal circuit.

24. The semiconductor chip of claim 23, wherein the test pad comprises four side surfaces, and the rounded corner is disposed on three side surfaces of the test pad, other than a side surface of the test pad distal from the internal circuit. ​ ​

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