Capacitor array structure, manufacturing method thereof, and semiconductor memory including the same
By forming the lower electrode layer in the semiconductor device in batches and setting the electrode connection layer, the problem of stopping high-deep aspect ratio trench etching in the semiconductor device is solved, and the performance and reliability of the capacitor are improved.
Patent Information
- Application Number
- CN201811417939.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2018-11-26
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2038-11-26
AI Technical Summary
In semiconductor devices, as the integration degree increases and the capacitor size shrinks, the trench depth increases and the opening size decreases, resulting in an increase in the depth-to-width ratio of the trench and an increase in etching difficulty, which easily leads to the problem of etching stop.
By forming the lower electrode layer in batches and setting an electrode connection layer between the lower electrode layers twice, the problems of etching stop and poor contact are solved. The specific method includes forming a plurality of spaced capacitive contact points on the substrate, forming first and second capacitive holes through an etching process, forming first and second lower electrode layers, respectively, and forming an electrode connection layer between the two.
By etching in batches and setting the electrode connection layer, the problem of high-deep aspect ratio trench etching stop is solved, and the alignment and contact quality of the lower electrode layer are improved, thereby enhancing the performance of the capacitor.
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Figure CN111223843B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a capacitor array structure, a manufacturing method thereof, and a semiconductor memory including the same. Background Art
[0002] Memory capacitors, as essential components in integrated circuits, have functions such as voltage regulation, filtering, and charge storage in the circuit.
[0003] A vertical capacitor forms a deep trench in a substrate, and uses the sidewall of the deep trench to provide the main plate area, thereby reducing the occupied area of the capacitor on the chip surface while still obtaining a relatively large capacitance.
[0004] With the improvement of the integration degree of semiconductor devices and the continuous miniaturization of the capacitor size, while the trench depth increases, the opening size continuously decreases, which greatly increases the aspect ratio of the trench and the etching difficulty. When etching a trench with a high aspect ratio, the problem of etching stop is likely to occur. Summary of the Invention
[0005] In order to overcome the above defects, the present invention provides a memory capacitor, a preparation method thereof, and a semiconductor memory including the same.
[0006] On the one hand, the present invention provides a capacitor array structure disposed on a semiconductor substrate, including an upper electrode layer, a lower electrode layer, and a capacitive dielectric layer adhered between the upper electrode layer and the lower electrode layer. The feature is that the lower electrode layer has a stepped surface in a direction perpendicular to the substrate.
[0007] According to an embodiment of the present invention, the lower electrode layer includes a first lower electrode layer and a second lower electrode layer, and the connection surface between the first lower electrode layer and the second lower electrode layer constitutes the stepped surface.
[0008] According to another embodiment of the present invention, the first lower electrode layer and the second lower electrode layer have different inclinations in a direction relative to perpendicular to the substrate.
[0009] According to another embodiment of the present invention, the first lower electrode layer is inclined 5° - 10° relative to the direction perpendicular to the substrate, and the second lower electrode layer is inclined 0° - 5° relative to the direction perpendicular to the substrate.
[0010] According to another embodiment of the present invention, the electrode connection layer of the first lower electrode layer and the second lower electrode layer include the same material.
[0011] According to another embodiment of the present invention, the first lower electrode layer and the second lower electrode layer are connected through an electrode connection layer.
[0012] According to another embodiment of the present invention, the electrode connection layer is parallel to the substrate direction.
[0013] According to another embodiment of the present invention, the electrode connection layer and the first lower electrode layer are made of the same material.
[0014] According to another embodiment of the present invention, the thickness of the electrode connection layer is 20 - 30 nm.
[0015] Another aspect of the present invention provides a method for manufacturing a capacitor array structure, comprising: providing a substrate having a plurality of capacitively contacting points distributed at intervals; sequentially forming a first sacrificial layer and a first support layer on the substrate; forming a first capacitor hole on the first support layer and the first sacrificial layer through an etching process, the first capacitor hole exposing the capacitively contacting points; forming a first lower electrode layer on the inner wall of the first capacitor hole; forming a capacitor filling layer in the first capacitor hole; sequentially forming a second sacrificial layer and a second support layer on the first support layer; etching the second sacrificial layer and the second support layer through an etching process to form a second capacitor hole above the first capacitor hole, the second capacitor hole exposing the capacitor filling layer, wherein: the second capacitor hole has a different inclination angle from the first capacitor hole in a direction perpendicular to the substrate; forming a second lower electrode layer on the sidewall of the second capacitor hole, the second lower electrode layer being connected to the first lower electrode layer; removing the capacitor filling layer; removing the first sacrificial layer and the second sacrificial layer; forming a capacitor dielectric layer covering the first lower electrode layer and the second lower electrode layer; forming an upper electrode layer covering the capacitor dielectric layer.
[0016] According to an embodiment of the present invention, the sidewall of the first capacitor hole inclines 5° - 10° outward relative to the direction perpendicular to the substrate, and the sidewall of the second capacitor hole inclines 0° - 5° outward relative to the direction perpendicular to the substrate.
[0017] According to another embodiment of the present invention, it further includes forming a capacitor recessed area on the capacitor filling layer before forming the second sacrificial layer and the second support layer, forming an electrode connection layer in the capacitor recessed area, the electrode connection layer connecting the first lower electrode layer and the second lower electrode layer.
[0018] According to another embodiment of the present invention, the depth of the capacitor recessed area is the same as the thickness of the first support layer.
[0019] According to another embodiment of the present invention, the electrode connection layer and the first lower electrode layer and the second lower electrode layer are made of the same material.
[0020] Another aspect of the present invention further provides a semiconductor memory device including the above capacitor array structure.
[0021] The present invention forms the lower electrode layer in two times, thereby solving the etching stop problem that occurs when etching trenches with a high aspect ratio. Further, an electrode connection layer is provided between the first lower electrode layer and the second lower electrode layer, thereby solving the misalignment problem and the poor contact problem that exist when the lower electrode layer is formed separately in two times. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The above and other features and advantages of the present invention will become more apparent by referring to the accompanying drawings and describing its exemplary embodiments in detail.
[0023] Figures 1 to 9 It is a schematic diagram of the preparation process of the capacitor array structure according to an embodiment of the present invention.
[0024] Among them, the reference numerals are described as follows:
[0025] 1: Substrate
[0026] 2: Capacitor contact point
[0027] 3: First sacrificial layer
[0028] 4: First support layer
[0029] 5: First lower electrode layer
[0030] 6: Capacitor filling layer
[0031] 7: Groove
[0032] 8: Electrode connection layer
[0033] 9: Second sacrificial layer
[0034] 10: Second support layer
[0035] 11: Second lower electrode layer
[0036] 12, 13: Guide port
[0037] 14: Capacitor dielectric layer
[0038] 15, 16: Upper electrode layer DETAILED DESCRIPTION OF THE EMBODIMENTS
[0039] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. In the figures, for clarity, the thickness of regions and layers is exaggerated. In the figures, the same reference numerals denote the same or similar structures, and thus their detailed description will be omitted.
[0040] It should be noted that the terms "upper", "lower", etc. in the present invention are only relative concepts to each other or are referenced based on the normal use state of the product, and should not be considered restrictive.
[0041] Please refer to Figures 1 - 9 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner and are not intended to limit the present invention. The diagrams only show the components related to the present invention rather than being drawn according to the number, shape, and size of the components in actual implementation. The form, number, and ratio of each component in actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex.
[0042] As Figure 1 shown, a substrate 1 having a plurality of spaced-apart capacitive contact points 2 is provided. A memory array structure is formed in the substrate 1, and the memory array structure includes a plurality of capacitive contact points 2. The memory array structure further includes transistor word lines and bit lines, and the capacitive contact points 2 are electrically connected to the transistor source electrodes in the memory array structure. The arrangement of the capacitive contact points 2 corresponds to the arrangement of the capacitor array structure to be fabricated subsequently.
[0043] A first sacrificial layer 3 and a first support layer 4 are sequentially formed on the upper surface of the substrate 1. The first sacrificial layer 3 and the first support layer 4 can be formed by chemical vapor deposition (CVD) or other suitable methods. The materials of the first sacrificial layer 3 and the first support layer 4 are different, and in the same etching process, the etching rate of the first sacrificial layer 3 is different from that of the first support layer 4. Specifically, in the same etching process, the etching rate of the first sacrificial layer 3 is much greater than that of the first support layer 4, so that when the first sacrificial layer 3 is completely removed, the first support layer 4 is almost completely retained. The first sacrificial layer 3 and the first support layer 4 are formed of a dielectric material. Preferably, the first sacrificial layer 3 is formed of silicon oxide, and the first support layer 4 is formed of silicon nitride. The thickness of the first sacrificial layer is 500 - 1000 nm. The thickness of the first support layer is 20 - 50 nm.
[0044] As Figure 2As shown, multiple openings can be formed in the first support layer 4 and the first sacrificial layer 3 through an etching method to define the position and shape of the first capacitor hole. The first capacitor hole exposes the capacitor contact point 2. The sidewall of the first capacitor hole is inclined 5-10° relative to the direction perpendicular to the substrate, preferably inclined outwardly, but not limited thereto, that is, a first capacitor hole with a narrower bottom and a wider top is formed to facilitate the subsequent filling process. Specifically, the method can be to etch the first support layer 4 and the first sacrificial layer 3 by using dry etching, wet etching or a combination of dry etching and wet etching to form a first capacitor hole that penetrates up and down in the first support layer 4 and the first sacrificial layer 3, and the first capacitor hole exposes the capacitor contact point 2. A first lower electrode layer 5 is formed in the first capacitor hole. Specifically, atomic layer deposition (ALD) or chemical vapor deposition can be used to deposit the first lower electrode layer 5 on the sidewall and bottom of the first capacitor hole. The first lower electrode layer 5 can be formed of a compound including one or two of metal nitride and metal silicide, such as titanium nitride (Titanium Nitride), titanium silicide (TitaniumSilicide), nickel silicide (Titanium Silicide), titanium silicon nitride (TiSi x N y ), preferably, in this embodiment, the material of the first lower electrode layer 5 is titanium nitride (TiN); then, the first lower electrode layer 5 on the upper surface of the first support layer 4 is removed by an etching method, and the first lower electrode layer 5 remaining on the sidewall and bottom of the first capacitor hole is retained. The bottom lower surface of the lower electrode layer 26 is bonded to the capacitor contact point 2. The thickness of the first lower electrode layer 5 can be 20-30 nm.
[0045] As Figure 3 shown, a capacitor filling layer 6 is formed in the capacitor hole formed with the first lower electrode layer 5, and the upper surface of the capacitor filling layer 6 is lower than the upper surface of the first support layer 4, so as to form a groove 7 relative to the upper surface of the first support layer 4. The specific formation method can be to fill a dielectric material, such as silicon oxide, in the first capacitor hole formed with the first lower electrode layer 5 by using ALD or other deposition methods. Then, for example, part of the silicon oxide is removed by etching to form a groove relative to the upper surface of the first support layer 4. The depth of the groove is preferably the same as the thickness of the first support layer 4.
[0046] As Figure 4As shown, an electrode connection layer 8 can be deposited and formed in the groove by ALD or other deposition methods. The upper surface of the electrode connection layer 8 is flush with the first formed layer 4. The function of the electrode connection layer 8 is to connect the first lower electrode layer and the second lower electrode layer. Therefore, the electrode connection layer 8 can be formed of the material used to form the first lower electrode layer 5. For example, it can be formed of a compound including one or two of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride. Preferably, it is formed of the same material as the first lower electrode layer 5. That is, in this embodiment, preferably, the electrode connection layer 8 is formed of TiN. The thickness of the electrode connection layer 8 can be 20 - 30 nm.
[0047] As Figure 5 shown, a second sacrificial layer 9 and a second support layer 10 are sequentially formed to cover the first support layer 4 and the electrode connection layer 8. The second sacrificial layer 9 and the second support layer 10 can be formed in the same manner as the first sacrificial layer 3 and the first support layer 4. The materials of the second sacrificial layer 9 and the second support layer 10 are different to meet the requirement that the etching rate of the second sacrificial layer 9 in the same etching process is much greater than the etching rate of the second support layer 10, so that when the second sacrificial layer 9 is completely removed, the second support layer 10 is almost completely retained. The second sacrificial layer 9 and the second support layer 10 are formed of dielectric materials. Preferably, the second sacrificial layer 9 is formed of silicon oxide, and the second support layer 10 is formed of silicon nitride. The thickness of the second sacrificial layer is 500 - 1000 nm. The thickness of the second support layer is 20 - 50 nm.
[0048] As Figure 6 shown, a plurality of openings can be formed in the second support layer 10, the second sacrificial layer 9, and the electrode connection layer 8 by etching to define the position and shape of the second capacitor holes. The second capacitor holes expose the capacitor filling layer 6. The side walls of the second capacitor holes are inclined 0 - 5° relative to the direction perpendicular to the substrate. Preferably, the side walls of the second capacitor holes are perpendicular to the surface of the substrate 1. By depositing electrode material in the second capacitor holes and then removing the electrode material formed on the capacitor filling layer 6, a second lower electrode layer 11 is formed on the side walls of the second capacitor holes. The second lower electrode layer 11 is connected to the electrode connection layer 8. The second lower electrode layer 11 can be formed of the material used to form the first lower electrode layer 5. For example, it can be formed of a compound including one or two of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride. Preferably, it is formed of the same material as the first lower electrode layer 5. That is, in this embodiment, preferably, the second lower electrode layer 11 is formed of TiN. The thickness of the second lower electrode layer 11 can be 20 - 30 nm.
[0049] As Figure 7 shown, the capacitor filling layer 6 can be removed by wet etching.
[0050] As Figure 8As shown, the first sacrificial layer 3 and the second sacrificial layer 9 are removed. Specifically, first, a guide opening 12 is formed on the second support layer 11 by using a dry etching method. The shape and size of the guide opening 12 can be selected according to the actual method. For example, a square, a rhombus, a circle, an ellipse or other shapes can be selected. Then, the second sacrificial layer 10 is removed by using a wet etching method. After that, a guide opening 13 is formed on the first support layer 4 by using a dry etching method. The shape and size of the guide opening 13 can be selected according to the actual method. For example, a square, a rhombus, a circle, an ellipse or other shapes can be selected. Then, the first sacrificial layer 3 is removed by using a wet etching method.
[0051] As Figure 9 shown, a capacitor dielectric layer 14 is deposited by using an ALD method or other methods to cover the first lower electrode layer 5 and the second lower electrode layer 11. The capacitor dielectric layer 14 can be formed of a high-K dielectric material to increase the capacitance value of the capacitor per unit area, and it includes ZrO x , HfO x , ZrTiOx, RuO x , SbO x , AlO x or one or more of them.
[0052] After that, an upper electrode layer 15, 16 is deposited by using a CVD method or other methods to cover the capacitor dielectric layer 14. The material of the upper electrode layer 15, 16 can include one or more of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, P-type polysilicon. Preferably, in this embodiment, the material of the upper electrode layer 15, 16 is generally formed of polysilicon.
[0053] The capacitor array structure of another embodiment of the present invention, as Figure 9As shown, a capacitor array structure is disposed on a semiconductor substrate 1, including a lower electrode layer, a capacitive dielectric layer 14 adhered between the upper electrode layer 1 and the lower electrode layer, and upper electrode layers 15, 16. The lower electrode layer has a stepped surface in a direction perpendicular to the substrate. The present invention solves the etch stop problem generated by etching high aspect ratio trenches in the prior art through sequential etching. During sequential etching, it is easy to form a stepped surface on the sidewall of the capacitive hole, thereby forming a stepped surface on the lower electrode layer. As shown in the figure, the lower electrode layer includes a first lower electrode layer 5 and a second lower electrode layer 11 connected to each other, and the connection surface therebetween (such as the electrode connection layer 8) constitutes the stepped surface of the lower electrode layer. The first lower electrode layer 5 and the second lower electrode layer 11 have different inclinations in a direction relative to perpendicular to the substrate. Preferably, the first lower electrode layer 5 is inclined 5 - 10° relative to the direction perpendicular to the substrate, and the second lower electrode layer 11 is inclined 0 - 5° relative to the direction perpendicular to the substrate. Preferably, the second lower electrode layer 11 is perpendicular to the substrate surface. The first lower electrode layer 5 and the second lower electrode layer 11 can be connected through the electrode connection layer 8, which can overcome the defect of poor contact caused by misalignment of the lower electrode layer during sequential etching. The first lower electrode layer 5, the second lower electrode layer 11, and the electrode connection layer 8 can be formed of the same material, such as formed of TiN. The thickness of the first lower electrode layer 5, the second lower electrode layer 11, and the electrode connection layer 8 is 20 - 30 nm. The upper electrode layers 15, 16 are formed of polysilicon. The thickness of the capacitive dielectric layer 14 is 45 - 55 nm.
[0054] A semiconductor memory according to another embodiment of the present invention includes a capacitor array prepared by the above structure or method.
[0055] In order to solve the problem of etch stop during the formation of memory capacitors, the present invention performs the etching process step by step. During step-by-step etching, by controlling the morphology of the holes in two etching steps, the alignment of the holes during two depositions of the lower electrode layer can be increased. During two depositions of the lower electrode layer, the problem of poor contact during two depositions of the lower electrode layer can be solved by increasing the electrode connection layer.
[0056] Certainly, the present invention may also have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding changes and deformations should all fall within the protection scope of the appended claims of the present invention.
Claims
1. A manufacturing method of a capacitor array structure, characterized in that, comprising: providing a substrate having a plurality of capacitively contacting points distributed at intervals; successively forming a first sacrificial layer and a first support layer on the substrate; forming a first capacitor hole on the first support layer and the first sacrificial layer by an etching process, the first capacitor hole exposing the capacitively contacting points; forming a first lower electrode layer on the inner wall of the first capacitor hole; forming a capacitor filling layer in the first capacitor hole; successively forming a second sacrificial layer and a second support layer on the first support layer; by an etching process, etching the second sacrificial layer and the second support layer to form a second capacitor hole above the first capacitor hole, the second capacitor hole exposing the capacitor filling layer, wherein: the second capacitor hole has a different inclination angle from the first capacitor hole in a direction perpendicular to the substrate; forming a second lower electrode layer on the sidewall of the second capacitor hole, the second lower electrode layer being connected to the first lower electrode layer; removing the capacitor filling layer; removing the first sacrificial layer and the second sacrificial layer; forming a capacitor dielectric layer covering the first lower electrode layer and the second lower electrode layer; forming an upper electrode layer covering the capacitor dielectric layer.
2. The manufacturing method according to claim 1, characterized in that, the sidewall of the first capacitor hole is inclined 5° - 10° outward relative to the direction perpendicular to the substrate, and the sidewall of the second capacitor hole is inclined 0° - 5° outward relative to the direction perpendicular to the substrate.
3. The manufacturing method according to claim 1, characterized in that, further comprising forming a capacitor recessed area on the capacitor filling layer and forming an electrode connection layer in the capacitor recessed area before forming the second sacrificial layer and the second support layer, the electrode connection layer connecting the first lower electrode layer and the second lower electrode layer.
4. The manufacturing method according to claim 3, characterized in that, the depth of the capacitor recessed area is the same as the thickness of the first support layer.
5. The manufacturing method according to claim 3 or 4, characterized in that, the electrode connection layer and the first lower electrode layer and the second lower electrode layer comprise the same material.
6. A semiconductor memory device, characterized in that, comprising a capacitor array structure formed by the manufacturing method according to any one of claims 1 - 5.
Citation Information
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Method for forming through hole and trench
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