Semiconductor package and method of manufacturing semiconductor package

Abstract

A semiconductor package includes a first semiconductor chip, a second semiconductor chip attached to an upper surface of the first semiconductor chip, a silicon heat spreader thermally connected to at least one of the first semiconductor chip and the second semiconductor chip, and a molding member configured to surround the first semiconductor chip and the second semiconductor chip and expose an upper surface of the silicon heat spreader.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application 10-2018-0146611, filed on November 23, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor package and a method for manufacturing the semiconductor package, and more specifically, to a semiconductor package having excellent heat dissipation characteristics and high reliability and which can be manufactured using a simple process, and a method for manufacturing the semiconductor package. Background Technology

[0004] Since logic chips typically generate a significant amount of heat during operation, their performance can be limited by temperature. Therefore, improvements related to heat dissipation in the semiconductor package that includes the logic chip are needed. Summary of the Invention

[0005] The present invention provides a semiconductor package that has excellent heat dissipation characteristics and high reliability, and can be manufactured using a simple process.

[0006] The present invention also provides a method for manufacturing semiconductor packages with excellent heat dissipation characteristics and high reliability using a simple process.

[0007] Furthermore, the present invention provides an electronic system including a semiconductor package.

[0008] According to one aspect of the present invention, a semiconductor package is provided. The semiconductor package includes: a first semiconductor chip; a second semiconductor chip attached to a upper surface of the first semiconductor chip; a silicon heat sink thermally connected to at least one of the first and second semiconductor chips; and a molding member configured to surround the first and second semiconductor chips and expose the upper surface of the silicon heat sink. The silicon heat sink is not electrically connected to either the first or second semiconductor chip included in the semiconductor package.

[0009] According to another aspect of the present invention, a semiconductor package is provided. The semiconductor package includes: a package substrate; a logic chip mounted on the package substrate; at least one memory chip attached to the logic chip; a molding member configured to encapsulate the logic chip and the memory chip; and a silicon heat sink attached to the upper surface of the logic chip, at least a portion of the silicon heat sink being exposed outside the package.

[0010] According to another aspect of the inventive concept, a method of manufacturing a semiconductor package is provided. The method includes mounting a logic chip on a package substrate; attaching a memory chip to the logic chip on an exposed portion of an upper surface of the logic chip; attaching a silicon heat spreader to the upper surface of the logic chip; and forming a molding member to encapsulate the logic chip and the memory chip while exposing an upper surface of the silicon heat spreader to an exterior of the package.

[0011] According to another aspect of the inventive concept, an electronic system is provided. The electronic system includes one or more of: a controller; an input / output (I / O) circuit configured to input or output data; a memory configured to store data; an interface configured to be able to transmit data to and receive data from an external device; and a bus configured to connect the controller, the I / O circuit, the memory, and / or the interface such that the controller, the I / O circuit, the memory, and / or the interface communicate with each other. The controller and the memory can be connected within a semiconductor package having a silicon heat spreader. BRIEF DESCRIPTION OF DRAWINGS

[0012] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] FIG. 1 is a plan view of a semiconductor package according to an embodiment;

[0014] FIG. 2A is a cross-sectional view of the semiconductor package taken along line IIA-IIA' of FIG. 1

[0015] FIG. 2B is a cross-sectional view of the semiconductor package taken along line IIB-IIB' of FIG. 1

[0016] FIG. 3 is an enlarged view of area III of FIG. 2A specifically showing a die attach film (DAF);

[0017] FIG. 4 is a plan view of a semiconductor package according to an embodiment;

[0018] FIG. 5A is a cross-sectional view of the semiconductor package taken along line VA-VA' of FIG. 4

[0019] FIG. 5B is a cross-sectional view of the semiconductor package taken along line VB-VB' of FIG. 4

[0020] FIG. 6 is a plan view of a semiconductor package according to an embodiment;​​​​

[0021] FIG. 7 is a cross-sectional view of the semiconductor package taken along line VIIA-VIIA' of FIG. 6 ;

[0022] FIG. 8 is a plan view of the semiconductor package according to the embodiment;

[0023] FIG. 9A is a cross-sectional view of the semiconductor package taken along line IXA-IXA' of FIG. 8 ;

[0024] FIG. 9B is a cross-sectional view of the semiconductor package taken along line IXB-IXB' of FIG. 8 ;

[0025] FIG. 10 is a plan view of the semiconductor package according to the embodiment;

[0026] FIG. 11A is a cross-sectional view of the semiconductor package taken along line XIA-XIA' of FIG. 10 ;

[0027] FIG. 11B is a cross-sectional view of the semiconductor package taken along line XIB-XIB' of FIG. 10 ;

[0028] FIG. 12 is a plan view of the semiconductor package according to the embodiment;

[0029] FIG. 13A is a cross-sectional view of the semiconductor package taken along line XIIIA-XIIIA' of FIG. 4 ;

[0030] FIG. 13B is a cross-sectional view of the semiconductor package taken along line XIIIB-XIIIB' of FIG. 4 ;

[0031] FIG. 14A to FIG. 14C is a cross-sectional view of the semiconductor package taken along line XIIIA-XIIIA' of ;

[0032] FIG. 15A and FIG. 15B is a cross-sectional view of the semiconductor package taken along line XIIIB-XIIIB' of

[0033] FIG. 16 is a block diagram of an electronic system according to the embodiment. DETAILED DESCRIPTION

[0034] FIG. 1 is a plan view of the semiconductor package 100 according to the embodiment. FIG. 2Ais a cross-sectional view taken along line IIA-IIA' of the semiconductor package 100. FIG. 1 is a cross-sectional view taken along line IIB-IIB' of the semiconductor package 100. FIG. 2B is a cross-sectional view taken along line IIA-IIA' of the semiconductor package 100. FIG. 1 is a cross-sectional view taken along line IIB-IIB' of the semiconductor package 100.

[0035] Referring to FIG. 1 , FIG. 2A and FIG. 2B , the semiconductor package 100 includes a first semiconductor chip 110 mounted on a package substrate 101. One or more second semiconductor chips 120 are located on the first semiconductor chip 110. Also, one or more silicon heat spreaders 130 are thermally connected to at least one of the first semiconductor chip 110 and the second semiconductor chip 120. In this example, the silicon heat spreaders 130 include a first silicon heat spreader 131 and a second silicon heat spreader 132. The first semiconductor chip 110, the second semiconductor chip 120, and the first and second silicon heat spreaders 131 and 132 can be surrounded by a molding member 150. Portions of the first and second silicon heat spreaders 131 and 132 can be exposed relative to the molding member 150.

[0036] The package substrate 101 can include, for example, a printed circuit board (PCB). In some embodiments, the package substrate 101 can include a multi-layer PCB. The package substrate 101 can include a base board layer, top and bottom pads formed on an upper and lower surface of the base board layer, respectively, and a solder resist layer configured to expose the top and bottom pads.

[0037] In some embodiments, the base board layer can include at least one material selected from a phenolic resin, an epoxy resin, and a polyimide. For example, the base board layer can include at least one material selected from a flame retardant 4 (FR4), a tetrafunctional epoxy resin, a polyphenylene ether, an epoxy resin / polyphenylene ether, a bismaleimide triazine (BT), a thermoset resin, a cyanate ester, a polyimide, and a liquid crystal polymer.

[0038] An interconnect pattern and conductive vias can be disposed on the upper and lower surfaces of the base board layer and / or within the base board layer. The interconnect pattern can electrically connect the top and bottom pads, and the conductive vias can electrically connect the interconnect pattern. The interconnect pattern can include, for example, an electro-deposited (ED) copper foil, a rolled annealed (RA) copper foil, a stainless steel foil, an aluminum foil, an ultra-thin copper foil, a sputtered copper, and / or a copper alloy. The conductive vias can be formed through at least a portion of the base board layer. In some embodiments, the conductive vias can include copper, nickel, stainless steel, or beryllium copper.

[0039] The terminal 101b can be provided on the bottom pad to electrically connect the package substrate 101 to an external device. The terminal 101b can be, for example, a bump, a solder ball, or a conductive filler. For example, the terminal 101b can include tin (Sn) as a main component, and include a material selected from silver (Ag), copper (Cu), gold (Au), zinc (Zn), bismuth (Bi), indium (In), lead (Pb), chromium (Cr), platinum (Pt), tungsten (W), titanium (Ti), iridium (Ir), nickel (Ni), cobalt (Co), iron (Fe), phosphorus (P), and alloys thereof, but the inventive concept is not limited thereto.

[0040] The first semiconductor chip 110 can be a logic chip. For example, the first semiconductor chip 110 can be a baseband chip (e.g., a modem chip), a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0041] The first semiconductor chip 110 can be mounted on the package substrate 101 in a flip-chip manner. In this case, the active surface of the first semiconductor chip 110 can face the package substrate 101, and the first semiconductor chip 110 can be electrically connected to the package substrate 101 through the chip connection member 110b.

[0042] The chip connection member 110b can be, for example, a bump, a solder ball, or a conductive filler. For example, the chip connection member 110b can include tin (Sn) as a main component, and include a material selected from silver (Ag), copper (Cu), gold (Au), zinc (Zn), bismuth (Bi), indium (In), lead (Pb), chromium (Cr), platinum (Pt), tungsten (W), titanium (Ti), iridium (Ir), nickel (Ni), cobalt (Co), iron (Fe), phosphorus (P), and alloys thereof, but the inventive concept is not limited thereto.

[0043] In some embodiments, a bottom fill layer can also be provided under the first semiconductor chip 110. The bottom fill layer can be formed by a capillary bottom fill method using an epoxy resin. In another embodiment, the bottom fill layer can be formed using a non-conductive film (NCF).

[0044] Each of the second semiconductor chips 120 can be a memory chip. For example, each of the second memory chips 120 can be a dynamic random access memory (DRAM) chip, a static RAM (SRAM) chip, a flash memory chip, an electrically erasable programmable ROM read-only memory (EEPROM) chip, a phase change RAM (PRAM) chip, a magnetic RAM (MRAM) chip, or a resistive RAM (RRAM) chip. Specifically, the second semiconductor chips 120 can include a plurality of memory chips, e.g., a first memory chip 120a and a second memory chip 120b. The first memory chip 120a and the second memory chip 120b can be arranged along a lateral direction (as shown in FIGS. 13A and 13B), but those skilled in the art will appreciate that the first memory chip 120a and the second memory chip 120b can be stacked in a vertical direction. Also, the first memory chip 120a and the second memory chip 120b can be arranged such that active surfaces of the first memory chip 120a and the second memory chip 120b face upward, i.e., face the silicon heat spreader 132 to be described below. That is, the first memory chip 120a and the second memory chip 120b can be oriented such that the active surfaces of the first memory chip 120a and the second memory chip 120b face away from the first semiconductor chip 110. FIG. 1 and FIG. 2B The first memory chip 120a and the second memory chip 120b can be arranged such that active surfaces of the first memory chip 120a and the second memory chip 120b face upward, i.e., face the silicon heat spreader 132 to be described below. That is, the first memory chip 120a and the second memory chip 120b can be oriented such that the active surfaces of the first memory chip 120a and the second memory chip 120b face away from the first semiconductor chip 110.

[0045] In some embodiments, an end portion of the first memory chip 120a and / or an end portion of the second memory chip 120b can overhang the chip (or the interposer) on which it is mounted and form an overhanging portion. Here, such an overhanging portion protrudes beyond a side surface of the first semiconductor chip 110. A bonding pad 120p to be connected to the package substrate 101 can be provided in the overhanging portion of the first memory chip 120a and / or the second memory chip 120b. Semiconductor devices in the first memory chip 120a and / or the second memory chip 120b can be electrically connected to the package substrate 101 through the bonding pad 120p. The bonding pad 120p can be electrically connected to the package substrate 101 through a bonding wire 120w.

[0046] The bonding wire 120w can include gold (Au), copper (Cu), palladium (Pd), silver (Ag), platinum (Pt), aluminum (Al), beryllium (B), yttrium (Y), zirconium (Zr), calcium (Ca), nickel (Ni), iron (Fe), cobalt (Co), bismuth (Bi), phosphorus (P), ruthenium (Ru), rhodium (Rh), and an alloy of at least two of them, but is not limited thereto.

[0047] The first memory chip 120a and the second memory chip 120b can be electrically connected to the first semiconductor chip 110 through the wire bonds 120w and the package substrate 101, and transmit and receive electrical signals to and from the first semiconductor chip 110.

[0048] The first memory chip 120a and the second memory chip 120b can be attached to the first semiconductor chip 110 using a die attach film (DAF) 120f.

[0049] The first silicon heat spreader 131 and the second silicon heat spreader 132 can be thermally connected to at least one of the first semiconductor chip 110 and the second semiconductor chip 120. It should be understood that when two objects are referred to as being "thermally connected" to each other, heat can be transferred from one object to the other object without there being a thermal insulator interposed between and separating the two objects. For example, when heat is transferred from one object to another object without there being intervening material (e.g., air) interposed between the two objects to separate the two objects, which has a thermal conductivity of 0.05 W / (mK) or less, 0.08 W / (mK) or less, or 0.1 W / (mK) or less, the two objects can be referred to as being thermally connected to each other.

[0050] In some embodiments, the first silicon heat spreader 131 can not be connected to any of the first semiconductor chip 110 and the second semiconductor chip 120 through an electrically conductive interconnect (e.g., a metallic interconnect). In some embodiments, the second silicon heat spreader 132 can not be connected to any of the first semiconductor chip 110 and the second semiconductor chip 120 through an electrically conductive interconnect (e.g., a metallic interconnect). Here, it should be understood that when the first silicon heat spreader 131 and / or the second silicon heat spreader 132 is not connected to any of the first semiconductor chip 110 and the second semiconductor chip 120 through an electrically conductive interconnect, there is no electrically conductive interconnect configured to connect the first silicon heat spreader 131 and / or the second silicon heat spreader 132 to the first semiconductor chip 110 or the second semiconductor chip 120.

[0051] The first silicon heat spreader 131 and the second silicon heat spreader 132 can be single-crystal silicon or poly-Si. Although the first silicon heat spreader 131 and the second silicon heat spreader 132 can be less expensive than silver (Ag), the first silicon heat spreader 131 and the second silicon heat spreader 132 can have a thermal conductivity similar to that of silver (Ag). In addition, as will be described in detail below, the first silicon heat spreader 131 and the second silicon heat spreader 132 can be easily attached to the first semiconductor chip 110 and the second semiconductor chip 120 through a DAF.

[0052] In some embodiments, a first silicon heat sink 131 may be thermally connected to a first semiconductor chip 110, and a second silicon heat sink 132 may be thermally connected to a second semiconductor chip 120. The first silicon heat sink 131 may extend vertically from the upper surface of the first semiconductor chip 110 to the upper surface of the semiconductor package 100. The second silicon heat sink 132 may extend vertically from the upper surface of the second semiconductor chip 120 to the upper surface of the semiconductor package 100.

[0053] The upper surface of the first silicon heat sink 131 and the upper surface of the second silicon heat sink 132 may be substantially coplanar. Terms such as “identical,” “equal,” “planar,” or “coplanar” as used herein include approximate similarity, including variations that may occur due to manufacturing processes, for example. Unless the context or other statement otherwise indicates otherwise, the term “substantially” may be used herein to emphasize that meaning.

[0054] For example, such as FIG. 2B As shown, the second silicon heat sink 132 can extend laterally across the upper surfaces of the first memory chip 120a and the second memory chip 120b. The second silicon heat sink 132 can extend laterally from the upper surface of the first memory chip 120a to the upper surface of the second memory chip 120b without encroaching on the area where the bonding pads 120p are formed. As described below, the space between the first memory chip 120a and the second memory chip 120b can be filled with a molding member 150, and the second silicon heat sink 132 can be supported by the molding member 150 between the first memory chip 120a and the second memory chip 120b.

[0055] The first silicon heat sink 131 and the second silicon heat sink 132 can be attached to the first semiconductor chip 110 and the second semiconductor chip 120 respectively via DAF 131f and DAF 132f.

[0056] FIG. 3 yes FIG. 2A An enlarged view of region III, which shows exemplary details of DAF 131f.

[0057] refer to FIG. 3 The first silicon heat sink 131 can be attached to the first semiconductor chip 110 using DAF 131f. In some embodiments, DAF 131f may include a thermal DAF. The thermal DAF may include filler 131ff dispersed in a matrix.

[0058] The filler 131ff can include a material having a higher thermal conductivity than the matrix. For example, the filler can have a thermal conductivity of 30 W / (mK) or more. For example, the filler 131ff can include a carbon-based nano-powder, an inorganic powder, a metal powder, or a mixture thereof, but is not limited thereto. Since the filler 131ff (e.g., an aluminum oxide (Al2O3) powder) having a high thermal conductivity (i.e., a high dielectric constant (k)) is dispersed in the DAF 131f, the DAF 131f can exhibit better heat transfer characteristics than a typical DAF.

[0059] The DAF 131f can have a thickness of about 8 µm to about 30 µm. As shown, a single layer of the DAF 131f can contact a lower surface of the respective first silicon heat spreader 131 and an upper surface of the first semiconductor chip 110 to affix them to each other. (The DAFs described elsewhere herein can similarly contact corresponding surfaces of various related structures to affix them.) FIG. 3

[0060] Referring back to FIG. 1 , FIG. 2A and FIG. 2B , an area of an exposed surface (e.g., an upper surface) of the second silicon heat spreader 132 can be greater than an area of an exposed surface (e.g., an upper surface) of each of the first silicon heat spreaders 131. For clarity, the shapes and sizes of the various components shown in FIG. 1 may be exaggerated, and the actual shapes and sizes of the first silicon heat spreaders 131 and the second silicon heat spreader 132 are not limited to the actual shapes and sizes shown in FIG. 1 . In some embodiments, an area of an exposed surface of one or both of the first silicon heat spreaders 131 can be greater than an area of an exposed surface of the second silicon heat spreader 132.

[0061] The molding member 150 can include an epoxy molding compound (EMC), but is not particularly limited thereto. The molding member 150 can also include a filler, which can include a material having a higher thermal conductivity than the EMC.

[0062] The molding member 150 can surround side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120. Also, the molding member 150 can surround side surfaces of the first silicon heat spreader 131 and the second silicon heat spreader 132. Meanwhile, upper surfaces of the first silicon heat spreader 131 and the second silicon heat spreader 132 can be exposed with respect to the molding member 150.

[0063] In some embodiments, the upper surfaces of the first silicon heat spreader 131 and the second silicon heat spreader 132 and an upper surface of the molding member 150 can be substantially coplanar with each other. The filler can include a carbon-based nano-powder, an inorganic powder, a metal powder, or a mixture thereof, but is not limited thereto. ​

[0064] FIG. 4 is a plan view of the semiconductor package 100a according to an embodiment. FIG. 5A is a cross-sectional view taken along a line VA-VA' of the semiconductor package 100a. FIG. 4 FIG. 5B is a cross-sectional view taken along a line VB-VB' of the semiconductor package 100a. FIG. 4

[0065] FIG. 4 , FIG. 5A and FIG. 5B Embodiments illustrated in FIGS. 11A, 11B, 12A, 12B, 13A, and 13B can differ from the embodiments described with reference to FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, and 10B in the configuration of the second silicon heat spreader 132a and the third silicon heat spreader 133. Accordingly, the following can omit repeated descriptions, and differences will be mainly described. FIG. 1 , FIG. 2A and FIG. 2B Embodiments illustrated in FIGS. 11A, 11B, 12A, 12B, 13A, and 13B can differ from the embodiments described with reference to FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, and 10B in the configuration of the second silicon heat spreader 132a and the third silicon heat spreader 133. Accordingly, the following can omit repeated descriptions, and differences will be mainly described.

[0066] With reference to FIGS. 11A, 11B, 12A, 12B, 13A, and 13B, the second silicon heat spreader 132a can be connected to the upper surfaces of the first memory chip 120a and the second memory chip 120b. The second silicon heat spreader 132a can extend in the +Y direction and the -Y direction, and extend above the upper surface of the first semiconductor chip 110 in the lateral direction. The second silicon heat spreader 132a can be formed on the upper surface of the second memory chip 120. FIG. 4 FIG. 5A FIG. 5B Since the area of the second silicon heat spreader 132a is greater than the area of each of the second semiconductor chips 120, heat generated by the second semiconductor chips 120 can be relatively smoothly discharged.

[0067] Since the area of the second silicon heat spreader 132a is greater than the area of each of the second semiconductor chips 120, heat generated by the second semiconductor chips 120 can be relatively smoothly discharged.

[0068] In some embodiments, the third silicon heat spreader 133 can be disposed below an extended portion of the second silicon heat spreader 132a, which can extend beyond the upper surface of the second memory chip 120. The third silicon heat spreader 133 can vertically extend in the Z direction from the upper surface of the first semiconductor chip 110 to the lower surface of the second silicon heat spreader 132a and thermally connect the two.

[0069] When the first semiconductor chip 110 is a logic chip, a large amount of heat can be generated in a short time. In this case, the heat can be smoothly dissipated to the outside through the third silicon heat spreader 133 and the second silicon heat spreader 132a. When the third silicon heat spreader 133 is not used, heat generated by the first semiconductor chip 110 can be discharged through the second semiconductor chip 120 and the second silicon heat spreader 132a. In this case, the heat dissipation efficiency can be reduced, and the second semiconductor chip 120 can be damaged by heat.

[0070] ​​​​The material of the third silicon heat spreader 133 and the method of attaching the third silicon heat spreader 133 can be the same as those described with reference to the first silicon heat spreader 131 and the second silicon heat spreader 132. FIG. 1 The material and method of the first silicon heat spreader 131 and the second silicon heat spreader 132 described are the same, and repetitive description thereof can be omitted.

[0071] FIG. 6 is a plan view of the semiconductor package 100b according to an embodiment. FIG. 7 is a cross-sectional view of the semiconductor package 100b taken along a line VIIA-VIIA' of FIG. 6 .

[0072] FIG. 6 and FIG. 7 the embodiments shown in FIGS. 1A to 1C can be different from the embodiments described with reference to FIGS. 2A to 2C in that the configuration of the second silicon heat spreader 132b is modified, and a metal heat spreader 139 is used. Thus, repetitive description can be omitted below, and the differences will be mainly described. FIG. 4 、 FIG. 5A and FIG. 5B the embodiments shown in FIGS. 1A to 1C can be different from the embodiments described with reference to FIGS. 2A to 2C in that the configuration of the second silicon heat spreader 132b is modified, and a metal heat spreader 139 is used. Thus, repetitive description can be omitted below, and the differences will be mainly described.

[0073] Referring to FIGS. 3A to 3C, the second silicon heat spreader 132b can be attached to the second semiconductor chip 120 by the DAF 132bf. The second silicon heat spreader 132b can extend in one lateral direction on the second semiconductor chip 120, and in the lateral direction above the upper surface of the first semiconductor chip 110. Meanwhile, the second silicon heat spreader 132b can not extend beyond the upper surface of the second semiconductor chip 120 in the opposite lateral direction. FIG. 6 and FIG. 7 Referring to FIGS. 3A to 3C, the second silicon heat spreader 132b can be attached to the second semiconductor chip 120 by the DAF 132bf. The second silicon heat spreader 132b can extend in one lateral direction on the second semiconductor chip 120, and in the lateral direction above the upper surface of the first semiconductor chip 110. Meanwhile, the second silicon heat spreader 132b can not extend beyond the upper surface of the second semiconductor chip 120 in the opposite lateral direction.

[0074] The semiconductor package 100b can include a metal heat spreader 139 connected to the upper surface of the first semiconductor chip 110. The metal heat spreader 139 can vertically extend from the upper surface of the first semiconductor chip 110 to the upper surface of the semiconductor package 100b.

[0075] The metal heat spreader 139 can be formed of a metal having high thermal conductivity. For example, the metal heat spreader 139 can be silver (Ag), aluminum (Al), copper (Cu), titanium (Ti), platinum (Pt), iron (Fe), cobalt (Co), nickel (Ni), zinc (Zn), or an alloy thereof.

[0076] The metal heat spreader 139 can be attached to the upper surface of the first semiconductor chip 110 using, for example, a thermal interface material (TIM). The TIM can be a solid material or a paste-like material capable of thermally joining two objects to each other. For example, the TIM can be a thermal grease, a thermal adhesive, or a thermal pad, but the present application is not limited thereto.

[0077] In some embodiments, the lower horizontal width of the metal heat spreader 139 can be greater than its upper horizontal width. That is, the vertical cross-section of the metal heat spreader 139 can have a trapezoidal shape.

[0078] The first semiconductor chip 110 can include various semiconductor devices, and can generate relatively high heat in areas densely populated with semiconductor devices configured to provide particular functionality. For example, the first semiconductor chip 110 can include a system on chip (SoC) including processor cores and several physically separate functional modules. Rapid dissipation of heat generated in areas densely populated with semiconductor devices configured to generate particularly high heat during operation (e.g., one or more functional modules of the SoC can be particularly prone to generating high heat in the case that the first semiconductor chip 110 is an SoC) can be desirable. Accordingly, the metal heat spreader 139 having a high thermal conductivity can be used in areas of the first semiconductor chip 110 where rapid heat dissipation of the first semiconductor chip 110 is particularly desirable (e.g., over areas of the first semiconductor chip 110 having one or more functional modules forming an SoC). In contrast, in other areas of the first semiconductor chip 110 (e.g., areas that generate heat during operation but have a temperature that rises at a relatively low rate), heat can be dissipated through the second semiconductor chip 120 and the second silicon heat spreader 132b attached to the upper portion of the second semiconductor chip 120.

[0079] FIG. 8 is a plan view of a semiconductor package 100c according to an embodiment. FIG. 9A is a cross-sectional view of the semiconductor package 100c taken along line IXA-IXA' of FIG. 8 . FIG. 9B is a cross-sectional view of the semiconductor package 100c taken along line IXB-IXB' of FIG. 8 .

[0080] FIG. 8 、 FIG. 9A and FIG. 9B the embodiments illustrated in FIG. 1 、 FIG. 2A and FIG. 2B may differ in that the second silicon heat spreader is omitted and the configuration of the first silicon heat spreader 131c is modified. Accordingly, the following can omit repeated descriptions and will mainly describe the differences.

[0081] Reference is made to FIG. 8 、 FIG. 9A and FIG. 9BThe silicon heat spreader attached to the second semiconductor chip 120 can be omitted. The first silicon heat spreader 131c attached to the first semiconductor chip 110 can not be in direct contact with the second semiconductor chip 120, but be in contact with the upper surface of the first semiconductor chip 110 over as large an area as possible. The first silicon heat spreader 131c can include a DAF 131cf to attach the first silicon heat spreader 131c to the upper surface of the first semiconductor chip 110.

[0082] As shown in FIG. 1, the second semiconductor chip 120 can include a first memory chip 120a and a second memory chip 120b, which can be arranged on the first semiconductor chip 110 in a lateral direction and spaced apart from each other by a predetermined distance. As a result, a path having a width corresponding to the predetermined distance can be formed between the first memory chip 120a and the second memory chip 120b. The path can connect the two oppositely greater extent exposed upper surfaces of the first semiconductor chip 110. FIG. 8 The first silicon heat spreader 131c can cover each of the two oppositely greater extent exposed upper surfaces of the first semiconductor chip 110 over the largest possible area. Also, the first silicon heat spreader 131c can cover a surface of the path to connect portions of the first silicon heat spreader 131c on the two oppositely greater extent exposed upper surfaces of the first semiconductor chip 110. As a result, the first silicon heat spreader 131c can have a planar shape similar to an I shape.

[0083] When the first silicon heat spreader 131c passes through the path, a side surface of the first silicon heat spreader 131c can extend to face at least three side surfaces of each of the first memory chip 120a and the second memory chip 120b. That is, in

[0084] one side surface of the first silicon heat spreader 131c can extend to face three side surfaces of the first memory chip 120a. Also, another side surface of the first silicon heat spreader 131c can extend to face three side surfaces of the second memory chip 120b. FIG. 8 The heat generated by the second semiconductor chip 120 (i.e., the first memory chip 120a and the second memory chip 120b) can be dissipated to the outside through the molding member 150. Meanwhile, the heat generated by the first semiconductor chip 110 can be dissipated to the outside through the first silicon heat spreader 131c. To maximize the contact area between the first semiconductor chip 110 and the first heat spreader 131c,

[0085] FIG. 8 ​The first semiconductor chip 110 and the second semiconductor chip 120 shown in FIGS. 1A to 1C can be arranged such that the first silicon heat spreader 131c can have a planar shape similar to an I shape. The maximized contact area can enable the heat generated by the first semiconductor chip 110 to be effectively dissipated.

[0086] In addition, the heat generated by the portion of the first semiconductor chip 110 covered by the second semiconductor chip 120 can be dissipated to the outside through the second semiconductor chip 120 and the molding member 150. It can be appreciated that the portion of the molding member 150 between the second semiconductor chip 120 and the first silicon heat spreader 131c can be made thinner, for example, thinner than the thickness of the molding member 150 disposed above the second semiconductor chip 120.

[0087] When the first semiconductor chip 110 is a logic chip, a large amount of heat can be generated at a relatively uniform rate over the entire area of the first semiconductor chip 110 in a short time. In this case, the heat generated by the first semiconductor chip 110 can be smoothly dissipated to the outside through the first silicon heat spreader 131c.

[0088] FIG. 10 is a plan view of a semiconductor package 100d according to an embodiment. FIG. 11A is a cross-sectional view of the semiconductor package 100d taken along a line XIA-XIA' of FIG. 10 . FIG. 11B is a cross-sectional view of the semiconductor package 100d taken along a line XIB-XIB' of FIG. 10 .

[0089] FIG. 10 , FIG. 11A and FIG. 11B The embodiments shown in FIGS. 1A to 1C can differ from the embodiments described with reference to FIGS. 2 to 4 in the arrangement of the second semiconductor chip 120 and the configuration of the first silicon heat spreader 131d. Accordingly, the following can omit repeated descriptions and will mainly describe the differences. FIG. 8 , FIG. 9A and FIG. 9B

[0090] Referring to FIGS. 2 to 4, FIG. 10 , FIG. 11A and FIG. 11B The second semiconductor chip 120 can include a first memory chip 120a and a second memory chip 120b that can be stacked in a vertical direction. Specifically, the first memory chip 120a and the second memory chip 120b can be stacked in a slightly offset manner to expose a bonding pad 120ap of the first memory chip 120a to assist a wire bonding process.

[0091] ​In detail, the first memory chip 120a can be attached to the first semiconductor chip 110 using the DAF 120af. Also, the second memory chip 120b can be attached to the first memory chip 120a using the DAF 120bf.

[0092] The bonding pads 120bp of the second memory chip 120b can be electrically connected to the first memory chip 120a through the bonding wires 120bw. Also, the bonding pads 120ap of the first memory chip 120a can be electrically connected to the package substrate 101 through the bonding wires 120aw.

[0093] Since the first memory chip 120a and the second memory chip 120b are stacked in a slightly offset manner, a space in which the first memory chip 120a is recessed can be formed under a side portion of the second memory chip 120b.

[0094] The first silicon heat spreader 131d can be connected to the upper surface of the first semiconductor chip 110. The first silicon heat spreader 131d can be attached to the upper surface of the first semiconductor chip 110 through the die attach pads 131df. As described above, the die attach pads 131df can include thermal DAFs including a filler.

[0095] The first silicon heat spreader 131d can partially surround the periphery of the second semiconductor chip 120. In some embodiments, the first silicon heat spreader 131d can surround three side surfaces of the first memory chip 120a and the second memory chip 120b. Also, the first silicon heat spreader 131d can vertically extend from the upper surface of the first semiconductor chip 110 to the upper surface of the semiconductor package 100d.

[0096] A portion of the first silicon heat spreader 131d can extend toward the first memory chip 120a under the overhanging portion of the second memory chip 120b. Accordingly, the first silicon heat spreader 131d can form an L-shaped structure (see FIG. 11B ). The portion of the first silicon heat spreader 131d extending toward the first memory chip 120a can be inserted into the space in which the first memory chip 120a is recessed. As a result, the upper surface of the portion of the first silicon heat spreader 131d extending toward the first memory chip 120a can face the lower surface of the second memory chip 120b.

[0097] A support structure 140s configured to support the overhanging portion can be disposed under the first memory chip 120a. The support structure 140s can be silicon (e.g., crystalline silicon), EMC, and / or any other material having an electrically insulating property.

[0098] FIG. 12 is a plan view of a semiconductor package 100e according to an embodiment.FIG. 13A It is the edge of semiconductor package 100e FIG. 4 A cross-sectional view taken from line XIIIA-XIIIA′. FIG. 13B It is the edge of semiconductor package 100e FIG. 4 A cross-sectional view taken from line XIIIB-XIIIB′.

[0099] FIG. 12 , FIG. 13A and FIG. 13B The embodiment shown can be configured similarly to the reference in terms of the first silicon heat sink 131e. FIG. 8 , FIG. 9A and FIG. 9B The described embodiments differ. Therefore, repeated descriptions can be omitted below, and the main differences will be described.

[0100] Reference FIG. 12 , FIG. 13A and FIG. 13B The first silicon heat sink 131e can be attached to the upper surface of the first semiconductor chip 110 through the die attach pad 131ef.

[0101] The first silicon heat sink 131e can extend from the upper surface of the first semiconductor chip 110 to the upper surface of the semiconductor package 100e. The surface area of ​​the upper surface of the first silicon heat sink 131e can be larger than the surface area of ​​the lower surface of the first silicon heat sink 131e. The vertical extension of the first silicon heat sink 131e can extend vertically from the lower surface of the first silicon heat sink 131e, and the horizontal extension of the first silicon heat sink 131e can extend laterally from the upper surface of the semiconductor package 100e. In some embodiments, the horizontal extension can extend laterally across the first memory chip 120a and the second memory chip 120b.

[0102] Because the first silicon heat sink 131e has a large upper surface, it can have an increased heat dissipation effect. In other words, since heat can be smoothly dissipated from the upper surface of the first silicon heat sink 131e, the temperature of the lower surface of the first silicon heat sink 131e can be kept relatively low, allowing the first semiconductor chip to be effectively cooled 110.

[0103] Although the first silicon heat sink 131e is in FIG. 13A The diagram shows an integrated type (e.g., continuous and monolithic), but two or more silicon heat sinks can be combined with each other via DAF to form a first silicon heat sink 131e.

[0104] In the following, a method for manufacturing a semiconductor package 100 according to an embodiment will be described.

[0105] FIG. 14A to FIG. 14Cis a cross-sectional view illustrating a method of manufacturing a semiconductor package 100 according to an embodiment.

[0106] Referring to FIG. 14A , a first semiconductor chip 110 can be mounted on the package substrate 101. As described with reference to FIG. 1 , FIG. 2A and FIG. 2B , the first semiconductor chip 110 can be mounted on the package substrate 101 in a flip-chip type, and a repeated detailed description thereof will be omitted.

[0107] One or more second semiconductor chips can be attached to the first semiconductor chip 110. Although an example in which a second memory chip 120b is shown as a second semiconductor chip is illustrated in FIG. 14A , the inventive concept is not limited thereto. The second memory chip 120b can be attached to the upper surface of the first semiconductor chip 110 using a DAF 120bf.

[0108] Referring to FIG. 14B , silicon heat spreaders 131m and 132m can be attached to the first semiconductor chip 110 and the second memory chip 120b. The silicon heat spreaders 131m and 132m can be attached to the first semiconductor chip 110 and the second memory chip 120b using DAFs 131f and 132f, e.g., thermal DAFs.

[0109] Referring to FIG. 14C , the first semiconductor chip 110, the second memory chip 120b, and the silicon heat spreaders 131m and 132m can be molded with a molding member 150 to surround side surfaces and an upper surface of the first semiconductor chip 110, the second memory chip 120b, and the silicon heat spreaders 131m and 132m.

[0110] For example, a molding method using the molding member 150 can be performed by injecting an EMC resin into a mold and curing the EMC resin, but the inventive concept is not limited thereto.

[0111] Thereafter, an upper portion of the molding member 150 can be removed, e.g., along a line P, to expose upper surfaces of the silicon heat spreaders 131m and 132m. Accordingly, a semiconductor package 100 according to embodiments described with reference to FIG. 1 , FIG. 2A and FIG. 2B can be obtained. The upper portion of the molding member 150 can be removed using, for example, a lapping process and a mechanical polishing process, e.g., by planarization, such as by chemical mechanical polishing (CMP).

[0112] FIG. 15A and FIG. 15B are cross-sectional views illustrating a method of manufacturing a semiconductor package 100 according to an embodiment.

[0113] Referring to FIG. 15A , the first semiconductor chip 110 and one or more second semiconductor chips (e.g., the second memory chip 120b) can be attached to the package substrate 101, and the silicon heat spreaders 131 and 132 can be attached to the first semiconductor chip 110 and the second semiconductor chip. Since FIG. 15A the process is the same as the process described with reference to FIG. 14A and FIG. 14B , a detailed description thereof will be omitted.

[0114] Referring to FIG. 15B , the upper surfaces of the silicon heat spreaders 131 and 132 can be in contact with the protective films 210 included in the molds 201 and 202, and then a molding resin (e.g., EMC) can be injected into the molds 201 and 202 and cured. The molding resin can be cured to form a molding member. The workpiece in which the molding resin is completely cured can be taken out of the molds 201 and 202, and the protective films 210 can be removed. Thus, the semiconductor package 100 according to the embodiments described with reference to FIG. 1 , FIG. 2A and FIG. 2B can be obtained.

[0115] The semiconductor package according to the embodiments described with reference to FIG. 4 to FIG. 13B can be manufactured using the same method, and a person skilled in the art can easily perform these embodiments as described with reference to FIG. 14A to FIG. 15B . A semiconductor package having excellent heat dissipation characteristics and high reliability can be manufactured using a simple process.

[0116] FIG. 16 is a block diagram of an electronic system 2000 according to an embodiment.

[0117] The electronic system 2000 can include a controller 2010, an input / output (I / O) circuit 2020, a memory 2030, and an interface 2040, which can be connected to each other through a bus 2050.

[0118] The controller 2010 can include at least one of a microprocessor, a digital signal processor, or a processor similar thereto. The I / O device 2020 can include at least one of a keypad, a keyboard, or a display device. The memory 2030 can be used to store commands executed by the controller 2010. For example, the memory 2030 can be used to store user data.

[0119] The electronic system 2000 can constitute a wireless communication device or a device capable of transmitting and / or receiving information in a wireless environment. The interface 2040 can include a wireless interface so that the electronic system 2000 can transmit and receive data via a wireless communication network. The interface 2040 can include an antenna and / or a wireless transceiver. In some embodiments, the electronic system 2000 can be used for a communication interface protocol of a third generation communication system, such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), North American Digital Cellular (NADC), Extended Time Division Multiple Access (E-TDMA), and / or Wideband Code Division Multiple Access (WCDMA). The electronic system 2000 (e.g., at least one of the controller 2010 and the memory 2030) can include at least one or more of the semiconductor packages according to any of the above-described embodiments and modified and changed within the scope of the inventive concept.

[0120] The electronic system 2000 can be applied to a portable phone, a desktop computer, a laptop computer, a tablet personal computer (PC), a game machine, a navigation device, a digital camera, a personal digital assistant (PDA), a wireless phone, a digital music player, or all electronic products capable of transmitting and / or receiving information in a wireless environment.

[0121] Hereinafter, the configuration and effects of the inventive concept will be described in more detail with reference to specific experimental examples and comparative examples. However, these examples are intended only to facilitate understanding, and are not intended to limit the scope of the inventive concept.

[0122] A temperature change experiment was performed on semiconductor packages in which a modem chip and a DRAM chip were mounted on a package substrate as shown in FIG. 1. FIG. 1

[0123] The following semiconductor packages were respectively manufactured: a semiconductor package lacking a silicon heat spreader (Comparative Example 1), a semiconductor package including a silicon heat spreader using a typical DAF as shown in FIG. 2 (Experimental Example 1), a semiconductor package including a silicon heat spreader using a thermal DAF as shown in FIG. 3 (Experimental Example 2), a semiconductor package including a silicon heat spreader using a thermal DAF as shown in FIG. 4 and using an EMC containing a filler as a molding member (Experimental Example 3), and a semiconductor package including a silicon heat spreader using a typical DAF as shown in FIG. 5 (Experimental Example 4). FIG. 1 FIG. 1 FIG. 1 FIG. 8 The specific configurations of the respective examples are shown in Table 1.

[0124] The temperature change was measured while about 1.55 W of power was supplied to each semiconductor package under the condition that the air temperature was 25°C, and the measurement results are listed in Table 1.

[0125] The temperature change was measured while about 1.55 W of power was supplied to each semiconductor package under the condition that the air temperature was 25°C, and the measurement results are listed in Table 1.

[0125] ​

[0126] [Table 1]

[0127] The thermal resistance obtained through the experiment refers to the temperature change per unit power supplied to each semiconductor package, and is expressed in units of °C / W. As heat dissipation becomes smoother, the temperature can rise at a lower rate, and the thermal resistance can be lower.

[0128] As shown in Table 1, it can be inferred that the silicon heat spreader, the thermal DAF, and the filler contained in the EMC all contribute to heat dissipation.

[0129] While the present concept has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package comprising: a package substrate; a first semiconductor chip, wherein an active surface of the first semiconductor chip faces the package substrate and the first semiconductor chip is electrically connected to the package substrate by a chip connection member; a second semiconductor chip attached to an upper surface of the first semiconductor chip, the second semiconductor chip comprising a first memory chip and a second memory chip arranged to be spaced apart from each other in a lateral direction, wherein each of the first memory chip and the second memory chip comprises at least one bond pad formed on an upper surface thereof and the at least one bond pad is electrically connected to the package substrate by at least one wire bond; a first silicon heat spreader thermally connected to the first memory chip and the second memory chip without covering the at least one bond pad; a second silicon heat spreader thermally connected to the first semiconductor chip; and a molding member configured to surround the first semiconductor chip and the second semiconductor chip, wherein the first silicon heat spreader has an exposed upper surface with respect to the molding member, and wherein the first silicon heat spreader and the second silicon heat spreader are not connected to any of the first semiconductor chip and the second semiconductor chip included in the semiconductor package by a conductive interconnection.

2. The semiconductor package of claim 1, wherein, At least one of the first silicon heat spreader and the second silicon heat spreader is single-crystal silicon or polycrystalline silicon.

3. The semiconductor package of claim 1, wherein, The first silicon heat spreader is attached to the first memory chip and the second memory chip by a die attach film (DAF).

4. The semiconductor package of claim 3, wherein, The DAF comprises a thermal DAF including a thermally conductive filler.

5. The semiconductor package of claim 1, wherein, The first semiconductor chip is mounted on the package substrate in a flip-chip type.

6. The semiconductor package of claim 1, wherein, The second semiconductor chip is mounted on the first semiconductor chip such that an active surface of the second semiconductor chip faces the first silicon heat spreader.

7. The semiconductor package of claim 1, wherein, The second semiconductor chip is mounted on the first semiconductor chip, wherein a portion of the second semiconductor chip overhangs above an edge of the first semiconductor chip to form an overhanging portion of the second semiconductor chip.

8. The semiconductor package of claim 7, wherein the at least one bond pad is formed on the overhanging portion of the second semiconductor chip.

9. The semiconductor package of claim 1, wherein, The first silicon heat spreader is attached to the upper surface of the second semiconductor chip and vertically extends from the upper surface of the second semiconductor chip to an upper surface of the semiconductor package.

10. The semiconductor package of claim 9, wherein the second silicon heat spreader is attached to the upper surface of the first semiconductor chip, the second silicon heat spreader vertically extends from the upper surface of the first semiconductor chip to an upper surface of the semiconductor package, and wherein an upper surface of the first silicon heat spreader is coplanar with an upper surface of the second silicon heat spreader.

11. The semiconductor package of claim 10, wherein the second silicon heat spreader comprises two portions spaced apart from each other, wherein the first silicon heat spreader is interposed between the two portions, and wherein the second silicon heat spreader has a larger surface area of the upper surface than the first silicon heat spreader.

12. The semiconductor package of claim 1, wherein the second silicon heat spreader extends vertically from the upper surface of the first semiconductor chip to a lower surface of the first silicon heat spreader.

13. The semiconductor package of claim 1, wherein, The first semiconductor chip is a logic chip.

14. A semiconductor package, comprising: a package substrate; a first semiconductor chip electrically connected to the package substrate by a chip connection member; a second semiconductor chip attached to an upper surface of the first semiconductor chip, the second semiconductor chip including a first memory chip and a second memory chip arranged to be spaced apart from each other in a lateral direction, wherein each of the first memory chip and the second memory chip includes at least one bonding pad formed on an upper surface thereof, and the at least one bonding pad is electrically connected to the package substrate by at least one bonding wire; a silicon heat spreader thermally connected to the first memory chip and the second memory chip without covering the at least one bonding pad; a metal heat spreader thermally connected to the first semiconductor chip; and a molding member configured to surround the first semiconductor chip and the second semiconductor chip, wherein each of the silicon heat spreader and the metal heat spreader has an exposed upper surface with respect to the molding member, and wherein the silicon heat spreader and the metal heat spreader are not connected to any of the first semiconductor chip and the second semiconductor chip included in the semiconductor package by a conductive interconnection.

15. An electronic system, comprising: a controller; a memory configured to store data; an interface circuit configured to transmit and receive data to and from an external device; and a bus configured to connect the controller, the memory, and the interface circuit such that the controller, the memory, and the interface circuit communicate with each other, wherein at least one of the controller and the memory includes the semiconductor package as claimed in claim 1.

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