Non-volatile memory devices and memory systems including memory planes

Abstract

A non-volatile memory device, a memory system, and a vertical NAND flash memory device are provided. The non-volatile memory device can include a plurality of memory planes and a plurality of plane-specific pad groups. The plurality of memory planes can include a plurality of memory cell arrays having non-volatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits can be connected to non-volatile memory cells among the non-volatile memory cells included in each of the plurality of memory cell arrays through a bit line. The plurality of plane-specific pad groups can be connected to the plurality of page buffer circuits through a plurality of data paths, respectively, such that each of the plurality of plane-specific pad groups is specifically connected to each of the plurality of page buffer circuits. Bandwidth of data transfer can be increased by reducing data transfer latency and supporting parallel data transfer, and power consumption can be reduced by removing data multiplexing and / or signal routing.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0150016, filed with the Korean Intellectual Property Office (KIPO) on November 28, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various aspects of this disclosure generally relate to a semiconductor integrated circuit, and more specifically, to a non-volatile memory device including a memory plane and a memory system including such a non-volatile memory device. Background Technology

[0004] Semiconductor memory devices used for storing data can be categorized into volatile memory devices and non-volatile memory devices. Volatile memory devices, such as Dynamic Random Access Memory (DRAM), are typically configured to store data by charging or discharging capacitors in memory cells and can lose the stored data when the power is turned off, removed, or disabled. Non-volatile memory devices, such as Flash Memory, retain the stored data even when the power is turned off, removed, or disabled. Volatile memory devices are widely used as main memory in various devices, while non-volatile memory devices are widely used to store program code and / or data in various electronic devices (such as computers, mobile devices, etc.).

[0005] Recently, non-volatile memory devices with three-dimensional structures (such as vertical NAND memory devices) have been developed to increase the integration and / or storage capacity of non-volatile memory devices. Along with the increase in integration and storage capacity, it is also desirable to increase the data transfer speed of non-volatile memory devices. Summary of the Invention

[0006] Some examples of the embodiments can provide non-volatile memory devices suitable for multi-planar structures.

[0007] Some examples of the embodiments may provide a memory system including a non-volatile memory device suitable for a multi-planar structure.

[0008] According to some examples of embodiments, a non-volatile memory device includes multiple memory planes and multiple dedicated pad groups. The multiple memory planes include multiple page buffer circuits and multiple memory cell arrays including non-volatile memory cells. Each of the multiple page buffer circuits is connected via a bit line to a non-volatile memory cell included in each of the multiple memory cell arrays. The multiple dedicated pad groups are connected to the multiple page buffer circuits via multiple data paths, such that each of the multiple dedicated pad groups is connected to a corresponding page buffer circuit in the multiple page buffer circuits.

[0009] According to some examples of embodiments, a memory system includes a non-volatile memory device and a memory controller configured to control the operation of the non-volatile memory device. The non-volatile memory device includes: a plurality of memory planes including a plurality of page buffer circuits; and a plurality of memory cell arrays including non-volatile memory cells, wherein each of the plurality of page buffer circuits is connected via a bit line to a non-volatile memory cell included in each of the plurality of memory cell arrays. A plurality of plane-specific pad groups are respectively connected to the plurality of page buffer circuits via a plurality of data paths, such that each of the plurality of plane-specific pad groups is dedicated to a corresponding page buffer circuit in the plurality of page buffer circuits.

[0010] According to some examples of embodiments, a vertical NAND flash memory device includes: a plurality of memory planes including a plurality of page buffer circuits; and a plurality of memory cell arrays including flash memory cells stacked in a vertical direction to form cell strings, wherein each of the plurality of page buffer circuits is connected via a bit line to a cell string included in each of the plurality of memory cell arrays. A plurality of plane-specific pad groups are respectively connected to the plurality of page buffer circuits via a plurality of data paths, such that each of the plurality of plane-specific pad groups is dedicated to a corresponding page buffer circuit in the plurality of page buffer circuits.

[0011] Non-volatile memory devices and memory systems according to some examples of embodiments can increase data transmission bandwidth by reducing data transmission latency and by supporting parallel data transmission through multiple plane-specific pad groups that are respectively assigned to multiple memory planes.

[0012] Non-volatile memory devices and memory systems according to some examples of embodiments can reduce power consumption by eliminating data multiplexing and / or signal routing and using multiple plane-specific pad groups that are respectively allocated to multiple memory planes. Attached Figure Description

[0013] Examples of embodiments of the present disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0014] Figure 1 This is a block diagram illustrating a memory system including a non-volatile memory device according to some examples of embodiments.

[0015] Figure 2 This is a block diagram illustrating some examples of non-volatile memory devices according to embodiments.

[0016] Figure 3A and Figure 3B These are illustrations showing some examples of embodiments of a command address decoder included in a non-volatile memory device.

[0017] Figure 4 It is shown that it includes Figure 2 A block diagram of a memory cell array in a non-volatile memory device.

[0018] Figure 5A It is shown that it includes Figure 4 A perspective view of an example embodiment of a memory block in a memory cell array.

[0019] Figure 5B It shows a reference. Figure 5A The circuit diagram of the equivalent circuit of the described memory block.

[0020] Figure 6 This is a diagram illustrating example control signals for a non-volatile memory device according to some examples of embodiments.

[0021] Figures 7 to 10 This is a timing diagram illustrating example operating modes of a non-volatile memory device according to some examples of embodiments.

[0022] Figure 11 This is a block diagram illustrating a memory system including a non-volatile memory device with a multiplexing structure.

[0023] Figure 12 It is shown Figure 11 A diagram illustrating the multiplane operation of a non-volatile memory device.

[0024] Figure 13 This is a diagram illustrating multi-plane operation of a non-volatile memory device according to some examples of embodiments.

[0025] Figure 14 This is a diagram illustrating the address layout of a non-volatile memory device according to some examples of embodiments.

[0026] Figures 15 to 22 This is a diagram illustrating example operation of a non-volatile memory device according to some examples of embodiments.

[0027] Figure 23, Figure 24 and Figure 25 This is a diagram illustrating an example layout of a non-volatile memory device according to some examples of embodiments.

[0028] Figure 26 This is a block diagram illustrating a mobile system including a non-volatile memory device according to some examples of embodiments. Detailed Implementation

[0029] Various examples of embodiments will be described more fully below with reference to the accompanying drawings, which show only a few examples of embodiments. In the drawings, the same reference numerals always denote the same elements. Repeated descriptions may be omitted.

[0030] Figure 1 This is a block diagram illustrating a memory system including a non-volatile memory device according to some examples of embodiments.

[0031] Reference Figure 1 The memory system 10 includes a memory controller 20 and at least one memory device 30.

[0032] At least one memory device 30 may be a non-volatile memory device, and may be referred to herein as a non-volatile memory device. The memory system 10 may include flash memory-based data storage media, such as memory cards, Universal Serial Bus (USB) memory, and / or solid-state drives (SSDs).

[0033] The non-volatile memory device 30 can be configured to perform read operations, erase operations, program operations, and / or write operations under the control of the memory controller 20. The non-volatile memory device 30 can receive commands (CMD) and addresses (ADD) from the memory controller 20, and can exchange data with the memory controller 20 for read and program operations. In some examples of embodiments, the non-volatile memory device 30 can receive control signals and power from the memory controller 20.

[0034] The non-volatile memory device 30 may include multiple memory planes PL_0 to PL_n-1, multiple data paths DTPH0 to DTPHn-1, and multiple dedicated planar pad groups PDPSM_0 to PDPSM_n-1.

[0035] Each of the plurality of memory planes PL_0 to PL_n-1 may include a corresponding one of the plurality of memory cell arrays MCA0 to MCAn-1, each memory cell array including non-volatile memory cells. Each of the plurality of memory planes PL_0 to PL_n-1 may also include a corresponding one of the plurality of page buffer circuits PBC0 to PBCn-1. Each page buffer circuit PBC0 to PBCn-1 can be connected via bit lines to the non-volatile memory cells included in each memory cell array MCA0 to MCAn-1. In other words, a first memory plane PL_0 may include a first memory cell array MCA0 and a first page buffer circuit PBC0, a second memory plane PL_1 may include a second memory cell array MCA1 and a second page buffer circuit PBC1, and in this way, an nth memory plane PL_n-1 may include an nth memory cell array MCAn-1 and an nth page buffer circuit PBCn-1. In some examples of the embodiments, each of the page buffer circuits PBC0 to PBCn-1 may correspond to the page size or the number of bit lines of each memory plane.

[0036] Multiple planar dedicated pad groups PDPSM_0 to PDPSM_n-1 can be connected one-to-one to multiple page buffer circuits PBC0 to PBCn-1 via multiple data paths DTPH0 to DTPHn-1, such that each of the planar dedicated pad groups PDPSM_0 to PDPSM_n-1 is dedicated to each of the page buffer circuits PBC0 to PBCn-1. For example, the first data path (e.g., DTPH0) of the multiple data paths can independently connect the first page buffer circuit (e.g., PBC0) to the first planar dedicated pad group (e.g., PDPSM_0). Each data path DTPH0 to DTPHn-1 may include data input / output circuitry, which will be referred to below. Figure 2 Describe the data input / output circuit.

[0037] Each of the planar dedicated pad groups PDPSM_0 to PDPSM_n-1 may include multiple data pads. For example, the first planar dedicated pad group PDPSM_0 may include m data pads DQ0 to DQm-1 for transmitting data signals DT[m-1:0], the second planar dedicated pad group PDPSM_1 may include m data pads DQm to DQ2m-1 for transmitting data signals DT[2m-1:m], and in this way, the nth planar dedicated pad group PDPSM_n-1 may include m data pads DQs to DQnm-1 for transmitting data signals DT[nm-1:s], where s is (n-1)*m-1. In other words, each of the n planar dedicated pad groups PDPSM_0 to PDPSM_n-1 may each include m data pads, and the total number of data pads DQ0 to DQnm-1 may be n*m. In some examples of the embodiments, the number of data pads included in each dedicated planar pad group can be eight, which can correspond to eight bits in a byte. In other words, in some examples of the embodiments, m can be equal to eight.

[0038] The memory controller 20 may include a plurality of host pad groups PDPSC_0 to PDPSC_n-1, which are respectively connected one-to-one to a plurality of planar dedicated pad groups PDPSM_0 to PDPSM_n-1, such that each host pad group PDPSC_0 to PDPSM_n-1 is dedicated to connecting to each of the planar dedicated pad groups PDPSM_0 to PDPSM_n-1. As is known to those skilled in the art, the internal configuration of the memory controller 20 may be determined differently.

[0039] Each of the plurality of host pad groups PDPSC_0 to PDPSC_n-1 may include a plurality of host data pads connected to a plurality of data pads included in each of the plurality of planar dedicated pad groups PDPSM_0 to PDPSM_n-1, such that each of the plurality of host data pads is dedicatedly connected to each of the plurality of data pads. In other words, each of the first host pad group PDPSC_0 and the first planar dedicated pad group PDPSM_0 may include m data pads DQ0 to DQm-1, each of the second host pad group PDPSC_1 and the second planar dedicated pad group PDPSM_1 may include m data pads DQm to DQ2m-1, and in this way, each of the nth host pad group PDPSC_n-1 and the nth planar dedicated pad group PDPSM_n-1 may include m data pads DQs to DQnm-1.

[0040] As will be described below, multiple planar dedicated pad groups PDPSM_0 to PDPSM_n-1 can be used to perform parallel and / or independent multi-plane operations with respect to multiple memory planes PL_0 to PL_n-1, wherein the multiple planar dedicated pad groups PDPSM_0 to PDPSM_n-1 are respectively assigned to or mapped to the multiple memory planes PL_0 to PL_n-1 in a one-to-one relationship.

[0041] According to some examples of embodiments, the non-volatile memory device 30 and memory system 10 can increase data transmission bandwidth by reducing data transmission latency and supporting parallel data transmission through multiple planar dedicated pad groups PDPSM_0 to PDPSM_n-1, wherein the multiple planar dedicated pad groups PDPSM_0 to PDPSM_n-1 are respectively allocated to multiple memory planes PL_0 to PL_n-1. Additionally, reference will be made to... Figure 11 , Figure 12 and Figure 13 According to the embodiments, the non-volatile memory device 30 and memory system 10 can reduce power consumption by eliminating data multiplexing and / or signal routing and using multiple plane-specific pad groups PDPSM_0 to PDPSM_n-1 that are respectively assigned to multiple memory planes PL_0 to PL_n-1.

[0042] Figure 2 This is a block diagram illustrating some examples of non-volatile memory devices according to embodiments.

[0043] Reference Figure 2 The non-volatile memory device 30 may include multiple memory planes 401, 402, and 403, each memory plane including a corresponding memory cell array and page buffer circuitry PBC. The non-volatile memory device 30 may also include a line decoder 430, multiple data paths 411, 412, and 413, multiple plane dedicated pad groups (PDPSMs) 421, 422, and 423, control circuitry 450, and a voltage generator 460.

[0044] Each memory cell array can be coupled to the row decoder 430 via multiple string select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). Additionally, each memory cell array can be coupled to a corresponding page buffer circuit (PBC) via multiple bit lines (not shown). Each memory cell array may include multiple memory cells coupled to the multiple word lines (WL) and multiple bit lines. In some examples of embodiments, the memory cell array may be a three-dimensional memory cell array, which may be formed on a substrate in a three-dimensional structure (or a vertical structure). In some examples of embodiments, each memory cell array may include multiple vertically oriented NAND strings or multiple cell strings, such that at least one memory cell is located on top of another memory cell.

[0045] Control circuit 450 can be from Figure 1 The memory controller 20 receives a command (signal) CMD and an address (signal) ADD, and controls erase, program, write, and / or read operations of the non-volatile memory device 30 based on the command signal CMD and the address signal ADD. An erase operation may include executing a series of erase cycles, and a programming operation may include executing a series of programming cycles. Each programming cycle may include a programming period and a programming verification period. Each erase cycle may include an erase period and an erase verification period. Read operations may include normal read operations and data recovery read operations.

[0046] Based on the command signal CMD, the control circuit 450 can generate the control signal VCTL for controlling the voltage generator 460, and the page buffer control signal PCTL for controlling the page buffer circuit PBC. Based on the address signal ADD, the control circuit 450 can generate the row address R_ADDR and the column address C_ADDR. The control circuit 450 can provide the row address R_ADDR to the row decoder 430, and the column address C_ADDR to the data paths 411, 412, and 413. The row decoder 430 can be coupled to the memory cell array via multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL.

[0047] During programming or reading operations, based on the row address R_ADDR, the row decoder 430 can determine that one of the word lines WL is the selected word line, and determine that the remaining word lines WL besides the selected word line are unselected word lines.

[0048] Additionally, during programming or reading operations, based on the row address R_ADDR, the row decoder 430 can determine that one of the string select lines SSL is the selected string select line, and determine that the remaining string select lines SSL are unselected string select lines.

[0049] Voltage generator 460 can generate word line voltage VWL based on control signal VCTL, which may be required for the operation of the memory cell array of non-volatile memory device 30. Voltage generator 460 can receive power PWR from memory controller 20. Word line voltage VWL can be applied to word line WL by row decoder 430.

[0050] For example, during programming operations, voltage generator 460 can apply a programming voltage to the selected word line and a programming pass voltage to an unselected word line. Additionally, during programming verification operations, voltage generator 460 can apply a programming verification voltage to the selected word line and a verification pass voltage to an unselected word line.

[0051] Additionally, during normal read operations, voltage generator 460 can apply a read voltage to the selected word line and can apply a read pass voltage to an unselected word line. During data recovery read operations, voltage generator 460 can apply a read voltage to the word line adjacent to the selected word line and can apply a recovery read voltage to the selected word line.

[0052] Each page buffer circuit (PBC) can be coupled to the memory cell array via a bit line. A page buffer circuit (PBC) may include multiple page buffers. In some examples of embodiments, each page buffer may be connected to only one bit line. In other examples of embodiments, each page buffer may be connected to two or more bit lines. The page buffer circuit (PBC) can temporarily store data to be programmed into or read from selected pages of the memory cell array (MCA).

[0053] Each of data paths 411, 412, and 413 may include a data input / output circuit. Each data input / output circuit can be coupled to a corresponding page buffer circuit (PBC) via a data line. During a programming operation, based on the column address C_ADDR received from the control circuit 450, the data input / output circuit can receive programming data DATA received from the memory controller 20 and provide the programming data DATA to the page buffer circuit (PBC). During a read operation, the data input / output circuit can provide the read data DATA, which has been read from the memory cell array and stored in the page buffer circuit (PBC), to the memory controller 20 based on the column address C_ADDR received from the control circuit 450.

[0054] Additionally, the page buffer circuit (PBC) and data input / output circuit included in each of data paths 411, 412, and 413 can read data from a first region of the memory cell array and write the read data to a second region of the memory cell array (e.g., without transferring data to a source outside the non-volatile memory device 30, such as the memory controller 20). In other words, the page buffer circuit and data input / output circuit can perform write-back operations.

[0055] Figure 3A and Figure 3B This is a diagram illustrating an example of an embodiment of a command address decoder included in a non-volatile memory device.

[0056] Reference Figure 3A The non-volatile memory device 455 may include a command address pad set CCAPS and a common command address decoder CADEC. The common command address decoder CADEC may be included in... Figure 2 In the control circuit 450.

[0057] The Command Address Pad Group (CCAPS) may include pads for receiving commands (CMD) and addresses (ADD) provided from the memory controller 20. Based on the commands (CMD) and addresses (ADD) received through the Command Address Pad Group (CCAPS), the Common Command Address Decoder (CADEC) can generate control signals (VCTL) and (PCTL), row address (R_ADDR), and column address (C_ADDR), which are jointly applied to multiple memory planes PL_0 to PL_n-1. Using the Command Address Pad Group (CCAPS) and the Common Command Address Decoder (CADEC), the same operation can be performed simultaneously or in parallel with respect to multiple memory planes PL_0 to PL_n-1.

[0058] In some examples of the embodiments, such as Figure 3B As shown, the non-volatile memory device 457 can receive commands CMD0 to CMDn-1 and addresses ADD0 to ADDn-1 corresponding to the multiple memory planes PL_0 to PL_n-1, respectively, through multiple data pads included in each of a plurality of plane-specific pad groups PDPSM_0 to PDPSM_n-1 independently configured for each memory plane. For example, the non-volatile memory device 457 may include multiple plane-specific command address decoders CADEC_0 to CADEC_n-1, such as... Figure 3BAs shown. Based on commands CMD0 to CMDn-1 and addresses ADD0 to ADDn-1 received from multiple data pads included in each of the multiple plane-specific pad groups PDPSM_0 to PDPSM_n-1, the plane-specific command address decoders CADEC_0 to CADEC_n-1 can generate control signals VCTL0 to VCTLn-1 and PCTL0 to PCTLn-1, row addresses R_ADDR0 to R_ADDRn-1, and column addresses C_ADDR0 to C_ADDRn-1, which are independently applied to each of the multiple memory planes PL_0 to PL_n-1. Using the multiple plane-specific command address decoders CADEC_0 to CADEC_n-1, the same or different operations can be performed simultaneously or in parallel with respect to the multiple memory planes PL_0 to PL_n-1.

[0059] In the following text, reference will be made to Figure 4 , Figure 5A and Figure 5B This describes a vertical NAND flash memory device according to some examples of embodiments. A first direction D1 represents a direction perpendicular to the upper surface of the semiconductor substrate, and a second direction D2 and a third direction D3 represent two directions parallel to the upper surface of the semiconductor substrate. For example, the second direction D2 and the third direction D3 can be perpendicular to each other. The first direction D1 can be referred to as the vertical direction, the second direction D2 as the row direction, and the third direction D3 as the column direction. Directions indicated by arrows in the figures and opposite directions can be considered the same direction.

[0060] Figure 4 It is shown that it includes Figure 2 A block diagram of a memory cell array in a non-volatile memory device. Figure 5A It is shown that it includes Figure 4 A perspective view of an example embodiment of a memory block in a memory cell array.

[0061] Reference Figure 4 The memory cell array (MCA) may include multiple memory blocks BLK1 to BLKz. In some examples of the embodiments, memory blocks BLK1 to BLKz may be composed of... Figure 2 The row decoder 430 selects from memory blocks BLK1 to BLKz, for example, a specific memory block BLK corresponding to a block address.

[0062] Reference Figure 5A The memory block BLKi may include NAND strings or cell strings formed on a substrate in a three-dimensional (or vertical) structure. The memory block BLKi may include a structure extending along a first direction D1, a second direction D2, and a third direction D3.

[0063] A substrate 111 is provided. For example, substrate 111 may have a first type (e.g., a first conductivity type) well. For example, substrate 111 may have a p-well formed by implanting a Group 3 element such as boron (B). For example, substrate 111 may have a pouch-shaped p-well disposed within an n-well. In some examples of the embodiments, substrate 111 has a p-type well (or a p-type pouch-shaped well). However, the conductivity type of substrate 111 is not limited to p-type.

[0064] A plurality of doped regions 311 to 314 extending in the second direction D2 are disposed in / on the substrate 111. For example, the plurality of doped regions 311 to 314 may have a second type (e.g., a second conductivity type) different from the first type of the substrate 111. In some examples of the embodiments, the first doped regions 311 to the fourth doped regions 314 may have an n-type conductivity. However, the conductivity type of the first doped regions 311 to the fourth doped regions 314 is not limited to n-type.

[0065] A plurality of insulating materials 112 extending along a second direction D2 are sequentially disposed along a first direction D1 on a region of a substrate 111 located between a first doped region 311 and a second doped region 312. For example, the plurality of insulating materials 112 extend along the second direction D2 and are spaced apart from each other by a specific distance in the first direction D1. For example, the insulating materials 112 may include insulating materials such as oxide layers.

[0066] A plurality of pillars 113 penetrating the insulating material along a first direction D1 are sequentially disposed along a second direction D2 on the region of the substrate 111 located between the first doped region 311 and the second doped region 312. For example, the plurality of pillars 113 penetrate the insulating material 112 and contact the substrate 111.

[0067] For example, each pillar 113 may comprise a variety of materials. For example, the channel layer 114 of each pillar 113 may comprise a silicon material of a first type. For example, the channel layer 114 of each pillar 113 may comprise a silicon material of the same type as the substrate 111. In some examples of embodiments, the channel layer 114 of each pillar 113 comprises p-type silicon. However, the channel layer 114 of each pillar 113 is not limited to p-type silicon.

[0068] The internal material 115 of each pillar 113 includes an insulating material. For example, the internal material 115 of each pillar 113 may include an insulating material such as silicon oxide. In some examples, the internal material 115 of each pillar 113 may include an air gap.

[0069] The insulating layer 116 can be disposed in the region between the first doped region 311 and the second doped region 312 along the exposed surface of the insulating material 112, the exposed surface of the pillar 113 and the exposed surface of the substrate 111.

[0070] Multiple first conductive materials 211 to 291 may be disposed on the surface of the insulating layer 116 in the region between the first doped region 311 and the second doped region 312. For example, the first conductive material 211 may extend along the second direction D2 and may be disposed between the substrate 111 and the insulating material 112 adjacent to the substrate 111. More specifically, the first conductive material 211 extending along the second direction D2 may be disposed between the substrate 111 and the insulating layer 116 located at the bottom of the insulating material 112 adjacent to the substrate 111. In some examples of embodiments, the first conductive material 211 extending in the second direction D2 may be disposed between the insulating layer 116 located on top of the substrate 111 and the insulating layer 116 located at the bottom of the insulating material 112 adjacent to the substrate 111.

[0071] A first conductive material extending along the second direction D2 may be disposed between an insulating layer 116 on top of a specific insulating material in the insulating material 112 and an insulating layer 116 on the bottom of an insulating material in the insulating material 112 adjacent to and located on the specific insulating material in the insulating material 112. For example, a plurality of first conductive materials 221 to 281 extending along the second direction D2 may be disposed between the insulating materials 112, and it is understood that the insulating layer 116 is disposed between the insulating material 112 and each of the first conductive materials 221 to 281. The first conductive materials 211 to 291 may be formed of a conductive metal. In some examples, the first conductive materials 211 to 291 may include a conductive material such as polycrystalline silicon.

[0072] A structure identical to that on the first doped region 311 and the second doped region 312 can be provided in the region between the second doped region 312 and the third doped region 313. In the region between the second doped region 312 and the third doped region 313, the following are provided: a plurality of insulating materials 112 extending along a second direction D2; a plurality of pillars 113 sequentially arranged along the second direction D2 and penetrating the plurality of insulating materials 112 along a first direction D1; an insulating layer 116 disposed on the exposed surfaces of the plurality of insulating materials 112 and the exposed surfaces of the plurality of pillars 113; and a plurality of conductive materials 213 to 293 extending along the second direction D2.

[0073] Drains 320 can be disposed on a plurality of pillars 113. Second conductive materials 331 to 333 extending along a third direction D3 are disposed on drains 320. The second conductive materials 331 to 333 can be spaced apart from each other in a second direction D2, and in some embodiments, the second conductive materials 331 to 333 can be spaced apart by a specific distance. The second conductive materials 331 to 333 can be connected to the drain 320 in corresponding regions. The drain 320 and the second conductive materials 331 to 333 extending along the third direction D3 can be connected through each contact plug. The second conductive materials 331 to 333 can include metallic materials. The second conductive materials 331 to 333 can include conductive materials, such as polycrystalline silicon.

[0074] Each layer having the first conductive material can correspond to a gate layer, and the first conductive material can form gate lines, such as serial select line (SSL), word line (WL), ground select line (GSL), etc. The second conductive material can form bit lines (BL).

[0075] Figure 5B It shows a reference. Figure 5A The circuit diagram of the equivalent circuit of the described memory block.

[0076] Figure 5B The memory block BLKi can be formed on the substrate in a three-dimensional (or vertical) structure. For example, multiple NAND strings or cell strings included in the memory block BLKi can be formed in a first direction D1 perpendicular to the upper surface of the substrate.

[0077] Reference Figure 5B The memory block BLKi may include NAND strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1 to MC8, and a ground select transistor GST. Figure 5B In the example, each of the NAND strings NS11 to NS33 is shown as comprising eight memory cells MC1 to MC8. However, the example is not limited thereto. In some examples of the embodiment, each of the NAND strings NS11 to NS33 may include any number of memory cells.

[0078] Each string select transistor (SST) can be connected to a corresponding string select line (one of SSL1 to SSL3). Multiple memory cells MC1 to MC8 can be connected to corresponding gate lines GTL1 to GTL8. Gate lines GTL1 to GTL8 can be word lines, and some of GTL1 to GTL8 can be dummy word lines. Each ground select transistor (GST) can be connected to a corresponding ground select line (one of GSL1 to GSL3). Each string select transistor (SST) can be connected to a corresponding bit line (e.g., one of BL1, BL2, and BL3), and each ground select transistor (GST) can be connected to the common source line CSL.

[0079] Word lines of the same height can be connected together, and ground select lines GSL1 to GSL3 and serial select lines SSL1 to SSL3 can be separated. Figure 5B In the diagram, memory block BLKi is shown coupled to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3. However, the example is not limited to this. Each memory block in the memory cell array MCA can be coupled to any number of word lines and any number of bit lines.

[0080] Figure 6 This is a diagram illustrating example control signals for a non-volatile memory device according to some examples of embodiments. Figures 7 to 10 This is a timing diagram illustrating example operating modes of a non-volatile memory device according to some examples of embodiments.

[0081] Figure 7 An example read operation is shown. Figure 8 An example write operation is shown. Figure 9 An example of setting feature operations is shown. Figure 10 An example of feature acquisition operation is shown.

[0082] Figures 6 to 10 The logic levels and waveforms of the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal / RE, data strobe signals DQS and / DQS, data signal DQx, and ready / busy signal R / B are shown. Figures 6 to 10In this context, H represents logic high level, L represents logic low level, Hi-Z represent high impedance state, tWC represents write cycle time, tRC represents read cycle time, tR represents data transfer time from the memory cell array to the page buffer circuit, tPROG represents programming time, tFEAT represents busy time for setting or fetching features, 00h, 30h, 80h, 10h, EEh, and EFh represent commands for various operations, and XXh represents the register address associated with feature information or feature data. D0 to Dn represent reading or writing data, R-B0 to R-B3 represent reading feature data, and R-W0 to R-W3 represent writing feature data.

[0083] Reference Figures 6 to 10 According to some examples of embodiments, non-volatile memory devices can synchronize with the conversion of the read enable signal / RE to read data through multiple data pads included in each of multiple dedicated planar pad groups.

[0084] Additionally, the non-volatile memory device can synchronize with the write enable signal / WE to latch commands and addresses received through multiple data pads included in each of the multiple planar dedicated pad groups. Furthermore, the non-volatile memory device can receive write data or output read data through multiple data pads included in each of the multiple planar dedicated pad groups when the write enable signal / WE is activated.

[0085] In addition, the non-volatile memory device can selectively receive commands or addresses received through multiple data pads included in each of multiple planar dedicated pad groups based on the command latch enable signal CLE and the address latch enable signal ALE.

[0086] Figure 11 This is a block diagram illustrating a memory system including a non-volatile memory device with a multiplexing structure.

[0087] Reference Figure 11 The memory system 50 includes a memory controller 60 and a memory device 70.

[0088] Memory device 70 may be a non-volatile memory device. Memory system 50 may include flash memory-based data storage media, such as memory cards, Universal Serial Bus (USB) memory, and / or solid-state drives (SSDs).

[0089] The non-volatile memory device 70 that accompanies the routing of data signals may include multiple memory planes PL_0 to PL_n-1, multiple data paths DTPH0 to DTPHn-1, a multiplexer MUX, and a common pad group CPSM.

[0090] Each of the plurality of memory planes PL_0 to PL_n-1 may include a corresponding one of a plurality of memory cell arrays MCA0 to MCAn-1 having non-volatile memory cells and a corresponding one of a plurality of page buffer circuits PBC0 to PBCn-1. Each page buffer circuit PBC0 to PBCn-1 may be connected via bit lines to the non-volatile memory cells included in each of the memory cell arrays MCA0 to MCAn-1. In other words, the first memory plane PL_0 includes a first memory cell array MCA0 and a first page buffer circuit PBC0, the second memory plane PL_1 includes a second memory cell array MCA1 and a second page buffer circuit PBC1, and in this way, the nth memory plane PL_n-1 includes the nth memory cell array MCAn-1 and the nth page buffer circuit PBCn-1. Each of the data paths DTPH0 to DTPHn-1 may include as referenced Figure 2 The aforementioned data input / output circuit.

[0091] The multiplexer MUX can selectively connect the common pad group CPSM to one of multiple data paths DTPH0 to DTPHn-1 in response to the plane selection signal PSEL.

[0092] The common pad group CPSM may include multiple data pads DQ0 to DQm-1. The memory controller 60 may include a host pad group CPSC corresponding to the common pad group CPSM. The host pad group CPSC may include multiple data pads DQ0 to DQm-1 connected to the multiple data pads DQ0 to DQm-1 included in the common pad group CPSM, such that each of the multiple data pads DQ0 to DQm-1 of the host pad group CPSC is dedicated to each of the multiple data pads DQ0 to DQm-1 of the common pad group CPSM.

[0093] Non-volatile memory device 70 with this multiplexing structure requires a circuit and a multiplexer MUX, wherein the circuit generates a plane selection signal PSEL based on information about the plane to be selected, and the multiplexer MUX routes data to the selected plane. This data routing structure increases power consumption. In particular, power consumption increases further as the basic x8 structure is extended to x32, x64, x128, etc.

[0094] Figure 12 It is shown Figure 11 A diagram illustrating the multiplane operation of a non-volatile memory device.

[0095] Reference Figure 12The non-volatile memory device 70 with a multiplexing structure sequentially receives addresses for read operations on multiple memory planes PL_0 to PL_n-1 via data pads DQ0 to DQm-1 included in the common pad group CPSM. Figure 12 The commands 00h and 30h shown are consistent with the reference. Figures 6 to 10 The same applies. tWC represents the cycle time of the write enable signal / WE, i.e., the write cycle time, and transferring the address ADD of one memory plane takes time k*tWC, where k is a positive integer related to the address cycle number. Therefore, transferring the addresses of n memory planes PL_0 to PL_n-1 takes time n*k*tWC. Figure 12 In this context, tR represents the data transfer time from the memory cell array to the page buffer circuit. After time tR, read data DOUT from memory planes PL_0 to PL_n-1 can be sequentially output via data pads DQ0 to DQm-1. When tDMA is the data output time for one memory plane, outputting read data DOUT for n memory planes PL_0 to PL_n-1 may require time n*tDMA.

[0096] Figure 13 This is a diagram illustrating multi-plane operation of a non-volatile memory device according to some examples of embodiments.

[0097] Reference Figure 1 , Figure 2 and Figure 13 According to some examples of embodiments, the non-volatile memory device 30 can simultaneously receive addresses for read operations on multiple memory planes PL_0 to PL_n-1 via n*m data pads DQ0 to DQnm-1 included in multiple dedicated planar pad groups PDPSM_0 to PDPSM_n-1. Additionally, the non-volatile memory device 30 can simultaneously output read data DOUT from multiple memory planes PL_0 to PL_n-1 via n*m data pads DQ0 to DQnm-1.

[0098] like Figure 12 and Figure 13 As shown, compared to a non-volatile memory device 70 with a multiplexing structure, a non-volatile memory device 30 with multiple planar dedicated pad groups according to some examples of embodiments can significantly reduce data read time.

[0099] In a non-volatile memory device 30 according to some example embodiments, multiple planar dedicated pad groups PDPSM_0 to PDPSM_n-1 can respectively receive read data corresponding to multiple memory planes PL_0 to PL_n-1 from multiple page buffer circuits PBC0 to PBCn-1, and simultaneously provide the read data corresponding to the multiple memory planes PL_0 to PL_n-1 to the memory controller 20. During write operations, to... Figure 13 In the same manner as the read operation, multiple dedicated planar pad groups PDPSM_0 to PDPSM_n-1 can simultaneously receive write data corresponding to multiple memory planes PL_0 to PL_n-1 from the memory controller 20 through multiple data pads included in the multiple dedicated planar pad groups PDPSM_0 to PDPSM_n-1, and provide the write data corresponding to the multiple memory planes PL_0 to PL_n-1 to multiple page buffer circuits PBC0 to PBCn-1 respectively.

[0100] Compared to the non-volatile memory device 70 with a multiplexing structure, in some examples of the non-volatile memory device 30 according to embodiments, the multiple data pads included in each of the multiple planar dedicated pad groups PDPSM_0 to PDPSM_n-1 are connected to a corresponding one of the multiple page buffer circuits PBC0 to PBCn-1, rather than being connected to other page buffer circuits via a multiplexer.

[0101] Thus, the non-volatile memory device 30 and memory system 10 according to some examples of embodiments can reduce power consumption by eliminating data multiplexing and / or signal routing and using multiple plane-specific pad groups PDPSM_0 to PDPSM_n-1 that are respectively assigned to multiple memory planes PL_0 to PL_n-1.

[0102] Figure 14 This is a diagram illustrating the address layout of a non-volatile memory device according to some examples of embodiments.

[0103] Reference Figure 14 The first address layout ADDLO1 corresponds to, as shown in the reference... Figure 11 and Figure 12 The non-volatile memory device 70 with a multiplexing structure, wherein the second address layout ADDLO2 corresponds to, according to reference... Figure 1 , Figure 2 and Figure 13 The described embodiments include some examples of non-volatile memory devices 30.

[0104] The non-volatile memory device 70 with a multiplexed structure receives plane addresses for data multiplexing. Conversely, the non-volatile memory device 30 of some examples according to embodiments does not require plane addresses because commands and addresses for each memory plane can be received through dedicated pad sets for each plane. As a result, compared to the non-volatile memory device 70 with a multiplexed structure, the non-volatile memory device 30 of some examples according to embodiments can reduce the address transfer time by the time ts for plane address transfer. In other words, Figure 13 The time q*tWC in the middle can be compared to Figure 12 The time k*tWC in the middle is short.

[0105] Figures 15 to 22 This is a diagram illustrating example operation of a non-volatile memory device according to some embodiments. For ease of illustration and description, it is assumed that the non-volatile memory device includes eight memory planes, and each plane has a dedicated pad group including... Figures 15 to 22 The example embodiment shows eight data pads, but the number of memory planes and the number of data pads are not limited to this.

[0106] Reference Figure 15 , Figure 16 and Figure 17 The memory system 11 may include a memory controller 21 and at least one memory device 31.

[0107] The memory device 31 may be a non-volatile memory device, and the memory system 11 may include flash memory-based data storage media, such as memory cards, Universal Serial Bus (USB) memory, and / or solid-state drives (SSDs).

[0108] The non-volatile memory device 31 can perform read, erase, program, and / or write operations under the control of the memory controller 21. The non-volatile memory device 31 can receive commands (CMD) and addresses (ADD), and can exchange data with the memory controller 21 for read and program operations. Additionally, the non-volatile memory device 31 can receive control signals and power from the memory controller 21.

[0109] The non-volatile memory device 31 may include multiple memory planes, such as eight memory planes PL_0 to PL7, eight data paths (not shown) as described above, and eight dedicated pad groups PDPSM_0 to PDPSM_7.

[0110] Each of the eight memory planes PL_0 to PL_7 may include each of the eight memory cell arrays MCA0 to MCA7 having non-volatile memory cells and each of the eight page buffer circuits PBC0 to PBC7. Each of the eight page buffer circuits PBC0 to PBC7 may be connected via bit lines to the non-volatile memory cells included in each of the eight memory cell arrays MCA0 to MCA7. In other words, the first memory plane PL_0 may include the first memory cell array MCA0 and the first page buffer circuit PBC0, the second memory plane PL_1 may include the second memory cell array MCA1 and the second page buffer circuit PBC1, and in this way, the eighth memory plane PL_7 may include the eighth memory cell array MCA7 and the eighth page buffer circuit PBC7. In some examples of the embodiments, the size of each of the page buffer circuits PBC0 to PBC7 may correspond to the page size or the number of bit lines of each memory plane.

[0111] Each of the eight planar dedicated pad groups PDPSM_0 to PDPSM_7 may include eight data pads. For example, the first planar dedicated pad group PDPSM_0 may include eight data pads DQ0 to DQ7, the second planar dedicated pad group PDPSM_1 may include eight data pads DQ8 to DQ15, and in this way, the eighth planar dedicated pad group PDPSM_7 may include eight data pads DQ56 to DQ63. In other words, each of the eight planar dedicated pad groups PDPSM_0 to PDPSM_7 may each include eight data pads, and the total number of data pads DQ0 to DQ63 may be 8*8 = 64.

[0112] The memory controller 21 may include eight host pad groups PDPSC_0 to PDPSC_7, each of which is connected to one of eight planar dedicated pad groups PDPSM_0 to PDPSM_7, such that each of the eight host pad groups PDPSC_0 to PDPSC_7 is dedicated to each of the eight planar dedicated pad groups PDPSM_0 to PDPSM_7. Each of the eight host pad groups PDPSC_0 to PDPSC_7 may include eight host data pads, which are connected to eight data pads included in each of the eight planar dedicated pad groups PDPSM_0 to PDPSM_7, such that each of the eight host data pads is dedicated to each of the eight data pads. In other words, each of the first host pad group PDPSC_0 and the first planar dedicated pad group PDPSM_0 may include eight data pads DQ0 to DQ7, each of the second host pad group PDPSC_1 and the second planar dedicated pad group PDPSM_1 may include eight data pads DQ8 to DQ15, and in such a way, each of the eighth host pad group PDPSC_7 and the eighth planar dedicated pad group PDPSM_7 may include eight data pads DQ56 to DQ63.

[0113] Figure 15 , Figure 16 and Figure 17 An example of an input-output mapping structure is shown. For example... Figure 15 As shown, in an eight-memory-plane architecture with a page size of 4KB, write and read operations can be performed in 32KB units. When only reading or writing 4KB of data, two scenarios are possible. First, through multi-plane operations on the eight memory planes PL_0 to PL_7, such as... Figure 16 As shown, each memory plane can be operated in 512-byte units. In this case, 4KB can be read from each memory plane, and then random read operations can be performed in 512-byte units. Secondly, it may be necessary to consider specific memory planes (e.g., such as...). Figure 17 The random read operation is shown for the first memory plane PL_0. In this case, only the specific memory plane PL_0 can be enabled, and the other memory planes PL_1 to PL_7 can be disabled.

[0114] In this way, the non-volatile memory device 31 can receive commands and addresses from the memory controller 21 through multiple data pads included in a portion of the multiple plane dedicated pad groups PDPSM_0 to PDPSM_7, to perform read or write operations on a portion of the memory planes PL_0 to PL_7 corresponding to that portion of the multiple plane dedicated pad groups PDPSM_0 to PDPSM_7. The internal configuration of the non-volatile memory device can be implemented according to high-bandwidth sequential read operations or random read operations.

[0115] Reference Figure 18 The non-volatile memory device 31, which includes multiple planar dedicated pad groups PDPSM_0_PDPSM_7, can receive the start address for read or write operations through multiple data pads DQ[7:0] included in one of the multiple planar dedicated pad groups PDPSM_0_PDPSM_7, and can receive the end address for read and write operations through multiple data pads DQ[15:8] included in another of the multiple planar dedicated pad groups PDPSM_0 to PDPSM_7. Figure 18 An example is shown where write and read operations can be implemented similarly.

[0116] Reference Figure 19 and Figure 20 The non-volatile memory device 31, comprising multiple planar dedicated pad groups PDPSM_0_PDPSM_7, can receive write data or output read data through multiple data pads DQ[7:0] included in one of the multiple planar dedicated pad groups PDPSM_0 to PDPSM_7, and output indicators such as Figure 19 The characteristic information FIOUT of the operating conditions of the non-volatile memory device 31 shown can be received, or it can be received through multiple data pads included in another of the multiple planar dedicated pad groups PDPSM_0 to PDPSM_7. Figure 20 The feature information FI IN is shown.

[0117] Reference Figure 21 The non-volatile memory device 31, comprising multiple planar dedicated pad groups PDPSM_0 to PDPSM_7, can simultaneously receive commands and addresses via multiple data pads DQ[7:0] to DQ[63:56] included in at least two of the multiple planar dedicated pad groups PDPSM_0 to PDPSM_7. Therefore, the transmission time of commands and addresses can be further reduced.

[0118] Reference Figure 22The non-volatile memory device 31, comprising multiple planar dedicated pad groups PDPSM_0_PDPSM_7, can perform a first multi-plane operation MPOP1, a second multi-plane operation MPOP2, and / or a third multi-plane operation MPOP3. In the first multi-plane operation MPOP1, the non-volatile memory device 31 can perform read operations RD for all memory planes PL_0 to PL_7. In the second multi-plane operation MPOP2, the non-volatile memory device 31 can perform write operations PGM for all memory planes PL_0 to PL_7. In the third multi-plane operation MPOP3, the non-volatile memory device 31 can use multiple data pads included in a portion of the multiple plane dedicated pad groups PDPSM_0 to PDPSM_7 that correspond to a portion of the multiple memory planes PL_0 to PL_7 to perform a read operation RD for that portion of the multiple memory planes PL_0 to PL_7. At the same time, the non-volatile memory device 31 can use multiple data pads included in another portion of the multiple plane dedicated pad groups PDPSM_0 to PDPSM_7 that correspond to another portion of the multiple memory planes PL_0 to PL_7 to perform a write operation PGM for the other portion of the multiple memory planes PL_0 to PL_7.

[0119] For such multi-plane operations, the non-volatile memory device 31 can receive commands CMD0 to CMD7 and addresses ADD0 to ADD7 corresponding to each of the multiple memory planes PL_0 to PL_7 via multiple data pads included in each of the multiple plane-specific pad groups PDPSM_0 to PDPSM_7, wherein the multiple plane-specific pad groups PDPSM_0 to PDPSM_7 are set independently for each memory plane. The addresses ADD0 to ADD7 corresponding to each of the multiple memory planes PL_0 to PL_7 can be determined independently, thus operations can be performed for different memory blocks and / or different pages PGa, PGb, and PGH, such as... Figure 22 As shown.

[0120] Figure 23 , Figure 24 and Figure 25 This is a diagram illustrating an example layout of a non-volatile memory device according to some examples of embodiments. For ease of illustration and description, Figure 23 , Figure 24 and Figure 25 The pads in the attached diagram are labeled with Figures 6 to 10 The symbols in the attached diagram are the same.

[0121] Reference Figure 23 , Figure 24 and Figure 25Each of the dedicated planar pad groups PDPSM_0 to PDPSM_7 may further include a pad configured to receive each of the data strobe signals DQS0 to DQS7 provided from the memory controller. For example... Figures 6 to 10 As shown, the non-volatile memory device can receive write data synchronously with the conversion of the data strobe signal DQS through multiple data pads included in each of the multiple planar dedicated pad groups PDPSM_0 to PDPSM_7.

[0122] like Figure 23 , Figure 24 and Figure 25 As shown, each of the planar dedicated pad groups PDPSM_0 to PDPSM_7 may further include at least one control pad, which is configured to receive at least one control signal provided from the memory controller for specifically controlling the operation of each of the plurality of memory planes PL_0 to PL_7 corresponding to each of the plurality of planar dedicated pad groups PDPSM_0 to PDPSM_7.

[0123] exist Figure 23 In the non-volatile memory device 33, all control pads / CE, R / B, / RE, / WE, CLE, and ALE can be included in the common pad group CPSMa. Figure 24 In the non-volatile memory device 35, control pads / CE, R / B, CLE, and ALE may be included in the common pad group CPSMb, and control pads / RE0 to / RE7 and / WE0 to / WE7 may be included in each of the planar dedicated pad groups PDPSM_0 to PDPSM_7. Figure 25 In the non-volatile memory device 37, control pads / CE and R / B may be included in the common pad group CPSSMc, and control pads / RE0 to / RE7, / WE0 to / WE7, CLE0 to CLE7 and ALE0 to ALE7 may be included in each of the planar dedicated pad groups PDPSM_0 to PDPSM_7.

[0124] Reference Figure 23 , Figure 24 and Figure 25Planar dedicated pad groups PDPSM_0 to PDPSM_7 can be positioned in the center of the semiconductor die. The non-volatile memory device in the semiconductor die is formed such that each of the multiple planar dedicated pad groups PDPSM_0 to PDPSM_7 can be adjacent to each of the multiple memory planes PL_0 to PL_7. This structure can be called a center pad structure with a wide input / output architecture. Overhead due to signal routing and power consumption can be reduced because the connection length between the data pads and page buffers can be shortened in the center pad structure. A redistribution layer (RDL) can be used to implement the connection between the pads and the package balls.

[0125] Figure 26 This is a block diagram illustrating a mobile system including a non-volatile memory device according to some examples of embodiments.

[0126] Reference Figure 26 The mobile system 3000 includes an application processor (AP) 3100, a connectivity unit 3200, a volatile memory device (VM) 3300, a non-volatile memory device (NVM) 3400, a user interface 3500, and a power supply 3600, all connected via a bus.

[0127] Application processor 3100 can execute applications such as web browsers, game applications, video players, etc. Connection unit 3200 can perform wired or wireless communication with external devices. Volatile memory device 3300 can store data processed by application processor 3100, or can operate as working memory. For example, volatile memory device 3300 can be DRAM, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power DDR (LPDDR) SDRAM, Graphics DDR (GDDR) SDRAM, Rambus DRAM (RDRAM), etc. Non-volatile memory device 3400 can store boot images and other data used to boot the mobile system 3000. User interface 3500 can include at least one input device such as a keypad, touchscreen, etc., and at least one output device such as a speaker, display device, etc. Power supply 3600 can provide power to mobile system 3000. In some examples of embodiments of the present invention, the mobile system 3000 may also include a camera image processor (CIS) and / or a memory device, such as a memory card, a solid-state drive (SSD), a hard disk drive (HDD), an optical disc read-only memory (CD-ROM), etc.

[0128] The non-volatile memory device 3400 may include, as referenced Figures 1 to 25The aforementioned multiple planar dedicated pad groups. As described above, each of the multiple planar dedicated pad groups may include multiple data pads, which are dedicatedly connected to each of the multiple page buffer circuits via each of the multiple data paths, such that the multiple data pads receive write data from the memory controller to provide write data to each of the multiple page buffer circuits, and receive read data from each of the multiple page buffer circuits to provide read data to the memory controller.

[0129] As described above, some examples of non-volatile memory devices and memory systems according to embodiments can increase data transmission bandwidth by reducing data transmission latency and supporting parallel data transmission through multiple plane-specific pad groups respectively allocated to multiple memory planes. Additionally, some examples of non-volatile memory devices and memory systems according to embodiments can reduce power consumption by eliminating data multiplexing and / or signal routing and using multiple plane-specific pad groups respectively allocated to multiple memory planes.

[0130] This invention concept can be applied to non-volatile memory devices and systems that include non-volatile memory devices. For example, this invention concept can be applied to systems such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMC), mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable camcorders, personal computers (PCs), server computers, workstations, laptops, digital televisions, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0131] The foregoing description is illustrative of some examples of the embodiments and should not be construed as limiting them. Although only a few examples of embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the examples of the embodiments and the inventive concept without substantially departing from the inventive concept.

Claims

1. A non-volatile memory device, comprising: Multiple memory planes, including multiple page buffer circuits and multiple memory cell arrays including non-volatile memory cells, wherein each of the multiple page buffer circuits is connected via a bit line to one of the non-volatile memory cells included in a corresponding memory cell array of the multiple memory cell arrays. as well as Multiple planar dedicated pad groups are connected to multiple page buffer circuits via multiple data paths, such that each of the multiple planar dedicated pad groups is connected to a corresponding page buffer circuit in the multiple page buffer circuits. Each of the plurality of data paths includes a corresponding data input / output circuit. The number of the plurality of dedicated planar pad groups is the same as the number of the plurality of data paths. Each of the plurality of dedicated planar pad groups is connected to one of the plurality of page buffer circuits via the plurality of data paths, such that each of the plurality of dedicated planar pad groups is dedicatedly connected to each of the plurality of page buffer circuits. The non-volatile memory device does not receive plane addresses, and the plurality of dedicated plane pad groups each independently receive commands and addresses to independently determine the address corresponding to each of the plurality of memory planes.

2. The nonvolatile memory device of claim 1, wherein, Each of the plurality of planar dedicated pad groups includes: Multiple data pads are dedicated to a corresponding page buffer circuit in the plurality of page buffer circuits and are configured to receive write data from the memory controller to provide the write data to the corresponding page buffer circuit in the plurality of page buffer circuits, and are configured to receive read data from the corresponding page buffer circuit in the plurality of page buffer circuits to provide the read data to the memory controller.

3. The nonvolatile memory device of claim 2, wherein, The plurality of dedicated planar pads are configured to simultaneously receive write data corresponding to the plurality of memory planes from the memory controller, and to provide the write data corresponding to the plurality of memory planes to the plurality of page buffer circuits respectively. The plurality of dedicated planar pads are configured to simultaneously receive read data corresponding to the plurality of memory planes from the plurality of page buffer circuits, and provide the read data corresponding to the plurality of memory planes to the memory controller.

4. The nonvolatile memory device of claim 2, wherein, The data path between the data pads and the corresponding page buffer circuits in the first planar dedicated pad group of the plurality of planar dedicated pad groups does not include a multiplexer.

5. The nonvolatile memory device of claim 2, wherein, The non-volatile memory device is configured to receive commands and addresses from the memory controller via data pads in a plurality of data pads included in at least one of the plurality of planar dedicated pad groups.

6. The nonvolatile memory device of claim 5, wherein, The command and the address correspond to a first memory plane among the plurality of memory planes, and wherein the non-volatile memory device is configured to receive the command and the address corresponding to the first memory plane via a dedicated set of planar pads connected to the page buffer circuit of the first memory plane.

7. The nonvolatile memory device of claim 5, wherein, The non-volatile memory device is configured to receive the command and the address from the memory controller via a portion of the plurality of planar dedicated pad groups to perform a read or write operation on a portion of the memory plane corresponding to the portion of the plurality of planar dedicated pad groups.

8. The nonvolatile memory device of claim 5, wherein, The non-volatile memory device is configured to receive a start address for a read operation or a write operation via a first planar dedicated pad group among the plurality of planar dedicated pad groups, and is configured to receive an end address for the read operation or the write operation via a second planar dedicated pad group among the plurality of planar dedicated pad groups.

9. The nonvolatile memory device of claim 5, wherein, The non-volatile memory device is configured to receive the write data or output the read data via a first planar dedicated pad group among the plurality of planar dedicated pad groups, and is configured to receive or output feature information indicating the operating conditions of the non-volatile memory device via a second planar dedicated pad group among the plurality of planar dedicated pad groups.

10. The nonvolatile memory device of claim 5, wherein, The non-volatile memory device is configured to perform read operations on a first portion of the memory plane corresponding to a first portion of the plurality of dedicated planar pad groups, and simultaneously to perform write operations on a second portion of the memory plane corresponding to a second portion of the plurality of dedicated planar pad groups.

11. The nonvolatile memory device of claim 2, wherein, Each of the plurality of planar dedicated pad groups also includes: At least one control pad is configured to receive at least one control signal provided from the memory controller and to control the operation of a corresponding memory plane among the plurality of memory planes that corresponds to a dedicated pad group for that plane.

12. The nonvolatile memory device of claim 2, wherein, Each of the plurality of planar dedicated pad groups also includes: The pads are configured to receive data strobe signals provided from the memory controller. The non-volatile memory device is configured to receive the write data synchronously with the conversion of the data strobe signal via a data pad among a plurality of data pads included in each of the plurality of planar dedicated pad groups.

13. The nonvolatile memory device of claim 2, wherein, Each of the plurality of planar dedicated pad groups also includes: The pads are configured to receive a read enable signal provided from the memory controller. The non-volatile memory device is configured to output the read data synchronously with the conversion of the read enable signal via a data pad in one of the plurality of data pads included in each of the plurality of planar dedicated pad groups.

14. The nonvolatile memory device of claim 2, wherein, Each of the plurality of planar dedicated pad groups also includes: The pads are configured to receive a write enable signal provided from the memory controller. The non-volatile memory device is configured to: synchronize with the transition of the write enable signal, latch commands and addresses received via data pads in a plurality of data pads included in each of the plurality of planar dedicated pad groups, and The non-volatile memory device is configured to receive the write data and / or output the read data through a data pad in one of a plurality of data pads included in each of the plurality of planar dedicated pad groups, while the write enable signal is activated.

15. The nonvolatile memory device of claim 2, wherein, Each of the plurality of planar dedicated pad groups also includes: A first pad, configured to receive a command latch enable signal provided from the memory controller; and The second pad is configured to receive an address latch enable signal provided from the memory controller. The non-volatile memory device is configured to selectively receive commands or addresses received via data pads in a plurality of data pads included in each of the plurality of planar dedicated pad groups, based on the command latch enable signal and the address latch enable signal.

16. The non-volatile memory device according to claim 1, further comprising: Command address pad group, which includes pads configured to receive commands and addresses provided from the memory controller; as well as A common command address decoder is configured to generate control signals, row addresses, and column addresses that are jointly applied to the plurality of memory planes based on commands and addresses received through the command address pad group.

17. A memory system comprising: Non-volatile memory devices; and A memory controller configured to control the operation of the non-volatile memory device. The non-volatile memory device includes: Multiple memory planes, each including multiple page buffer circuits, are connected via bit lines to multiple memory cell arrays comprising multiple non-volatile memory cells. Each page buffer circuit is connected via the bit lines to a non-volatile memory cell within the corresponding memory cell array. Multiple planar dedicated pad groups are connected to multiple page buffer circuits via multiple data paths. Each data path includes a corresponding data input / output circuit. The number of the plurality of dedicated planar pad groups is the same as the number of the plurality of data paths. Each of the plurality of dedicated planar pad groups is connected to one of the plurality of page buffer circuits via the plurality of data paths, such that each dedicated planar pad group is specifically connected to one of the plurality of page buffer circuits via one of the plurality of data paths. The non-volatile memory device does not receive plane addresses, and the plurality of dedicated plane pad groups each independently receive commands and addresses to independently determine the address corresponding to each of the plurality of memory planes.

18. The memory system of claim 17, wherein, The memory controller includes: Multiple host pad groups, which are respectively connected to the multiple planar dedicated pad groups.

19. The memory system according to claim 18, wherein, Each of the plurality of planar dedicated pad groups includes: Multiple data pads, dedicated to corresponding page buffer circuits via data paths, are configured to receive write data from the memory controller and provide the write data to the corresponding page buffer circuit, and to receive read data from the corresponding page buffer circuit and provide the read data to the memory controller. Each of the plurality of host pad groups includes: Multiple host data pads are connected to data pads in a plurality of data pads included in each of the plurality of planar dedicated pad groups, such that each of the plurality of host data pads is dedicated to each of the plurality of data pads.

20. A vertical NAND flash memory device, comprising: Multiple memory planes, each memory plane including page buffer circuitry and a memory cell array, the memory cell array including flash memory cells stacked in a vertical direction to form a cell string, wherein each page buffer circuit is connected via a bit line to the cell string included in the memory cell array; as well as Multiple dedicated planar pad groups are connected to the multiple memory planes via multiple data paths. Each data path includes a corresponding data input / output circuit. The number of the plurality of dedicated planar pad groups is the same as the number of the plurality of data paths. Each of the plurality of dedicated planar pad groups is connected to the page buffer circuit through the plurality of data paths, such that each dedicated planar pad group is specifically connected to one of the plurality of memory planes through its corresponding data path and corresponding page buffer circuit. The vertical NAND flash memory device does not receive plane addresses; each of the plurality of dedicated plane pad groups independently receives commands and addresses to independently determine the address corresponding to each of the plurality of memory planes.

Images