A semiconductor package and a manufacturing method thereof

Abstract

The present invention discloses a semiconductor package and a manufacturing method. The semiconductor package includes: a redistribution layer including a first surface and a second surface opposite to the first surface; a plurality of first connectors connected to the first surface of the redistribution layer; a plurality of chips all disposed on a side of the first connectors away from the redistribution layer and all connected to the first connectors; a plurality of interposers all connected to the second surface of the redistribution layer, a groove being formed between two adjacent interposers, and a side surface of the groove close to the redistribution layer being in direct contact with the second surface of the redistribution layer; and a plurality of second connectors connected to a side of the interposers away from the redistribution layer, wherein the chips are electrically connected to the second connectors through the first connectors, the redistribution layer, and the interposers. The provision of the groove effectively avoids chipping of the semiconductor package during the manufacturing process due to warping of the interposer substrate, improving the yield of the semiconductor package.

Description

Technical Field

[0001] The present invention generally relates to a semiconductor device packaging technology, and in particular, to a semiconductor package and a manufacturing method thereof. Background Art

[0002] With the rapid development of wireless communications, automotive electronics and other consumer electronics, microelectronics packaging technology is developing towards multi-function, miniaturization, portability, high speed, low power consumption and high reliability. In order to achieve miniaturization, high speed and modularization of electronic devices, one of the packaging technologies is to package multiple chips together to form a packaged device, and then install the packaged device on a printed circuit board.

[0003] In the existing multi-chip packaging technology, multiple chips are usually packaged on an intermediate substrate. As the number of chips increases or the chip size increases, the size of the intermediate substrate becomes larger and larger, and the size of the intermediate substrate is usually larger than 40mm×40mm. However, when a larger-sized intermediate substrate is used as a supporting element for semiconductor packaging, it often has obvious warping, which is particularly obvious during the reflow process. In the manufacturing process of semiconductor packages, the warping of the intermediate substrate will reduce the process yield and affect the reliability of the package.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] A main object of the present invention is to overcome at least one of the above-mentioned defects of the prior art and provide a semiconductor package, which comprises:

[0007] A redistribution layer, comprising a first surface and a second surface opposite to the first surface;

[0008] A plurality of first connectors connected to the first surface of the redistribution layer;

[0009] A plurality of chips are arranged on a side of the first connecting member away from the redistribution layer and are connected to the first connecting member;

[0010] A plurality of interposers are connected to the second surface of the redistribution layer, a groove is formed between two adjacent interposers, and a side surface of the groove close to the redistribution layer is in direct contact with the second surface of the redistribution layer; and

[0011] A plurality of second connecting members connected to a side of the interposer away from the redistribution layer,

[0012] The chip is electrically connected to the second connector through the first connector, the redistribution layer, and the intermediate component.

[0013] According to an embodiment of the present invention, the redistribution layer includes an etch stop layer covering the groove.

[0014] According to an embodiment of the present invention, the chip and the interposer are both square plates.

[0015] The chip includes a first side and a second side adjacent to the first side, the interposer includes a third side parallel to the first side and a fourth side adjacent to the third side and parallel to the second side,

[0016] The sum of the lengths of the third sides of the plurality of intermediate members is greater than twice the length of the first side, and the sum of the lengths of the fourth sides of the plurality of intermediate members is greater than twice the length of the second side.

[0017] According to one embodiment of the present invention, the length of the third side is less than or equal to 1.2 times the length of the first side, and the length of the fourth side is less than or equal to 1.2 times the length of the second side.

[0018] According to an embodiment of the present invention, the length of the third side ranges from 0.2 to 0.8 times the length of the first side, and the length of the fourth side ranges from 0.2 to 0.8 times the length of the second side.

[0019] According to an embodiment of the present invention, a plurality of the interposers are arranged in a matrix on the second surface of the redistribution layer.

[0020] According to an embodiment of the present invention, two adjacent chips are separated from each other to form a gap between the two adjacent chips, and the gap is aligned with a groove located on the other side of the redistribution layer.

[0021] According to an embodiment of the present invention, the semiconductor package further comprises a first molding member, wherein the first molding member is used to package the redistribution layer, the first connector and the chip together;

[0022] The first molded part includes a first molding layer filled between the chip and the redistribution layer, and a plurality of first through-holes for accommodating the first connectors are provided on the first molding layer;

[0023] The first molded part further includes a second molding layer extending from the first molding layer toward the chip direction and filling the gaps between adjacent chips.

[0024] According to an embodiment of the present invention, the surface of the chip facing away from the first connector is exposed from the first molded part.

[0025] According to an embodiment of the present invention, the semiconductor package further includes a second molded part;

[0026] The second molded part includes a third molding layer covering the surface of the plurality of interposers facing away from the redistribution layer and covering the grooves, and a plurality of second through-holes for passing the second connectors are provided on the third molding layer;

[0027] The second molded part further includes a filling portion connecting the third molding layer and filling the grooves.

[0028] According to an embodiment of the present invention, at least two chips are electrically connected to each other through the first connectors and the redistribution layer.

[0029] According to an embodiment of the present invention, a through-silicon via is provided in the interposer, one end of which is connected to the redistribution layer and the other end is connected to the second connector.

[0030] An embodiment of the present invention also provides a method for manufacturing a semiconductor package, which includes:

[0031] Providing a redistribution layer on an interposer board and electrically connecting the interposer board to the redistribution layer;

[0032] Connecting the redistribution layer to multiple chips using a plurality of first connectors;

[0033] Forming a first molded part encapsulating the plurality of first connectors, the multiple chips, and the redistribution layer together;

[0034] Cutting the interposer board to form a plurality of separated interposers, and a groove is formed between adjacent two interposers;

[0035] Forming a second molded part encapsulating the multiple interposers together;

[0036] Connecting a second connector to the interposer and electrically connecting the chip to the second connector through the first connector, the redistribution layer, and the interposer.

[0037] According to an embodiment of the present invention, during the process of disposing the redistribution layer on the interposer, an etch stop layer is formed on the surface of the interposer.

[0038] The interposer is cut by an etching method, and the slit on the interposer is aligned with the etch stop layer, so that the etch stop layer blocks the etching of the redistribution layer.

[0039] According to an embodiment of the present invention, the method further includes: after forming the first molded part, grinding the first molded part to expose a partial surface of the chip.

[0040] According to an embodiment of the present invention, the interposer has through-silicon vias.

[0041] The method further includes: before cutting the interposer, grinding the interposer to expose the through-silicon vias in the interposer.

[0042] According to an embodiment of the present invention, after forming the second molded part, the second molded part is further drilled to form a second through hole exposing the through-silicon vias.

[0043] The second connector is connected to the through-silicon vias through the second through hole.

[0044] As can be seen from the above technical solutions, the advantages and positive effects of the semiconductor package and the manufacturing method of the present invention are as follows:

[0045] The chip can be electrically connected to the second connector through the first connector, the redistribution layer and the interposer in sequence, and the second connector can be used as an external interface of the semiconductor package to be connected to other electronic devices. At the same time, since a groove is formed between adjacent two interposers, and the groove is an expansion joint of the interposer substrate composed of multiple interposers, it can become narrower or wider along with the thermal expansion and contraction of the semiconductor package during the semiconductor package manufacturing process, effectively avoiding the chip cracking due to the warping of the interposer substrate during the semiconductor package manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] By considering the following detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings, various objectives, features and advantages of the present invention will become more obvious. The drawings are only illustrative diagrams of the present invention and are not necessarily drawn to scale. In the drawings, the same reference numerals always represent the same or similar components. Among them:

[0047] Figure 1 is a top view schematic diagram of a semiconductor package shown according to Embodiment 1;

[0048] Figure 2 isFigure 1 Schematic cross-sectional view of the semiconductor package shown on the A-A plane;

[0049] Figure 3 Flowchart of a method for manufacturing a semiconductor package shown according to Embodiment 1;

[0050] Figure 4 Schematic cross-sectional view of the semiconductor package after step S110 shown according to Embodiment 1;

[0051] Figure 5 Schematic cross-sectional view of the semiconductor package after step S120 shown according to Embodiment 1;

[0052] Figure 6 Schematic cross-sectional view of the semiconductor package after step S130 shown according to Embodiment 1;

[0053] Figure 7 Schematic cross-sectional view of the semiconductor package after step S150 shown according to Embodiment 1;

[0054] Figure 8 Schematic cross-sectional view of the semiconductor package after step S160 shown according to Embodiment 1;

[0055] Figure 9 Schematic cross-sectional view of the semiconductor package after step S170 shown according to Embodiment 1;

[0056] Figure 10 Schematic cross-sectional view of the semiconductor package after step S180 shown according to Embodiment 1;

[0057] Figure 11 Schematic cross-sectional view of the semiconductor package after step S190 shown according to Embodiment 1;

[0058] Figure 12 Top view of a semiconductor package shown according to Embodiment 2;

[0059] Figure 13 Top view of a semiconductor package shown according to Embodiment 3. Detailed implementation manners

[0060] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed description will be omitted.

[0061] Embodiment 1

[0062] Figure 1 、 2 shows the structure of a semiconductor package 1 in this embodiment. The semiconductor package 1 includes a plurality of interposers 123, a plurality of chips 11, a plurality of first connectors 14, a plurality of second connectors 17, and a redistribution layer 13. The plurality of first connectors 14 and the plurality of interposers 123 are respectively fixed on both sides of the redistribution layer 13. The plurality of chips 11 are fixed on the first connectors 14. The second connectors 17 are disposed on a side of the interposer 123 facing away from the redistribution layer 13. Two chips 11 can be electrically connected to each other through the redistribution layer 13, and the chip 11 is electrically connected to the second connector 17 through the first connector 14, the redistribution layer 13, and the interposer 123 connected in sequence. The second connector 17 serves as a pin of the semiconductor package 1 and can be connected to other electronic devices.

[0063] In this embodiment, the redistribution layer 13 (Redistribution Layer, RDL) is a sheet-like structure. The redistribution layer 13 includes a first surface 133 and a second surface 134 opposite to the first surface 133. The first surface 133 and the second surface 134 are parallel to each other. The redistribution layer 13 is a multi-layer dielectric conductive layer stacked in sequence, and each layer of dielectric conductive layer includes an insulating substrate layer and a metal layer 131 embedded in the insulating substrate layer. The insulating substrate layer can be made of materials such as silicon nitride, silicon oxide, or polyimide. The metal layer 131 can be made of metal materials, such as metals and their alloys including aluminum, gold, copper, tungsten, titanium, etc. The metal layers 131 of adjacent two layers of dielectric conductive layers are in contact with each other to form a conductive path, which can electrically conduct between the first surface 133 and the second surface 134 of the redistribution layer 13. Also, by reasonably arranging the patterns of the metal layers 131 in each layer of dielectric conductive layer, a complex three-dimensional circuit layout can be formed in the redistribution layer 13. The redistribution layer 13 can simultaneously achieve electrical conduction between a specific point on the first surface 133 and another specific point on the first surface 133, between a specific point on the first surface 133 and a specific point on the second surface 134, and between a specific point on the second surface 134 and another specific point on the second surface 134.

[0064] The first connector 14 is a conductor. The first connector 14 can be a metal ball or a metal bump, preferably a tin ball, a solder bump, or a solder columnar bump (Copper pillar bump, CPB). The plurality of first connectors 14 are distributed on the first surface 133 of the redistribution layer 13, and adjacent two first connectors 14 are separated from each other. The first connector 14 is fixedly connected to the metal layer 131 on the first surface 133 of the redistribution layer 13 to form an electrical connection with the redistribution layer 13.

[0065] The shape of the chip 11 can be a square chip 11. Bond pads are provided on one side of the chip 11, and the bond pads are the input / output interfaces of the chip 11 to the outside. The thickness of each chip 11 can be the same. The number of chips 11 can be two. The chips 11 are all laid flat on a plurality of first connectors 14, and the side of the chip 11 with the bond pads faces the first connectors 14. The first connectors 14 are connected to the bond pads of the chip 11, and the first connectors 14 are connected to the bond pads one by one. A fixed connection is formed between the chip 11 and the first connectors 14, and a plurality of first connectors 14 support one chip 11. The chip 11 is preferably parallel to the first surface 133 of the redistribution layer 13, and the distance between each chip 11 and the first surface 133 is the same, so that the chip 11 and the redistribution layer 13 can be interconnected by using first connectors 14 of a unified size. Adjacent chips 11 are separated from each other. Adjacent chips 11 can be electrically connected to each other through the first connectors 14 and the redistribution layer 13.

[0066] The interposer 123 includes an interposer substrate 125 and through-silicon vias 122 (TSV) provided in the interposer substrate 125. The interposer substrate 125 can be made of an insulating material such as silicon or silicon oxide. The interposer substrate 125 is configured as a plate-like structure, preferably a square plate. The through-silicon vias 122 vertically penetrate the interposer substrate 125. The through-silicon vias 122 are conductive channels penetrating the interposer 123. The through-silicon vias 122 can be metal wires extending from one side of the interposer 123 to the opposite side, and the metal wires can be gold wires, copper wires or aluminum wires. A plurality of interposers 123 are distributed on the second surface 134 of the redistribution layer 13 and are fixedly connected to the redistribution layer 13. The through-silicon vias 122 of each interposer 123 are connected to the redistribution layer 13 and form an electrical connection with the redistribution layer 13. Adjacent interposers 123 are separated from each other so that a groove 124 is formed between adjacent interposers 123. The side surface of the groove 124 close to the redistribution layer 13 is in direct contact with the second surface 134 of the redistribution layer 13

[0067] The second connector 17 is a conductor. The second connector 17 can be a metal ball or a metal bump, preferably a solder ball, a solder bump or a solder columnar bump. The second connector 17 is provided on the side of the interposer 123 facing away from the redistribution layer 13 and is connected to the through-silicon vias 122 one by one. In this way, an electrical connection is formed between the through-silicon vias 122 and the second connector 17.

[0068] The chip 11 can be electrically connected to the second connector 17 through the first connector 14, the redistribution layer 13, and the interposer 123 in sequence. The second connector 17 can be used as an external interface of the semiconductor package 1 to connect to other electronic devices (such as a printed circuit board). At the same time, since a groove 124 is formed between two adjacent interposers 123, the groove 124 is an expansion joint of the interposer substrate composed of multiple interposers 123, and can become narrower or wider with the thermal expansion and contraction of the semiconductor package 1 during the semiconductor package manufacturing process, effectively avoiding the cracking of the semiconductor package 1 due to the warping of the interposer substrate during the manufacturing process.

[0069] Further, multiple interposers 123 can be cut from an interposer plate 12 covering the second surface 134 of the redistribution layer 13. In this way, the redistribution layer 13 can be fabricated on the interposer plate 12 first, and the chip 11 can be connected to the redistribution layer 13 using the first connector 14. The interposer plate 12 can be etched and split into multiple interposers 123, and the etching method used can be dry etching or chemical etching.

[0070] Further, the redistribution layer 13 further includes an etch stop layer 132. The etch stop layer 132 is disposed on the side of the redistribution layer 13 close to the interposer 123, covering the groove 124 between two adjacent interposers 123. Before etching, the etch stop layer 132 is arranged along the dividing line of the interposer plate 12 to block the etching medium and prevent the etching medium from etching the redistribution layer 13 when etching the interposer plate 12.. The etch stop layer 132 can be a metal layer, such as metals like copper, aluminum, and gold.

[0071] Further, the chip 11, the interposer plate 12, and the interposer 123 are all configured as square plates. The chip 11 includes a first side and a second side adjacent to the first side.

[0072] The interposer 123 includes a third side and a fourth side adjacent to the third side. The third side of the interposer 123 is parallel to the first side of the chip 11. The fourth side of the interposer 123 is parallel to the second side of the chip 11.

[0073] The sum of the side lengths of the third sides of multiple interposers is greater than twice the side length of the first side, and the sum of the side lengths of the fourth sides of multiple interposers is greater than twice the side length of the second side, so that the semiconductor package 1 becomes an RDL fan-out type.

[0074] The side length of the third side is less than or equal to 1.2 times the side length of the first side. The side length of the fourth side is less than or equal to 1.2 times the side length of the second side. More preferably, the value range of the side length of the third side is 0.2 to 0.8 times the side length of the first side, and the value range of the side length of the fourth side is 0.2 to 0.8 times the side length of the second side.

[0075] After being set up like this, the area of a single interposer 123 is small, and the grooves 124 are distributed more densely, which can better release stress.

[0076] Furthermore, multiple interposers 123 are arranged in a matrix on the second surface 134 of the redistribution layer 13. In this way, both the interposers 123 and their grooves 124 are distributed more evenly, and the acting forces between the interposers 123 and the redistribution layer 13 are also distributed more evenly. When cutting the interposer 12, one or more slits can be set along a direction parallel to one side of the interposer 12 and one or more slits can be set along a direction parallel to the other side of the interposer 12, so that the grooves 124 of the finally cut interposer 12 extend in a grid pattern.

[0077] When cutting, align the slit with the gap between two adjacent chips 11, so that a finally formed groove 124 is aligned with the gap, which makes two adjacent chips 11 relatively independent and reduces the mutual influence between two adjacent chips 11.

[0078] Furthermore, the semiconductor package 1 further includes a first molding 15. The first molding 15 is used to encapsulate the redistribution layer 13, the first connecting member 14, and the chips 11 together. The first molding 15 can be formed by a plastic encapsulation process. The first molding 15 covers all the chips 11 and fills the gap between the chips 11 and the redistribution layer 13. One side of the chip 11 facing away from the first connecting member 14 can be exposed from the first molding 15, so that the chip 11 dissipates heat better.

[0079] The first molding 15 includes a first molding layer 151. The first molding layer 151 is filled between the chips 11 and the redistribution layer 13. A plurality of first through holes 153 for accommodating the first connecting member 14 are provided on the first molding layer 151, and the first connecting member 14 is located in the first through holes 153. The first molding 15 encapsulates and fixes the chips 11, the first connecting member 14, and the redistribution layer 13 together, strengthening the connection structure between the chips 11, the first connecting member 14, and the redistribution layer 13.

[0080] The first molding 15 further includes a second molding layer 152. The second molding layer 152 extends from the first molding layer 151 towards the chips 11 and fills the gaps between the chips 11. The second molding layer 152 is fixedly connected to the first molding layer 151 and the chips 11 and fixes two adjacent chips 11 together, further enhancing the structure of the entire semiconductor package 1.

[0081] Furthermore, the first molding layer 151 and the second molding layer 152 can be an integrally formed structure, which is formed by one-time injection molding with the same molding compound. The molding compound can be a molding sealant (epoxy resin molding compound).

[0082] As an alternative, the first molding layer 151 and the second molding layer 152 can be formed by two injection moldings using two different molding compounds respectively. The first molding layer 151 can be made of underfill, and the second molding layer 152 can be made of molding compound.

[0083] Furthermore, the semiconductor package 1 further includes a second molded part 16. The second molded part 16 includes a third molding layer 161. The third molding layer 161 covers one side of all the interposers 123 facing away from the redistribution layer 13, and covers the openings of the grooves 124 between two adjacent interposers 123. A plurality of second through holes 163 for passing through the second connecting member 17 are provided on the third molding layer 161, and the second connecting member 17 is disposed in the second through holes 163. The third molding layer 161 can be a passivation layer or a molding compound layer.

[0084] The third molding layer 161 connects the interposers 123 to each other, and further relatively fixes the second connecting member 17 to the interposers 123, so that the structural strength of the semiconductor package 1 is greater.

[0085] Furthermore, the second molded part 16 further includes a filling part 162. The filling part 162 fills the grooves 124 between the interposers 123. The filling part 162 is also connected to the third molding layer 161. The material of the filling part 162 can be a molding compound, and can be a molding compound. The material of the filling part 162 is preferably the same as that of the first molding layer 151.

[0086] The filling part 162 fills the grooves 124 between the interposers 123, so that the interposers 123 are connected to each other, further increasing the structural strength of the interposers 123. At the same time, the filling part 162 also supports the redistribution layer 13. Since the coefficient of thermal expansion of the material used for the filling part 162 is similar to or the same as that of the first molded part 15, filling the grooves 124 between the interposers 123 will not reduce the function of the grooves 124 as expansion joints.

[0087] Referring to Figure 3 , this embodiment also provides a manufacturing method of the semiconductor package 1. The above semiconductor package 1 can be manufactured by using this manufacturing method. The manufacturing method includes:

[0088] Step S110: Referring to Figure 4 , a redistribution layer 13 is provided on the interposer 12 such that one end of the through-silicon via 122 in the interposer 12 is connected to the redistribution layer 13.

[0089] The interposer 12 is preferably a silicon interposer substrate. A through-silicon via 122 extending perpendicular to the interposer 12 is provided inside the interposer 12. During the formation of the redistribution layer 13, the metal pattern on the redistribution layer 13 is connected to one end of the through-silicon via 122, and an etch stop layer 132 is formed on the surface of the interposer 12.

[0090] Step S120: Refer to Figure 5 , and connect the redistribution layer 13 to multiple chips 11 by using a plurality of first connectors 14.

[0091] In this step, the flip chip technology can be used to connect the chip 11 to the redistribution layer 13 through the molten first connectors 14.

[0092] Step S130: Refer to Figure 6 , and fill the molding compound to form a first molded part 15 that encapsulates the plurality of first connectors 14, the multiple chips 11, and the redistribution layer 13 together.

[0093] By using an injection molding process, the molten molding compound is injected into the chamber accommodating the first connectors 14, the multiple chips 11, and the redistribution layer 13 for encapsulation. After cooling, the molding compound solidifies to form the first molded part 15 that connects the first connectors 14, the chips 11, and the redistribution layer 13 together.

[0094] In this step, a first molding layer 151 filled between the chip 11 and the redistribution layer 13 can be formed first. After the first molding layer 151 solidifies, a second molding layer 152 that fills the gaps between the chips 11 can be formed on the first molding layer 151; alternatively, the first molding layer 151 and the second molding layer 152 can be formed simultaneously to form an integrally molded first molded part 15.

[0095] Step S140: Grind the first molded part 15 to expose a part of the surface of the chip 11.

[0096] In this step, a part of the first molded part 15 covering the side of the chip 11 facing away from the first connector 14 is ground until the chip 11 is exposed.

[0097] Step S150: Refer to Figure 7 , and remove one end of the interposer 12 facing away from the redistribution layer 13 to expose the other end of the through-silicon via 122 facing away from the redistribution layer 13.

[0098] In this step, one end of the interposer 12 facing away from the redistribution layer 13 can be ground to grind off a part of the interposer substrate until the through-silicon via 122 is exposed.

[0099] Step S160: Refer to Figure 8, the interposer 12 is cut to form a plurality of separated interposer elements 123, and a groove 124 is formed between two adjacent interposer elements 123.

[0100] In this step, the method of cutting the interposer 12 can be an etching method, which can be a dry etching method or a chemical etching method. Etch from the side of the interposer 12 facing away from the redistribution layer 13 towards the redistribution layer 13, and stop etching when reaching the redistribution layer 13. The surface of the redistribution layer 13 is preferably provided with an etch stop layer 132 to control the etching depth and avoid damaging the redistribution layer 13 due to etching. When cutting, the slit on the interposer 12 is aligned with the etch stop layer 132, so that the etch stop layer 132 can block the etching of the redistribution layer 13. After cutting, a groove 124 is formed between two adjacent interposer elements 123, and the etch stop layer 132 covers the groove 124.

[0101] Step S170: Refer to Figure 9 , fill the molding compound to form a second molded part 16 that encapsulates the plurality of interposer elements 123 together.

[0102] In this step, the molten molding compound can be injected into the chamber containing the redistribution layer 13 and the interposer elements 123. After the molding compound completely fills the groove 124 between the interposer elements, it is cooled and solidified to form the second molded part 16 filled between the grooves 124 of the interposer elements 123.

[0103] In another embodiment, this step can be replaced by directly forming a conformal passivation layer covering the plurality of interposer elements 123 on the side of the plurality of interposer elements 123 facing away from the redistribution layer 13.

[0104] Step S180: Refer to Figure 10 , open a second through hole 163 in the second molded part 16 so that the end of the through-silicon via 122 facing away from the redistribution layer 13 is exposed.

[0105] In this embodiment, after the second molded part 16 is formed, the second molded part 16 blocks one end of the through-silicon via 122 facing away from the redistribution layer 13. It is necessary to first open a second through hole 163 in the second molded part 16. The second through hole 163 can be opened in the second molded part 16 by using a laser drilling method.

[0106] Step S190: Refer to Figure 11 , connect the second connector 17 to the interposer element 123 and connect it to the other end of the through-silicon via 122.

[0107] Heat and melt the second connector 17 and then weld it to the interposer element 123 and connect it to the through-silicon via 122.

[0108] Example 2

[0109] The difference between the semiconductor package 1a in Example 2 and the semiconductor package 1 in Example 1 lies only in the interposer and the groove. For the sake of simplicity, only the structures and shapes of the interposer 123a and the groove 124a in Example 2 are described below.

[0110] Referring to Figure 12 , in this embodiment, the interposer 123a is a right triangle. The interposers 123a are arranged in pairs. The hypotenuses of the two paired interposers 123a are parallel to each other and close to each other, and the groove 124a separates the hypotenuses of these two interposers 123a. There are two pairs of interposers 123a, and the two pairs of interposers 123a are separated from each other by the groove 124a. There are two chips 11a, and each chip 11a can be projected onto a pair of paired interposers 123a.

[0111] Since a groove 124a is formed between two adjacent interposers 123a, and this groove 124a is an expansion joint of the interposer substrate composed of multiple interposers 123a, it can become narrower or wider as the semiconductor package 1a expands and contracts during the manufacturing process of the semiconductor package 1a, effectively avoiding the semiconductor package 1a from cracking due to warping of the interposer substrate during the manufacturing process. At the same time, setting the number of such grooves 124a is small, making it easier to process.

[0112] Example 3

[0113] The difference between the semiconductor package 1b in Example 3 and the semiconductor package 1 in Example 1 lies only in the interposer and the groove. For the sake of simplicity, only the interposer 123b and the groove 124b in Example 3 are described below.

[0114] Referring to Figure 13 , in this embodiment, the interposer 123b is a rectangle. There are four interposers 123b. Two adjacent interposers 123b are separated from each other, and a groove 124b is formed between two adjacent interposers 123b. The grooves 124 are connected to form a "cross" structure. There are two chips 11b, one chip 11b can be projected onto two interposers 123b, and the other chip 11b can be projected onto the other two interposers 123b.

[0115] Since a groove 124b is formed between two adjacent interposers 123b, and the groove 124b serves as an expansion joint for the interposer substrate composed of multiple interposers 123b, it can become narrower or wider along with the thermal expansion and contraction of the semiconductor package 1b during the manufacturing process of the semiconductor package 1b, effectively preventing the semiconductor package 1b from cracking due to warping of the interposer substrate during the manufacturing process. At the same time, with such a setting, the number of grooves 124b is small, making it easier to process.

[0116] It should be understood that the above-described multiple examples can be utilized in multiple directions (such as inclined, inverted, horizontal, vertical, etc.) and in multiple configurations without departing from the principles of the present invention. The embodiments shown in the drawings are only shown and described as examples of the effective application of the principles of the present invention, and the present invention is not limited to any specific details of these embodiments.

[0117] Of course, once the above description of the representative embodiments is carefully considered, those skilled in the art will readily understand that various modifications, additions, substitutions, deletions, and other changes can be made to these specific embodiments, and these changes are within the scope of the principles of the present invention. Therefore, the foregoing detailed description should be clearly understood to be given only by way of illustration and example, and the spirit and scope of the present invention are defined only by the appended claims and their equivalents.

Claims

1. A semiconductor package, characterized in that, Comprising: A redistribution layer, including a first surface and a second surface opposite to the first surface; A plurality of first connectors, connected to the first surface of the redistribution layer; A plurality of chips, all disposed on a side of the first connector away from the redistribution layer and all connected to the first connector; A plurality of interposers, all connected to the second surface of the redistribution layer, a groove is formed between two adjacent interposers, a side surface of the groove close to the redistribution layer is in direct contact with the second surface of the redistribution layer, two adjacent chips are separated from each other to form a gap therebetween, and the gap is aligned with one of the grooves located on the other side of the redistribution layer; And A plurality of second connectors, connected to a side of the interposer away from the redistribution layer, wherein, the chip is electrically connected to the second connector through the first connector, the redistribution layer, and the interposer.

2. The semiconductor package according to claim 1, wherein The redistribution layer includes an etch stop layer covering the groove.

3. The semiconductor package according to claim 1, wherein Both the chip and the interposer are square plates, The chip includes a first side and a second side adjacent to the first side, the interposer includes a third side parallel to the first side and a fourth side adjacent to the third side and parallel to the second side, The sum of the side lengths of the third sides of the plurality of interposers is greater than twice the side length of the first side, and the sum of the side lengths of the fourth sides of the plurality of interposers is greater than twice the side length of the second side.

4. The semiconductor package according to claim 3, wherein The side length of the third side is less than or equal to 1.2 times the side length of the first side, and the side length of the fourth side is less than or equal to 1.2 times the side length of the second side.

5. The semiconductor package according to claim 4, wherein The side length of the third side ranges from 0.2 to 0.8 times the side length of the first side, and the side length of the fourth side ranges from 0.2 to 0.8 times the side length of the second side.

6. The semiconductor package according to claim 1, wherein The plurality of interposers are arranged in a matrix on the second surface of the redistribution layer.

7. The semiconductor package according to claim 1, wherein The semiconductor package further includes a first molding compound, and the first molding compound is used to encapsulate the redistribution layer, the first connector, and the chip together; The first molding compound includes a first molding layer filled between the chip and the redistribution layer, and a plurality of first through holes for accommodating the first connector are provided on the first molding layer; The first molding compound further includes a second molding layer extending from the first molding layer towards the chip direction and filling the gap between adjacent chips.

8. The semiconductor package according to claim 7, wherein A surface of the chip facing away from the first connector is exposed from the first molding compound.

9. The semiconductor package according to claim 7, wherein, The semiconductor package further includes a second molding compound; The second molding compound includes a third molding layer covering a surface of the plurality of interposers facing away from the redistribution layer and covering the groove, and a plurality of second through holes for passing through the second connector are provided on the third molding layer; The second molding compound further includes a filling portion connecting the third molding layer and filling the groove.

10. The semiconductor package according to claim 1, characterized in that, At least two chips are electrically connected to each other through the first connector and the redistribution layer.

11. The semiconductor package according to any one of claims 1 to 10, characterized in that, A through-silicon via is provided in the interposer, one end of which is connected to the redistribution layer and the other end is connected to the second connector.

12. A method for manufacturing a semiconductor package, characterized in that, Comprising: A redistribution layer is provided on the interposer and the interposer is electrically connected to the redistribution layer; A plurality of first connectors are used to connect the redistribution layer to a plurality of chips; A first molding is formed to encapsulate the plurality of first connectors, the plurality of chips, and the redistribution layer together; The interposer is cut to form a plurality of separated interposer elements, and a groove is formed between two adjacent interposer elements. Two adjacent chips are separated from each other to form a gap therebetween, and the gap is aligned with one of the grooves on the other side of the redistribution layer; A second molding is formed to encapsulate the plurality of interposer elements together; A second connector is connected to the interposer element and the chip is electrically connected to the second connector through the first connector, the redistribution layer, and the interposer element; 13. The manufacturing method according to claim 12, characterized in that, During the process of providing the redistribution layer on the interposer, an etch stop layer is formed on the surface of the interposer; The interposer is cut by an etching method, and the cut seam on the interposer is aligned with the etch stop layer so that the etch stop layer blocks the etching of the redistribution layer; 14. The manufacturing method according to claim 12, characterized in that, The method further includes: after forming the first molding, grinding the first molding to expose a partial surface of the chip; 15. The manufacturing method according to claim 12, wherein, The interposer has a through-silicon via; The method further includes: before cutting the interposer, grinding the interposer to expose the through-silicon via in the interposer; 16. The manufacturing method according to claim 15, characterized in that, After forming the second molding, the second molding is further drilled to form a second through hole exposing the through-silicon via; The second connector is connected to the through-silicon via through the second through hole.

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