Integrated circuit packaging method

Abstract

The invention discloses an integrated circuit packaging method, which comprises the following steps of: 1, constructing a thermal expansion gradual change buffer layer, and arranging a buffer transition layer with a thermal expansion coefficient changing step by step between a chip and a re-wiring layer to realize smooth transition of thermal deformation between different materials, so that interface stress concentration caused by mismatching of thermal expansion is reduced; 2, flexible stress absorption layers are introduced, and the flexible stress absorption layers with elastic deformation capacity are arranged between the chip and the rewiring layer and between the rewiring layer and the substrate. A gradual change buffer structure with a thermal expansion coefficient changing step by step is introduced between a chip and a re-wiring layer and between the re-wiring layer and a substrate, and a flexible stress absorption layer with an elastic deformation capability is combined, so that thermal expansion mismatch transits from sudden change to continuous change, and generation of thermal stress in packaging is weakened from the source.

Description

Technical Field

[0001] This application relates to the field of integrated circuit packaging technology, specifically to an integrated circuit packaging method. Background Technology

[0002] As a crucial link connecting chips to external circuits, integrated circuit packaging technology directly affects the overall quality and lifespan of integrated circuit products through its structural reliability, electrical performance, and heat dissipation performance. As integrated circuits develop towards high performance, high integration, and miniaturization, packaging structures are becoming increasingly complex, and packaging methods such as multilayer rewiring and chip-on-chip are widely used.

[0003] Existing integrated circuit packaging methods typically employ a multi-material stack, including a chip, substrate, redistribution layer, metal interconnect layer, and insulating dielectric layer. However, the coefficients of thermal expansion of different packaging materials vary significantly. Under the conditions of reflow soldering, curing processes during packaging, and repeated thermal cycling during actual device operation, large thermal stresses can easily be generated inside the package. Due to insufficient consideration of stress release and buffering design in existing packaging structures, the resulting residual stresses are difficult to eliminate effectively and tend to concentrate at the chip, solder joints, or interfaces between packaging layers. This can lead to problems such as package delamination, metal interconnect cracking, or solder joint fatigue failure, affecting the stability and long-term reliability of the packaging structure.

[0004] Therefore, those skilled in the art provide an integrated circuit packaging method to solve the problems mentioned above. Summary of the Invention

[0005] In view of the shortcomings of the prior art, this application provides an integrated circuit packaging method to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, this application provides the following technical solution: an integrated circuit packaging method, comprising the following steps:

[0007] Step 1: Construct a thermal expansion gradient buffer layer. Set a buffer transition layer with a gradually changing coefficient of thermal expansion between the chip and the redistribution layer to achieve a smooth transition of thermal deformation between different materials, thereby reducing the interface stress concentration caused by thermal expansion mismatch.

[0008] Step 2: Introduce a flexible stress-absorbing layer. A flexible stress-absorbing layer with elastic deformation capability is set between the chip and the redistribution layer, and between the redistribution layer and the substrate, so as to absorb and alleviate thermal stress during temperature changes and reduce the stress on the solder joints and interconnect structures.

[0009] Step 3: Optimize the stress dispersion structure of the redistribution layer. By optimizing the structure of the redistribution layer, a connection structure with a certain deformation capability is formed between adjacent redistribution layers to disperse thermal stress and reduce the failure risk of the metal interconnect layer and dielectric layer.

[0010] Step 4: Construct thermal stress relief paths, perform stress zoning design on the packaging structure, and set thermal stress relief paths between each functional area so that the thermal stress generated inside the packaging can be released step by step along the preset direction to avoid the accumulation of residual stress.

[0011] Step 5: Achieve synergistic optimization of electrical performance and heat dissipation. While introducing stress buffering and release structures, optimize the metal interconnect layout and heat conduction path to reduce parasitic parameters and improve heat dissipation efficiency, thereby enhancing the electrical performance stability and long-term reliability of the package.

[0012] Preferably, a thermal expansion gradient buffer layer is provided between the chip and the redistribution layer. The thermal expansion gradient buffer layer includes at least two buffer sub-layers, each of which is stacked sequentially along the direction from the chip to the redistribution layer. The thermal expansion coefficient of each buffer sub-layer is monotonically increasing, so that the thermal expansion difference between the chip and the redistribution layer can be gradually transitioned, thereby reducing the thermal stress concentration at the interface.

[0013] Preferably, the equivalent interfacial thermal stress between adjacent buffer sub-layers in the thermal expansion gradient buffer layer satisfies the following relationship:

[0014]

[0015] σ i E represents the equivalent interfacial thermal stress generated between the i-th buffer sublayer and the (i+1)-th buffer sublayer. i E i+1 These are the elastic moduli of the i-th and (i+1)-th buffer sublayers, respectively; α i α i+1 ΔT and η are the linear thermal expansion coefficients of the i-th and i+1-th buffer sublayers, respectively; ΔT is the temperature change range experienced during the packaging process or device operation; η is the stress relief correction coefficient, and 0 < η ≤ 1, used to characterize the deformation absorption capacity of the buffer sublayer.

[0016] Preferably, a flexible stress-absorbing layer is provided between the redistribution layer and the substrate. The flexible stress-absorbing layer is formed of a flexible material with elastic deformation capability, and absorbs the thermal stress caused by the thermal expansion mismatch of different packaging materials by undergoing recoverable deformation during temperature changes, thereby reducing the stress level borne by the solder joints and interconnect structure.

[0017] Preferably, the thermal stress absorption efficiency of the flexible stress-absorbing layer satisfies the following relationship:

[0018]

[0019] Ψ represents the thermal stress absorption efficiency of the flexible stress-absorbing layer; σ0 represents the equivalent thermal stress borne by the interconnect structure without the flexible stress-absorbing layer; σ f E represents the equivalent thermal stress borne by the interconnect structure after the flexible stress-absorbing layer is installed. f E represents the elastic modulus of the flexible stress-absorbing layer. s Δ is the equivalent elastic modulus of the adjacent rigid structural layer; α为 The difference in thermal expansion coefficients between adjacent structural layers; ΔT represents the temperature change during the packaging process or device operation; t f denoted as , where is the effective thickness of the flexible stress-absorbing layer; k is the thickness-deformation coupling coefficient, used to characterize the stress attenuation capability of the flexible stress-absorbing layer in the thickness direction.

[0020] Preferably, the redistribution layer includes at least two redistribution sublayers stacked along the thickness direction, and adjacent redistribution sublayers are interconnected by a deformable connection structure. The connection structure can undergo controlled deformation when the temperature changes to disperse the thermal stress caused by thermal expansion mismatch, thereby reducing the failure risk of the metal interconnect layer and dielectric layer.

[0021] Preferably, the thermal stress dispersion coefficient of the redistribution layer satisfies the following relationship:

[0022]

[0023] Ω is the thermal stress dispersion coefficient of the redistribution layer, and 0 < Ω ≤ 1. The smaller the Ω, the stronger the stress dispersion ability; E m E represents the elastic modulus of the metal interconnect material in the redistribution layer. d L represents the equivalent elastic modulus of the dielectric material in the redistribution layer. c h is the equivalent deformation length of the connection structure between adjacent redistribution sublayers. c λ is the equivalent height of the connecting structure in the thickness direction; λ is the structural deformation control coefficient, used to characterize the influence of the geometry of the connecting structure on the stress transmission path.

[0024] Preferably, the packaging structure is divided into at least two stress functional zones along the thickness direction, and a thermal stress release path is provided between each stress functional zone. The thermal stress release path is used to guide the thermal stress generated inside the package to be transmitted and released step by step along a preset direction during temperature changes, so as to avoid the accumulation of thermal stress in the chip area, interconnect area or interface area.

[0025] Preferably, the residual thermal stress attenuation relationship corresponding to the thermal stress release path satisfies the following formula:

[0026]

[0027] σ r The residual thermal stress remaining in the target area after passing through the aforementioned thermal stress relief path; σ init The initial thermal stress generated by the encapsulation structure before stress zoning and stress relief design are performed; n is the number of stress relief units set in the thermal stress relief path; μ j Let I be the stress relief coefficient of the j-th stress relief unit, used to characterize the stress dissipation capability of that unit; j A is the equivalent length of the j-th release unit along the direction of thermal stress transmission; j Let be the effective stress relief cross-sectional area of ​​the j-th release unit.

[0028] Preferably, based on the aforementioned thermal expansion gradient buffer layer, flexible stress absorption layer, redistribution layer stress dispersion structure, and thermal stress release path, the metal interconnect layout and heat conduction path in the package are synergistically optimized to simultaneously reduce parasitic electrical parameters and thermal resistance parameters. This improves the electrical performance stability and long-term reliability of the package structure while ensuring heat dissipation efficiency. To quantitatively characterize the synergistic optimization effect of electrical performance and heat dissipation performance, the following synergistic performance factor is introduced, and its formula is:

[0029]

[0030] " is the electro-thermal synergistic performance factor, used to comprehensively evaluate the electrical performance stability and heat dissipation capability of the packaging structure, and 0 < " ≤ 1, the larger " is, the better the synergistic optimization effect; Z th P represents the equivalent thermal resistance of the package structure from the chip to the external heat dissipation interface. par γ represents the comprehensive parasitic parameters corresponding to the metal interconnect structure, which are obtained by weighting parasitic resistance, parasitic inductance, and parasitic capacitance; β is the thermal performance weighting coefficient, used to characterize the degree of influence of thermal resistance variation on device reliability; γ is the electrical performance weighting coefficient, used to characterize the degree of influence of parasitic parameter variation on signal integrity and power consumption.

[0031] This application provides an integrated circuit packaging method. It has the following advantages:

[0032] 1. This application addresses the problem of large differences in the coefficient of thermal expansion of different packaging materials and the easy concentration of interfacial thermal stress. It introduces a gradually changing buffer structure with progressively changing coefficient of thermal expansion between the chip and the redistribution layer and between the redistribution layer and the substrate, and combines it with a flexible stress-absorbing layer with elastic deformation capability. This transforms the thermal expansion mismatch from abrupt change to continuous change, thereby reducing the generation of internal thermal stress in the package from the source.

[0033] 2. This application designs the redistribution layer as a stress-dispersing structure composed of multiple sub-layers and controllable deformation connection structures, and divides the entire package into stress functional zones. Thermal stress release paths are set between each zone, so that the thermal stress generated inside the package is dispersed during the transmission process and released step by step along the preset path, avoiding the accumulation of thermal stress in the interconnect structure and interface area.

[0034] 3. Based on the introduction of multi-level thermal stress buffering, dispersion and release structures, this application conducts a collaborative design of the metal interconnect layout and heat conduction path in the package, and comprehensively considers thermal resistance and parasitic electrical parameters through a unified collaborative performance evaluation factor, thereby achieving simultaneous optimization of heat dissipation performance, electrical performance stability and structural reliability. Attached Figure Description

[0035] Figure 1 This is a flowchart of this application. Detailed Implementation

[0036] To enable those skilled in the art to understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0037] Please see the appendix Figure 1 This application provides an integrated circuit packaging method, including:

[0038] Step 1: Construct a thermal expansion gradient buffer layer. Set a buffer transition layer with a gradually changing coefficient of thermal expansion between the chip and the redistribution layer to achieve a smooth transition of thermal deformation between different materials, thereby reducing the interface stress concentration caused by thermal expansion mismatch.

[0039] Step 2: Introduce a flexible stress-absorbing layer. A flexible stress-absorbing layer with elastic deformation capability is set between the chip and the redistribution layer, and between the redistribution layer and the substrate, so as to absorb and alleviate thermal stress during temperature changes and reduce the stress on the solder joints and interconnect structures.

[0040] Step 3: Optimize the stress dispersion structure of the redistribution layer. By optimizing the structure of the redistribution layer, a connection structure with a certain deformation capability is formed between adjacent redistribution layers to disperse thermal stress and reduce the failure risk of the metal interconnect layer and dielectric layer.

[0041] Step 4: Construct thermal stress relief paths, perform stress zoning design on the packaging structure, and set thermal stress relief paths between each functional area so that the thermal stress generated inside the packaging can be released step by step along the preset direction to avoid the accumulation of residual stress.

[0042] Step 5: Achieve synergistic optimization of electrical performance and heat dissipation. While introducing stress buffering and release structures, optimize the metal interconnect layout and heat conduction path to reduce parasitic parameters and improve heat dissipation efficiency, thereby enhancing the electrical performance stability and long-term reliability of the package.

[0043] Reference Figure 1 A thermal expansion gradient buffer layer is provided between the chip and the redistribution layer. The thermal expansion gradient buffer layer includes at least two buffer sub-layers. Each buffer sub-layer is stacked sequentially along the direction from the chip to the redistribution layer, and the thermal expansion coefficient of each buffer sub-layer is monotonically increasing. This allows the thermal expansion difference between the chip and the redistribution layer to transition gradually, thereby reducing the concentration of thermal stress at the interface.

[0044] The equivalent interfacial thermal stress between adjacent buffer sub-layers in the thermal expansion gradient buffer layer satisfies the following relationship:

[0045]

[0046] σ i E represents the equivalent interfacial thermal stress generated between the i-th buffer sublayer and the (i+1)-th buffer sublayer. i E i+1 These are the elastic moduli of the i-th and (i+1)-th buffer sublayers, respectively; α i α i+1 ΔT represents the linear thermal expansion coefficients of the i-th and i+1-th buffer sublayers, respectively; ΔT represents the temperature change range experienced during the packaging process or device operation; η is the stress relief correction coefficient, and 0 < η ≤ 1, used to characterize the deformation absorption capacity of the buffer sublayer.

[0047] Specifically, by setting at least two gradually increasing buffer sub-layers with monotonically increasing coefficients of thermal expansion between the chip and the redistribution layer, the abrupt change in the thermal expansion difference of the material is transformed into a gradual transition. Through the controlled relationship of equivalent interface thermal stress between adjacent buffer sub-layers, the thermal stress is dispersed and weakened between layers, thereby effectively reducing the concentration of interface thermal stress and the level of residual stress. At the same time, a quantitative constraint model considering elastic modulus, thermal expansion difference, and stress relief correction coefficient is introduced to make the buffering effect designable and predictable, significantly improving the reliability and stability of the packaging structure during temperature cycling.

[0048] Reference Figure 1 A flexible stress-absorbing layer is provided between the redistribution layer and the substrate. The flexible stress-absorbing layer is formed of a flexible material with elastic deformation capability. During temperature changes, it can absorb the thermal stress caused by the thermal expansion mismatch of different packaging materials by undergoing recoverable deformation, thereby reducing the stress level borne by the solder joints and interconnect structure.

[0049] The thermal stress absorption efficiency of the flexible stress absorption layer satisfies the following relationship:

[0050]

[0051] Ψ represents the thermal stress absorption efficiency of the flexible stress-absorbing layer; σ0 represents the equivalent thermal stress borne by the interconnect structure without the flexible stress-absorbing layer; σ f E represents the equivalent thermal stress borne by the interconnect structure after the flexible stress-absorbing layer is installed. f E represents the elastic modulus of the flexible stress-absorbing layer. s Δα is the equivalent elastic modulus of adjacent rigid structural layers; Δα is the difference in thermal expansion coefficients between adjacent structural layers; ΔT is the temperature change amplitude during the packaging process or device operation; t f denoted as , where is the effective thickness of the flexible stress-absorbing layer; k is the thickness-deformation coupling coefficient, used to characterize the stress attenuation capability of the flexible stress-absorbing layer in the thickness direction.

[0052] Specifically, by setting a flexible stress-absorbing layer with elastic deformation capability between the redistribution layer and the substrate, the layer can absorb the thermal stress caused by the thermal expansion mismatch of different packaging materials through recoverable deformation when temperature changes occur during the packaging process or device operation. This effectively reduces the equivalent stress level borne by the solder joints and interconnect structures. At the same time, by introducing a thermal stress absorption efficiency model related to the elastic modulus, effective thickness, and stress attenuation capability in the thickness direction of the flexible stress-absorbing layer, the stress relief effect becomes designable and predictable, improving the reliability and stability of the packaging structure under temperature cycling conditions.

[0053] Reference Figure 1 The redistribution layer includes at least two redistribution sublayers stacked along the thickness direction. Adjacent redistribution sublayers are interconnected by a deformable connection structure. The connection structure can undergo controlled deformation when the temperature changes to disperse the thermal stress caused by thermal expansion mismatch, thereby reducing the failure risk of the metal interconnect layer and dielectric layer.

[0054] The thermal stress dispersion coefficient of the redistribution layer satisfies the following relationship:

[0055]

[0056] Ω is the thermal stress dispersion coefficient of the redistribution layer, and 0 < Ω ≤ 1. The smaller the Ω, the stronger the stress dispersion ability; E m E represents the elastic modulus of the metal interconnect material in the redistribution layer. d L represents the equivalent elastic modulus of the dielectric material in the redistribution layer. c h is the equivalent deformation length of the connection structure between adjacent redistribution sublayers. cλ is the equivalent height of the connecting structure in the thickness direction; λ is the structural deformation control coefficient, used to characterize the influence of the geometry of the connecting structure on the stress transmission path.

[0057] Specifically, by designing a deformable connection structure between redistribution layers, the thermal expansion differences between different packaging layers no longer cause abrupt stress. Instead, the thermal stress is gradually released through deformation, effectively reducing the risk of packaging failure caused by thermal expansion mismatch. Furthermore, by predicting the stress relief effect through a quantitative model, the reliability and stability of the package under temperature variation conditions are improved.

[0058] Reference Figure 1 The packaging structure is divided into at least two stress functional zones along the thickness direction, and a thermal stress release path is provided between each stress functional zone. The thermal stress release path is used to guide the thermal stress generated inside the package to be transmitted and released step by step along a preset direction during temperature changes, so as to avoid the accumulation of thermal stress in the chip area, interconnect area or interface area.

[0059] The residual thermal stress attenuation relationship corresponding to the thermal stress release path satisfies the following formula:

[0060]

[0061] σ r The residual thermal stress remaining in the target area after passing through the aforementioned thermal stress relief path; σ init The initial thermal stress generated by the encapsulation structure before stress zoning and stress relief design are performed; n is the number of stress relief units set in the thermal stress relief path; μ j Let be the stress relief coefficient of the j-th stress relief unit, used to characterize the stress dissipation capability of that unit; l j A is the equivalent length of the j-th release unit along the direction of thermal stress transmission; j Let be the effective stress relief cross-sectional area of ​​the j-th release unit.

[0062] Specifically, by dividing the structure into multiple stress functional zones along the thickness direction of the package structure and setting thermal stress release paths between adjacent zones, the thermal stress generated during temperature changes can be transmitted and attenuated step by step along a preset direction, thereby avoiding the concentration of thermal stress in the chip area, interconnect area, or interface area. At the same time, by establishing a quantitative attenuation relationship between residual thermal stress and the number of release units, stress release coefficient, transmission equivalent length, and effective release cross-sectional area, the stress release effect can be designed and predicted, effectively reducing the residual thermal stress level in the target area and improving the reliability and stability of the package structure under thermal cycling conditions.

[0063] Reference Figure 1Based on the aforementioned thermal expansion gradient buffer layer, flexible stress absorption layer, redistribution layer stress dispersion structure, and thermal stress release path, the metal interconnect layout and heat conduction path in the package are synergistically optimized to simultaneously reduce parasitic electrical parameters and thermal resistance parameters. This improves the electrical performance stability and long-term reliability of the package structure while ensuring heat dissipation efficiency. To quantitatively characterize the synergistic optimization effect of electrical and heat dissipation performance, the following synergistic performance factor is introduced, with the following formula:

[0064]

[0065] Γ is the electro-thermal synergistic performance factor, used to comprehensively evaluate the electrical performance stability and heat dissipation capability of the packaging structure, and 0 < Γ ≤ 1, the larger the Γ, the better the synergistic optimization effect; Z th P represents the equivalent thermal resistance of the package structure from the chip to the external heat dissipation interface. par γ represents the comprehensive parasitic parameters corresponding to the metal interconnect structure, which are obtained by weighting parasitic resistance, parasitic inductance, and parasitic capacitance; β is the thermal performance weighting coefficient, used to characterize the degree of influence of thermal resistance variation on device reliability; γ is the electrical performance weighting coefficient, used to characterize the degree of influence of parasitic parameter variation on signal integrity and power consumption.

[0066] Specifically, based on the setting of a thermal expansion gradient buffer layer, a flexible stress absorption layer, and stress dispersion and release paths, the metal interconnect layout and heat conduction path in the package are synergistically optimized to simultaneously reduce parasitic electrical parameters and equivalent thermal resistance. Furthermore, by introducing an electro-thermal synergistic performance factor, the electrical performance stability and heat dissipation capability are uniformly and quantitatively evaluated. This ensures efficient heat dissipation while improving the signal integrity, electrical performance stability, and long-term reliability of the package structure, thus achieving synergistic optimization of electrical and thermal performance.

[0067] Although embodiments of this application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An integrated circuit packaging method, characterized in that, include: Step 1: Construct a thermal expansion gradient buffer layer. Set a buffer transition layer with a gradually changing coefficient of thermal expansion between the chip and the redistribution layer to achieve a smooth transition of thermal deformation between different materials, thereby reducing the interface stress concentration caused by thermal expansion mismatch. Step 2: Introduce a flexible stress-absorbing layer. A flexible stress-absorbing layer with elastic deformation capability is set between the chip and the redistribution layer, and between the redistribution layer and the substrate, so as to absorb and alleviate thermal stress during temperature changes and reduce the stress on the solder joints and interconnect structures. Step 3: Optimize the stress dispersion structure of the redistribution layer. By optimizing the structure of the redistribution layer, a connection structure with a certain deformation capability is formed between adjacent redistribution layers to disperse thermal stress and reduce the failure risk of the metal interconnect layer and dielectric layer. Step 4: Construct thermal stress relief paths, perform stress zoning design on the packaging structure, and set thermal stress relief paths between each functional area so that the thermal stress generated inside the packaging can be released step by step along the preset direction to avoid the accumulation of residual stress. Step 5: Achieve synergistic optimization of electrical performance and heat dissipation. While introducing stress buffering and release structures, optimize the metal interconnect layout and heat conduction path to reduce parasitic parameters and improve heat dissipation efficiency, thereby enhancing the electrical performance stability and long-term reliability of the package.

2. The integrated circuit packaging method according to claim 1, characterized in that, A thermal expansion gradient buffer layer is provided between the chip and the redistribution layer. The thermal expansion gradient buffer layer includes at least two buffer sub-layers, each of which is stacked sequentially along the direction from the chip to the redistribution layer. The thermal expansion coefficient of each buffer sub-layer is monotonically increasing, so that the thermal expansion difference between the chip and the redistribution layer can be gradually transitioned, thereby reducing the thermal stress concentration at the interface.

3. The integrated circuit packaging method according to claim 2, characterized in that: The equivalent interfacial thermal stress between adjacent buffer sub-layers in the thermal expansion gradient buffer layer satisfies the following relationship: σ i E represents the equivalent interfacial thermal stress generated between the i-th buffer sublayer and the (i+1)-th buffer sublayer. i E i+1 These are the elastic moduli of the i-th and (i+1)-th buffer sublayers, respectively; α i α i+1 ΔT represents the linear thermal expansion coefficients of the i-th and (i+1)-th buffer sub-layers, respectively; ΔT is the temperature range experienced during the packaging process or device operation. η is the stress relief correction coefficient, and 0 < η ≤ 1, used to characterize the deformation absorption capacity of the buffer sublayer.

4. The integrated circuit packaging method according to claim 1, characterized in that, A flexible stress-absorbing layer is disposed between the redistribution layer and the substrate. The flexible stress-absorbing layer is formed of a flexible material with elastic deformation capability. During temperature changes, it undergoes recoverable deformation to absorb the thermal stress caused by the thermal expansion mismatch of different packaging materials, thereby reducing the stress level borne by the solder joints and interconnect structure.

5. The integrated circuit packaging method according to claim 4, characterized in that, The thermal stress absorption efficiency of the flexible stress absorption layer satisfies the following relationship: Ψ represents the thermal stress absorption efficiency of the flexible stress-absorbing layer; σ0 represents the equivalent thermal stress borne by the interconnect structure without the flexible stress-absorbing layer; σ f E represents the equivalent thermal stress borne by the interconnect structure after the flexible stress-absorbing layer is installed. f E represents the elastic modulus of the flexible stress-absorbing layer. s Δα is the equivalent elastic modulus of adjacent rigid structural layers; Δα is the difference in thermal expansion coefficients between adjacent structural layers; ΔT is the temperature change amplitude during the packaging process or device operation; t f denoted as , where is the effective thickness of the flexible stress-absorbing layer; k is the thickness-deformation coupling coefficient, used to characterize the stress attenuation capability of the flexible stress-absorbing layer in the thickness direction.

6. The integrated circuit packaging method according to claim 1, characterized in that, The redistribution layer includes at least two redistribution sublayers stacked along the thickness direction. Adjacent redistribution sublayers are interconnected by a deformable connection structure. The connection structure can undergo controlled deformation when the temperature changes to disperse the thermal stress caused by thermal expansion mismatch, thereby reducing the failure risk of the metal interconnect layer and dielectric layer.

7. The integrated circuit packaging method according to claim 6, characterized in that, The thermal stress dispersion coefficient of the redistribution layer satisfies the following relationship: Ω is the thermal stress dispersion coefficient of the redistribution layer, and 0 < Ω ≤ 1. The smaller the Ω, the stronger the stress dispersion ability; E m E represents the elastic modulus of the metal interconnect material in the redistribution layer. d L represents the equivalent elastic modulus of the dielectric material in the redistribution layer. c h is the equivalent deformation length of the connection structure between adjacent redistribution sublayers. c The equivalent height of the connection structure in the thickness direction; λ is the structural deformation control coefficient, used to characterize the influence of the geometry of the connecting structure on the stress transfer path.

8. The integrated circuit packaging method according to claim 1, characterized in that, The packaging structure is divided into at least two stress functional zones along the thickness direction, and a thermal stress release path is provided between each stress functional zone. The thermal stress release path is used to guide the thermal stress generated inside the package to be transmitted and released step by step along a preset direction during temperature changes, so as to avoid the accumulation of thermal stress in the chip area, interconnect area or interface area.

9. An integrated circuit packaging method according to claim 8, characterized in that, The residual thermal stress attenuation relationship corresponding to the thermal stress release path satisfies the following formula: σ r The residual thermal stress remaining in the target area after passing through the aforementioned thermal stress relief path; σ init The initial thermal stress generated in the encapsulation structure when stress zoning and release design are not performed; n is the number of release units set in the thermal stress release path; μ j Let be the stress relief coefficient of the j-th stress relief unit, used to characterize the stress dissipation capability of that unit; l j A is the equivalent length of the j-th release unit along the direction of thermal stress transmission; j Let be the effective stress relief cross-sectional area of ​​the j-th release unit.

10. An integrated circuit packaging method according to claim 1, characterized in that, Based on the aforementioned thermal expansion gradient buffer layer, flexible stress absorption layer, redistribution layer stress dispersion structure, and thermal stress release path, the metal interconnect layout and heat conduction path in the package are synergistically optimized to simultaneously reduce parasitic electrical parameters and thermal resistance parameters. This improves the electrical performance stability and long-term reliability of the package structure while ensuring heat dissipation efficiency. To quantitatively characterize the synergistic optimization effect of electrical and heat dissipation performance, the following synergistic performance factor is introduced, with the following formula: Γ is the electro-thermal synergistic performance factor, used to comprehensively evaluate the electrical performance stability and heat dissipation capability of the packaging structure, and 0 < Γ ≤ Γ, the larger the Γ, the better the synergistic optimization effect; Z th P represents the equivalent thermal resistance of the package structure from the chip to the external heat dissipation interface. par The comprehensive parasitic parameters corresponding to the metal interconnect structure are obtained by weighting parasitic resistance, parasitic inductance, and parasitic capacitance. β is the thermal performance weighting coefficient, used to characterize the degree of influence of thermal resistance variation on device reliability; γ is the electrical performance weighting coefficient, used to characterize the degree of impact of parasitic parameter changes on signal integrity and power consumption.

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