Integrated Circuit Capacitor Array Structure, Semiconductor Memory, and Preparation Method

Abstract

The present invention provides an integrated circuit capacitor array structure, a semiconductor memory, and a manufacturing method thereof. The integrated circuit capacitor array structure includes: a substrate; a lower electrode layer protruding on the substrate, with capacitor holes formed in the lower electrode layer; a capacitive dielectric layer conformally covering the surface of the lower electrode layer; an upper electrode layer conformally covering the surface of the capacitive dielectric layer; a capacitor plate located in a block shape on the substrate and formed on the upper electrode layer. The capacitor plate includes a metal filling layer stacked sequentially from bottom to top and a conductive covering layer conformally covering the metal filling layer. The conductive covering layer constitutes the top surface layer and the side surface layer of the upper electrode structure for bonding at least one first interconnect structure on the top surface layer. The integrated circuit capacitor array structure provided by the present invention can effectively avoid capacitor leakage. At the same time, when forming the capacitor plate, only depositing the metal filling layer / conductive covering layer as the capacitor plate can ensure low resistance.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor devices and manufacturing, and particularly relates to an integrated circuit capacitor array structure, a semiconductor memory structure, and a manufacturing method thereof. Background Art

[0002] In existing capacitors, due to limitations in the upper electrode layer material and deposition process, when filling the upper electrode material in the capacitor holes, voids are likely to form in the upper electrode structure within the capacitor holes, resulting in differences in the resistance values of the capacitors, which may lead to leakage.

[0003] To address the above problems, an existing improvement method is to form a capacitor plate (PLATE) on the top of the capacitor structure. The capacitor plate will fill the inside of the capacitor to a certain extent to reduce the problem of non-uniform resistance. However, existing capacitor plates have problems such as a relatively thick thickness and complex process steps. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a capacitor structure array, a semiconductor memory structure, and a preparation method thereof, so as to solve the problems in the prior art that the resistance values of capacitors are different, which may lead to leakage problems, and the problems of relatively thick capacitor plate thickness and complex process steps in forming the capacitor plate.

[0005] To achieve the above object and other related objects, the present invention provides an integrated circuit capacitor array structure, which includes:

[0006] A substrate;

[0007] A lower electrode layer, protruding on the substrate, and capacitor holes are formed in the lower electrode layer;

[0008] A capacitor dielectric layer, conformally covering the surface of the lower electrode layer;

[0009] An upper electrode layer, conformally covering the surface of the capacitor dielectric layer;

[0010] A capacitor plate, block-shaped on the substrate and formed on the upper electrode layer. The capacitor plate includes a metal filling layer stacked in sequence from bottom to top and a conductive covering layer conformally covering the metal filling layer. The conductive covering layer constitutes the top surface layer and the side surface layer of the upper electrode structure for bonding at least one first interconnect structure on the top surface layer.

[0011] As a preferred embodiment of the present invention, it further includes an upper electrode filling body, which is located between the upper electrode layer and the capacitor electrode plate and fills the capacitor hole without pores, and the capacitor electrode plate extends from the top surface of the upper electrode filling body to the peripheral surface of the substrate outside the coverage area of the upper electrode filling body.

[0012] As a preferred embodiment of the present invention, the upper electrode filling body is directly attached to the surface of the upper electrode layer and is also formed between adjacent lower electrode layers. The upper electrode filling body has a top surface and a side surface, and the metal filling layer is directly attached to the top surface and the side surface of the upper electrode filling body.

[0013] As a preferred embodiment of the present invention, the metal filling layer fills the capacitor hole to be electrically connected to the upper electrode layer and makes the inside of the capacitor hole in a non-porous filled state.

[0014] As a preferred embodiment of the present invention, the metal filling layer is directly attached to the surface of the upper electrode layer, and the metal filling layer is also formed between the lower electrode layers.

[0015] As a preferred embodiment of the present invention, the upper electrode layer fills the capacitor hole without pores and is electrically connected to the capacitor electrode plate.

[0016] As a preferred embodiment of the present invention, it further includes a bottom support layer, an intermediate support layer and a top support layer, all of which are formed on the substrate and connect and support the lower electrode layer; the bottom support layer is located at the bottom periphery of the lower electrode layer, the intermediate support layer is located at the middle part of the lower electrode layer, and the top support layer is located at the periphery of the opening of the lower electrode layer.

[0017] As a preferred embodiment of the present invention, it further includes:

[0018] A dielectric layer, which is formed on the substrate and covers the upper surface, side surface of the capacitor electrode plate and the peripheral surface on the substrate;

[0019] The first interconnect structure, which is located in the dielectric layer and on the capacitor electrode plate and is connected to the conductive covering layer of the capacitor electrode plate; and

[0020] A second interconnect structure, which is located in the dielectric layer and outside the coverage area of the capacitor electrode plate, and the second interconnect structure is longer than the first interconnect structure.

[0021] As a preferred embodiment of the present invention, a plurality of capacitor contact nodes and connection pads are formed on the substrate. The capacitor contact nodes are connected to the bottom of the lower electrode layer, and the connection pads are connected to the bottom of the second interconnect structure.

[0022] As a preferred embodiment of the present invention, the upper electrode layer includes a titanium nitride layer formed by atomic layer deposition, the metal filling layer includes a tungsten layer, and the conductive covering layer includes a tungsten nitride layer.

[0023] The present invention also provides a semiconductor memory, which includes the integrated circuit capacitor array structure as described in any of the above embodiments.

[0024] The present invention also provides an integrated circuit capacitor array structure, and the preparation method of the integrated circuit capacitor array structure includes the following steps:

[0025] 1) Provide a substrate;

[0026] 2) Form an alternating stack of a sacrificial layer and a support layer on the substrate;

[0027] 3) Form a patterned mask layer on the alternating stack of the sacrificial layer and the support layer. The patterned mask layer has a plurality of openings for defining the positions and shapes of the capacitor holes;

[0028] 4) Etch the support layer and the sacrificial layer according to the patterned mask layer to form capacitor holes in the support layer and the sacrificial layer;

[0029] 5) Form a lower electrode layer in the capacitor holes, and the support layer is connected to the lower electrode layer;

[0030] 6) Remove the sacrificial layer, wherein the support layer remains on the substrate;

[0031] 7) Form a capacitor dielectric layer on the inner and outer surfaces of the lower electrode layer. The capacitor dielectric layer conformally covers the lower electrode layer;

[0032] 8) Form an upper electrode layer on the surface of the capacitor dielectric layer. The upper electrode layer conformally covers the surface of the capacitor dielectric layer; and

[0033] 9) Form a capacitor plate on the upper electrode layer. The capacitor plate is block-shaped on the substrate and is formed on the upper electrode layer. The capacitor plate includes a metal filling layer and a conductive covering layer that conformally covers the metal filling layer stacked in sequence from bottom to top. The conductive covering layer constitutes the top surface layer and the side surface layer of the upper electrode structure for combining at least one first interconnect structure on the top surface layer.

[0034] As a preferred embodiment of the present invention, between step 8) and step 9), the following step is further included: forming an upper electrode filler on the surface of the upper electrode layer. The upper electrode filler fills the capacitor holes without pores, and the capacitor plate extends from the top surface of the upper electrode filler to the peripheral surface of the substrate outside the coverage area of the upper electrode filler.

[0035] As a preferred embodiment of the present invention, the upper electrode filling body is directly attached to the surface of the upper electrode layer and is also formed between adjacent lower electrode layers. The upper electrode filling body has a top surface and side surfaces, and the metal filling layer formed in step 9) is directly attached to the top surface and the side surfaces of the upper electrode filling body.

[0036] As a preferred embodiment of the present invention, the metal filling layer formed in step 9) fills the capacitor via holes to be electrically connected to the upper electrode layer and make the capacitor via holes in a non-porous filled state.

[0037] As a preferred embodiment of the present invention, the metal filling layer is directly attached to the surface of the upper electrode layer, and the metal filling layer is also formed between the lower electrode layers.

[0038] As a preferred embodiment of the present invention, the upper electrode layer formed in step 8) fills the capacitor via holes without pores and is electrically connected to the capacitor electrode plates.

[0039] As a preferred embodiment of the present invention, in step 1), a plurality of capacitor contact nodes are formed in the substrate; in step 4), the formed capacitor via holes expose the capacitor contact nodes; the support layer formed in step 2) includes a top support layer, an intermediate support layer, and a bottom support layer. The top support layer, the intermediate support layer, and the bottom support layer are all formed on the substrate and are all located within the sacrificial layer, with a spacing therebetween.

[0040] As a preferred embodiment of the present invention, step 9) includes the following steps:

[0041] 9-1) Placing the structure obtained in step 8) in a process chamber and forming the metal filling layer on the top surface of the upper electrode filling body by a sputtering process; and

[0042] 9-2) Introducing nitrogen gas into the process chamber and heating the metal filling layer to form the conductive covering layer on the surface of the metal filling layer.

[0043] As a preferred embodiment of the present invention, in step 9-2), the flow rate of the nitrogen gas introduced into the process chamber is 10 standard milliliters per minute to 20 standard milliliters per minute.

[0044] As a preferred embodiment of the present invention, a connection pad is further formed in the substrate provided in step 1). The connection pad is located outside the covering area of the capacitor electrode plates. After step 9), the following steps are further included:

[0045] 10) Form a dielectric layer on the surface of the structure obtained in step 9), where the dielectric layer covers the upper surface, side surfaces of the capacitor electrodes, and the surface of the substrate;

[0046] 11) Form a first connection via hole and a second connection via hole in the dielectric layer. Among them, the first connection via hole is located on the capacitor electrode and exposes a part of the conductive covering layer of the capacitor electrode, the second connection via hole exposes a part of the connection pad, and the second connection via hole is longer than the first connection via hole; and

[0047] 12) Form a first interconnect structure in the first connection via hole and a second interconnect structure in the second connection via hole. The first interconnect structure is in contact with the capacitor electrode, and the second interconnect structure is in contact with the connection pad.

[0048] As a preferred solution of the present invention, in step 8), a titanium nitride layer is deposited on the surface of the capacitor dielectric layer by atomic layer deposition process as the upper electrode layer, and the metal filling layer includes a tungsten layer, and the conductive covering layer includes a tungsten nitride layer.

[0049] The present invention also provides a method for manufacturing a semiconductor memory, and the method for manufacturing the semiconductor memory includes the step of manufacturing an integrated circuit capacitor array structure by using the method for manufacturing an integrated circuit capacitor array structure described in any of the above solutions.

[0050] As described above, the integrated circuit capacitor array structure, semiconductor memory, and manufacturing method of the present invention have the following beneficial effects:

[0051] The integrated circuit capacitor array structure provided by the present invention can effectively avoid capacitor leakage; at the same time, when forming the capacitor electrodes, there is no need to deposit silicon germanide, and only depositing the metal filling layer / conductive covering layer as the capacitor electrodes can ensure low resistance;

[0052] In the integrated circuit capacitor array structure provided by the present invention, the metal filling layer and the conductive covering layer are used as the capacitor electrodes. The metal filling layer can be used as an etching stop layer for forming connection via holes above it, and can effectively avoid problems such as over-etching through or under-etching resulting in unopened connection via holes during the process of etching to form connection via holes; at the same time, tungsten has a lower resistivity than silicon germanide, and the thickness can be smaller while ensuring the required electrical performance, so that the height of the connection via hole can be reduced, which is beneficial to the subsequent process. Description of the Drawings

[0053] Figure 1 It shows a cross-sectional structure schematic diagram of the integrated circuit capacitor array structure provided in Embodiment 1 of the present invention.

[0054] Figure 2 It shows the process flow chart of the preparation of the integrated circuit capacitor array structure provided in the second embodiment of the present invention.

[0055] Figure 3 It shows the schematic cross-sectional structure diagram of the structure obtained in step 1) of the method for preparing the integrated circuit capacitor array structure provided in the second embodiment of the present invention.

[0056] Figure 4 It shows the schematic cross-sectional structure diagram of the structure obtained in step 2) of the method for preparing the integrated circuit capacitor array structure provided in the second embodiment of the present invention.

[0057] Figure 5 It shows the schematic cross-sectional structure diagram of the structure obtained in step 3) of the method for preparing the integrated circuit capacitor array structure provided in the second embodiment of the present invention.

[0058] Figure 6 It shows the schematic cross-sectional structure diagram of the structure obtained in step 4) of the method for preparing the integrated circuit capacitor array structure provided in the second embodiment of the present invention.

[0059] Figure 7 It shows the schematic cross-sectional structure diagram of the structure obtained in step 5) of the method for preparing the integrated circuit capacitor array structure provided in the second embodiment of the present invention.

[0060] Figure 8 It shows the schematic cross-sectional structure diagram of the structure obtained in step 6) of the method for preparing the integrated circuit capacitor array structure provided in the second embodiment of the present invention.

[0061] Figure 9 It shows the schematic cross-sectional structure diagram of the structure obtained in step 7) of the method for preparing the integrated circuit capacitor array structure provided in the second embodiment of the present invention.

[0062] Figures 10 to 11 It shows the schematic cross-sectional structure diagram of the structure obtained in step 8) of the method for preparing the integrated circuit capacitor array structure provided in the second embodiment of the present invention.

[0063] Figure 12 It shows the schematic cross-sectional structure diagram of the structure obtained in step 9) of the method for preparing the integrated circuit capacitor array structure provided in the second embodiment of the present invention.

[0064] Figure 13 It shows the schematic cross-sectional structure diagram of the structure obtained in step 10) of the method for preparing the integrated circuit capacitor array structure provided in the second embodiment of the present invention.

[0065] Figure 14 It shows the schematic cross-sectional structure diagram of the structure obtained in step 11) of the method for preparing the integrated circuit capacitor array structure provided in the second embodiment of the present invention.

[0066] Figure 15 Schematic cross-sectional view of the structure obtained in step 12) of the method for preparing an integrated circuit capacitor array structure provided in Embodiment 2 of the present invention.

[0067] Figure 16 Schematic cross-sectional view of the integrated circuit capacitor array structure provided in Embodiment 3 of the present invention.

[0068] Figures 17 to 18 Schematic cross-sectional view of the structure obtained in step 8) of the method for preparing an integrated circuit capacitor array structure provided in Embodiment 4 of the present invention.

[0069] Figure 19 Schematic cross-sectional view of the integrated circuit capacitor array structure provided in Embodiment 5 of the present invention.

[0070] Figure 20 Schematic cross-sectional view of the structure obtained in step 8) of the method for preparing an integrated circuit capacitor array structure provided in Embodiment 6 of the present invention.

[0071] Figure 21 Schematic cross-sectional view of the structure obtained in step 9) of the method for preparing an integrated circuit capacitor array structure provided in Embodiment 6 of the present invention.

[0072] Element number description

[0073] 10 Substrate

[0074] 111 Lower electrode layer

[0075] 12 Capacitor dielectric layer

[0076] 112 Upper electrode layer

[0077] 13 Upper electrode filler

[0078] 131 Top surface

[0079] 132 Side surface

[0080] 14 Capacitor electrode plate

[0081] 141 Metal filling layer

[0082] 142 Titanium nitride layer

[0083] 15 Bottom support layer

[0084] 16 Intermediate support layer

[0085] 17 Top support layer

[0086] 171 First opening

[0087] 18 Dielectric layer

[0088] 181 First connection via hole

[0089] 182 Second connection via hole

[0090] 19 First interconnect structure

[0091] 20 Second interconnect structure

[0092] 21 Capacitive contact node

[0093] 211 Diffusion barrier layer

[0094] 22 Connection pad

[0095] 23 Sacrificial layer

[0096] 24 Patterned mask layer

[0097] 241 Opening

[0098] 25 Capacitor via hole

[0099] S1 to S9 Steps 1) to 9) Detailed implementation manner

[0100] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0101] Please refer to Figures 1 to 15 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although only the components related to the present invention are shown in the diagrams and are not drawn according to the number, shape, and size of the components in actual implementation, the form, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout form may also be more complex.

[0102] Embodiment 1

[0103] As Figure 1As shown in the figure, the present invention provides an integrated circuit capacitor array structure, which includes: a substrate 10; a lower electrode layer 111, which protrudes on the substrate 10, and capacitance holes are formed in the lower electrode layer 111; a capacitance dielectric layer 12, which conformally covers the surface of the lower electrode layer 111; an upper electrode layer 112, which is located on the substrate 10 and conformally covers the surface of the capacitance dielectric layer 12; and a capacitor plate 14, which is block-shaped on the substrate 10 and formed on the upper electrode layer 112. The capacitor plate 14 includes a metal filling layer 141 stacked in sequence from bottom to top and a conductive covering layer 142 that conformally covers the metal filling layer. The conductive covering layer 142 constitutes the top surface layer and the side surface layer of the upper electrode structure for bonding at least one first interconnect structure 19 on the top surface layer.

[0104] As the best example, applicable to the design with a more reduced aperture of the capacitance holes, the upper electrode layer 112 fills the capacitance holes without pores and is electrically connected to the capacitor plate 14. The upper electrode layer 112 in the integrated circuit capacitor array structure provided by the present invention can specifically be formed by filling titanium nitride in the capacitance holes without pores, so as to effectively avoid capacitor leakage. At the same time, by filling the upper electrode layer 112 without pores, when forming the capacitor plate 14, there is no need to deposit semiconductor pore filling materials such as silicon germanide, and only depositing the metal filling layer 141 and the conductive covering layer 142 as the capacitor plate 14 can ensure low resistance. In the integrated circuit capacitor array structure provided by the present invention, the metal filling layer 141 and the conductive covering layer 142 are used as the capacitor plate 14. The metal filling layer 141 can be used as an etching stop layer for forming connection vias above it, and can effectively avoid problems such as over-etching through holes or incomplete etching resulting in unopened connection vias during the process of etching to form the connection vias. At the same time, tungsten has a lower resistivity than silicon germanide, and the thickness can be smaller while ensuring the required electrical performance, so as to reduce the height of the connection vias, which is beneficial to the subsequent process.

[0105] As an example, the substrate 10 of the base material may be a semiconductor material such as silicon, and a memory array transistor structure and a dielectric layer may be formed on the surface. The memory array structure may include a plurality of capacitor contact nodes 21 located in the memory array structure and a plurality of connection pads 22. The capacitor contact nodes 21 may include tungsten pads, and the connection pads 22 may also include tungsten pads. The memory array structure may further include a transistor word line and a bit line. The bottom of the capacitor contact node 21 is electrically connected to the transistor source in the memory array structure, and the top of the capacitor contact node 21 is connected to the bottom of the lower electrode layer 111. A diffusion barrier layer (211) may be formed on the bottom or / and side surface of the capacitor contact node 21; specifically, the diffusion barrier layer has a U-shaped cross-sectional shape.

[0106] As an example, the capacitor contact nodes 21 may, but are not limited to, be arranged in a hexagonal array, and the capacitor arrangement in the integrated circuit capacitor array structure may correspond to that of the capacitor contact nodes 21.

[0107] As an example, the capacitor contact nodes 21, the connection pads 22, and between the capacitor contact nodes 21 and the connection solder joints 22 may be isolated by an isolation structure, and the material of the isolation structure may include at least one of silicon nitride, silicon oxide, and aluminum oxide.

[0108] As an example, the lower electrode layer 111 may include a conductive compound formed by one or two of metal nitride and metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride (TiSi x N y ). In this embodiment, the lower electrode layer 111 may include a titanium nitride layer formed by atomic layer deposition (ALD). The shape of the lower electrode layer 111 may be an elongated tube protruding from the substrate 10. The arrangement of the plurality of tubular lower electrode layers 111 may be arranged in a hexagonal array.

[0109] As an example, the capacitor dielectric layer 12 may be a high-K dielectric layer to increase the capacitance value of the capacitor per unit area, and it includes ZrO x 、HfO x 、ZrTiO x 、RuO x 、SbO x 、AlO xA laminate formed by one of the above materials or two or more of the groups formed by the above materials. Specifically, the capacitive dielectric layer 12 conformally covers the inner and outer surfaces of the tubular lower electrode layer 111 exposed to the substrate 10.

[0110] As an example, the upper electrode layer 112 may include a compound formed by one or two of metal nitrides and metal silicides, such as Titanium Nitride, Titanium Silicide, Titanium Silicide, TiSi x N y )). Preferably, in this embodiment, the upper electrode layer 112 includes a titanium nitride layer formed by atomic layer deposition (ALD). The upper electrode layer 112 is specifically attached directly to the surface of the capacitive dielectric layer 12 along the outer contour of the lower electrode layer 111.

[0111] As an example, the metal filling layer 141 may include a tungsten layer, and the conductive covering layer 142 may include a tungsten nitride layer.

[0112] As an example, the metal filling layer 141 may be directly electrically connected to the upper electrode layer 112.

[0113] As an example, the capacitor plate 14 extends from the top surface of the upper electrode layer 112 to the surface of the substrate 10 to cover the capacitor array.

[0114] As an example, the integrated circuit capacitor array structure further includes a bottom support layer 15, an intermediate support layer 16, and a top support layer 17, all formed on the substrate 10 and connecting and supporting the lower electrode layer 111; the bottom support layer 15 is located at the bottom periphery of the lower electrode layer 111, the intermediate support layer 16 is located in the middle of the lower electrode layer 111, the top support layer 17 is located at the periphery of the opening of the lower electrode layer 111, and extends perpendicular to the extending direction of the U-shaped side wall of the lower electrode layer 111.

[0115] As an example, the bottom support layer 15, the intermediate support layer 16, and the top support layer 17 are arranged in parallel at intervals.

[0116] As an example, the bottom support layer 15, the intermediate support layer 16, and the top support layer 17 may all include, but are not limited to, silicon nitride layers.

[0117] As an example, the capacitor array structure may further include: a dielectric layer 18, a first interconnect structure 19, and a second interconnect structure 20; the dielectric layer 18 is formed on the substrate 10 and covers the upper surface, side surfaces, and peripheral surfaces on the substrate 10 of the capacitor plate 14; the first interconnect structure 19 is located within the dielectric layer 18 and on the capacitor plate 14 and is connected to the conductive covering layer 142 of the capacitor plate 14 to electrically lead out the capacitor plate 14. Specifically, the first interconnect structure 19 may be connected to the upper surface of the capacitor plate 14; the second interconnect structure 20 is located within the dielectric layer 18 and outside the covering area of the capacitor plate 14. The second interconnect structure 20 is longer than the first interconnect structure 19, and the bottom of the second interconnect structure 20 is connected to the connection pad 22 to electrically lead out the connection pad 22.

[0118] As an example, the dielectric layer 18 may include, but is not limited to, a silicon oxide layer or a silicon nitride layer. The materials of the first interconnect structure 19 and the second interconnect structure 20 may include, but are not limited to, tungsten (W), copper (Cu), nickel (Ni), gold (Au), silver (Ag), etc. The forms of the first interconnect structure 19 and the second interconnect structure 20 may be plugs.

[0119] Embodiment 2

[0120] Please refer to Figure 2 , the present invention further provides a method for manufacturing an integrated circuit capacitor array structure. The method for manufacturing the integrated circuit capacitor array structure includes the following steps:

[0121] 1) Provide a substrate;

[0122] 2) Form an alternating stack of a sacrificial layer and a support layer on the substrate;

[0123] 3) Form a patterned mask layer on the alternating stack of the sacrificial layer and the support layer. The patterned mask layer has a plurality of openings for defining the positions and shapes of the capacitor holes;

[0124] 4) Etch the support layer and the sacrificial layer according to the patterned mask layer to form capacitor holes in the support layer and the sacrificial layer;

[0125] 5) Form a lower electrode layer in the capacitor holes, and the support layer is connected to the lower electrode layer;

[0126] 6) Remove the sacrificial layer, wherein the support layer remains on the substrate;

[0127] 7) Form a capacitor dielectric layer on the inner surface and the outer surface of the lower electrode layer. The capacitor dielectric layer conformally covers the lower electrode layer;

[0128] 8) Form an upper electrode layer on the surface of the capacitive dielectric layer, the upper electrode layer covering the surface of the capacitive dielectric layer; and

[0129] 9) Form a capacitor plate on the upper electrode layer, the capacitor plate being block-shaped on the substrate and formed on the upper electrode layer, the capacitor plate including a metal filling layer stacked in sequence from bottom to top and a conductive covering layer conformally covering the tungsten layer, the conductive covering layer constituting the top surface layer and the side surface layer of the upper electrode structure for bonding at least one first interconnect structure on the top surface layer.

[0130] In step 1), refer to Figure 2 the S1 step in Figure 3 , and provide a substrate 10.

[0131] As an example, a memory array structure may be formed in the substrate 10, the memory array structure may include a plurality of capacitive contact nodes 21 located in the memory array structure and a plurality of connection pads 22, the connection pads 22 may include tungsten pads. The memory array structure may further include a transistor word line and a bit line, the bottom of the capacitive contact node 21 is electrically connected to the transistor source in the memory array structure, and the top of the capacitive contact node 21 is connected to the bottom of the lower electrode layer 111.

[0132] As an example, the capacitive contact nodes 21 may but are not limited to be arranged in a hexagonal array, and the arrangement of the capacitive contact nodes 21 may correspond to the capacitance arrangement in the integrated circuit capacitor array structure.

[0133] As an example, between the capacitive contact nodes 21, between the connection pads 22, and between the capacitive contact nodes 21 and the connection solder joints 22 may be isolated by an isolation structure, and the material of the isolation structure may include at least one of silicon nitride, silicon oxide, and aluminum oxide.

[0134] In step 2), refer to Figure 2 the S2 step in Figure 4 , and form an alternately stacked sacrificial layer 23 and support layers 15, 16, 17 on the substrate 10.

[0135] As an example, the sacrificial layer 23 and the support layers 15, 16, 17 are formed by an atomic layer deposition process or a chemical vapor deposition process.

[0136] As an example, the sacrificial layer 23 is made of a material different from that of the support layer. By taking advantage of the fact that the etching rate of the sacrificial layer 23 is different from that of the support layer in the same etching process, specifically, in the subsequent same wet etching process, the etching rate of the sacrificial layer 23 is much greater than that of the support layer, so that when the sacrificial layer 23 is completely removed, the support layers 15, 16, and 17 can be almost completely retained (as Figure 8 shown).

[0137] Preferably, in this embodiment, the sacrificial layer 23 can be a polysilicon layer or a borophosphosilicate glass (BPSG), and the support layer can be a silicon nitride layer.

[0138] As an example, the support layer includes a top support layer 17, an intermediate support layer 16, and a bottom support layer 15. The top support layer 17, the intermediate support layer 16, and the bottom support layer 15 are all formed on the substrate 10, and the sacrificial layer 23 can separate the support layers from each other, so that there is a spacing between the upper and lower support layers.

[0139] In step 3), please refer to Figure 2 the S3 step in Figure 5 , and form a patterned mask layer 24 on the alternately stacked sacrificial layer 23 and support layers 15, 16, and 17. The patterned mask layer 24 has a plurality of openings 241 therein, which are used to define the position and shape of the capacitor holes 25.

[0140] As an example, first, a photoresist is formed on the upper surfaces of the alternately stacked sacrificial layer 23 and support layers as a mask layer. Of course, in other examples, a mask layer made of other materials (such as a silicon nitride hard mask layer, etc.) can also be formed; then, the mask layer is patterned by a photolithography process to obtain the patterned mask layer 24 having the openings 241.

[0141] As an example, the openings 241 can be arranged in a hexagonal array along the surface of the patterned mask layer 24, and can be aligned with the capacitor contact nodes 21.

[0142] It should be noted that the openings 241 in the patterned mask layer 24 also define the shape and position of the region outside the capacitor array.

[0143] In step 4), please refer to Figure 2 the S4 step in Figure 6 , and etch the support layer and the sacrificial layer 23 according to the patterned mask layer 24 to form capacitor holes 25 in the support layer and the sacrificial layer 23.

[0144] As an example, the specific method of step 4) is as follows: According to the patterned mask layer 24, a dry etching process or a plasma-enhanced dry etching process can be used to etch the support layer and the sacrificial layer 23 to form the vertically penetrating capacitor holes 25 in the support layer and the sacrificial layer 23, and the capacitor holes 25 expose the capacitor contact nodes 21, as Figure 6 shown.

[0145] It should be noted that when the opening 241 in the patterned mask layer 24 also defines the shape and position of the area outside the capacitor array, the support layer and the sacrificial layer 23 located outside the capacitor array are also removed in this step.

[0146] It should be further noted that after step 4), the bottom support layer 15 in the area outside the capacitor array can be Figure 8 retained as shown, or can be removed in step 4).

[0147] In step 5), please refer to Figure 2 the S5 step in and Figure 7 , and a lower electrode layer 111 is formed in the capacitor holes 25, and the support layers 15, 16, 17 are connected to the lower electrode layer 111.

[0148] As an example, first, an atomic layer deposition process (Atomic Layer Deposition) or a chemical vapor deposition process (Chemical Vapor Deposition) is used to deposit a lower electrode material layer on the sidewalls and bottom of the capacitor holes 25 and on the sacrificial layer 23. The lower electrode material layer includes a compound formed by one or two of metal nitrides and metal silicides, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide), titanium silicon nitride (TiSixNy); then, an etching process is used to remove the lower electrode material layer on the sacrificial layer 23, and the remaining lower electrode material layer on the sidewalls and bottom of the capacitor holes 25 forms the lower electrode layer 111.

[0149] In step 6), please refer to Figure 2 the S6 step in and Figure 8 , and a wet etching process or a combination thereof can be used to remove the sacrificial layer 23, wherein the support layers 15, 16, 17 are retained on the substrate 10.

[0150] As an example, step 6) can specifically include the following steps:

[0151] 6-1) Form a first opening 171 in the top support layer 17 first, and the first opening 171 exposes a first part of the sacrificial layer 23 between the top support layer 17 and the intermediate support layer 16;

[0152] 6-2) Through the first opening 171, use a wet etching process to remove the first part of the sacrificial layer 23 between the top support layer 17 and the intermediate support layer 16;

[0153] 6-3) For the first opening 171, form a second opening in the intermediate support layer 16, and the second opening exposes a second part of the sacrificial layer 23 between the intermediate support layer 16 and the substrate 10;

[0154] 6-4) Through the second opening, use a wet etching process to remove the second part of the sacrificial layer 23 between the intermediate support layer 26 and the substrate 10.

[0155] As an example, between step 6-2) and step 6-3), there is also a step of depositing a support layer material on the upper surface of the top support layer 17 to thicken the top support layer 17. This is because during step 6-2), a part of the top support layer 17 will be removed. In order to prevent the top support layer 17 from being etched through during the subsequent corrosion process and to ensure that the top support layer 17 has sufficient support strength, it is necessary to add a step of depositing a support layer material on the upper surface of the top support layer 17 between step 6-2) and step 6-3).

[0156] As an example, in step 6-1), one first opening 171 can only partially overlap with one capacitor hole 25, or / and one first opening 171 can simultaneously partially overlap with multiple capacitor holes 25; in step 6-2), one second opening can only partially overlap with one capacitor hole 25, or / and one second opening can simultaneously partially overlap with multiple capacitor holes 25.

[0157] In step 7), please refer to Figure 2 step S7 in Figure 9 as shown, form a capacitor dielectric layer 12 on the inner surface and the outer surface of the lower electrode layer 111, and the capacitor dielectric layer 12 conformally covers the lower electrode layer 111.

[0158] As an example, the material of the capacitor dielectric layer 12 can be selected as a high-K dielectric material to increase the capacitance value of the capacitor per unit area, and it includes one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx or a laminate formed by two or more of the above materials in a group.

[0159] In step 8), refer to Figure 2 step S8 in Figures 10 to 11 , and form an upper electrode layer 112 on the surface of the capacitive dielectric layer 12, and the upper electrode layer 112 covers the surface of the capacitive dielectric layer 12.

[0160] As an example, the upper electrode layer 112 can fill the capacitive holes 25 without pores and is used for electrical connection to the capacitive electrode plate 14.

[0161] As an example, an atomic layer deposition process (ALD) can be used to deposit a titanium nitride layer on the surface of the capacitive dielectric layer 12 as the upper electrode layer 112.

[0162] As an example, at the beginning of the formation of the upper electrode layer 112, the upper electrode layer 112 can also cover the area outside the capacitive array and also cover the area where the connection pad 22 is located (as Figure 10 shown); at this time, it is also necessary to perform the step of removing the upper electrode layer 112 in the area outside the capacitive array, and the resulting structure after removal is as Figure 11 shown.

[0163] In step 9), refer to Figure 2 step S9 in Figure 12 , and form a capacitive electrode plate 14 on the upper electrode layer 112. The capacitive electrode plate 14 is block-shaped on the substrate 10 and is formed on the upper electrode layer 112. The capacitive electrode plate 14 includes a metal filling layer 141 stacked in sequence from bottom to top and a conductive covering layer 142 conformally covering the metal filling layer 141. The conductive covering layer 142 constitutes the top surface layer and the side surface layer of the upper electrode structure for bonding at least one first interconnect structure on the top surface layer.

[0164] As an example, step 9) includes the following steps:

[0165] 9-1) Place the structure obtained in step 8) in a process chamber, and use a sputtering process to form the metal filling layer 141 on the surface of the upper electrode layer 112; and

[0166] 9-2) Introduce nitrogen gas into the process chamber, and heat the metal filling layer 141 to form the conductive covering layer 142 on the surface of the metal filling layer 141.

[0167] As an example, in step 9-2), the flow rate of introducing the nitrogen gas into the process chamber can be 10 standard milliliters per minute to 20 standard milliliters per minute.

[0168] As an example, the capacitor plate 14 extends from the top surface of the upper electrode layer 112 to the surface of the substrate 10 to cover the capacitor array.

[0169] As an example, the metal filling layer 141 is electrically connected to the part of the upper electrode layer 112 within the lower electrode layer 111 and the part between the lower electrode layers 111.

[0170] As an example, the metal filling layer 141 may include a tungsten layer, and the conductive covering layer 142 may include a titanium nitride layer.

[0171] In the integrated circuit capacitor array structure provided by the present invention, the metal filling layer 141 and the conductive covering layer 142 are used as the capacitor plate 14. The metal filling layer 141 can be used as an etching stop layer for forming connection vias above it, and can effectively avoid problems such as over-etching through holes or unopened connection vias caused by insufficient etching during the process of etching to form the connection vias. At the same time, tungsten has a lower resistivity than silicon germanide, and the thickness can be smaller while ensuring the required electrical performance, so that the height of the connection vias can be reduced, which is beneficial to the subsequent process.

[0172] As an example, please refer to Figures 13 to 15 , after step 9), the following steps are further included:

[0173] 10) A dielectric layer 18 is formed on the surface of the structure obtained in step 9), and the dielectric layer 18 covers the upper surface, side surface of the capacitor plate 14 and the surface of the substrate 10; specifically, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process can be used to form the dielectric layer 18 on the upper surface and side surface of the capacitor plate 14 and the surface of the substrate 10 outside the array region, as Figure 13 shown; the dielectric layer 18 may include but is not limited to a silicon oxide layer or a silicon nitride layer;

[0174] 11) A first connection via 181 and a second connection via 182 are formed in the dielectric layer 18. Among them, the first connection via 181 is located on the capacitor plate 14 and exposes a part of the conductive covering layer 142 of the capacitor plate 14, and the second connection via 182 exposes a part of the connection pad 22. The second connection via 182 is longer than the first connection via 181, as Figure 14 shown; specifically, the first connection via 181 and the second connection via 182 can be formed by a photolithography and dry etching process; and

[0175] (12) A first interconnect structure 19 is formed within the first connection through-hole 181, and a second interconnect structure 20 is formed within the second connection through-hole 182. The first interconnect structure 19 is in contact with the capacitor plate 14, and the second interconnect structure 20 is in contact with the connection pad 22, as Figure 15 shown; specifically, processes such as electroplating and deposition can be used to deposit tungsten (W), copper (Cu), nickel (Ni), gold (Au), silver (Ag), etc. within the first connection through-hole 181 and the second connection through-hole 182 to form the first interconnect structure 19 and the second interconnect structure 20.

[0176] Embodiment III

[0177] Please refer to Figure 16 and compare with the reference Figure 1 . The present invention also provides an integrated circuit capacitor array structure. The integrated circuit capacitor array structure described in this embodiment is substantially the same as the integrated circuit capacitor array structure described in Embodiment I. The difference between the two is that: in Embodiment I, the upper electrode layer 112 fills the capacitor hole without pores; in this embodiment, the upper electrode layer 112 does not fill the capacitor hole. Compared with Embodiment I, the integrated circuit capacitor array structure described in this embodiment further includes an upper electrode filler 13. The upper electrode filler 13 is located between the upper electrode layer 112 and the capacitor plate 114 and fills the capacitor hole without pores. The capacitor plate 14 extends from the top surface of the upper electrode filler 13 to the peripheral surface of the substrate 10 outside the coverage area of the upper electrode filler 13, and is applicable to the design with a relatively large aperture of the capacitor hole.

[0178] As an example, the upper electrode filler 13 is directly attached to the surface of the upper electrode layer 112 and is also formed between adjacent lower electrode layers 111. The upper electrode filler 13 has a top surface 131 and a side surface 132. The metal filling layer 141 is directly attached to the top surface 131 and the side surface 132 of the upper electrode filler 13.

[0179] As an example, the upper electrode filler 13 may include, but is not limited to, a polysilicon layer or a silicon germanide (SiGe) layer. The upper surface of the upper electrode filler 13 is 10 nm to 100 nm higher than the top of the capacitor dielectric layer 12.

[0180] The other structures of the integrated circuit capacitor array structure described in this embodiment are the same as the corresponding structures in the integrated circuit capacitor array structure described in Embodiment I. For details, please refer to Embodiment I and will not be repeated here.

[0181] Embodiment IV

[0182] Please refer to Figures 17 to 18, the present invention also provides a method for manufacturing an integrated circuit capacitor array structure. The method for manufacturing the integrated circuit capacitor array structure described in this embodiment is substantially the same as that in the corresponding embodiment two. The difference between the two is that: in step 8) of embodiment two, the upper electrode layer 112 formed has no pores and fills the capacitor holes 25; while in this embodiment, the upper electrode layer 112 formed in step 8) does not fill the capacitor holes 25, and between step 8) and step 9), the following steps are further included: forming an upper electrode filler 13 on the surface of the upper electrode layer 112, the upper electrode filler 13 has no pores and fills the capacitor holes 25, and the capacitor electrode plate 14 extends from the top surface of the upper electrode filler 13 to the peripheral surface of the substrate 10 outside the coverage area of the upper electrode filler 13. Figures 2 to 15 The method for manufacturing the integrated circuit capacitor array structure described above is substantially the same. The difference between the two is that: in step 8) of embodiment two, the upper electrode layer 112 formed has no pores and fills the capacitor holes 25; while in this embodiment, the upper electrode layer 112 formed in step 8) does not fill the capacitor holes 25, and between step 8) and step 9), the following steps are further included: forming an upper electrode filler 13 on the surface of the upper electrode layer 112, the upper electrode filler 13 has no pores and fills the capacitor holes 25, and the capacitor electrode plate 14 extends from the top surface of the upper electrode filler 13 to the peripheral surface of the substrate 10 outside the coverage area of the upper electrode filler 13.

[0183] As an example, the upper electrode filler 13 is directly attached to the surface of the upper electrode layer 112 and is also formed between adjacent lower electrode layers 111. The upper electrode filler 13 has a top surface 131 and a side surface 132; the metal filler layer 141 formed in step 9) is directly attached to the top surface 131 and the side surface 132 of the upper electrode filler 13.

[0184] As an example, the upper electrode filler 13 may include but is not limited to a titanium nitride filler. The upper surface of the upper electrode filler 13 is 10 nm to 100 nm higher than the top of the capacitor dielectric layer 12.

[0185] Other steps of the method for manufacturing the integrated circuit capacitor array structure described in this embodiment are the same as the corresponding steps in the method for manufacturing the integrated circuit capacitor array structure described in embodiment two. For details, please refer to embodiment two, and will not be repeated here.

[0186] Embodiment Five

[0187] Please refer to Figure 19 And compare with Figure 1 , the present invention also provides an integrated circuit capacitor array structure. The integrated circuit capacitor array structure described in this embodiment is substantially the same as the integrated circuit capacitor array structure described in embodiment one. The difference between the two is that: in embodiment one, the upper electrode layer 112 has no pores and fills the capacitor holes; in this embodiment, the upper electrode layer 112 does not fill the capacitor holes, and the metal filler layer 141 in this embodiment fills the capacitor holes to be electrically connected to the upper electrode layer 112 and makes the inside of the capacitor holes in a non-porous filled state, which is applicable to the design of medium pore diameter size of the capacitor holes.

[0188] As an example, the metal filling layer 141 is directly attached to the surface of the upper electrode layer 112, and the metal filling layer 141 is also formed between the lower electrode layers 111.

[0189] Other structures of the integrated circuit capacitor array structure described in this embodiment are the same as the corresponding structures in the integrated circuit capacitor array structure described in Embodiment 1. For details, please refer to Embodiment 1 and will not be repeated here.

[0190] Embodiment 6

[0191] Please refer to Figures 2 to 15 and Figures 20 to 21 , the present invention also provides a method for manufacturing an integrated circuit capacitor array structure. The method for manufacturing the integrated circuit capacitor array structure described in this embodiment is substantially the same as the method for manufacturing the integrated circuit capacitor array structure described in Embodiment 2. The difference between the two is that: in step 8) of Embodiment 2, the upper electrode layer 112 formed has no pores and fills the capacitor holes 25; while in this embodiment, in step 8), the upper electrode layer 112 formed does not fill the capacitor holes 25, and in step 9), the metal filling layer 141 formed fills the capacitor holes 25 to electrically connect the upper electrode layer 112 and make the capacitor holes 25 in a non-porous filled state, that is, the metal filling layer 141 fills the capacitor holes 25 without pores.

[0192] As an example, the metal filling layer 141 is directly attached to the surface of the upper electrode layer 112, and the metal filling layer 141 is also formed between the lower electrode layers 111.

[0193] Other steps of the method for manufacturing the integrated circuit capacitor array structure described in this embodiment are the same as the corresponding steps in the method for manufacturing the integrated circuit capacitor array structure described in Embodiment 2. For details, please refer to Embodiment 2 and will not be repeated here.

[0194] Embodiment 7

[0195] Please continue to refer to Figure 1 , Figure 16 and 19 , this embodiment also provides a semiconductor memory. The semiconductor memory includes an integrated circuit capacitor array structure as described in any one of Embodiment 1, Embodiment 3, or Embodiment 5. For the specific structure of the integrated circuit capacitor array structure, please refer to Embodiment 1, Embodiment 3, and Embodiment 5 and will not be repeated here.

[0196] As an example, the semiconductor memory structure further includes a transistor structure, and each memory cell generally includes a capacitor and a transistor; the gate of the transistor is connected to a word line, the drain of the transistor is connected to a bit line, and the source of the transistor is connected to the capacitor; the voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0197] Embodiment VIII

[0198] Please continue to refer to Figures 2 to 15 、 Figures 17 to 18 and Figures 20 to 21 This embodiment also provides a method for manufacturing a semiconductor memory. The method for manufacturing the semiconductor memory includes a step of manufacturing an integrated circuit capacitor array structure by using the method for manufacturing an integrated circuit capacitor array structure described in any one of Embodiment II, Embodiment IV, and Embodiment VI. For the method for manufacturing the integrated circuit capacitor array structure, please refer to Embodiment II, Embodiment IV, and Embodiment VI, and details will not be repeated here.

[0199] In summary, the present invention provides an integrated circuit capacitor array structure, a semiconductor memory, and a manufacturing method. The integrated circuit capacitor array structure includes: a substrate; a lower electrode layer protruding on the substrate, with capacitor holes formed in the lower electrode layer; a capacitive dielectric layer conformally covering the surface of the lower electrode layer; an upper electrode layer conformally covering the surface of the capacitive dielectric layer; a capacitor plate block-shaped on the substrate and formed on the upper electrode layer. The capacitor plate includes a metal filling layer stacked in sequence from bottom to top and a conductive covering layer conformally covering the metal filling layer. The conductive covering layer constitutes the top surface layer and the side surface layer of the upper electrode structure for bonding at least one first interconnect structure on the top surface layer. The integrated circuit capacitor array structure provided by the present invention can effectively avoid capacitor leakage; at the same time, when forming the capacitor plate, there is no need to deposit silicon germanide, and only depositing the metal filling layer / conductive covering layer as the capacitor plate can ensure low resistance; in the integrated circuit capacitor array structure provided by the present invention, the metal filling layer and the conductive covering layer are used as the capacitor plate. The metal filling layer can be used as an etching stop layer for forming connection vias above it, and can effectively avoid problems such as over-etching through holes or incomplete etching resulting in unopened connection vias during the process of etching to form connection vias; at the same time, tungsten has a lower resistivity than silicon germanide, and the thickness can be smaller while ensuring the required electrical performance, thereby reducing the height of the connection vias and facilitating subsequent processes.

[0200] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. An integrated circuit capacitor array structure, characterized in that, comprising: a substrate; a lower electrode layer, protruding on the substrate, and having capacitor holes formed therein; a capacitor dielectric layer, conformally covering the surface of the lower electrode layer; an upper electrode layer, conformally covering the surface of the capacitor dielectric layer; a capacitor electrode plate, block-shaped on the substrate and formed on the upper electrode layer, the capacitor electrode plate including a metal filling layer stacked in sequence from bottom to top and a conductive covering layer conformally covering the metal filling layer, the conductive covering layer constituting the top surface layer and the side surface layer of the upper electrode structure for bonding at least one first interconnect structure on the top surface layer; the metal filling layer is a tungsten layer, and the conductive covering layer is a tungsten nitride layer.

2. The integrated circuit capacitor array structure according to claim 1, characterized in that, further comprising an upper electrode filler, located between the upper electrode layer and the capacitor electrode plate and filling the capacitor holes without voids, and the capacitor electrode plate extending from the top surface of the upper electrode filler to the peripheral surface of the substrate outside the coverage area of the upper electrode filler.

3. The integrated circuit capacitor array structure according to claim 2, characterized in that, the upper electrode filler is directly attached to the surface of the upper electrode layer and is also formed between adjacent lower electrode layers, the upper electrode filler having a top surface and a side surface, and the metal filling layer being directly attached to the top surface and the side surface of the upper electrode filler.

4. The integrated circuit capacitor array structure according to claim 1, characterized in that, the metal filling layer fills the capacitor holes to be electrically connected to the upper electrode layer and makes the capacitor holes filled without voids.

5. The integrated circuit capacitor array structure according to claim 4, characterized in that, the metal filling layer is directly attached to the surface of the upper electrode layer, and the metal filling layer is also formed between the lower electrode layers.

6. The integrated circuit capacitor array structure according to claim 1, characterized in that, the upper electrode layer fills the capacitor holes without voids and is electrically connected to the capacitor electrode plate.

7. The integrated circuit capacitor array structure according to claim 1, characterized in that, further comprising a bottom support layer, an intermediate support layer and a top support layer, all formed on the substrate and connecting and supporting the lower electrode layer; the bottom support layer is located at the bottom periphery of the lower electrode layer, the intermediate support layer is located at the middle part of the lower electrode layer, and the top support layer is located at the periphery of the opening of the lower electrode layer.

8. The integrated circuit capacitor array structure according to claim 1, characterized in that, further comprising: a dielectric layer, formed on the substrate and covering the upper surface, side surface of the capacitor electrode plate and the peripheral surface on the substrate; the first interconnect structure, located in the dielectric layer and on the capacitor electrode plate and connected to the conductive covering layer of the capacitor electrode plate; and a second interconnect structure, located in the dielectric layer and outside the coverage area of the capacitor electrode plate, the second interconnect structure being longer than the first interconnect structure.

9. The integrated circuit capacitor array structure according to claim 8, wherein, a plurality of capacitor contact nodes and connection pads are formed on the substrate, the capacitor contact nodes are connected to the bottom of the lower electrode layer, and the connection pads are connected to the bottom of the second interconnect structure.

10. A semiconductor memory, wherein, the semiconductor memory includes the integrated circuit capacitor array structure according to claim 1.

11. A method for manufacturing an integrated circuit capacitor array structure, wherein, the manufacturing method includes the following steps: 1) Provide a substrate; 2) Form an alternating stack of a sacrificial layer and a support layer on the substrate; 3) Form a patterned mask layer on the alternating stack of the sacrificial layer and the support layer, and the patterned mask layer has a plurality of openings for defining the positions and shapes of capacitor holes; 4) Etch the support layer and the sacrificial layer according to the patterned mask layer to form capacitor holes in the support layer and the sacrificial layer; 5) Form a lower electrode layer in the capacitor holes, and the support layer connects the lower electrode layer; 6) Remove the sacrificial layer, wherein the support layer remains on the substrate; 7) Form a capacitor dielectric layer on the inner and outer surfaces of the lower electrode layer, and the capacitor dielectric layer conformally covers the lower electrode layer; 8) Form an upper electrode layer on the surface of the capacitor dielectric layer, and the upper electrode layer conformally covers the surface of the capacitor dielectric layer; and 9) Form a capacitor plate on the upper electrode layer, the capacitor plate is block-shaped on the substrate and formed on the upper electrode layer, the capacitor plate includes a metal filling layer stacked in sequence from bottom to top and a conductive covering layer conformally covering the metal filling layer, and the conductive covering layer constitutes the top surface layer and the side surface layer of the upper electrode structure for bonding at least one first interconnect structure on the top surface layer; the metal filling layer is a tungsten layer, and the conductive covering layer is a tungsten nitride layer.

12. The method for manufacturing an integrated circuit capacitor array structure according to claim 11, wherein, a step is further included between step 8) and step 9): form an upper electrode filler on the surface of the upper electrode layer, the upper electrode filler fills the capacitor holes without voids, and the capacitor plate extends from the top surface of the upper electrode filler to the peripheral surface of the substrate outside the coverage area of the upper electrode filler.

13. The method for manufacturing an integrated circuit capacitor array structure according to claim 12, wherein, the upper electrode filler is directly attached to the surface of the upper electrode layer and is also formed between adjacent lower electrode layers, the upper electrode filler has a top surface and a side surface, and the metal filling layer formed in step 9) is directly attached to the top surface and the side surface of the upper electrode filler.

14. The method for manufacturing an integrated circuit capacitor array structure according to claim 11, wherein, the metal filling layer formed in step 9) fills the capacitor holes to be electrically connected to the upper electrode layer and makes the inside of the capacitor holes in a non-porous filled state.

15. The method for fabricating an integrated circuit capacitor array structure according to claim 14, characterized in that, the metal filling layer is directly attached to the surface of the upper electrode layer, and the metal filling layer is also formed between the lower electrode layers.

16. The method for fabricating an integrated circuit capacitor array structure according to claim 11, characterized in that, the upper electrode layer formed in step 8) fills the capacitor holes without pores and is electrically connected to the capacitor plates.

17. The method for fabricating an integrated circuit capacitor array structure according to claim 11, characterized in that, in step 1), a plurality of capacitor contact nodes are formed in the substrate; in step 4), the formed capacitor holes expose the capacitor contact nodes; the support layer formed in step 2) includes a top support layer, an intermediate support layer and a bottom support layer, and the top support layer, the intermediate support layer and the bottom support layer are all formed on the substrate and are all located in the sacrificial layer, with a spacing therebetween.

18. The method for fabricating an integrated circuit capacitor array structure according to claim 11, characterized in that, step 9) includes the following steps: 9-1) placing the structure obtained in step 8) in a process chamber, and forming the metal filling layer on the top surface of the upper electrode filling body by using a sputtering process; and 9-2) introducing nitrogen gas into the process chamber, and heating the metal filling layer to form the conductive covering layer on the surface of the metal filling layer.

19. The method for fabricating an integrated circuit capacitor array structure according to claim 18, characterized in that, in step 9-2), the flow rate of introducing the nitrogen gas into the process chamber is 10 standard milliliters per minute to 20 standard milliliters per minute.

20. The method for fabricating an integrated circuit capacitor array structure according to claim 11, characterized in that, a connection pad is further formed in the substrate provided in step 1), the connection pad is located outside the covering area of the capacitor plate, and the following steps are further included after step 9): 10) forming a dielectric layer on the surface of the structure obtained in step 9), the dielectric layer covering the upper surface, the side surface of the capacitor plate and the surface of the substrate; 11) forming a first connection through hole and a second connection through hole in the dielectric layer, wherein the first connection through hole is located on the capacitor plate and exposes a part of the conductive covering layer of the capacitor plate, the second connection through hole exposes a part of the connection pad, and the second connection through hole is longer than the first connection through hole; and 12) forming a first interconnecting structure in the first connection through hole and forming a second interconnecting structure in the second connection through hole, the first interconnecting structure being in contact with the capacitor plate, and the second interconnecting structure being in contact with the connection pad.

21. The method for fabricating an integrated circuit capacitor array structure according to any one of claims 11 to 20, characterized in that, in step 8), a titanium nitride layer is deposited on the surface of the capacitor dielectric layer by using an atomic layer deposition process as the upper electrode layer, and the metal filling layer includes a tungsten layer, and the conductive covering layer includes a tungsten nitride layer.

22. A method for manufacturing a semiconductor memory, characterized in that, the method for manufacturing the semiconductor memory includes a step of manufacturing an integrated circuit capacitor array structure by using the method for manufacturing the integrated circuit capacitor array structure as described in claim 11.

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