Reducing Gate-Induced Drain Leakage in DRAM Wordlines

Abstract

A memory device and a method of forming the memory device are described. The memory device includes two work function metal layers, where one work function layer has a lower work function than the other work function layer. The low work function layer can reduce gate-induced drain leakage current loss. A method of forming the memory device is also described.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of electronic devices and electronic device manufacturing. More specifically, embodiments of the present disclosure provide dynamic random access memory cells with buried word lines having reduced gate-induced drain leakage. Background Art

[0002] Electronic devices such as personal computers, workstations, computer servers, mainframes, and other computer-related devices such as printers, scanners, and hard disk drives use memory devices that provide strong data storage capabilities while incurring low power consumption. There are two main types of random access memory cells, namely, dynamic and static, which are well-suited for use in electronic devices. Dynamic random access memory (DRAM) can be programmed to store a voltage representing one of two binary values, but needs to be reprogrammed or "refreshed" periodically to maintain this voltage for more than a very short period of time. Static random access memory (SRAM) is so named because they do not require periodic refreshing.

[0003] DRAM memory circuits are fabricated by replicating millions of identical circuit elements, called DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary number) of data. In the most common form of a DRAM cell, the DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.

[0004] The fabrication of DRAM cells includes the fabrication of transistors, capacitors, and three contacts: the three contacts are connected to a bit line, a word line, and a reference voltage, respectively. DRAM fabrication is a highly competitive business. There is a continuous pressure to reduce the size of individual cells and increase the memory cell density to allow more storage capacity to be squeezed onto a single memory chip, especially for densities greater than 256 megabits. Limitations on cell size reduction include having both active and passive word lines pass through the cell, the size of the cell capacitor, and the compatibility of array devices with non-array devices.

[0005] Traditionally, DRAM word lines utilize a high work function material as the gate electrode in order to reduce channel impurities. An important leakage component in DRAM devices is gate-induced drain leakage (GIDL), which is caused by trap-assisted band-to-band tunneling at the surface of the drain of the transistor where the gate overlaps the drain. During fabrication, interface states are generated in the substrate. These surface states increase the generation rate of electron-hole pairs, thereby enhancing GIDL. The high work function material used in DRAM word lines can increase gate-induced drain leakage near the source / drain regions due to band-to-band tunneling. Accordingly, a DRAM cell is needed that can maintain a low resistance while also maintaining a low gate-induced drain leakage. Summary of the Invention

[0006] Embodiments of the present disclosure relate to memory devices and methods of forming memory devices. In one or more embodiments, a memory device includes: a substrate having a substrate surface with a plurality of trenches extending to a certain depth into the substrate, each trench including a bottom and sidewalls; a gate oxide layer on the bottom and sidewalls of the trenches; a recessed metal layer on the gate oxide layer, the recessed metal layer including a first work function metal layer and a bulk metal layer, the recessed metal layer having a top surface within the depth of the trenches; and a second work function metal layer on the recessed metal layer.

[0007] In one or more embodiments, a method of forming a memory device includes: providing a substrate having a plurality of trenches thereon; depositing a conformal gate oxide layer on the substrate; forming a metal layer on the gate oxide layer; recessing the metal layer to form a recessed metal layer; and depositing a second work function metal layer on the recessed metal layer.

[0008] In one or more embodiments, a memory cell includes: a recessed access device; and a word line electrically coupled to the recessed access device, the word line including a substrate having a substrate surface with a plurality of trenches extending to a certain depth into the substrate, each trench including a bottom and sidewalls; a gate oxide layer on the bottom and sidewalls of the trenches; a recessed metal layer on the gate oxide layer, the recessed metal layer including a first work function metal layer and a bulk metal layer, the recessed metal layer having a top surface within the depth of the trenches; and a second work function metal layer on the recessed metal layer. Brief Description of the Drawings

[0009] In order to understand the above-described features of the present disclosure in a detailed manner, a more specific description of the present disclosure briefly outlined above can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of the present disclosure and thus are not considered as limiting the scope of the present disclosure, as the present disclosure may allow other equivalent embodiments. The embodiments described herein are illustrated in the figures of the accompanying drawings by way of example and not limitation, where like reference numerals indicate similar elements.

[0010] FIG. 1 shows a circuit diagram of a DRAM cell block according to the prior art;

[0011] Figure 2 FIG. shows a cross-sectional view of a device according to one or more embodiments of the present disclosure;

[0012] Figure 3 FIG. shows a cross-sectional view of a device according to one or more embodiments of the present disclosure;

[0013] Figure 4 FIG. shows a cross-sectional view of a device according to one or more embodiments of the present disclosure;

[0014] Figure 5 FIG. shows a cross-sectional view of a device according to one or more embodiments of the present disclosure;

[0015] Figure 6 FIG. shows a cross-sectional view of a device according to one or more embodiments of the present disclosure;

[0016] Figure 7 FIG. shows a cross-sectional view of a device according to one or more embodiments of the present disclosure;

[0017] Figure 8 FIG. shows a cross-sectional view of a device according to one or more embodiments of the present disclosure; and

[0018] Figure 9 FIG. shows a cross-sectional view of a device according to one or more embodiments of the present disclosure. Detailed Description

[0019] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0020] As used in this specification and the appended claims, the terms "precursor", "reactant", "reactive gas" and the like are used interchangeably to refer to any gaseous substance capable of reacting with the surface of a substrate.

[0021] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores a data bit by storing a packet of charge (or a packet of no charge when at zero) on a capacitor; the charge is gated onto the capacitor via an access transistor and sensed by turning on the same transistor and viewing the voltage perturbation created on an interconnect line by piling up the packet of charge on the transistor output. Thus, a single DRAM cell consists of one transistor and one capacitor. As shown in FIG. 1, a DRAM device is formed by an array of DRAM cells. The rows of access transistors are connected by word lines 52a, 52b, and the transistor inputs / outputs are connected by bit lines 54a, 54b, 54c. Historically, DRAM capacitors have evolved from planar polysilicon oxide substrate capacitors to 3D structures, which are divided into "stacked" capacitors (where both plates are above the substrate) and "trench" capacitors that use an etched cavity in the substrate as a common plate.

[0022] Traditionally, DRAM cells have a recessed high work function metal structure in a buried word line structure. In a DRAM device, bit lines are formed in a metal level located above the substrate, while word lines are formed at a polysilicon gate level at the surface of the substrate. In a buried word line (bWL), the word line is buried below the surface of the semiconductor substrate using metal as the gate electrode.

[0023] In one or more embodiments, a memory device, such as a DRAM cell, is provided that utilizes a low work function material on top of a high work function material. Such a memory device advantageously maintains a low resistance while also maintaining low gate-induced drain leakage (GIDL). The buried word line cell array transistor has a word line that is buried below the surface of the semiconductor substrate using metal as the gate electrode in the structure.

[0024] The example embodiments are described with reference to cross-sectional views that are schematic illustrations of example embodiments (and intermediate structures). Accordingly, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected. Thus, the example embodiments should not be construed as limited to the specific shapes of regions shown herein, but may include, for example, deviations in shapes due to manufacturing. For example, an implantation region shown as rectangular may typically have rounded or curved features and / or an implantation concentration gradient at the edges of the implantation region rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may cause some implantation in the region between the buried region and the surface through which the implantation passes. Accordingly, the regions shown in the figures are schematic in nature, and the shapes of these regions are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the example embodiments.

[0025] Figures 2 to 9 is a cross-sectional view showing a memory device 100 according to one or more embodiments. Referring to Figure 2 , a substrate 102 having a plurality of trenches 104 is formed, and these trenches form recessed channels. The trenches have bottoms 106 and sidewalls 108. The plurality of trenches 104 may be formed to have a width in the range of about 10 to about 100 nm, including but not limited to in the range of about 10 nm to about 80 nm, in the range of about 10 nm to about 70 nm, in the range of about 10 nm to about 60 nm, in the range of about 10 nm to about 50 nm, or in the range of about 10 nm to about 40 nm. As will be appreciated by those skilled in the art, the width of the plurality of trenches 104 is defined by the distance W1 from one sidewall 108 to the other sidewall 108. As will be appreciated by those skilled in the art, the depth of the plurality of trenches 104 is defined by the distance D1 from the substrate surface 103 to the bottoms 106 of the plurality of trenches 104.

[0026] As used herein, "substrate" refers to any substrate or the surface of a material formed on a substrate, on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material (such as metals, metal nitrides, metal alloys, and other conductive materials), depending on the application. Substrates include, but are not limited to, semiconductor wafers. The substrate can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps can also be performed on a lower layer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include such a lower layer as indicated by the context. Thus, for example, when a film / layer or a portion of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0027] To form the plurality of trenches 104, a buffer insulating layer (e.g., a silicon oxide layer, not shown) can be formed on the substrate surface 103, and / or a hard mask layer (e.g., a nitride layer, not shown) can be formed. Such techniques are well known to those skilled in the art and are therefore not shown.

[0028] Reference Figure 3 , the gate oxide layer 110 is deposited conformally on the substrate 102, on the substrate surface 103, and along the sidewalls 108 and bottom 106 of the plurality of trenches 104. In one or more embodiments, the gate oxide layer 110 includes one or more of silicon oxynitride (SiON), silicon oxide, or a high-k dielectric material. Although the term "silicon oxide" may be used to describe the gate oxide layer 110, those skilled in the art will recognize that the present disclosure is not limited to a specific stoichiometry. For example, both the terms "silicon oxide" and "silicon dioxide" can be used to describe materials having any suitable stoichiometric ratio of silicon and oxygen atoms. The same is true for the other materials listed in the present disclosure, such as silicon nitride, silicon oxynitride, tungsten oxide, zirconium oxide, aluminum oxide, hafnium oxide, and the like.

[0029] In one or more embodiments, the term "high-k dielectric" refers to a material having a high dielectric constant (compared to, for example, silicon dioxide). In one or more embodiments, the high-k dielectric material is selected from one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), vanadium oxide (VO2), titanium oxide (TiO2), tin oxide (SnO2), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium silicate (HfSiO), or zirconium silicate (ZrSiO).

[0030] In one or more embodiments, the gate oxide layer 110 has a thickness in the range of about 1 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.

[0031] Reference Figure 4 and Figure 5 , a metal layer 113 is formed on the gate oxide layer 110. In one or more embodiments, the metal layer 113 is formed by depositing a conformal first work function metal layer 112 (see Figure 4 ) on the conformal gate oxide layer 110, and then depositing a bulk metal layer 114 (see Figure 5 ) on the first work function metal layer 112. The bulk metal layer 114 is deposited using any of several methods known to those skilled in the art, including but not limited to chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0032] As used herein, "atomic layer deposition" or "cyclic deposition" refers to sequentially exposing two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate, or portions of the substrate, are separately exposed to two or more reactive compounds introduced into the reaction zone of a processing chamber. In a time-domain ALD process, the exposure to each reactive compound is separated by a time delay to allow each compound to adhere to and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are considered to be sequentially exposed to the substrate. In a spatial ALD process, different portions of the substrate surface or the material on the substrate surface are simultaneously exposed to two or more reactive compounds such that at any given point on the substrate, it is not substantially simultaneously exposed to more than one reactive compound. As used in this specification and the appended claims, the term "substantially" in this regard, as will be understood by those skilled in the art, means that there is a small possibility that a small portion of the substrate may be simultaneously exposed to multiple reactive gases due to diffusion, and the simultaneous exposure is not intentional.

[0033] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A, such as an aluminum precursor) is pulsed into the reaction zone, followed by a first time delay. Then, a second precursor or compound B (such as an oxidizer) is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas (such as argon) is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compounds or reaction by-products from the reaction zone. Alternatively, the purge gas can flow continuously throughout the deposition process such that only the purge gas flows during the time delays between pulses of the reactive compounds. The reactive compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either case, an ALD process that pulses compound A, the purge gas, compound B, and the purge gas is one cycle. The cycle can start with compound A or compound B and continue in the corresponding order of the cycle until a film of a predetermined thickness is obtained.

[0034] In an embodiment of a spatial ALD process, a first reactive gas and a second reactive gas (such as nitrogen) are simultaneously delivered to the reaction zone, but are separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas delivery device such that any given point on the substrate is exposed to the first reactive gas and the second reactive gas.

[0035] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is simultaneously or substantially simultaneously exposed to a precursor and / or a co-reactant. As used herein, "substantially simultaneously" refers to co-flow or a situation in which most of the exposure of the precursors overlaps.

[0036] Due to cost effectiveness and film property versatility, plasma-enhanced chemical vapor deposition (PECVD) is widely used for depositing thin films. In a PECVD process, for example, a hydrocarbon source (such as a vapor of a gaseous hydrocarbon or a liquid hydrocarbon) entrained in a carrier gas is introduced into a PECVD chamber. A gas that initiates a plasma (typically helium) is also introduced into the chamber. Then a plasma is initiated in the chamber to generate excited CH radicals. The excited CH radicals chemically bond to the surface of a substrate positioned within the chamber, thereby forming a desired film on the surface. Any suitable thin film deposition system can be used to implement the embodiments described herein with reference to the PECVD process. Any device description herein is illustrative and should not be construed or interpreted as limiting the scope of the embodiments described herein.

[0037] As used herein, the term "work function" refers to the bulk chemical potential of a material (e.g., a metal) relative to the vacuum level. In one or more embodiments, the first work function metal layer has a work function greater than or equal to 4.3 eV. In some embodiments, the first work function metal layer has a work function greater than or equal to 4.5 eV. In other embodiments, the first work function metal layer has a work function greater than or equal to 4.3 eV, including greater than or equal to 4.4 eV, greater than or equal to 4.5 eV, greater than or equal to 4.6 eV, greater than or equal to 4.7 eV, greater than or equal to 4.8 eV, greater than or equal to 4.9 eV, greater than or equal to 5.0 eV, greater than or equal to 5.1 eV, or greater than or equal to 5.2 eV.

[0038] In one or more embodiments, the first work function metal layer comprises a metal nitride. In another embodiment, the first work function metal layer comprises one or more of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN / TiN, or WN / TiN. In another embodiment, the first work function metal layer is selected from the group consisting of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN / TiN, WN / TiN, and combinations of the foregoing. In one or more embodiments, the first work function metal layer comprises titanium nitride. In one or more embodiments, the first work function metal layer may also be referred to as a high / medium work function metal layer.

[0039] In one or more embodiments, the first work function metal layer 112 has a thickness in the range of about 1 nm to about 5 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, or about 5 nm.

[0040] In one or more embodiments, the bulk metal layer 114 is also referred to as a word line. Referring Figure 6 , the bulk metal layer 114 (i.e., the word line) is buried (recessed) by chemical mechanical polishing (CMP) and etch back such that the bulk metal layer 114 and the first work function metal layer 112 do not protrude beyond the substrate surface 103 (e.g., such that the bulk metal layer 114 is completely buried within the substrate 102).

[0041] In one or more embodiments, the buried word line 115 (i.e., the recessed bulk metal layer 115) can be formed by forming a word line layer 114 (i.e., the bulk metal layer 114) on the substrate 102 to bury the trench 104. The word line layer 114 can then be polished using a chemical mechanical polishing (CMP) method and etched back using a dry etching process to expose the substrate surface 103. The buried word line 115 can be formed by recessing the polished word line layer 114 into the substrate 102 using a partial etching process. As Figure 6 shown, the first work function metal layer 112 is recessed to the same level as the buried word line 115. The top surface 117 of the buried word line 115 and the first work function metal layer 112 is the recessed depth or distance D2 from the substrate surface 103 in the plurality of trenches 104. In one or more embodiments, the buried word line 115 has a top surface 117 within the depth D1 of the trench 104. Thus, in one or more embodiments, D2 is less than D1.

[0042] In one or more embodiments, the bulk metal layer 114 (i.e., the word line) includes one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the bulk metal layer 114 includes tungsten (W). In other embodiments, the bulk metal layer 114 includes ruthenium (Ru). In one or more embodiments, the buried word line 115 (i.e., the recessed bulk metal layer 115) includes one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the buried word line 115 includes tungsten (W). In other embodiments, the buried word line 115 includes ruthenium (Ru).

[0043] Referring to Figure 7 , in one or more embodiments, the second work function metal layer 116 is deposited on the substrate 102 that is on the recessed bulk metal layer 115 (i.e., on the buried word line). Referring to Figure 8 , the second work function metal layer 116 is then polished using a chemical mechanical polishing (CMP) method and etched back to expose the substrate surface 103. The top surface 118 of the second work function metal layer 116 is the distance D3 from the substrate surface 103 in the plurality of trenches 104. In one or more embodiments, the second work function metal layer 116 has a top surface 118 within the depth D1 of the trench 104. Thus, in one or more embodiments, D3 is less than D1.

[0044] In one or more embodiments, the second work function metal layer 116 has a work function less than that of the first work function layer. In one or more embodiments, the second work function metal layer 116 has a work function less than about 4.3 eV. In some embodiments, the second work function metal layer 116 has a work function less than or equal to about 4.2 eV. In some embodiments, the work function of the second work function metal layer 116 is less than or equal to about 4.25 eV, less than or equal to about 4.2 eV, less than or equal to about 4.15 eV, less than or equal to about 4.1 eV, less than or equal to about 4.05 eV, less than or equal to about 4 eV, less than or equal to about 3.5 eV, or less than or equal to about 3.0 eV.

[0045] In one or more embodiments, the second work function metal layer 116 may also be referred to as a low work function layer. Resistivity is a property of a material that quantifies how strongly the material resists the flow of electric current. A low resistivity indicates that the material readily permits the flow of electric current. A high resistivity material does not readily permit the flow of electric current. As used herein, the term "high resistivity material" refers to a material or substance having a resistivity greater than about 500 μΩ·cm. In one or more embodiments, the second work function metal layer 116 has a resistivity less than about 500 μΩ·cm, including less than about 400 μΩ·cm, less than about 300 μΩ·cm, less than about 200 μΩ·cm, or less than about 100 μΩ·cm. In one or more specific embodiments, the second work function metal layer 116 is substantially free of polysilicon and / or doped polysilicon. As used herein, the term "substantially free of" means that there is less than 5% polysilicon and / or doped polysilicon present in the second work function metal layer 116, including less than 4%, less than 3%, less than 2%, less than 1%, and less than 0.5%. As used herein, the term "polysilicon" or "polycrystalline Si" refers to the polycrystalline form of silicon.

[0046] In one or more embodiments, the second work function metal layer 116 includes a metal carbide or metal silicide having one or more metals selected from aluminum (Al), gallium (Ga), indium (In), or thallium (Tl). As used herein, the term "metal carbide" refers to a composite material composed of carbon and a generally less electronegative metal. As used herein, the term "metal silicide" refers to a composite material composed of silicon and a generally more electropositive metal. As will be appreciated by those skilled in the art, metal silicides, as composite materials, are different from polysilicon and doped polysilicon.

[0047] In other embodiments, the second work function metal layer 116 includes a metal carbide or metal silicide having one or more metals selected from gallium (Ga), indium (In), or thallium (Tl). In one or more embodiments, the second work function metal layer 116 includes aluminum carbide or aluminum silicide. In one or more embodiments, the second work function metal layer 116 includes gallium carbide or gallium silicide. In one or more embodiments, the second work function metal layer 116 includes indium carbide or indium silicide. In one or more embodiments, the second work function metal layer 116 includes thallium carbide or thallium silicide. In one or more embodiments, the second work function metal layer 116 includes one or more metals selected from aluminum (Al), gallium (Ga), indium (In), or thallium (Tl). In other embodiments, the second work function metal layer 116 includes one or more metals selected from gallium (Ga), indium (In), or thallium (Tl). In one or more embodiments, the second work function metal layer 116 includes aluminum. In one or more embodiments, the second work function metal layer 116 includes gallium. In one or more embodiments, the second work function metal layer 116 includes indium. In one or more embodiments, the second work function metal layer 116 includes thallium.

[0048] In one or more embodiments, the second work function metal layer 116 has a thickness T1 in the range of about 10 nm to about 50 nm, including about 10 nm, about 15 nm, about 20 nm, about 25 nm, about 30 nm, about 35 nm, about 40 nm, about 45 nm, or about 50 nm.

[0049] Reference Figure 9 , an insulating layer 120 is deposited on the second work function metal layer 116. In one or more embodiments, the insulating layer has a top surface 122 that is generally coplanar with the substrate surface 103.

[0050] In one or more embodiments, the insulating layer 120 includes a dielectric material. As used herein, the term "dielectric" refers to an electrically insulating material that can be polarized by an applied electric field. In one or more embodiments, the dielectric material includes, but is not limited to, oxides (e.g., SiO2, Al2O3), nitrides (e.g., Si3N4). In one or more embodiments, the dielectric material includes silicon nitride (Si3N4). In some embodiments, the insulating layer composition is non-stoichiometric relative to the ideal chemical formula. For example, in some embodiments, the dielectric material includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), carbon oxides (e.g., silicon oxycarbide (SiOC)), and carbon oxynitrides (e.g., silicon carbon oxynitride (SiNCO)).

[0051] One or more embodiments are directed to memory cells. In one or more embodiments, a memory cell includes: a recessed access device; and a word line electrically coupled to the recessed access device, the word line including a substrate having a substrate surface with a plurality of trenches extending to a depth into the substrate, each trench including a bottom and sidewalls; a gate oxide layer on the bottom and the sidewalls of the trenches; a recessed metal layer on the gate oxide layer, the recessed metal layer including a first work function metal layer and a bulk metal layer, the recessed metal layer having a top surface within the depth of the trenches; and a second work function metal layer on the recessed metal layer.

[0052] Spatial relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It should be understood that these spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "beneath" or "below" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relative descriptors used herein interpreted accordingly.

[0053] In the context of describing the materials and methods discussed herein (especially in the context of the appended claims), the terms "a," "an," "the," and similar referents should be construed to cover both the singular and the plural unless otherwise indicated herein or clearly contradicted by context. Stating ranges of values herein is merely a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein is merely intended to better illuminate the materials and methods and does not pose a limitation on the scope unless otherwise indicated. No language in this specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0054] References throughout this specification to "one embodiment", "certain embodiments", "one or more embodiments" or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases such as "in one or more embodiments", "in certain embodiments", "in one embodiment" or "in an embodiment" throughout this specification are not necessarily referring to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0055] Although the present disclosure has been described with reference to particular embodiments, it should be understood that these embodiments are illustrative only of the principles and applications of the present disclosure. Those skilled in the art will appreciate that various modifications and changes can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and variations that fall within the scope of the appended claims and equivalents of the claims.

Claims

1. A memory device, comprising: A substrate having a substrate surface with a plurality of trenches extending to a certain depth into the substrate, each trench including a bottom and sidewalls; A gate oxide layer on the bottom and the sidewalls of the trenches; A recessed metal layer on the gate oxide layer, the recessed metal layer including a first work function metal layer and a bulk metal layer, the recessed metal layer having a top surface within the depth of the trenches, the top surface of the first work function metal layer and the top surface of the bulk metal layer being at the same depth from the substrate surface; And A second work function metal layer on the first work function metal layer and the bulk metal layer, wherein the second work function metal layer is substantially free of polysilicon and / or doped polysilicon, and the second work function metal layer has a work function of less than 4.3 eV.

2. The memory device according to claim 1, wherein the first work function metal layer is formed on the gate oxide layer on the sidewalls and the bottom of the plurality of trenches, and the bulk metal layer is formed on the first work function metal layer.

3. The memory device according to claim 1, wherein the first work function metal layer comprises a metal nitride.

4. The memory device according to claim 1, wherein the first work function metal layer comprises one or more of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN / TiN, or WN / TiN.

5. The memory device according to claim 1, wherein the bulk metal layer comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh).

6. The memory device according to claim 1, wherein the first work function metal layer comprises a material having a work function greater than or equal to 4.3 eV.

7. The memory device according to claim 6, wherein the second work function metal layer comprises a metal carbide or a metal silicide having one or more metals selected from aluminum (Al), gallium (Ga), indium (In), or thallium (Tl).

8. The memory device according to claim 1, wherein the second work function metal layer has a top surface within the depth of the plurality of trenches.

9. The memory device according to claim 8, further comprising an insulating layer in the plurality of trenches on the second work function metal layer, the insulating layer having a top surface substantially coplanar with the substrate surface.

10. A method of forming a memory device, the method comprising: Providing a substrate having a plurality of trenches thereon; Depositing a conformal gate oxide layer on the substrate; Forming a metal layer on the conformal gate oxide layer, the forming including depositing a conformal first work function metal layer on the conformal gate oxide layer and depositing a bulk metal layer on the conformal first work function metal layer; The metal layer is recessed to form a recessed metal layer, wherein the conformal first work function metal layer and the bulk metal layer are recessed to the same depth from the substrate surface; and A second work function metal layer is deposited on the conformal first work function metal layer and the bulk metal layer, wherein the second work function metal layer is substantially free of polysilicon and / or doped polysilicon, and the second work function metal layer has a work function less than 4.3 eV.

11. The method of claim 10, wherein recessing the metal layer moves the top surface of the conformal first work function metal layer and the top surface of the bulk metal layer to the depth of the recess in the plurality of trenches.

12. The method of claim 10, wherein the second work function metal layer has a thickness in the range of 10 nm to 50 nm.

13. The method of claim 10, wherein the gate oxide layer comprises one or more of silicon oxynitride (SiON), silicon oxide (SiO), or a high-k dielectric material.

14. The method of claim 10, wherein the conformal first work function metal layer comprises a material having a work function greater than or equal to 4.3 eV.

15. The method of claim 14, wherein the second work function metal layer comprises a metal carbide or a metal silicide having one or more metals selected from aluminum (Al), gallium (Ga), indium (In), or thallium (Tl).

16. The method of claim 10, further comprising etching the second work function metal layer.

17. The method of claim 16, further comprising depositing an insulating layer on the second work function metal layer.

18. A memory cell, comprising: A recessed access device; and A word line electrically coupled to the recessed access device, the word line comprising a substrate having a substrate surface with a plurality of trenches extending to a certain depth into the substrate, each trench comprising a bottom and sidewalls; A gate oxide layer on the bottom and the sidewalls of the trenches; A recessed metal layer on the gate oxide layer, the recessed metal layer comprising a first work function metal layer and a bulk metal layer, the recessed metal layer having a top surface within the depth of the trenches, the top surface of the first work function metal layer and the top surface of the bulk metal layer being at the same depth from the substrate surface; And a second work function metal layer on the first work function metal layer and the bulk metal layer, wherein the second work function metal layer is substantially free of polysilicon and / or doped polysilicon, and the second work function metal layer has a work function less than 4.3 eV.

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