Semiconductor memory device and method of operating the same

Abstract

A semiconductor memory device includes: a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computing circuit configured to: receive internal data from a first memory bank group among the plurality of memory bank groups during each of a plurality of first cycles, receive external data through the internal memory bus during each of a plurality of second cycles, the second cycle being shorter than the first cycle, and perform process-in-memory (PIM) arithmetic operations on the internal data and the external data during each of the second cycles.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0153725 filed on December 3, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present application relates to a semiconductor memory device employing process-in-memory (PIM) and a method of operating the semiconductor memory device. Background Art

[0004] A semiconductor memory device according to the related art has a function completely separated from a processor that performs arithmetic operations. Therefore, in a system that implements applications such as neural networks, big data, and the Internet of Things (IoT) that must process a large amount of data, a large amount of data is sent and received between the semiconductor memory device and the processor, and thus a bottleneck frequently occurs. In order to solve this problem, as a semiconductor memory device that combines the function of a processor for performing arithmetic operations with a memory function, research on a processing-in-memory (PIM) device is being conducted. Summary of the invention

[0005] This summary is provided to introduce a selection of concepts in a simplified form that are further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0006] In one general aspect, a semiconductor memory device includes: a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computing circuit configured to: receive internal data from a first memory bank group among the plurality of memory bank groups during each of a plurality of first cycles, receive the external data through the internal memory bus during each of a plurality of second cycles, the second cycle being shorter than the first cycle, and perform process-in-memory (PIM) arithmetic operations on the internal data and the external data during each second cycle.

[0007] The first cycle may correspond to a delay time required to continuously access the same memory bank group among the plurality of memory bank groups, and the second cycle may correspond to a delay time required to continuously access a different memory bank group among the plurality of memory bank groups.

[0008] The first period may be n times the second period, where n is a natural number greater than or equal to 2.

[0009] The computation circuit may also be configured to reuse the internal data n times when performing the PIM arithmetic operation on the internal data and the external data.

[0010] The semiconductor memory device may also include multiple memory channels, the multiple memory channels may include a first memory channel, the first memory channel includes a first memory body group, and the external data may be any one of the following or any combination of any two or more of the following: data stored in any one of the multiple memory channels except the first memory channel, data stored in another semiconductor memory device external to the semiconductor memory device, and data processed by a host processor external to the semiconductor memory device.

[0011] The first calculation circuit may include n buffers, each buffer configured to store a result of a PIM arithmetic operation performed on the internal data and the external data, wherein n is a quotient obtained by dividing the first cycle by the second cycle.

[0012] The first calculation circuit may be further configured to: continuously store results of the PIM arithmetic operations performed on the internal data and the external data in the n buffers.

[0013] The first calculation circuit may further include a demultiplexer connected to the n buffers, and a selector configured to output a control signal for controlling the demultiplexer to select one of the n buffers for storing a result of the PIM arithmetic operation performed on the internal data and the external data.

[0014] The selector may include a counter configured to count the second period and output a count value of the counter as the control signal.

[0015] The semiconductor memory device may further include a second computing circuit connected to a second memory bank group among the plurality of memory bank groups, wherein the first computing circuit and the second computing circuit may be configured to operate in parallel with each other.

[0016] In another general aspect, in a semiconductor memory device including multiple memory bank groups configured to be accessed in parallel and an internal memory bus configured to receive external data from outside the multiple memory bank groups, and a computing circuit, a method of operating the computing circuit in the semiconductor memory device includes: receiving internal data from a first memory bank group among the multiple memory bank groups during each of a plurality of first cycles; receiving external data through the internal memory bus during each of a plurality of second cycles, the second cycle being shorter than the first cycle; and performing process-in-memory (PIM) arithmetic operations on the internal data and the external data during each second cycle.

[0017] The first cycle may correspond to a delay time required to continuously access the same memory bank group among the plurality of memory bank groups, and the second cycle may correspond to a delay time required to continuously access a different memory bank group among the plurality of memory bank groups.

[0018] The first period may be n times the second period, where n is a natural number greater than or equal to 2.

[0019] Performing the PIM arithmetic operation on the internal data and the external data may include reusing the internal data n times when performing the PIM arithmetic operation on the internal data and the external data.

[0020] The semiconductor memory device may also include multiple memory channels, the multiple memory channels include a first memory channel, the first memory channel includes a first memory body group, and the external data may be any one of the following or any combination of any two or more of the following: data stored in any one of the multiple memory channels except the first memory channel including the first memory body group, data stored in another semiconductor memory device external to the semiconductor memory device, and data processed by a host processor external to the semiconductor memory device.

[0021] The calculation circuit may include n buffers, where n is a quotient obtained by dividing the first cycle by the second cycle, and the method may further include: continuously storing results of the PIM arithmetic operation performed on the internal data and the external data in the n buffers.

[0022] The computing circuit may further include a demultiplexer connected to n buffers, and continuously storing the results of the PIM arithmetic operations performed on the internal data and the external data includes: outputting a control signal for controlling the demultiplexer to select one of the n buffers for storing the results of the PIM arithmetic operations performed on the internal data and the external data.

[0023] In another general aspect, a semiconductor memory device includes: a plurality of memory banks configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory banks; and a computing circuit configured to: receive internal data from a first memory bank among the plurality of memory banks during each of a plurality of first cycles, receive external data through the internal memory bus during each of a plurality of second cycles, the second cycles being shorter than the first cycles, and perform process-in-memory (PIM) arithmetic operations on the internal data and the external data during each of the second cycles.

[0024] The semiconductor memory device may also include multiple memory channels, the multiple memory channels include a first memory channel, the first memory channel includes a first memory body, and the external data may be any one of the following or any combination of any two or more of the following: data stored in any one of the multiple memory channels except the first memory channel including the first memory body, data stored in another semiconductor memory device outside the semiconductor memory device, and data processed by a host processor outside the semiconductor memory device.

[0025] The semiconductor memory device may further include a second computing circuit connected to a second memory bank among the plurality of memory banks, wherein the computing circuit and the second computing circuit may be configured to operate in parallel with each other.

[0026] In another general aspect, a semiconductor memory device includes: a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a computing circuit configured to: receive first internal data from a first memory bank group among the plurality of memory bank groups, receive first external data through the internal memory bus, perform a process-in-memory (PIM) arithmetic operation on the first internal data and the first external data, receive second external data through the internal memory bus, and perform a PIM arithmetic operation on the first internal data and the second external data.

[0027] The waiting time between the time when the computing circuit receives the first external data and the time when the computing circuit receives the second external data can be equal to the delay time required for continuously accessing different storage groups in the multiple storage groups, and the delay time required for continuously accessing different storage groups in the multiple storage groups is less than the delay time required for continuously accessing the same storage group in the multiple storage groups.

[0028] The computing circuit may include: a first operand buffer configured to receive internal data from a first memory bank group during each first cycle of a plurality of first cycles, the first cycle being equal to a delay time required for continuously accessing the same memory bank group of the plurality of memory bank groups; a second operand buffer configured to receive external data through an internal memory bus during each second cycle of a plurality of second cycles, the second cycle being equal to a delay time required for continuously accessing different memory bank groups of the plurality of memory bank groups, and the second cycle being shorter than the first cycle; and an arithmetic logic unit (ALU) configured to receive internal data from the first operand buffer, receive external data from the second operand buffer, and perform PIM arithmetic operations on the internal data and the external data.

[0029] The first operand buffer may include an input connected to the first memory bank group and configured to receive internal data, and an output configured to output the internal data, the second operand buffer may include an input connected to the internal memory bus and configured to receive external data, and an output configured to output the external data, the ALU may include a first input connected to the output of the first operand buffer and configured to receive internal data, a second input connected to the output of the second operand buffer and configured to receive external data, and an output configured to output a result of the PIM operation performed on the internal data and the external data; and the computing circuit may further include: a demultiplexer including an input connected to the ALU; A first input configured to receive a result of a PIM operation performed on internal data and external data, a second input configured to receive a control signal, a first output, and a second output, the demultiplexer being configured to alternately connect the first input of the demultiplexer to the first output of the demultiplexer and the second output of the demultiplexer in response to the control signal; a first buffer including an input connected to the first output of the demultiplexer; a second buffer including an input connected to the second output of the demultiplexer; and a selector including an output connected to the second input of the demultiplexer, the selector being configured to count a second cycle, generate a control signal based on a count value of the second cycle, and output the control signal through an output of the selector.

[0030] The computing circuit may also be configured to receive second internal data from the first memory bank group, receive third external data via the internal memory bus, perform PIM arithmetic operations on the second internal data and the third external data, receive fourth external data via the internal memory bus, and perform PIM arithmetic operations on the second internal data and the fourth external data.

[0031] The waiting time between the time when the computing circuit receives the first internal data and the time when the computing circuit receives the second internal data can be equal to the first delay time required for continuously accessing the same storage body group among multiple storage body groups, and the waiting time between the time when the computing circuit receives the first external data and the time when the computing circuit receives the second external data, the waiting time between the time when the computing circuit receives the second external data and the time when the computing circuit receives the third external data, and the waiting time between the time when the computing circuit receives the third external data and the time when the computing circuit receives the fourth external data can be equal to the second delay time required for continuously accessing different storage body groups among multiple storage body groups, and the second delay time is shorter than the first delay time.

[0032] The semiconductor memory device may further include: a first buffer; and a second buffer, wherein the calculation circuit may further be configured to: store a result of the PIM arithmetic operation performed on the first internal data and the first external data in the first buffer, store a result of the PIM arithmetic operation performed on the first internal data and the second external data in the second buffer, add the result of the PIM arithmetic operation performed on the second internal data and the third external data to the result of the PIM arithmetic operation performed on the first internal data and the first external data stored in the first buffer to obtain a first summation result, store the first summation result in the first buffer, add the result of the PIM arithmetic operation performed on the second internal data and the fourth external data to the result of the PIM arithmetic operation performed on the first internal data and the second external data stored in the second buffer to obtain a second summation result, and store the second summation result in the second buffer.

[0033] Other features and aspects will become apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a block diagram of an example of a semiconductor memory device.

[0035] Figure 2 : is a diagram for explaining an example of the first cycle and the second cycle.

[0036] Figure 3 and Figure 4 is a diagram for comparing a method of operating a semiconductor memory device according to the disclosure of the present application with a method of operating a semiconductor memory device according to the related art.

[0037] Figure 5 is a diagram for explaining an example of external data.

[0038] Figure 6 is a block diagram of an example of a computing circuit.

[0039] Figure 7 is a diagram for explaining an example of a process in which a semiconductor memory device performs a matrix multiplication operation.

[0040] Figure 8 is a diagram showing simulation results comparing the performance of a method of operating a semiconductor memory device according to the disclosure of the present application with the performance of a method of operating a semiconductor memory device according to the related art.

[0041] Fig. 9 is a block diagram of an example of a semiconductor memory device.

[0042] Fig.10is a flow chart illustrating an example method of operating a computing circuit included in a semiconductor memory device.

[0043] Fig.11 is a block diagram of an example of an electronic system including a semiconductor memory device.

[0044] Fig.12 yes Figure 1 , Figure 3 , Figure 5 , Figure 6 and Fig. 9 A block diagram of an example of a computing circuit.

[0045] Throughout the drawings and detailed description, the same reference numerals refer to the same elements. The drawings may not be drawn to scale, and the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated for purposes of clarity, illustration, and convenience. DETAILED DESCRIPTION

[0046] The following detailed description is provided to help the reader obtain a comprehensive understanding of the methods, devices and / or systems described herein. However, after understanding the disclosure of the present application, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be obvious. For example, the order of operations described herein is only an example and is not limited to those orders set forth herein, but can be changed, and such changes will be obvious after understanding the disclosure of the present application, but this does not include operations that need to appear in a specific order. In addition, for greater clarity and conciseness, the description of features known in the prior art may be omitted.

[0047] The features described herein can be embodied in different forms and should not be considered to be limited to the examples described herein. Instead, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein, which will be apparent after understanding the disclosure of the present application.

[0048] Throughout the specification, when an element such as a layer, a region, or a substrate is described as being "on another element," "connected to," or "coupled to" another element, it may be directly "on another element," "connected to," or "coupled to" another element, or one or more other elements may be present between them. Conversely, when an element is described as being "directly on another element," "directly connected to," or "directly coupled to" another element, there may be no other elements present between them.

[0049] Although terms such as "first," "second," and "third" may be used herein to describe various components, assemblies, regions, layers, or portions, these components, assemblies, regions, layers, or portions are not limited by these terms. Instead, these terms are used only to distinguish one component, component, region, layer, or portion from another component, component, region, layer, or portion. Therefore, what is referred to as a first component, component, region, layer, or portion in the examples described herein may also be referred to as a second component, component, region, layer, or portion without departing from the teachings of the examples.

[0050] The terms used herein are only used to describe each example and are not used to limit the present disclosure. Unless the context clearly indicates otherwise, the articles "a", "an", and "the" are intended to include plural forms at the same time. The terms "include", "comprise", and "have" specify the presence of the described features, numbers, operations, components, elements, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements, and / or combinations thereof.

[0051] Unless otherwise defined, all terms used herein, including technical terms and scientific terms, have the same meanings as those commonly understood by ordinary technicians in the field to which the disclosure of the present application belongs based on an understanding of the disclosure of the present application. Terms such as those defined in general dictionaries are interpreted as having a meaning consistent with their meaning in the context of the relevant field and the disclosure of the present application, rather than being interpreted in an idealized or overly formal sense, except as clearly defined herein.

[0052] The features of the examples described herein can be combined in various ways, which will be apparent after understanding the disclosure of the present application. Moreover, although the examples described herein have various configurations, other configurations are also possible, which will be apparent after understanding the disclosure of the present application.

[0053] Figure 1 is a block diagram of an example of a semiconductor memory device.

[0054] refer to Figure 1 , the semiconductor memory device 10 includes a first memory bank group 110, a second memory bank group 115, an internal memory bus 120, a first calculation circuit 130, and a second calculation circuit 135. Figure 1 The semiconductor memory device 10 of FIG. 1 shows components related to this example. Therefore, the semiconductor memory device 10 may also include Figure 11. For example, the semiconductor memory device 10 may further include a memory controller (not shown). The memory controller may perform operations for controlling the overall operation of the semiconductor memory device 10. The memory controller may be implemented by a logic gate array, or may be implemented by a combination of a microprocessor and a memory storing a program executed by the microprocessor for performing operations of the memory controller.

[0055] exist Figure 1 In FIG. 1 , it is shown that the semiconductor memory device 10 includes only one memory channel. However, the semiconductor memory device 10 may also include additional memory channels. Figure 1 Only two memory bank groups and two computing circuits are shown in FIG. 1 , but the semiconductor memory device 10 may include a greater number of memory bank groups and computing circuits.

[0056] Each of the first memory bank group 110 and the second memory bank group 115 is a storage area that can be accessed in parallel. The first memory bank group 110 and the second memory bank group 115 share an internal memory bus 120, and therefore in a general memory read or write operation, only one of the first memory bank group 110 and the second memory bank group 115 can use the internal memory bus 120. Since each of the first memory bank group 110 and the second memory bank group 115 can be accessed independently, a separate read operation can be performed on the first memory bank group 110 and the second memory bank group 115 at the same time. For example, when reading data from the first memory bank group 110, data can also be read from the second memory bank group 115. In this case, the semiconductor memory device 10 can be described as having memory bank group unit parallelism. Each of the first memory bank group 110 and the second memory bank group 115 includes a plurality of memory banks. Each of the plurality of memory banks is the minimum unit of a memory area that can be accessed in parallel.

[0057] The internal memory bus 120 is a data transmission path formed between components included in the semiconductor memory device 10 so that data can be sent and received between the components. For example, the internal memory bus 120 is shared between the first memory bank group 110 and the second memory bank group 115. In addition, the internal memory bus 120 forms a connection path between the components included in the semiconductor memory device 10 and the components outside the semiconductor memory device 10. For example, the internal memory bus 120 receives external data from outside the plurality of memory bank groups included in the semiconductor memory device 10. The internal memory bus 120 supplies external data to one of the first computing circuit 130 and the second computing circuit 135 or to both. The meaning of the outside of the plurality of memory bank groups will be referred to Figure 5 Described in more detail below.

[0058] The first computing circuit 130 is hardware that performs arithmetic operations within the semiconductor memory device 10. For example, the first computing circuit 130 may include an arithmetic logic unit (ALU), and the arithmetic operation may be operations such as addition, subtraction, integration, and accumulation, but is not limited thereto. The first computing circuit 130 may be implemented by a logic gate array, or by a combination of a logic gate array and a buffer for temporarily storing data. Since the semiconductor memory device 10 includes the first computing circuit 130 for performing arithmetic operations in the semiconductor memory device 10, the semiconductor memory device 10 corresponds to a processing-in-memory (PIM) architecture.

[0059] The first computing circuit 130 is hardware with processing functions similar to a host processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), or a digital signal processor (DSP) outside the semiconductor memory device 10), and may be a processor packaged together with a plurality of memory bank groups in a chip of a memory package of the semiconductor memory device 10. The first computing circuit 130 may be referred to as an internal processor because the first computing circuit 130 is inside the semiconductor memory device 10, and the host processor may be referred to as an external processor because the host processor is outside the semiconductor memory device 10. In the PIM architecture, the internal processor and the memory are implemented on a single chip, achieving fast memory access with low latency. In addition, when the PIM architecture uses parallelism in units of memory banks or in units of memory bank groups, the PIM architecture may have a memory bandwidth several to tens of times greater than that of an architecture using general memory access. The semiconductor memory device 10 having the PIM architecture may also be referred to as an intelligent random access memory (RAM), a computing RAM, or an intelligent memory.

[0060] The first calculation circuit 130 connected to the first memory bank group 110 operates in parallel with the second calculation circuit 135 connected to the second memory bank group 115. The first calculation circuit 130 and the second calculation circuit 135 perform arithmetic operations independently of each other. For example, while the first calculation circuit 130 performs arithmetic operations using data received from the first memory bank group 110, the second calculation circuit 135 performs arithmetic operations using data received from the second memory bank group 115.

[0061] The first calculation circuit 130 receives internal data from the first memory bank group 110 during each of the plurality of first cycles. The internal data is data stored in the first memory bank group 110 and corresponds to data stored in at least some of the plurality of memory addresses assigned to the first memory bank group 110. In addition, the first calculation circuit 130 receives external data through the internal memory bus 120 during each of the plurality of second cycles, the second cycle being shorter than the first cycle. The external data is data stored outside the plurality of memory bank groups or processed outside the plurality of memory bank groups, and will be referred to Figure 5 The meaning of the external data is described in more detail below. The first calculation circuit 130 performs arithmetic operations on the internal data and the external data during each second cycle. Figure 2 The first and second cycles are described in detail and reference will be made to Figure 3 and Figure 4 The effects obtained by the operation of the first calculation circuit 130 described above will be described in more detail.

[0062] Figure 2 : is a diagram for explaining an example of the first cycle and the second cycle.

[0063] Figure 2 A timing diagram showing the timing of performing a read operation on a memory bank group according to a clock signal CLK. When a command "column command (Column CMD)" for performing a read operation on the memory bank group is sent to the memory bank group, the delay time tCCD_L required for continuously accessing the same memory bank group is greater than the delay time tCCD_S required for continuously accessing different memory bank groups. Figure 1 The first cycle described corresponds to the delay time tCCD_L required for consecutive accesses to the same memory bank group, while the reference Figure 1 The second cycle described corresponds to the delay time tCCD_S required for consecutive accesses to different memory bank groups. tCCD represents the column-to-column delay, L represents "long", and S represents "short".

[0064] The PIM architecture can be implemented using double data rate (DDR) DRAM or DDR SDRAM. The PIM architecture based on the latest DDR DRAM or DDR SDRAM usually uses parallelism in units of memory banks or uses parallelism in units of memory bank groups. For example, the PIM architecture based on DDR4 uses parallelism in units of memory bank groups and has the following problems: the delay time is always tCCD_L because the PIM architecture always needs to access the same memory bank group continuously. Since data is read from multiple memory bank groups at the same time, the amount of data read at one time increases, but the rate at which data is read is always limited to tCCD_L. Therefore, the overall arithmetic operation speed of the PIM architecture based on DDR4 is limited.

[0065] According to the disclosure of the present application, the overall arithmetic operation speed of the PIM architecture based on DDR4 is improved by supplying external data to the first calculation circuit 130 with a period tCCD_S during a waiting period tCCD_L after reading data from a memory bank group until data can be read again from the same memory bank group. The waiting period tCCD_L is greater than the delay time tCCD_S for reading data during general memory use.

[0066] Figure 3 and Figure 4 is a diagram for comparing a method of operating a semiconductor memory device according to the disclosure of the present application with a method of operating a semiconductor memory device according to the related art.

[0067] Figure 3 A conceptual diagram 310 illustrating a method of operating a semiconductor memory device according to the related art and a conceptual diagram 320 illustrating a method of operating a semiconductor memory device according to the disclosure of the present application are shown. Figure 3 In the figure, "bank / bank group" refers to a bank or a bank group, and "bus" refers to an internal memory bus.

[0068] Referring to the conceptual diagram 310 showing a method of operating a semiconductor memory device according to the related art, internal data is read from a memory bank group during each first cycle, and thus the internal data is supplied to the computing circuit during each first cycle. In addition, external data is supplied to the computing circuit through an internal memory bus during each first cycle. Since the computing circuit performs arithmetic operations using internal data and external data, arithmetic operations are performed during each first cycle. Therefore, in the method of operating a semiconductor memory device according to the related art, the arithmetic operation speed of the computing circuit is limited to the first cycle.

[0069] Referring to the conceptual diagram 320 showing a method of operating a semiconductor device according to the disclosure of the present application, internal data is read from a memory bank group during each first cycle (similar to the conceptual diagram 310), and thus the internal data is supplied to the computing circuit during each first cycle. However, unlike the conceptual diagram 310, in the semiconductor memory device according to the disclosure of the present application, external data is supplied to the computing circuit through the internal memory bus during each second cycle, and thus the computing circuit performs arithmetic operations on the internal data and the external data during each second cycle. Since the second cycle is shorter than the first cycle, in the method of operating a semiconductor memory device according to the disclosure of the present application, the arithmetic operation speed of the computing circuit is improved.

[0070] exist Figure 3 In the example described in , the first period is n times the second period (where n is a natural number greater than or equal to 2). However, n does not necessarily need to be a natural number greater than or equal to 2. That is, n can have any value as long as n is greater than or equal to 2. For example, n can be any real number greater than or equal to 2. Figure 3 Table 330 in FIG. 3 shows data supplied from a memory bank group and data supplied from outside the memory bank group according to time when the first cycle and the second cycle in a semiconductor memory device according to the disclosure of the present application are 4 ns and 2 ns respectively and n is 2. Figure 5 The meaning of "external to a bank group" and "external data" is described in more detail.

[0071] Figure 5 is a diagram for explaining an example of external data.

[0072] refer to Figure 5 , shows the configuration of a semiconductor memory device. The semiconductor memory device includes a plurality of memory channels. In this example, in addition to the first memory channel 510 including the first memory bank group 110, the internal memory bus 120, and the first computing circuit 130, the semiconductor memory device also includes a second memory channel 520. The memory channel 520 has the same structure as the memory channel 510. Although in Figure 5 Only two memory channels are shown in FIG. 1 , but the semiconductor memory device may include additional memory channels.

[0073] For the first memory bank group 110, the external data is data stored in the memory channel 520 other than the memory channel 510 including the first memory bank group 110. In this example, "outside the first memory bank group 110" refers to the memory channel 520. However, this is only an example, and "outside the first memory bank group 110" may refer to any data source as long as the data source is outside the memory channel 510. For example, the external data may be Figure 5 data stored in another semiconductor memory device external to the semiconductor memory device shown in the figure, or by Figure 5 The host processor may include (but is not limited to) a CPU, a GPU, or a DSP.

[0074] Return to reference Figure 3 According to the table 330 in FIG. 3 , the calculation circuit receives internal data W0 from the memory bank group at 0 ns and receives external data A0 from the outside of the memory bank group through the internal memory bus at 0 ns. The calculation circuit performs an arithmetic operation on the internal data W0 and the external data A0.

[0075] The calculation circuit receives new external data B0 from the outside of the memory bank group through the internal memory bus at 2ns, and new internal data cannot be supplied from the memory bank group at this time. Therefore, the calculation circuit performs arithmetic operations on the existing internal data W0 and the new external data B0 at 2ns. In this way, even if new internal data cannot be supplied from the memory bank group, the calculation circuit can perform additional arithmetic operations on the existing internal data and the new external data supplied from the outside of the memory bank group. When performing arithmetic operations on internal data and external data, the internal data is reused n times, so the overall arithmetic operation speed of the semiconductor memory device is increased by about n times.

[0076] Figure 4 A timing diagram 410 illustrating a method of operating a semiconductor memory device according to the related art and a timing diagram 420 illustrating a method of operating a semiconductor memory device according to the disclosure of the present application are shown.

[0077] Each row in the timing diagram 410 and the timing diagram 420 represents the operation of the memory bank group according to time, R (read) represents reading of internal data from the memory bank group, and C (compute) represents execution of an arithmetic operation by a computing circuit.

[0078] Referring to the timing diagram 410 illustrating the method of operating a semiconductor memory device according to the related art, after the computing circuit performs an arithmetic operation when simultaneously reading internal data from all memory bank groups at 0 ns, the computing circuit can perform a new arithmetic operation only when reading new internal data from all memory bank groups at 4 ns. Therefore, in the method of operating a semiconductor memory device according to the related art, the arithmetic operation of the computing circuit depends on the speed of reading internal data from the memory bank groups, and thus the arithmetic operation speed of the computing circuit is limited to 4 ns.

[0079] Referring to the timing diagram 420 of the method for operating a semiconductor memory device according to the disclosure of the present application, after the computing circuit performs an arithmetic operation when reading internal data from all memory bank groups simultaneously at 0 ns, the computing circuit performs a new arithmetic operation when new external data is supplied from the outside of the computing circuit at 2 ns. Therefore, in the method for operating a semiconductor memory device according to the disclosure of the present application, the arithmetic operation speed of the computing circuit is increased to a cycle of 2 ns. As the arithmetic operation speed of the computing circuit is increased, the overall arithmetic operation speed of the semiconductor memory device is increased. Figure 6 Let's describe the calculation circuit in more detail.

[0080] Figure 6 is a block diagram of an example of a computing circuit.

[0081] refer to Figure 6 The computing circuit includes a first operand buffer 610 for storing internal data supplied from a memory bank group during each first cycle, and a second operand buffer 615 for storing external data supplied from an internal memory bus during each second cycle. The computing circuit also includes an ALU 620 for performing arithmetic operations on the internal data stored in the first operand buffer 610 and the external data stored in the second operand buffer 615. The ALU 620 may be, but is not limited to, a multiplier, an adder, or an integrator. The ALU 620 may be implemented in any suitable manner based on the type of arithmetic operations to be performed in the PIM architecture.

[0082] The calculation circuit includes a plurality of buffers for storing results of arithmetic operations performed on internal data and external data. The number of buffers is equal to the quotient obtained by dividing the first cycle by the second cycle. For example, when the first cycle is n times the second cycle, the calculation circuit includes n buffers. Figure 3 and Figure 4 The examples described assume that n is 2, so Figure 6 A calculation circuit including two buffers, a first buffer 630 and a second buffer 635, is shown. The number of buffers included in the calculation circuit may vary as the relationship between the first cycle and the second cycle varies.

[0083] The first buffer 630 and the second buffer 635 included in the calculation circuit alternately store the results of arithmetic operations on the internal data and the external data performed by the ALU 620. Figure 3330, the first buffer 630 stores the result of the arithmetic operation performed on the internal data W0 and the external data A0 at 0 ns, and the second buffer 635 stores the result of the arithmetic operation performed on the internal data W0 and the external data B0 at 2 ns. Subsequently, the first buffer 630 stores the result of the arithmetic operation performed on the internal data W1 and the external data A1 at 4 ns, and the second buffer 635 stores the result of the arithmetic operation performed on the internal data W1 and the external data B1 at 6 ns.

[0084] The calculation circuit further includes a selector 640, a demultiplexer (DEMUX) 645, and a multiplexer (MUX) 650 to select a buffer for storing the result of the arithmetic operation from the n buffers. The selector 640 outputs a control signal for selecting the first buffer 630 or the second buffer 635 to store the result of the arithmetic operation performed on the internal data stored in the first operand buffer 610 and the external data stored in the second operand buffer 615.

[0085] The demultiplexer 645 is a combinational circuit that outputs data received through one input to one of a plurality of output lines. The multiplexer 650 is a combinational circuit that selects one of a plurality of input lines and connects the selected input line to a single output line. The demultiplexer 645 and the multiplexer 650 determine which of the first buffer 630 and the second buffer 635 is to be connected to the ALU 620 based on a control signal output by the selector 640.

[0086] The selector 640 includes a counter that counts each second cycle, and the control signal output by the selector 640 is an output signal of the counter. For example, the selector 640 includes a counter that changes the count value after each second cycle. The count value that changes after each second cycle is output from the counter to the control input of the demultiplexer 645 and the multiplexer 650, and thus the buffer connected to the ALU 620 changes between the first buffer 630 and the second buffer 635 after each second cycle.

[0087] Figure 7 is a diagram for explaining an example of a process in which a semiconductor memory device performs a matrix multiplication operation.

[0088] refer to Figure 7 , showing the semiconductor memory device execution matrix and matrix The matrix multiplication operation between An example of the process. Figure 7 The example corresponds to the case where the first period is 4 ns, the second period is 2 ns, and n is 2.

[0089] At 0 ns, the memory bank group supplies the matrix to the computing circuit. The internal data B0 of the (1, 1) component, and the matrix data B0 supplied from the outside of the memory bank group to the calculation circuit The calculation circuit is configured as a multiplier to perform a matrix multiplication operation and to perform a multiplication operation on A0 and B0. A0*B0 as a result of the multiplication operation is stored in the first buffer.

[0090] At 2ns, the matrix is ​​supplied from the outside of the memory bank to the calculation circuit. The calculation circuit performs a multiplication operation on the new external data A2 and the existing internal data B0. A2*B0 as a result of the multiplication operation is stored in the second buffer.

[0091] At 4 ns, the memory bank group supplies the matrix to the computing circuit. The new internal data B2 of the (2, 1) component is supplied from the outside of the memory bank group to the calculation circuit as a matrix The computing circuit performs a multiplication operation on the new external data A1 and the new internal data B2. A1*B2 as the result of the multiplication operation is accumulated and stored in the first buffer. An accumulator can be added to either or both of the front end and the back end of each buffer in the computing circuit to accumulate the results of the multiplication operation. After A1*B2 is accumulated in the first buffer, the first buffer stores the value of A0*B0+A1*B2. The value of A0*B0+A1*B2 is obtained by executing the matrix and matrix The matrix obtained by matrix multiplication operation between The (1, 1) component C0 of .

[0092] At 6 ns, the matrix is ​​supplied from the outside of the memory bank to the calculation circuit. The calculation circuit performs a multiplication operation on the new external data A3 and the existing internal data B2. A3*B2 as the result of the multiplication operation is accumulated and stored in the second buffer. After A3*B2 is accumulated in the second buffer, the second buffer stores the value A2*B0+A3*B2. The value A2*B0+A3*B2 is obtained by performing the matrix and matrix The matrix obtained by matrix multiplication operation between The (2, 1) component of C2.

[0093] The semiconductor memory device repeats the above process to complete the matrix by replacing the internal data B0 and B2 with the new internal data B1 and B3. and matrix The matrix multiplication operation between them is performed to obtain The (1, 2) component and the (2, 2) component of C1 and C3.

[0094] Since external data is supplied from the outside of the memory bank group during the second cycle which is shorter than the first cycle during which data is read from the memory bank group, the semiconductor memory device according to the disclosure of the present application performs matrix processing faster than the semiconductor memory device according to the related art. and matrix Matrix multiplication operation between .

[0095] The arithmetic operation performed by the semiconductor memory device is not limited to matrix multiplication. Instead, the semiconductor memory device may perform various other arithmetic operations, and components included in the semiconductor memory device may be controlled in various ways by various PIM arithmetic operation instructions.

[0096] Figure 8 is a diagram showing simulation results for comparing the performance of a method of operating a semiconductor memory device according to the disclosure of the present application with the performance of a method of operating a semiconductor memory device according to the related art.

[0097] refer to Figure 8 , shows the calculation time in clock cycles required for performing 204,800 multiplication operations of 32-bit floating point data in the semiconductor memory device according to the disclosure of the present application and the semiconductor memory device according to the related art. The calculation time is obtained using a memory simulator Ramulator known in the art.

[0098] refer to Figure 8 In the graph 810, the computing time required for the semiconductor memory device according to the related art to perform 204,800 multiplication operations of 32-bit floating point data is about 730 clock cycles. Figure 8 As shown in FIG. 820 , the computing time required for the semiconductor memory device according to the disclosure of the present application to perform 204,800 multiplication operations of 32-bit floating point data is approximately 390 clock cycles.

[0099] Therefore, in the method of operating a semiconductor memory device according to the disclosure of the present application, far fewer cycles are required to perform the same number of multiplication operations compared to the method of operating a semiconductor memory device according to the related art, and therefore the arithmetic operation speed of the semiconductor memory device according to the disclosure of the present application is faster than the arithmetic operation speed of the semiconductor memory device according to the related art.

[0100] Fig. 9 is a block diagram of another example of the semiconductor memory device 90 .

[0101] refer to Fig. 9 , which is different from using parallelism in memory bank groups. Figure 1 The semiconductor memory device 90 uses parallelism in units of memory banks. The semiconductor memory device 90 has the same basic structure as the semiconductor memory device 10, except that a computing circuit is allocated to each memory bank in a memory bank group in the semiconductor memory device 90 instead of being allocated to each memory bank group in the semiconductor memory device 10.

[0102] The semiconductor memory device 90 includes a first memory bank 910, a second memory bank 915, an internal memory bus 920, a first calculation circuit 930, and a second calculation circuit 935. The first memory bank 910 is connected to the first calculation circuit 930, and the second memory bank 915 is connected to the second calculation circuit 935. The first calculation circuit 930 and the second calculation circuit 935 perform arithmetic operations independently of each other. For example, when the first calculation circuit 930 performs arithmetic operations by using data received from the first memory bank 910, the second calculation circuit 935 also performs arithmetic operations by using data received from the second memory bank 915. The first calculation circuit 930 and the second calculation circuit 935 perform arithmetic operations independently of each other. Figure 1 The first calculation circuit 130 described above operates in substantially the same manner, and therefore a detailed description of the first calculation circuit 930 and the second calculation circuit 935 is omitted.

[0103] Fig.10 is a flowchart illustrating an example of a method of operating a computing circuit included in a semiconductor memory device.

[0104] refer to Fig.10 , a method of operating a computing circuit included in a semiconductor memory device comprises Figure 1 , Figure 3 , Figure 5 , Figure 6 and Fig. 9 The operations performed sequentially in the calculation circuit shown in FIG. Figure 1 , Figure 3 , Figure 5 , Figure 6 and Fig. 9 The description of the computational circuit in also applies to the operation Fig.10 A method for a computing circuit included in a semiconductor memory device shown in FIG.

[0105] In operation 1010, the computing circuit receives internal data from the first memory bank group during each first cycle of a plurality of first cycles. Figure 2 For the reason discussed, the cycle in which internal data can be read from the same memory bank group is limited to the first cycle.

[0106] In operation 1020, the computing circuit receives external data from outside the first memory bank group through the internal memory bus during each second cycle in a plurality of second cycles, the second cycle being shorter than the first cycle. The semiconductor memory device includes a plurality of memory channels, and the plurality of memory channels include a first memory channel, the first memory channel including the first memory bank group. The external data is any one of the following or any combination of any two or more of the following: data stored in a memory channel other than the first memory channel including the first memory bank group among the plurality of memory channels, data stored in another semiconductor memory device outside the semiconductor memory device, and data processed by a host processor outside the semiconductor memory device. The host processor may include, but is not limited to, a CPU, a GPU, or a DSP.

[0107] The first cycle corresponds to the delay time tCCD_L required for continuous access to the same memory bank group, and the second cycle corresponds to the delay time tCCD_S required for continuous access to different memory bank groups. For example, the first cycle may be n times the second cycle, where n is a natural number greater than or equal to 2. However, n does not necessarily need to be a natural number greater than or equal to 2. That is, n can have any value as long as n is greater than or equal to 2.

[0108] In operation 1030, the computing circuit performs a PIM arithmetic operation on the internal data and the external data during each second cycle. The PIM arithmetic operation is an arithmetic operation performed by a computing circuit having a processing function in a semiconductor memory device. The external data is supplied to the computing circuit during the second cycle during the waiting period tCCD_L after reading the data from the memory bank group until the data can be read again from the same memory bank group. The waiting period tCCD_L is greater than the delay time tCCD_S for reading the data during the general memory use. Therefore, the computing circuit performs arithmetic operations during the second cycle. When performing arithmetic operations on the internal data and the external data, the computing circuit reuses the internal data n times. Since the second cycle is shorter than the first cycle, in the method of operating a semiconductor memory device according to the disclosure of the present application, the arithmetic operation speed of the computing circuit is improved.

[0109] The calculation circuit continuously stores the results of arithmetic operations performed on the internal data and the external data in n buffers, where n is a quotient obtained by dividing the first cycle by the second cycle. For example, the calculation circuit can select one buffer connected to the calculation circuit from the n buffers by outputting a control signal for controlling the demultiplexer to select one buffer among the n buffers to store the results of arithmetic operations performed on the internal data and the external data.

[0110] Fig.11 is a block diagram of an example of an electronic system including a semiconductor memory device.

[0111] refer to Fig.11 , the electronic system 1100 extracts effective information by analyzing input data in real time using a neural network, and determines a situation or controls a component of an electronic device in which the electronic system 1100 is installed. For example, the electronic system 1100 may be applied to a robot device such as a drone or an advanced driver assistance system (ADAS), a smart TV, a smart phone, a medical device, a mobile device, an image display device, a measuring device, or an IoT device. In addition, the electronic system 1100 may be various other types of electronic devices. For example, the electronic system 1100 may be a server.

[0112] The electronic device 1100 includes a processor 1110, a semiconductor memory device 1120, a neural network device 1130, a system memory 1140, a sensor module 1150, and a communication module 1160. The electronic system 1100 may also include other elements such as an input / output module, a security module, and a power control device. At least some of the hardware components of the electronic system 1100 may be mounted on at least one semiconductor chip.

[0113] The processor 1110 controls the overall operation of the electronic device 1100. The processor 1110 may be a single-core processor or a multi-core processor. The processor 1110 processes and executes the program stored in the system memory 1140. The processor 1110 controls the operation of the neural network device 1130 by executing the program stored in the system memory 1140. The processor 1110 may be implemented using a CPU, a GPU, or an application processor (AP).

[0114] The semiconductor memory 1120 temporarily stores programs, data, and instructions. For example, the programs, data, and instructions stored in the system memory 1140 are temporarily stored in the semiconductor memory device 1120 according to the control or boot code of the processor 1110. The semiconductor memory device 1120 can be implemented with a memory such as DRAM. The semiconductor memory device 1120 and the reference Figures 1 to 10Since the semiconductor memory device 1120 has a PIM architecture, the semiconductor memory device 1120 not only performs a memory function for storing data, but also performs a processor function for performing arithmetic operations. Therefore, arithmetic operations are not over-allocated to the processor 1110, and the overall performance of the electronic system 1100 is improved.

[0115] The neural network device 1130 performs arithmetic operations of the neural network based on the received input data, and generates an information signal based on the result of the arithmetic operations. The neural network may be a convolutional neural network (CNN), a recurrent neural network (RNN), a feedforward neural network (FNN), a deep belief network (DBN), a restricted Boltzmann machine (RBM), etc., but is not limited thereto.

[0116] The information signal may be one of various types of recognition signals, for example, a voice recognition signal, an object recognition signal, an image recognition signal, or a biometric information recognition signal. For example, the neural network device 1130 may receive frame data included in a video stream as input data, and generate a recognition signal for an object included in an image represented by the frame data based on the frame data. However, the neural network device 1130 is not limited to this example. Instead, the neural network device 1130 may receive various types of input data depending on the type or function of the electronic device in which the electronic system 1100 is installed, and generate a recognition signal based on the input data.

[0117] The system memory 1140 is a storage location configured to store data, and can store an operating system (OS), various programs, and various data. In one example, the system memory 1140 stores intermediate results generated in arithmetic operations of the neural network device 1130 .

[0118] The system memory 1140 may include any one or both of a volatile memory and a non-volatile memory. The non-volatile memory may be a ROM, a PROM, an EPROM, a flash memory, a PRAM, an MRAM, an RRAM, a FRAM, or any other non-volatile memory. The volatile memory may be a DRAM, an SRAM, an SDRAM, a PRAM, an MRAM, an RRAM, a ferroelectric RAM (FeRAM), or any other volatile memory. In one example, the system memory 1140 may include any one of the following or any combination of any two or more of the following: an HDD card, an SSD card, a CF card, an SD card, a micro SD card, a mini SD card, an xD card, and a memory stick.

[0119] The sensor module 1150 collects information related to the electronic device in which the electronic system 1100 is installed. The sensor module 1150 senses or receives a signal (e.g., a video signal, a voice signal, a magnetic signal, a biometric signal, or a touch signal) from the outside of the electronic device, and converts the sensed or received signal into data. Therefore, the sensor module 1150 may include any one of the following or any combination of any two or more of the following among various types of sensor devices, for example, a microphone, an image acquisition device, an image sensor, a light detection and ranging (LIDAR) sensor, an ultrasonic sensor, an infrared sensor, a biosensor, and a touch sensor.

[0120] The sensor module 1150 provides the converted data as input data to the neural network device 1130. In one example, the sensor module 1150 includes an image sensor, generates a video stream by photographing the external environment of the electronic device, and sequentially provides continuous data frames of the video stream to the neural network device 1130 as input data, however, this is only an example, and the sensor module 1150 can provide various other types of data to the neural network device 1130.

[0121] The communication module 1160 includes various wired or wireless interfaces that can communicate with external devices. For example, the communication module 1160 may include an interface that can be connected to a local area network (LAN), a wireless local area network (WLAN) (e.g., Wi-Fi), a wireless personal area network (WPAN) (e.g., Bluetooth or ZigBee), a wireless universal serial bus (USB), a near field communication (NFC), a radio frequency identification (RFID), a power line communication (PLC), or a mobile cellular network (e.g., a third generation (3G), a fourth generation (4G), or a long term evolution (LTE)).

[0122] Fig.12 yes Figure 1 , Figure 3 , Figure 5 , Figure 6 , Fig. 9 and Fig.11 A block diagram of an example of a computing circuit.

[0123] refer to Fig.12 , the memory 1210 stores instructions, which, when executed by the processor 1220, cause the processor 1220 to execute Figure 1 , Figure 3 , Figure 5 , Figure 6 and Fig. 9 The function of the computing circuit.

[0124] Perform the operations described in this application Figure 1 , Figure 3 , Figure 5, Figure 6 and Fig. 9 The computing circuit is implemented by a hardware component configured to perform the operation performed by the hardware component described in the present application. Examples of hardware components that can be used to perform the operation described in the present application include controllers, sensors, generators, drivers, memories, buffers, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, multiplexers, demultiplexers, transistors, and other electronic components configured to perform the operation described in the present application, where appropriate. In other examples, one or more hardware components performing the operation described in the present application are implemented by computing hardware (for example, by one or more processors or computers). A processor or computer can be implemented by one or more processing elements (for example, logic gate arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field programmable gate arrays, programmable logic arrays, microprocessors, or any other devices or combinations of devices configured to respond to instructions in a defined manner and execute instructions to obtain desired results). In one example, a processor or computer includes or is connected to one or more memories storing instructions or software executed by a processor or computer. The hardware components implemented by a processor or a computer can execute instructions or software (for example, an operating system (OS) and one or more software applications running on the OS) to perform the operations described in the present application. The hardware components can also access, manipulate, process, create and store data in response to the execution of instructions or software. For simplicity, the terms "processor" or "computer" in the singular form can be used in the description of the examples described in the present application, but multiple processors or computers can be used in other examples, or the processor or computer can include multiple processing elements or multiple types of processing elements or both. For example, a single hardware component or two or more hardware components can be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components can be implemented by one or more processors, or a processor and a controller, and one or more other hardware components can be implemented by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller can implement a single hardware component, or two or more hardware components. The hardware components may have any one or more of different processing configurations, examples of which include a single processor, independent multiple processors, parallel multiple processors, single instruction single data (SISD) multiprocessing, single instruction multiple data (SIMD) multiprocessing, multiple instruction single data (MISD) multiprocessing, and multiple instruction multiple data (MIMD) multiprocessing.

[0125] Combination Figures 1 to 9 Described in the application to perform the operations described Fig.10The method of the present invention is performed by hardware components or by computing hardware (e.g., by one or more processors or computers implemented as described above to execute instructions or software to perform the operations described in the present application performed by the method). For example, a single operation or two or more operations may be performed by a single processor, or two or more processors, or a processor and a controller. One or more operations may be performed by one or more processors, or a processor and a controller, and one or more other operations may be performed by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller may perform a single operation, or two or more operations.

[0126] The instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above can be written as a computer program, code segment, instruction, or any combination thereof that individually or collectively instructs or configures one or more processors or computers to operate as a machine or special-purpose computer to perform the operations and methods performed by the hardware components as described above. In one example, the instructions or software include machine code (e.g., machine code generated by a compiler) that is directly executed by one or more processors or computers. In another example, the instructions or software include high-level code that is executed by one or more processors or computers using an interpreter. Any programming language can be used to write instructions or software based on the block diagrams and flow charts shown in the accompanying drawings and the corresponding descriptions in the specification that disclose the operations performed by the hardware components and the methods described above.

[0127] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform methods as described above, as well as any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), flash memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state disk, and any other device configured to store instructions or software and any associated data, data files, and data structures in a non-transitory manner and provide instructions or software and any associated data, data files, and data structures to one or more processors or computers so that one or more processors or computers can execute instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed among a network-coupled computer system so that one or more processors or computers store, access, and execute the instructions and software and any associated data, data files, and data structures in a distributed manner.

[0128] Although the present disclosure includes specific examples, after understanding the disclosure of the present application, various changes in form and detail can be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be considered only in a descriptive sense rather than for restrictive purposes. The description of the features or aspects in each example is deemed to be applicable to similar features or aspects in other examples. If the described techniques are performed in different orders, and / or if the components in the described systems, architectures, devices or circuits are combined in different ways, and / or the components in the described systems, architectures, devices or circuits are replaced or supplemented by other components or their equivalent components, appropriate results can be obtained. Therefore, the scope of the present disclosure is not defined by specific embodiments, but by claims and their equivalents, and all changes within the scope of claims and their equivalents are deemed to be included in the present disclosure.

Claims

1. A semiconductor memory device, comprising: A plurality of memory bank groups are configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; as well as a first computing circuit configured to: receive internal data from a first memory bank group of the plurality of memory bank groups during each of a plurality of first cycles, receive the external data through the internal memory bus during each of a plurality of second cycles, the second cycle being shorter than the first cycle, and perform a process-in-memory (PIM) arithmetic operation on the internal data and the external data during each of the second cycles, The first calculation circuit is configured to perform a first PIM arithmetic operation among the PIM arithmetic operations using one of the internal data before receiving another different internal data used in a subsequent PIM arithmetic operation among the PIM arithmetic operations.

2. The semiconductor memory device according to claim 1, wherein The first period corresponds to a delay time required for continuously accessing the same memory bank group among the plurality of memory bank groups, and The second period corresponds to a delay time required to continuously access different memory bank groups among the plurality of memory bank groups.

3. The semiconductor memory device according to claim 1, wherein: The first period is n times the second period, where n is a natural number greater than or equal to 2.

4. The semiconductor memory device according to claim 3, wherein: The first calculation circuit is further configured to reuse the internal data n times when performing the PIM arithmetic operation on the internal data and the external data.

5. The semiconductor memory device according to claim 1, wherein The semiconductor memory device further includes a plurality of memory channels, The plurality of memory channels include a first memory channel, the first memory channel includes the first memory bank group, and The external data is any one of the following or any combination of any two or more of the following: data stored in any memory channel among the multiple memory channels except the first memory channel, data stored in other semiconductor memory devices outside the semiconductor memory device, and data processed by a host processor outside the semiconductor memory device.

6. The semiconductor memory device according to claim 1, wherein The first calculation circuit includes n buffers, each buffer being configured to store a result of a PIM arithmetic operation performed on the internal data and the external data, wherein n is a quotient obtained by dividing the first cycle by the second cycle.

7. The semiconductor memory device according to claim 6, wherein: The first calculation circuit is further configured to: continuously store results of the PIM arithmetic operations performed on the internal data and the external data in the n buffers.

8. The semiconductor memory device according to claim 6, wherein: The first calculation circuit further includes: demultiplexer, connected to the n buffers, and The selector is configured to output a control signal for controlling the demultiplexer to select one of the n buffers for storing a result of the PIM arithmetic operation performed on the internal data and the external data.

9. The semiconductor memory device according to claim 8, wherein: The selector includes a counter configured to count the second period and output a count value of the counter as the control signal.

10. The semiconductor memory device according to claim 1, further comprising a second calculation circuit connected to a second memory bank group among the plurality of memory bank groups, in, The first computation circuit and the second computation circuit are configured to operate in parallel with each other.

11. A method of operating a computing circuit in a semiconductor memory device, the semiconductor memory device comprising a plurality of memory bank groups configured to be accessed in parallel, an internal memory bus configured to receive external data from outside the plurality of memory bank groups, and a computing circuit, the method comprising: receiving internal data from a first memory bank group of the plurality of memory bank groups during each first cycle of a plurality of first cycles; receiving the external data through the internal memory bus during each second cycle of a plurality of second cycles, the second cycle being shorter than the first cycle; as well as performing a process-in-memory "PIM" arithmetic operation on said internal data and said external data during each second cycle, wherein a first PIM arithmetic operation among the PIM arithmetic operations is performed using one of the internal data before receiving another different internal data used in a subsequent PIM arithmetic operation among the PIM arithmetic operations.

12. The method according to claim 11, wherein: The first cycle corresponds to a delay time required to continuously access the same memory bank group among the plurality of memory bank groups, and the second cycle corresponds to a delay time required to continuously access different memory bank groups among the plurality of memory bank groups.

13. The method according to claim 11, wherein: The first period is n times the second period, where n is a natural number greater than or equal to 2.

14. The method according to claim 13, wherein: Performing a PIM arithmetic operation on the internal data and the external data includes: When the PIM arithmetic operation is performed on the internal data and the external data, the internal data is repeatedly used n times.

15. The method according to claim 11, wherein: The semiconductor memory device further includes a plurality of memory channels, the plurality of memory channels including a first memory channel, the first memory channel including the first memory bank group, and The external data is any one of the following or any combination of any two or more of the following: data stored in any memory channel among the multiple memory channels except the first memory channel including the first memory body group, data stored in other semiconductor memory devices outside the semiconductor memory device, and data processed by a host processor outside the semiconductor memory device.

16. The method according to claim 11, wherein: The calculation circuit includes n buffers, wherein n is a quotient obtained by dividing the first cycle by the second cycle, and The method further includes successively storing results of the PIM arithmetic operations performed on the internal data and the external data in the n buffers.

17. The method according to claim 16, wherein: The computing circuit further includes a demultiplexer connected to the n buffers, and Continuously storing the result of the PIM arithmetic operation performed on the internal data and the external data includes: outputting a control signal for controlling the demultiplexer to select one of the n buffers for storing the result of the PIM arithmetic operation performed on the internal data and the external data.

18. A semiconductor memory device comprising: A plurality of memory banks, configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory banks; as well as a first computing circuit configured to: receive internal data from a first memory bank of the plurality of memory banks during each of a plurality of first cycles, receive the external data through the internal memory bus during each of a plurality of second cycles, the second cycle being shorter than the first cycle, and perform a process-in-memory (PIM) arithmetic operation on the internal data and the external data during each of the second cycles, The first calculation circuit is configured to perform a first PIM arithmetic operation among the PIM arithmetic operations using one of the internal data before receiving another different internal data used in a subsequent PIM arithmetic operation among the PIM arithmetic operations.

19. The semiconductor memory device according to claim 18, wherein: The semiconductor memory device further includes a plurality of memory channels, the plurality of memory channels including a first memory channel, the first memory channel including the first memory bank, and The external data is any one of the following or any combination of any two or more of the following: data stored in any memory channel among the multiple memory channels except the first memory channel including the first memory body, data stored in other semiconductor memory devices outside the semiconductor memory device, and data processed by a host processor outside the semiconductor memory device.

20. The semiconductor memory device according to claim 18, further comprising a second calculation circuit connected to a second memory bank among the plurality of memory banks, in, The first computing circuit and the second computing circuit are configured to operate in parallel with each other.

21. A semiconductor memory device comprising: A plurality of memory bank groups are configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; as well as The computing circuit is configured as follows: receiving first internal data from a first memory bank group among the plurality of memory bank groups; receiving first external data via the internal memory bus and performing a process-in-memory (PIM) arithmetic operation on the first internal data and the first external data, and receiving second external data through the internal memory bus and performing a PIM arithmetic operation on the first internal data and the second external data, The calculation circuit is configured to perform a first PIM arithmetic operation among the PIM arithmetic operations using the first internal data before receiving additional different internal data used in a subsequent PIM arithmetic operation among the PIM arithmetic operations.

22. The semiconductor memory device according to claim 21, wherein The waiting time between the time when the computing circuit receives the first external data and the time when the computing circuit receives the second external data is equal to the delay time required for continuously accessing different storage body groups among the multiple storage body groups, and the delay time required for continuously accessing different storage body groups among the multiple storage body groups is less than the delay time required for continuously accessing the same storage body group among the multiple storage body groups.

23. The semiconductor memory device according to claim 21, wherein The calculation circuit comprises: a first operand buffer configured to receive internal data from the first memory bank group during each first cycle of a plurality of first cycles, the first cycle being equal to a delay time required for consecutively accessing the same memory bank group of the plurality of memory bank groups; a second operand buffer configured to receive external data through the internal memory bus during each second cycle of a plurality of second cycles, the second cycle being equal to a delay time required for consecutively accessing different memory bank groups of the plurality of memory bank groups and being shorter than the first cycle; and An arithmetic logic unit (ALU) is configured to receive internal data from the first operand buffer, receive external data from the second operand buffer, and perform a PIM arithmetic operation on the internal data and the external data.

24. The semiconductor memory device according to claim 23, wherein: The first operand buffer includes an input connected to the first memory bank group and configured to receive internal data, and an output configured to output the internal data, The second operand buffer includes an input connected to the internal memory bus and configured to receive external data, and an output configured to output the external data, The ALU includes a first input connected to an output of the first operand buffer and configured to receive internal data, a second input connected to an output of the second operand buffer and configured to receive external data, and an output configured to output a result of a PIM operation performed on the internal data and the external data; as well as The calculation circuit also includes: a demultiplexer comprising a first input connected to the output of the ALU and configured to receive a result of the PIM operation performed on the internal data and the external data, a second input configured to receive a control signal, a first output, and a second output, the demultiplexer being configured to alternately connect the first input of the demultiplexer to the first output of the demultiplexer and the second output of the demultiplexer in response to the control signal; a first buffer comprising an input connected to a first output of the demultiplexer; a second buffer comprising an input connected to a second output of the demultiplexer; and A selector includes an output connected to the second input of the demultiplexer, the selector being configured to count the second period, generate the control signal based on the count value of the second period, and output the control signal through the output of the selector.

25. The semiconductor memory device according to claim 21, wherein The computing circuit is also configured to receive second internal data from the first memory bank group, receive third external data through the internal memory bus, perform PIM arithmetic operations on the second internal data and the third external data, receive fourth external data through the internal memory bus, and perform PIM arithmetic operations on the second internal data and the fourth external data.

26. The semiconductor memory device according to claim 25, wherein: A waiting time between a time when the computing circuit receives the first internal data and a time when the computing circuit receives the second internal data is equal to a first delay time required for continuously accessing the same memory bank group among the plurality of memory bank groups, and The waiting time between the time when the computing circuit receives the first external data and the time when the computing circuit receives the second external data, the waiting time between the time when the computing circuit receives the second external data and the time when the computing circuit receives the third external data, and the waiting time between the time when the computing circuit receives the third external data and the time when the computing circuit receives the fourth external data is equal to the second delay time required for continuously accessing different storage body groups among the multiple storage body groups, and the second delay time is shorter than the first delay time.

27. The semiconductor memory device according to claim 25, further comprising: First buffer; as well as The second buffer, Wherein, the computing circuit is further configured as: storing in the first buffer a result of the PIM arithmetic operation performed on the first internal data and the first external data, storing in the second buffer a result of the PIM arithmetic operation performed on the first internal data and the second external data, adding a result of the PIM arithmetic operation performed on the second internal data and the third external data to a result of the PIM arithmetic operation performed on the first internal data and the first external data stored in the first buffer to obtain a first summation result, storing the first summation result in the first buffer, adding a result of the PIM arithmetic operation performed on the second internal data and the fourth external data to a result of the PIM arithmetic operation performed on the first internal data and the second external data stored in the second buffer to obtain a second summation result, and The second summation result is stored in the second buffer.

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