Display device

Abstract

The display device includes: a substrate, the substrate including a display area, a peripheral area and a pad area; a first main voltage line in the peripheral area, and a first connector extending from the first main voltage line to the pad area; and a second main voltage line in the peripheral area, and a second connector extending from the second main voltage line to the pad area, wherein each of the first connector and the second connector includes a first layer and a second layer overlapping each other, a first insulating layer is provided between the first layer and the second layer, the first insulating layer is in the display area and the peripheral area, the peripheral area includes an open area, the open area exposes the first connector and the second connector and surrounds the display area, and the first insulating layer includes a gap, the gap is between the first connector and the second connector, and extends from the end of the first insulating layer toward the display area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0153019 filed on November 30, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure herein relates to a display device. Background Art

[0004] With the rapid progress in the field of displays that allow visual display of various electrical signal information, various display devices with improved characteristics, such as slim profile, light weight and low power consumption, are being studied and developed. One type of these displays is an organic light emitting display device, which is a self-emitting display device that does not require an additional power supply, so it can be driven with a low voltage and is formed by a light film. In addition, the organic light emitting display device provides high-quality features, such as wide viewing angle, high contrast and rapid response. Therefore, it has received a lot of attention as a display device of the next generation.

[0005] The organic light emitting display device includes a plurality of pixels. When the organic light emitting display device is operated by an analog driving method, the pixels of the organic light emitting display device express grayscale images by adjusting the brightness according to the size of input voltage or current data. When the organic light emitting display device is operated by a digital driving method, even when the pixels of the organic light emitting display device emit light with the same brightness, they express grayscale images according to different light emitting time periods. In a power supply line that supplies power to the pixels, a voltage drop (or current-resistance (IR) drop) may occur due to a resistance component. This may deteriorate the image quality of the organic light emitting display device. Summary of the invention

[0006] One or more embodiments include a display device configured to display a high-quality image and prevent a short circuit between electric wires.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0008] According to one or more embodiments, a display device includes a substrate, the substrate including a display area, a peripheral area outside the display area, and a pad area in the peripheral area; a first main voltage line, the first main voltage line is arranged in the peripheral area of ​​the substrate and between the edge of the display area and the pad area, and a first connector extends from the first main voltage line to the pad area; and a second main voltage line, the second main voltage line is arranged in the peripheral area of ​​the substrate and corresponds to the other edge of the display area, and a second connector extends from the second main voltage line to the pad area, wherein each of the first connector and the second connector includes a first layer and a second layer overlapping each other with a first insulating layer therebetween, wherein the first insulating layer is arranged in the display area and the peripheral area of ​​the substrate, the peripheral area includes an open area, the open area exposes the first connector and the second connector, and surrounds the display area, and the first insulating layer includes a plurality of gaps, the plurality of gaps are arranged between the first connector and the second connector, and extend from the end of the first insulating layer toward the display area.

[0009] The display device may further include a second insulating layer on the second layer in the open region.

[0010] The second insulating layer may further include a height difference reducer at a boundary of the second insulating layer and the open area between the first connector and the second connector, and a thickness of the height difference reducer may be smaller than a thickness of the second insulating layer.

[0011] Two opposite distal ends of the height difference reducer may overlap the first connector and the second connector, respectively.

[0012] The second insulating layer may include a plurality of concave portion portions in positions respectively overlapping the plurality of slits.

[0013] In the open region, the first connector and the second connector each may include the second layer, and may not include the first layer.

[0014] In the open area, the side surface of the first connector and the side surface of the second connector may include an embossed structure.

[0015] In a region where the second layer overlaps the first layer, the second layer may include a plurality of holes exposing the first insulating layer.

[0016] The plurality of holes may constitute a plurality of rows, and among the plurality of rows, holes in two rows adjacent to each other may be arranged to be staggered with each other in the longitudinal direction.

[0017] The first insulating layer may include a plurality of contact holes, the first layer is connected to the second layer via the plurality of contact holes, and the plurality of contact holes may be respectively arranged between the plurality of holes.

[0018] According to one or more embodiments, a display device includes a substrate, the substrate including a display area, a peripheral area outside the display area, and a pad area in the peripheral area; a first main voltage line, the first main voltage line is arranged in the peripheral area of ​​the substrate and between the edge of the display area and the pad area, and a first connector extends from the first main voltage line to the pad area; and a second main voltage line, the second main voltage line is arranged in the peripheral area of ​​the substrate and corresponds to another edge of the display area, and a second connector extends from the second main voltage line to the pad area, wherein each of the first connector and the second connector includes a structure in which a first layer and a second layer are stacked, a first insulating layer is arranged between the first layer and the second layer, and a second insulating layer is arranged on the second layer, the peripheral area includes an open area, the open area exposes a portion of the first connector and a portion of the second connector, and surrounds the display area, and the second insulating layer includes a height difference reducer, the height difference reducer is at a boundary between the second insulating layer and the open area between the first connector and the second connector, wherein the height difference reducer has a thickness less than the thickness of the second insulating layer.

[0019] Two opposite distal ends of the height difference reducer may overlap the first connector and the second connector, respectively.

[0020] In the open area, the first connector and the second connector may each include the second layer, and may not include the first layer.

[0021] In the open area, the side surface of the first connector and the side surface of the second connector may include an embossed structure.

[0022] In a region where the second layer overlaps the first layer, the second layer may include a plurality of holes exposing the first insulating layer.

[0023] The plurality of holes may constitute a plurality of rows, and among the plurality of rows, holes in two rows adjacent to each other may be arranged to be staggered with each other in the longitudinal direction.

[0024] The first insulating layer may include a plurality of contact holes, the first layer is connected to the second layer via the plurality of contact holes, and the plurality of contact holes may be respectively arranged between the plurality of holes.

[0025] The first insulating layer may include a plurality of slits disposed between the first connector and the second connector and extending from an end of the first insulating layer toward the display area.

[0026] The second insulating layer may include a plurality of concave portion portions in positions respectively overlapping the plurality of slits.

[0027] In the open area, at least one dam may be disposed, and the at least one dam surrounds the display area.

[0028] In addition to the above-described aspects, features, and effects, other aspects, features, and effects will become apparent from the following drawings, claims, and detailed description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] These and / or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a schematic plan view illustrating an example of a display device according to an embodiment;

[0031] Figure 2 yes Figure 1 An equivalent circuit diagram of a pixel of a display device;

[0032] Figure 3 is to explain along the Figure 1 A schematic cross-sectional view of an embodiment of a cross section taken along line II';

[0033] Figure 4 yes Figure 1 A schematic plan view of area A;

[0034] Figure 5 is to explain along the Figure 4 A schematic cross-sectional view of an embodiment of a cross section taken along line II-II';

[0035] Figure 6 yes Figure 4 A schematic plan view of area B;

[0036] Figure 7 is to explain along the Figure 6 A schematic cross-sectional view of an embodiment of a cross section taken along line III-III';

[0037] Figure 8 is to explain along the Figure 6 A schematic cross section of an embodiment of a cross section taken along line IV-IV';

[0038] Fig. 9 is to explain along the Figure 6 A schematic cross-sectional view of an embodiment of a cross section taken along line V-V';

[0039] Fig.10 is to explain along the Figure 6 A schematic cross-sectional view of an embodiment of a cross section taken along line VI-VI'; and

[0040] Fig.11 is to explain along the Figure 6 Schematic cross-sectional view of an embodiment of a cross section taken along line VII-VII'. DETAILED DESCRIPTION

[0041] The embodiments in the accompanying drawings will now be explained in detail with reference to their examples, wherein the same reference numerals always refer to the same elements. In this regard, the present embodiments may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain aspects of the present description. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. Expressions such as "at least one" when preceding a list of elements modify the entire list of elements without modifying the individual elements of the list.

[0042] Since the present disclosure allows various changes and many embodiments, specific embodiments will be illustrated in the drawings and described in detail in the written description. The effects and features of the present disclosure and methods for achieving these effects and features will become apparent to those skilled in the art from the following detailed description that discloses various embodiments in conjunction with the drawings. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0043] It should be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another component.

[0044] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0045] It should be further understood that the terms “comprises” and / or “comprising” as used herein indicate the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0046] It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, it may be directly or indirectly formed on the other layer, region, or component. That is, for example, intervening layers, regions, or components may be present.

[0047] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings are arbitrarily explained for the convenience of explanation, the following embodiments are not limited thereto.

[0048] When a certain embodiment can be implemented differently, a specific process order may be performed differently from the described order. For example, two processes described in succession may be performed substantially simultaneously or in the reverse order of the described order.

[0049] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote the same elements, and thus their description will not be repeated.

[0050] Figure 1 is a schematic plan view illustrating an example of a display device 10 according to an embodiment. Figure 2 yes Figure 1 1 is an equivalent circuit diagram of a pixel of the display device 10.

[0051] refer to Figure 1 and Figure 2 According to an embodiment of the present inventive concept, the display device 10 includes a display area DA in which an image is displayed, and a peripheral area PA outside the display area DA. It can be understood that the substrate 100 included in the display device 10 includes the display area DA and the peripheral area PA.

[0052] In the display area DA, a plurality of (sub) pixels P are arranged. Figure 2 An embodiment of an equivalent circuit diagram of a (sub) pixel P is explained. Figure 2 , the (sub) pixel P may include a pixel circuit PC connected to the scan line SL and the data line DL, and a light emitting diode connected to the pixel circuit PC. As an example, the light emitting diode may be an organic light emitting diode OLED.

[0053] The pixel circuit PC may include a driving thin film transistor Td, a switching thin film transistor Ts, and a storage capacitor Cst. The switching thin film transistor Ts is connected to the scan line SL and the data line DL, and when a data signal is input through the data line DL, the switching thin film transistor Ts may transfer the data signal to the driving thin film transistor Td according to the scan signal input through the scan line SL. The storage capacitor Cst is connected to the switching thin film transistor Ts and the driving voltage line PL. The storage capacitor Cst may store a voltage corresponding to the difference between the voltage transferred from the switching thin film transistor Ts and the driving voltage ELVDD supplied to the driving voltage line PL.

[0054] The driving thin film transistor Td is connected to the driving voltage line PL and the storage capacitor Cst. The driving thin film transistor Td may control a driving current flowing from the driving voltage line PL through the organic light emitting diode OLED corresponding to the value of the voltage stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light having a certain brightness according to the driving current. The organic light emitting diode OLED may emit, for example, red light, green light, blue light, or white light.

[0055] refer to Figure 2, describes the case where the (sub) pixel P includes two thin film transistors and one storage capacitor. However, the present disclosure is not limited thereto. As another exemplary embodiment, various modifications may be made, such a pixel circuit PC of the (sub) pixel P includes three or more thin film transistors and two or more storage capacitors.

[0056] Return to reference Figure 1 , the peripheral area PA of the substrate 100 may surround the display area DA. The peripheral area PA is an area in which a plurality of (sub) pixels P are not arranged. The peripheral area PA includes a pad area PADA, which is an area to which various electronic devices, printed circuit boards, etc. are electrically attached. A first voltage line 210 and a second voltage line 220, each supplying power for driving a light emitting diode, may be arranged in the peripheral area PA. The first voltage line 210 may be a line for a driving voltage ELVDD, and the second voltage line 220 may be a line for a common voltage ELVSS. As an example, the first voltage line 210 may be arranged between an edge of the display area DA and the pad area PADA, and the second voltage line 220 may be arranged corresponding to another edge of the display area DA. As an example, the second voltage line 220 may surround other edges of the display area DA without surrounding the edge of the display area DA where the first voltage line 210 is arranged.

[0057] Figure 1 It can be understood as a plan view of the substrate 100 and other components when manufacturing the display device 10. In an electronic device that is a final product, such as the display device 10, or a smartphone including the display device 10, part of the substrate 100 and other components may be curved to minimize the size of the peripheral area PA seen by the user.

[0058] Figure 3 is to explain along the Figure 1 Schematic cross-sectional view of an embodiment of a cross section taken along line II'. Figure 4 yes Figure 1 Schematic plan view of area A. Figure 5 is to explain along the Figure 4 Schematic cross-sectional view of an embodiment of a cross section taken along line II-II'.

[0059] As described above, a portion of the substrate 100 may be bent to minimize the size of the peripheral area PA. Figure 4 In the embodiment shown in FIG. 1 , the peripheral area PA may include a bending area BA, and the bending area BA may be arranged between the pad area PADA and the display area DA. In this case, by bending the substrate 100 in the bending area BA, at least part of the pad area PADA may be arranged to overlap the display area DA. The bending direction is set so that the pad area PADA does not cover the display area DA but is arranged behind the display area DA. Therefore, the user may think that the display area DA occupies most of the display device 10.

[0060] The substrate 100 may include various flexible or bendable materials. For example, the substrate 100 may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), cellulose acetate propionate (CAP), etc. However, the substrate 100 may be modified in various ways, for example, to have a multilayer structure including two layers including such a polymer resin and a barrier layer disposed therebetween, wherein the barrier layer includes an inorganic material (such as silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiO x N y )).

[0061] Below, reference Figure 3 , describing the structure of (sub) pixels in detail.

[0062] like Figure 3 As shown in FIG. 1 , in the display area DA, a first thin film transistor T1, a second thin film transistor T2, a storage capacitor Cst, and a light emitting diode 300 may be arranged. As an example, the light emitting diode 300 may include an organic light emitting diode OLED. The first thin film transistor T1 may include a reference Figure 2 The pixel circuit PC described (shown in Figure 2 The driving thin film transistor Td (shown in Figure 2 In addition, the second thin film transistor T2 and the storage capacitor Cst may correspond to the reference Figure 2 The pixel circuit PC described (shown in Figure 2 The switching thin film transistor Ts (shown in Figure 2 in) and the storage capacitor Cst (shown in Figure 2 middle).

[0063] The first thin film transistor T1 may include a first semiconductor layer Act1 and a first gate electrode G1. The second thin film transistor T2 may include a second semiconductor layer Act2 and a second gate electrode G2.

[0064] The first semiconductor layer Act1 and the second semiconductor layer Act2 may each include amorphous silicon, polycrystalline silicon, an oxide semiconductor material, or an organic semiconductor material. The first semiconductor layer Act1 may include a channel region C1, and a source region S1 and a drain region D1 respectively arranged at two sides of the channel region C1. The second semiconductor layer Act2 may include a channel region C2, and a source region S2 and a drain region D2 respectively arranged at two sides of the channel region C2. The source region S1 and the drain region D1 of the first semiconductor layer Act1 may be respectively understood as a source electrode and a drain electrode of the first semiconductor layer Act1. The source region S2 and the drain region D2 of the second semiconductor layer Act2 may be respectively understood as a source electrode and a drain electrode of the second semiconductor layer Act2.

[0065] The first gate electrode G1 may overlap the channel region C1 of the first semiconductor layer Act1 with the gate insulating layer 120 therebetween. The second gate electrode G2 may overlap the channel region C2 of the second semiconductor layer Act2 with the gate insulating layer 120 therebetween. The first gate electrode G1 and the second gate electrode G2 may each include a single layer or multiple layers including a conductive material including at least one selected from molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).

[0066] Figure 3 It is shown that the first gate electrode G1 and the second gate electrode G2 are arranged on the same layer. However, the present disclosure is not limited thereto. As another embodiment, the first gate electrode G1 and the second gate electrode G2 may be arranged on different layers. In addition, Figure 3 An embodiment in which the first gate electrode G1 and the second gate electrode G2 are respectively arranged above the first semiconductor layer Act1 and the second semiconductor layer Act2 is explained. However, the present disclosure is not limited thereto. As another embodiment, the first thin film transistor T1 and the second thin film transistor T2 may be bottom-gate transistors in which the first semiconductor layer Act1 and the second semiconductor layer Act2 are respectively arranged above the first gate electrode G1 and the second gate electrode G2.

[0067] The storage capacitor Cst may include a first storage capacitor plate CE1 and a second storage capacitor plate CE2. The first storage capacitor plate CE1 and the second storage capacitor plate CE2 may each include a low resistance conductive material including at least one selected from Mo, Al, Cu, and Ti.

[0068] The storage capacitor Cst may be arranged to overlap with the first thin film transistor T1 (which is a driving thin film transistor). Therefore, the sizes of the storage capacitor Cst and the first thin film transistor T1 may be increased, and a high-quality image may be provided. As an example, the first storage capacitor plate CE1 may be the first gate electrode G1 of the first thin film transistor T1. However, the present disclosure is not limited thereto. As another embodiment, the storage capacitor Cst may be arranged not to overlap with the first thin film transistor T1, and the first storage capacitor plate CE1 may be an element separated from the first gate electrode G1 of the first thin film transistor T1.

[0069] A buffer layer 110 may be disposed between the substrate 100 and the first and second thin film transistors T1 and T2. The buffer layer 110 may include an inorganic insulating material. For example, the buffer layer 110 may include a material selected from SiO x N y 、SiO x and SiN x A single layer or multiple layers of at least one of the above.

[0070] Between the first gate electrode G1 and the second gate electrode G2 and the first semiconductor layer Act1 and the second semiconductor layer Act2, a gate insulating layer 120 may be disposed. The gate insulating layer 120 may include an inorganic insulating material. For example, the gate insulating layer 120 may include a material selected from SiO x N y 、SiO x and SiN x A single layer or multiple layers of at least one of the above.

[0071] The first thin film transistor T1 and the second thin film transistor T2 may be covered by the interlayer insulating layer 130. The interlayer insulating layer 130 may include a first interlayer insulating layer 131 and a second interlayer insulating layer 132. The first interlayer insulating layer 131 may be directly disposed on the first thin film transistor T1 and the second thin film transistor T2 and / or the first storage capacitor plate CE1, and may be in direct contact with the first thin film transistor T1 and the second thin film transistor T2 and / or the first storage capacitor plate CE1. The second interlayer insulating layer 132 may be directly disposed on the second storage capacitor plate CE2, and may be in direct contact with the second storage capacitor plate CE2. Each of the first interlayer insulating layer 131 and the second interlayer insulating layer 132 may include a material selected from SiO x N y 、SiO x and SiN x In one embodiment, the first interlayer insulating layer 131 may include SiN x The second interlayer insulating layer 132 may include a single layer including SiN x and SiO x Multiple layers.

[0072] On the interlayer insulating layer 130, a data line DL may be arranged. The data line DL may be connected to the second semiconductor layer Act2 of the second thin film transistor T2 through a contact hole in the interlayer insulating layer 130. As an example, Figure 3 It is explained that the data line DL is connected to the drain region D2 of the second thin film transistor T2. In this case, the data line DL can be understood as a drain electrode. The data line DL may include a single layer or multiple layers including at least one selected from Al, Cu, Ti and alloys thereof. In one embodiment, the data line DL may include three layers including Ti / Al / Ti respectively.

[0073] On the interlayer insulating layer 130, a lower driving voltage line PL1 of the driving voltage line PL may be arranged. The lower driving voltage line PL1 may include the same material as that of the data line DL. In addition, above the interlayer insulating layer 130, in the display area DA and / or the peripheral area PA, various conductive layers may be arranged. In this way, the conductive layers above the interlayer insulating layer 130 may be collectively referred to as "first metal wiring".

[0074] The first metal wiring includes at least a data line DL and a lower driving voltage line PL1, and may be covered by an inorganic protective layer 134. The inorganic protective layer 134 may include SiN x or SiO x The inorganic protective layer 134 can prevent the first metal wiring from being used in manufacturing the display device 10 (displayed in Figure 1 The semiconductor device may be damaged during an etching process performed during the process of FIG.

[0075] The first insulating layer 141 may be disposed on the first metal wiring, and the upper driving voltage line PL2 of the driving voltage line PL may be disposed on the first insulating layer 141. The upper driving voltage line PL2 may be disposed to overlap with the lower driving voltage line PL1, and connected to the lower driving voltage line PL1 via a contact hole in the first insulating layer 141. The upper driving voltage line PL2 may include Mo, Al, Cu, Ti, etc., and include a single layer or multiple layers. In some embodiments, the upper driving voltage line PL2 may include a three-layer structure including Ti / Al / Ti.

[0076] Thus, when the driving voltage line PL includes the lower driving voltage line PL1 and the upper driving voltage line PL2, the resistance of the driving voltage line PL is reduced. Figure 1 When the driving voltage line PL is large, the voltage drop phenomenon caused by the resistance of the driving voltage line PL is also reduced, thereby providing a high-quality image.

[0077] In addition to the upper driving voltage line PL2, various conductive layers may be disposed above the first insulating layer 141. Thus, the conductive layers above the first insulating layer 141 may be collectively referred to as "second metal wirings".

[0078] The upper driving voltage line PL2 may be covered by the second insulating layer 142 (which is a planarized insulating layer). The first insulating layer 141 and the second insulating layer 142 described above may include organic materials. The organic material may include an imide polymer, a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative containing a phenol group, an acrylic polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a blend thereof.

[0079] On the second insulating layer 142, a light emitting diode 300 may be disposed, wherein the light emitting diode 300 includes a pixel electrode 310, a common electrode 330, and an intermediate layer 320 disposed between the pixel electrode 310 and the common electrode 330 and including a light emitting layer. As an example, the light emitting diode 300 may include an organic light emitting diode OLED.

[0080] The pixel electrode 310 is disposed on the second insulating layer 142. Although not illustrated in the drawings, the pixel electrode 310 may be electrically connected to the first thin film transistor T1 thereunder through a contact hole in the second insulating layer 142.

[0081] On the second insulating layer 142, a pixel defining layer 150 covering the edge of the pixel electrode 310 may be disposed. The pixel defining layer 150 includes an opening corresponding to each pixel, that is, an opening that exposes at least the central portion of the pixel electrode 310 to define the pixel. In addition, the pixel defining layer 150 can prevent arcing and other problems between the edge of the pixel electrode 310 and the common electrode 330 by increasing the distance between the edge of the pixel electrode 310 and the common electrode 330. The pixel defining layer 150 may be formed of an organic material such as polyimide, hexamethyldisiloxane (HMDSO), and the like.

[0082] On the pixel electrode 310 exposed by the opening in the pixel defining layer 150, an intermediate layer 320 may be arranged. The intermediate layer 320 may include a low molecular weight material or a polymer material. When the intermediate layer 320 includes a low molecular weight material, the intermediate layer 320 may have a single layer structure or a composite stacked structure including a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and / or an electron injection layer (EIL), and include various organic materials such as copper phthalocyanine (CuPc), N,N'-di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (NPB), tris-(8-hydroxyquinoline) aluminum (Alq 3 ) etc. These layers can be formed by using a vacuum deposition method.

[0083] When the intermediate layer 320 includes a polymer material, the intermediate layer 320 may generally have a structure including an HTL or an EML. The HTL may include poly-(2,4)-ethylene-dihydroxythiophene (PEDOT). The EML may include a polymer material such as polyphenylene vinylene (PPV), polyfluorene, etc. However, the structure of the intermediate layer 320 is not limited thereto and may have various structures. For example, the intermediate layer 320 may include a layer integrally arranged above the plurality of pixel electrodes 310 or a layer patterned corresponding to the plurality of pixel electrodes 310.

[0084] On the intermediate layer 320 , the common electrode 330 may be disposed to cover the display area DA. That is, the common electrode 330 may be formed as one continuous body to cover the plurality of pixel electrodes 310 and the plurality of intermediate layers 320 .

[0085] On the common electrode 330, an encapsulation layer 400 is disposed. The encapsulation layer 400 protects the light emitting diode 300 from external moisture, oxygen, etc. To this end, the encapsulation layer 400 has a shape extending not only through the display area DA in which the light emitting diode 300 is disposed but also to the peripheral area PA outside the display area DA. The encapsulation layer 400 may have a shape such as Figure 3 In detail, the encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430 that are sequentially stacked.

[0086] The first inorganic encapsulation layer 410 is disposed on the common electrode 330 and may include SiO x 、SiN x and / or SiO x N y The first inorganic encapsulating layer 410 may be formed along the structure below the first inorganic encapsulating layer 410 .

[0087] The organic encapsulation layer 420 is disposed on the first inorganic encapsulation layer 410 and has a thickness sufficient to substantially planarize an upper surface of the organic encapsulation layer 420. The organic encapsulation layer 420 may include one or more materials selected from the group consisting of polyethylene terephthalate, polyacrylate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and HMDSO.

[0088] The second inorganic encapsulation layer 430 may cover the organic encapsulation layer 420 and include SiO x 、SiN x and / or SiO x N yThe first inorganic encapsulating layer 410 and the second inorganic encapsulating layer 430 may each be larger than the organic encapsulating layer 420. The first inorganic encapsulating layer 410 may contact the second inorganic encapsulating layer 430 outside the organic encapsulating layer 420. That is, the first inorganic encapsulating layer 410 and the second inorganic encapsulating layer 430 may prevent the organic encapsulating layer 420 from being exposed to the outside.

[0089] As such, since the encapsulation layer 400 includes the first inorganic encapsulation layer 410, the organic encapsulation layer 420, and the second inorganic encapsulation layer 430, even when cracks occur in the encapsulation layer 400 due to such a multi-layer structure, the cracks may not be connected to each other between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420 or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430. Therefore, the formation of a path through which external moisture, oxygen, etc. penetrate into the display area DA may be prevented or minimized.

[0090] like Figure 4 As shown in FIG. 1 , in the peripheral area PA, the first voltage line 210 and the second voltage line 220 may be arranged, and a bending area BA may be set, wherein the first voltage line 210 and the second voltage line 220 supply driving power to the light emitting diode 300 .

[0091] As an example, the first voltage line 210 may be a line for a first power voltage (which is a driving voltage ELVDD), and the second voltage line 220 may be a line for a second power voltage (which is a common voltage ELVSS). The first voltage line 210 may be connected to the driving voltage line PL. The second voltage line 220 may be connected to the common electrode 330 directly or via another line.

[0092] The first voltage line 210 may be arranged between the edge of the display area DA and the pad area PADA. The first voltage line 210 may include a first connector 214 and a first main voltage line 212 arranged to correspond to the edge of the display area DA. For example, when the display area DA has a rectangular shape, the first main voltage line 212 may be arranged to correspond to the side of the display area DA. The first main voltage line 212 may be parallel to the side of the display area DA and longer than the side of the display area DA. The side of the display area DA corresponding to the first main voltage line 212 may be adjacent to the pad area PADA.

[0093] The first connector 214 may extend from the first main voltage line 212 and extend in a first direction Y. Here, the first direction is a direction Y from the display area DA to the pad area PADA. The first connector 214 may be connected to a pad (not shown).

[0094] The second voltage line 220 may surround and be directly adjacent to the remaining edge of the display area DA, but not surround and be directly adjacent to the edge of the display area DA adjacent to the first voltage line 210. The second voltage line 220 may include a second main voltage line 222 corresponding to two opposite distal ends of the first main voltage line 212 and the remaining edge of the display area DA, and a second connector 224 extending from an end of the second main voltage line 222 in the first direction Y and extending in the first direction Y. The second connector 224 may be connected to a pad (not shown).

[0095] The bending area BA is disposed between the display area DA and the pad area PADA. Figure 5 As shown in FIG. 1 , the bending area BA is an area of ​​the substrate 100 from which a portion of the buffer layer 110, a portion of the gate insulating layer 120, a portion of the first interlayer insulating layer 131, and a portion of the second interlayer insulating layer 132 are removed. Hereinafter, the buffer layer 110, the gate insulating layer 120, and the interlayer insulating layer 130 are collectively referred to as "inorganic insulating layer". That is, it can be understood that the inorganic insulating layer stacked on the substrate 100 includes a groove at a position corresponding to the bending area BA. By removing part of the inorganic insulating layer, the bending of the substrate 100 can be easily performed in the bending area BA, and when the substrate 100 is bent, cracks or the like can be prevented from occurring in the inorganic insulating layer.

[0096] The area where a portion of the inorganic insulating layer is removed may be filled with an organic material layer 160. Referring to the bending area BA, the organic material layer 160 may extend to a non-bending area adjacent to the bending area BA. The organic material layer 160 may not only compensate for the height difference in the bending area BA where the inorganic insulating layer is removed, but also absorb stress generated by bending. Therefore, when bending is performed, stress concentration on various connection wires arranged in the bending area BA to transfer electrical signals from pads (not shown) in the pad area PADA to the display area DA may be effectively and greatly reduced.

[0097] The organic material layer 160 may include at least one material selected from the group consisting of acrylic, methacrylate, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and HMDSO.

[0098] On the bending area BA, a first insulating layer 141, a second insulating layer 142, and a pixel defining layer 150 are arranged. In addition, on the bending area BA, a bending protection layer (not shown) may be further arranged above the pixel defining layer 150, and configured so that when bending is performed, the stress neutral plane is arranged in the periphery of the wiring in the bending area BA.

[0099] Figure 6 yes Figure 4Schematic plan view of area B. Figures 7 to 11 is to explain respectively along Figure 6 Schematic cross-sectional views of embodiments of cross sections taken along lines III-III', IV-IV', V-V', VI-VI' and VII-VII'.

[0100] First, refer to Figures 6 to 8 , describing the construction of the second connector 224. Figures 6 to 8 , the second connector 224 may include a first layer M1 and a second layer M2 overlapping each other with a first insulating layer 141 therebetween.

[0101] The first layer M1 is a conductive layer on the interlayer insulating layer 130. The first layer M1 may be included in the first metal wiring. Therefore, the first layer M1 may have a conductive layer connected to the data line DL (shown in FIG. Figure 3 For example, the first layer M1 may include a single layer or multiple layers including one selected from Al, Cu, Ti, and alloys thereof. As an embodiment, the first layer M1 may include three layers including Ti / Al / Ti, respectively.

[0102] The second layer M2 is a conductive layer on the first insulating layer 141. The second layer M2 may be included in the second metal wiring. Therefore, the second layer M2 may have a conductive layer connected to the upper driving voltage line PL2 (shown in FIG. Figure 4 The same structure as in Figure 7 As shown in FIG. 1 , the second layer M2 may be connected to the first layer M1 via a plurality of contact holes CNT in the first insulating layer 141 .

[0103] In addition, if Figure 8 As shown in FIG. 1 , the second layer M2 may include a plurality of holes H. The plurality of holes H in the second layer M2 may emit gas from the inside of the first insulating layer 141. Therefore, it is possible to prevent the display device 10 (displayed in FIG. 1 ) from being manufactured. Figure 1 After the light emitting diode 300 ( Figure 3 The middle layer 320 (shown in Figure 3 When the first insulating layer 141 is degraded due to outgassing, defects such as pixel shrinkage may be caused.

[0104] The plurality of holes H constitute a plurality of rows. Among the plurality of rows, the holes H in two rows adjacent to each other may be arranged to be staggered with each other in the longitudinal direction. In order to connect the first layer M1 to the second layer M2, the plurality of contact holes CNT in the first insulating layer 141 may be arranged between the plurality of holes H. Therefore, the plurality of contact holes CNT in the first insulating layer 141 also constitute a plurality of rows, and among the plurality of rows, the contact holes CNT in two rows adjacent to each other may be arranged to be staggered with each other in the longitudinal direction. Therefore, the height difference in the longitudinal direction is reduced compared to when the first insulating layer 141 is removed in the horizontal direction to connect the first layer M1 to the second layer M2. Therefore, the probability that cracks may occur in the second layer M2 may be reduced, and the connection resistance between the first layer M1 and the second layer M2 may be reduced.

[0105] So far, the configuration of the second connector 224 has been described. However, the first connector 214, the first main voltage line 212 (shown in FIG. Figure 4 in) and the second main voltage line 222 (shown in Figure 4 ) may also have the same structure as the second connector 224. That is, because the first connector 214, the first main voltage line 212 (shown in Figure 4 in) and the second main voltage line 222 (shown in Figure 4 ) includes the first layer M1 and the second layer M2 in the first region AR1, so the resistance can be reduced, wherein the first layer M1 and the second layer M2 are connected to each other in parallel via the plurality of contact holes CNT in the first insulating layer 141. In this case, the second layer M2 may include a plurality of holes H.

[0106] Here, the first area AR1 refers to an area in which both the first layer M1 and the second layer M2 are arranged. On the other hand, the second area AR2 adjacent to the first area AR1 includes a bending area BA (shown in FIG. Figure 4 in the middle) and can be tolerated in the bending area BA (shown in Figure 4 In order to prevent damage caused by stress in the first connector 214 and the second connector 224, only the second layer M2 is arranged in the second area AR2, that is, the first layer M1 is not arranged in the second area AR2.

[0107] Therefore, even when the first connector 214 and the second connector 224 cross the bending area BA (shown in FIG. Figure 4 ), and extends to the pad area PADA (shown in Figure 4 Since only the second layer M2 is arranged in the second area AR2, it can be prevented that when the bending area BA (shown in Figure 4 In the bending substrate 100 (shown in Figure 1 When the first connector 214 and the second connector 224 are damaged due to stress.

[0108] like Figure 6 As shown in FIG. 1 , in the second area AR2, an open area OA in which the first insulating layer 141 and the second insulating layer 142 are removed may be arranged. In detail, the end of the first insulating layer 141 directed toward the open area OA may be covered by the end of the second insulating layer 142. Therefore, the end of the second insulating layer 142 may be a boundary with the open area OA. The open area OA may expose the first connector 214 and the second connector 224. The open area OA may be arranged in the peripheral area PA (shown in FIG. 1 ). Figure 1 and may surround the display area DA (displayed in Figure 1 Therefore, it is possible to prevent external moisture and the like from penetrating into the display area DA (displayed in FIG. 1 ) through the first insulating layer 141 and / or the second insulating layer 142 (both formed of organic materials). Figure 1 in Chinese.

[0109] The first voltage line 210 (shown in Figure 4 ) and the second voltage line 220 (shown in Figure 4 ) has a structure in which a first layer M1 and a second layer M2 are stacked. Therefore, when the first voltage line 210 (shown in Figure 4 ) and the second voltage line 220 (shown in Figure 4 Compared with the case where only the first layer M1 or the second layer M2 is included, the first voltage line 210 (shown in FIG. Figure 4 ) and the second voltage line 220 (shown in Figure 4 Therefore, the height difference between the upper surface of the open area OA and the second insulating layer 142 is increased. That is, as the depth of the open area OA increases, because in manufacturing the display device 10 (displayed in Figure 1 Foreign matter generated in the process of (in) is precipitated from the open area OA, or a residual layer is generated in a region where a height difference occurs between the open area OA and the second insulating layer 142, so a short circuit may occur between the first connector 214 and the second connector 224.

[0110] refer to Fig. 9 In order to prevent the occurrence of a short circuit, the first insulating layer 141 may include a first insulating layer 141 extending from the end of the first insulating layer 141 toward the display area DA (displayed in FIG. Figure 1 The plurality of slits SL are formed by removing the first insulating layer 141 in a direction perpendicular to the imaginary line connecting the first connector 214 to the second connector 224. According to the plurality of slits SL, each of the plurality of concave portions G may be formed in a portion of the second insulating layer 142 corresponding to each of the plurality of slits SL. Therefore, for example, even when particles are deposited between the first connector 214 and the second connector 224, wherein the particles are formed when etching the second layer M2 or forming the pixel electrode 310 (shown in FIG. 1 ), the plurality of slits SL are formed. Figure 3 The formation of a continuous short-circuit path connecting the first connector 214 and the second connector 224 can also be prevented.

[0111] In addition, the second insulating layer 142 may include a height difference reducer 143 at a boundary with the open area OA. The height difference reducer 143 has a thickness smaller than that of the second insulating layer 142. When the second insulating layer 142 is formed, the height difference reducer 143 may be formed together with the second insulating layer 142 by adjusting an exposure dose using a half-tone mask. In this way, when the height difference reducer 143 is arranged in a region adjacent to the open area OA, the height difference between the second insulating layer 142 and the open area OA may be reduced, as shown in FIG. Fig.10 . Therefore, in the subsequent process, the generation of a residual layer in the area adjacent to the open area OA can be effectively prevented. The height difference reducer 143 can be arranged at least between the first connector 214 and the second connector 224. Two opposite distal ends of the height difference reducer 143 can overlap with the first connector 214 and the second connector 224, respectively.

[0112] In the open area OA, the first baffle 610 may be arranged. When the organic encapsulation layer 420 is formed, the first baffle 610 may limit the material of the organic encapsulation layer 420 to the inside of a predetermined area. The first baffle 610 may have a multi-layer structure. As an example, Fig.11 , the first barrier 610 may have a structure in which a first layer 611, a second layer 613, and a third layer 615 are stacked. The first layer 611 may be formed of the same material as the second insulating layer 142 and formed simultaneously with the second insulating layer 142. The second layer 613 may be formed of the same material as the pixel defining layer 150 (shown in FIG. Figure 3 The third layer 615 may be formed of the same material as that of the second layer 613 and may be formed simultaneously with the pixel defining layer 150.

[0113] The first baffle 610 supports the intermediate layer 320 (shown in FIG. Figure 3 in) or common electrode 330 (shown in Figure 3 In this process, the first baffle 610 can prevent previously formed components from contacting the mask and being damaged by such contact. In addition, when the organic encapsulation layer 420 is formed on the first inorganic encapsulation layer 410, the first baffle 610 can prevent the material of the organic encapsulation layer 420 from being deposited toward the substrate 100 (shown in FIG. Figure 1 Move in the direction of the edge of the

[0114] like Fig.11As shown in FIG. 6 , the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may cover the first baffle 610 and extend to the outside of the first baffle 610 , thereby effectively preventing the penetration of external moisture or oxygen.

[0115] Inside the first baffle 610, that is, between the first baffle 610 and the height difference reducer 143, a second baffle 620 may be further arranged. The second baffle 620 may include a lower layer 623 and an upper layer 625, wherein the lower layer 623 may be formed of the same material as the second layer 613 of the first baffle 610 and formed simultaneously with the second layer 613, and the upper layer 625 is arranged on the lower layer 623 and may be formed of the same material as the third layer 615 of the first baffle 610 and formed simultaneously with the third layer 615. The second baffle 620 may be shorter than the first baffle 610.

[0116] The first baffle 610 and the second baffle 620 may be provided around the display area DA (displayed on the display Figure 1 The organic encapsulation layer 420 is prevented from spreading to the edge of the substrate 100. Therefore, the formation of the edge tail of the organic encapsulation layer 420 can be prevented.

[0117] As described above, the height difference in the open area OA may change rapidly. Therefore, when the material of the organic encapsulation layer 420, such as a liquid organic material, is applied to the open area OA, the reflow of the material of the organic encapsulation layer 420 may mainly occur in the open area OA. In addition, recently, with the peripheral area PA (shown in FIG. Figure 1 The space between the first baffle 610 and the second baffle 620 has been greatly reduced, gradually reducing the space between the first baffle 610 and the second baffle 620. Therefore, it may be difficult to restrict the flow of the material of the organic encapsulation layer 420. In particular, the material of the organic encapsulation layer 420 flows toward the pad area PADA (shown in FIG. 1 ) along the side of the first connector 214 and the second connector 224. Figure 4 The organic encapsulation layer 420 is dispersed much more rapidly in the direction of the organic encapsulation layer 420 than in the direction in which the first baffle 610 and the second baffle 620 are arranged. Therefore, in order to prevent the formation of the edge tail of the organic encapsulation layer 420, it is necessary to prevent the material of the organic encapsulation layer 420 from being dispersed in the direction toward the organic encapsulation layer 420. Figure 4 The pad area is scattered in the direction of PADA.

[0118] For this reason, Figure 6As shown in , the side 214E of the first connector 214 and the side 224E of the second connector 224 may each include an embossed structure in the open area OA. For example, the side 214E of the first connector 214 and the side 224E of the second connector 224 may have a zipper shape. In this way, when the side 214E of the first connector 214 and the side 224E of the second connector 224 are arranged, the dominant flow of the material of the organic encapsulation layer 420 can be blocked at the side 214E of the first connector 214 and the side 224E of the second connector 224. Therefore, when the material of the organic encapsulation layer 420 is applied, the material of the organic encapsulation layer 420 can be effectively prevented from being dispersed to the substrate 100 above the first baffle 610 (shown in Figure 1 edge of the center).

[0119] For ease of description, Figures 7 to 10 The first inorganic encapsulation layer 410, the organic encapsulation layer 420, and the second inorganic encapsulation layer 430 are not illustrated. Figures 7 to 10 The area shown in FIG. 6 is the inner area of ​​the first baffle 610 and the second baffle 620. Figures 7 to 10 The illustrated embodiment also includes a first inorganic encapsulating layer 410 , an organic encapsulating layer 420 , and a second inorganic encapsulating layer 430 .

[0120] According to an embodiment, since the first voltage line and the second voltage line each include a first layer and a second layer connected in parallel to each other, the resistance in the first voltage line and the second voltage line is reduced, so that the display device can display a high-quality image. In addition, a short circuit between the first connector of the first voltage line and the second connector of the second voltage line can be effectively prevented, thereby enhancing the reliability of the display device. However, the scope of the present disclosure is not limited to this effect.

[0121] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects in each embodiment should generally be considered as being applicable to other similar features or aspects in other embodiments.

[0122] Although one or more embodiments have been described with reference to the drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope defined by the following claims.

Claims

1. A display device, comprising: A substrate, the substrate comprising a display area, a peripheral area outside the display area, and a pad area in the peripheral area; a first main voltage line, the first main voltage line being arranged in the peripheral area of ​​the substrate and between an edge of the display area and the pad area, and a first connector extending from the first main voltage line to the pad area; and a second main voltage line, the second main voltage line being arranged in the peripheral area of ​​the substrate and corresponding to another edge of the display area, and a second connector extending from the second main voltage line to the pad area, wherein each of the first connector and the second connector comprises a first layer and a second layer overlapping each other, a first insulating layer is disposed between the first layer and the second layer, wherein the first insulating layer is disposed in the display area and the peripheral area of ​​the substrate, The peripheral area includes an open area that exposes the first connector and the second connector and surrounds the display area, and The first insulating layer includes a plurality of slits disposed between the first connector and the second connector and extending from an end of the first insulating layer toward the display area. 2 . The display device according to claim 1 , further comprising a second insulating layer on the second layer in the open area.

3. The display device according to claim 2, wherein the second insulating layer further comprises a height difference reducer at a boundary of the second insulating layer and the open area between the first connector and the second connector, and The height difference reducer has a thickness smaller than that of the second insulating layer. 4 . The display device of claim 3 , wherein two opposite distal ends of the height difference reducer overlap the first connector and the second connector, respectively. 5 . The display device according to claim 2 , wherein the second insulating layer includes a plurality of concave portions respectively overlapping the plurality of slits. 6 . The display device according to claim 1 , wherein in the open area, the first connector and the second connector each include the second layer and do not include the first layer. 7 . The display device of claim 6 , wherein in the open area, a side surface of the first connector and a side surface of the second connector include an embossed structure. 8 . The display device according to claim 1 , wherein the second layer includes a plurality of holes exposing the first insulating layer in a region where the second layer overlaps the first layer. 9 . The display device according to claim 8 , wherein the plurality of holes constitute a plurality of rows, and among the plurality of rows, the holes in two rows adjacent to each other are arranged to be staggered with each other in a longitudinal direction. 10 . The display device of claim 9 , wherein the first insulating layer comprises a plurality of contact holes through which the first layer is connected to the second layer, and the plurality of contact holes are respectively arranged between the plurality of holes.

11. A display device, comprising: A substrate, the substrate comprising a display area, a peripheral area outside the display area, and a pad area in the peripheral area; a first main voltage line, the first main voltage line being arranged in the peripheral area of ​​the substrate and between an edge of the display area and the pad area, and a first connector extending from the first main voltage line to the pad area; and a second main voltage line, the second main voltage line being arranged in the peripheral area of ​​the substrate and corresponding to another edge of the display area, and a second connector extending from the second main voltage line to the pad area, wherein each of the first connector and the second connector includes a structure in which a first layer and a second layer are stacked, a first insulating layer is arranged between the first layer and the second layer, and a second insulating layer is arranged on the second layer, The peripheral area includes an open area, the open area exposes a portion of the first connector and a portion of the second connector and surrounds the display area, and The second insulating layer includes a height difference reducer at a boundary of the second insulating layer and the open area between the first connector and the second connector, wherein the height difference reducer has a thickness smaller than a thickness of the second insulating layer. 12 . The display device of claim 11 , wherein two opposite distal ends of the height difference reducer overlap the first connector and the second connector, respectively. 13 . The display device of claim 11 , wherein in the open area, the first connector and the second connector each include the second layer and do not include the first layer. 14 . The display device of claim 13 , wherein in the open area, a side surface of the first connector and a side surface of the second connector include an embossed structure. 15 . The display device of claim 13 , wherein the second layer includes a plurality of holes exposing the first insulating layer in a region where the second layer overlaps the first layer. 16 . The display device according to claim 15 , wherein the plurality of holes constitute a plurality of rows, and among the plurality of rows, the holes in two rows adjacent to each other are arranged to be staggered with each other in a longitudinal direction. 17 . The display device of claim 15 , wherein the first insulating layer comprises a plurality of contact holes through which the first layer is connected to the second layer, and the plurality of contact holes are respectively arranged between the plurality of holes. 18 . The display device of claim 11 , wherein the first insulating layer comprises a plurality of slits disposed between the first connector and the second connector and extending from an end of the first insulating layer toward the display area. 19 . The display device according to claim 18 , wherein the second insulating layer includes a plurality of concave portions respectively overlapping the plurality of slits. 20 . The display device according to claim 11 , wherein in the open area, at least one baffle is arranged, and the at least one baffle surrounds the display area.

21. A display device comprising: a substrate including a display area in which an image is displayed and a peripheral area outside the display area, wherein a pad area is arranged in the peripheral area; a first main voltage line extending in the peripheral area along a first edge of the display area and arranged between the first edge and the pad area; a second main voltage line, the second main voltage line extending in the peripheral area along a second edge of the display area, the second edge being connected to the first edge, and a portion of the second main voltage line being bent from the second edge along the first edge and extending parallel to and spaced apart from the first main voltage line in a plane; a first connector extending from the first main voltage line toward the pad area; and a second connector extending from the portion of the second main voltage line toward the pad area and spaced apart from and parallel to the first connector on the plane, wherein each of the first connector and the second connector comprises a first conductive layer arranged on the substrate, a first insulating layer arranged on the first conductive layer, a second conductive layer arranged on the first insulating layer, and a second insulating layer arranged on the second conductive layer, and A first zone, a second zone, a third zone and a fourth zone are provided between the first connector and the second connector, in the first zone the second insulating layer is arranged on the first insulating layer, in the second zone the second insulating layer is arranged with a first thickness, in the third zone the second insulating layer is arranged with a second thickness less than the first thickness, and in the fourth zone the first insulating layer and the second insulating layer do not exist. 22 . The display device according to claim 21 , wherein the first region, the second region, the third region, and the fourth region are sequentially arranged in a direction from the display region to the pad region. 23 . The display device of claim 22 , wherein an end portion of the second insulating layer has a shape of a plurality of slits between the first connector and the second connector, and the second region and the third region correspond to the shape of the plurality of slits. 24 . The display device according to claim 23 , wherein the plurality of slits are arranged to be spaced apart from each other in a direction perpendicular to an extending direction of the first connector. 25 . The display device of claim 21 , further comprising a fifth region in which the second insulating layer is arranged on the first insulating layer with a third thickness, and a sixth region in which the second insulating layer is arranged on the first insulating layer with a fourth thickness. 26 . The display device of claim 25 , wherein the second region is adjacent to the fifth region, and the third region is adjacent to the sixth region.

27. The display device of claim 25, wherein the first insulating layer and the second insulating layer extend from the display area. 28 . The display device of claim 27 , wherein a baffle surrounding the display area is disposed between the second insulating layer and the pad area. 29 . The display device of claim 28 , wherein the barrier comprises a third insulating layer, the third insulating layer comprising the same material as the second insulating layer.

30. The display device of claim 29, wherein the second insulating layer and the third insulating layer are formed in the same process.

31. The display device according to claim 21, wherein: In the fourth region, each of the first connector and the second connector includes only the second conductive layer.

32. The display device according to claim 31, wherein: In the fourth region, each of a side surface of the first connector and a side surface of the second connector includes an uneven structure.

33. The display device according to claim 21, wherein: In the first connector, the second conductive layer includes a plurality of holes exposing the first insulating layer.

34. The display device according to claim 33, wherein the plurality of holes constitute a plurality of rows, and among the plurality of rows, the holes in two rows adjacent to each other are arranged to be staggered with each other in a longitudinal direction.

35. The display device of claim 33, wherein the first insulating layer includes a plurality of contact holes, the first conductive layer is connected to the second conductive layer via the plurality of contact holes, and the plurality of contact holes are respectively arranged between the plurality of holes.

Images