Method and storage device for processing read commands and pre-read commands using unified cache

Abstract

The present application provides a method for processing read commands and pre-read commands using a unified cache and a storage device thereof. The disclosed method for a storage device includes: in response to receiving a read command, querying an FTL table through a logical address indicated by the read command, if the query to the FTL table obtains a first FTL entry recording an index of a first cache container; then allocating an idle second cache unit and associating the second cache unit with the first cache container; and, copying the data of the first cache unit associated with the first cache container to the second cache unit; and reading out the data of the second cache unit in response to the read command.

Description

Technical Field

[0001] The present application relates to storage technology, and in particular, to a method for processing read commands and pre-read commands using a unified cache of a storage device and a storage device thereof. Background Art

[0002] Figure 1 The block diagram of the storage device is shown. The storage device 102 is coupled to the host to provide storage capacity for the host. The host and the storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and the storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fiber Channel, wireless communication network, etc. The host can be an information processing device that can communicate with the storage device in the above manner, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data of the DRAM 110. The data of the FTL table and / or cached IO commands can be stored in the DRAM.

[0006] The control component 104 includes a flash memory interface controller (or medium interface controller, flash memory channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that complies with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

[0007] A memory target is one or more logic units (LUNs) within a NAND flash package that share a CE (Chip Enable) signal. A NAND flash package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, and multiple logic units within a NAND flash chip can execute commands and report status independently of each other.

[0008] Data is usually stored and read on a storage medium in pages. Data is erased in blocks. A block (also called a physical block) contains multiple pages. A page on a storage medium (called a physical page) has a fixed size, such as 17664 bytes. A physical page can also have other sizes.

[0009] In the storage device, the FTL (Flash Translation Layer) is used to maintain the mapping information from the logical address to the physical address. The logical address constitutes the storage space of the solid-state storage device perceived by the upper-layer software such as the operating system. The physical address is the address used to access the physical storage unit of the solid-state storage device. In the related art, the address mapping can also be implemented using the intermediate address form. For example, the logical address is mapped to the intermediate address, and then the intermediate address is further mapped to the physical address.

[0010] The table structure that stores the mapping information from logical addresses to physical addresses is called an FTL table. The FTL table is an important metadata in a solid-state storage device. Usually, the data items of the FTL table record the address mapping relationship in units of data pages in the solid-state storage device.

[0011] The FTL of some storage devices is provided by the host coupled to the storage device, the host's memory stores the FTL table, and the host's CPU executes software to provide the FTL. Some storage management devices arranged between the host and the storage device provide the FTL.

[0012] Providing a cache for a storage device to improve the performance of the storage device. For example, Chinese patent applications 201710219077.1, 201710219096.4, and 201710219112.X provide a distributed cache for a solid-state storage device. Chinese patent applications 2018112036939, 2018111542948, 2018112036905, and 2018111541907 provide a unified cache for a storage device. The cache may also be provided by a host or a storage management device. Summary of the invention

[0013] This application aims to improve the FTL, which uniformly manages the address mapping and cache of the storage device, thereby improving the performance of the storage device.

[0014] According to a first aspect of the present application, a first method for a storage device according to the first aspect of the present application is provided, comprising: in response to receiving a read command, querying an FTL table through a logical address indicated by the read command, if the query FTL table obtains a first FTL entry recording an index of a first cache container; then allocating an idle second cache unit, associating the second cache unit with the first cache container; and copying data of the first cache unit associated with the first cache container to the second cache unit; and reading out data of the second cache unit in response to the read command.

[0015] According to the first method for a storage device of the first aspect of the present application, in response to associating the second cache unit with the first cache container, a reference count indicating the number of cache units associated with the first cache container is incremented.

[0016] According to the first or second method for a storage device of the first aspect of the present application, in response to reading out data of the second cache unit, the association between the second cache unit and the first cache container is revoked.

[0017] According to a third method for a storage device according to the first aspect of the present application, in response to revoking the association between the second cache unit and the first cache container, a reference count indicating the number of cache units associated with the first cache container is decremented.

[0018] According to one of the first to fourth methods for a storage device of the first aspect of the present application, in response to revoking the association between the second cache unit and the first cache container, the data of the first cache unit associated with the first cache container is data read from the NVM data frame address through a pre-read command.

[0019] The fifth method for a storage device according to the first aspect of the present application also includes querying the FTL table through the logical address indicated by the pre-read command to obtain a second FTL entry recording the address of the second NVM data frame; allocating an idle third cache unit, and storing the data read from the second NVM data frame address in the third cache unit; allocating an idle second cache container, and associating the third cache unit with the second cache container; and updating the second FTL entry in the FTL table that records the NVM data frame address with the third cache container index.

[0020] According to a sixth method for a storage device according to the first aspect of the present application, in response to updating the second FTL entry, a generated pre-read data message indicating that the third cache unit is associated with the second cache container is added to the pre-read queue.

[0021] According to the seventh method for a storage device according to the first aspect of the present application, it also includes: in response to querying the FTL table according to the received read command to obtain a second FTL entry recording the second cache container index, allocating an idle fourth cache unit, associating the fourth cache unit with the second cache container; and copying the data of the third cache unit associated with the second cache container to the fourth cache unit; reading out the data of the fourth cache unit in response to the read command.

[0022] According to an eighth method for a storage device according to the first aspect of the present application, under specified conditions, a third cache unit accommodating data indicated by a pre-read command is released.

[0023] According to a ninth method for a storage device according to the first aspect of the present application, in response to releasing the third storage unit, a reference count indicating the number of cache units associated with the second cache container is decremented.

[0024] According to a tenth method for a storage device according to the first aspect of the present application, in response to a reference count of the second cache container being 0, the second cache container is released.

[0025] According to an eleventh method for a storage device according to the first aspect of the present application, in response to releasing the second cache container, a second FTL entry recording the second cache container index is updated with the NVM data frame address recorded by the second cache container.

[0026] According to one of the sixth to twelfth methods for a storage device according to the first aspect of the present application, the pre-read command is a read command generated inside the control component.

[0027] One of the first to thirteenth methods for a storage device according to the first aspect of the present application, wherein, in response to receiving a read command, the FTL table is queried by the logical address indicated by the read command, if the third FTL entry recording the NVM data frame address is obtained by querying the FTL table; then an idle fifth cache unit is allocated, and the data read out according to the NVM data frame address recorded in the third FTL entry is stored in the fifth cache unit; the data of the fifth cache unit is read out in response to the read command.

[0028] According to the fourteenth method for a storage device of the first aspect of the present application, a third cache container is allocated, and a fifth cache unit is associated with the third cache container; and a third FTL entry recording an NVM data frame address in an FTL table is updated with an index of the third cache container.

[0029] According to the fifteenth method for a storage device of the first aspect of the present application, the NVM data frame address is recorded in a third cache container, and in response to the fifth cache unit and the third cache container being released, the third FTL entry recording the third cache container index in the FTL table is updated with the NVM data frame address recorded in the third cache container.

[0030] According to one of the first to sixteenth methods for a storage device according to the first aspect of the present application, in response to reading out all data of the second cache unit or the fifth cache unit, a message indicating that the read command is completed is sent to the host.

[0031] According to a seventeenth method for a storage device according to the first aspect of the present application, in response to completion of the read command processing, the second cache unit or the fifth cache unit is released.

[0032] According to the first to eighteenth methods for a storage device of the first aspect of the present application, one of them also includes: in response to data indicated by a write command being written to a sixth cache unit of the cache, adding an elimination message indicating that the sixth cache unit is associated with a sixth cache container of the cache to the tail of the elimination queue; writing the data of the seventh cache unit into the seventh data frame of the NVM chip according to the elimination message at the head of the elimination queue, and updating the seventh entry recording the seventh cache container index in the FTL table with the address of the seventh data frame, wherein the elimination message at the head of the elimination queue indicates that the seventh cache unit is associated with the seventh cache container.

[0033] According to the nineteenth method for a storage device according to the first aspect of the present application, it also includes checking whether the association relationship between the seventh cache unit and the seventh cache container recorded in the elimination message at the head of the elimination queue is valid; if valid, writing the data of the seventh cache unit into the seventh data frame of the NVM chip, and updating the seventh entry recording the seventh cache container index in the FTL table with the address of the seventh data frame.

[0034] According to the nineteenth or twentieth method for a storage device of the first aspect of the present application, it is checked whether the association between the seventh cache unit and the seventh cache container recorded in the elimination message of the head of the elimination queue is valid; if invalid, the elimination message of the head of the elimination queue is discarded, and the data of the seventh cache unit is not written to the NVM chip, and the FTL table is not updated with the address of the seventh data frame.

[0035] According to one of the nineteenth to twenty-first methods for a storage device of the first aspect of the present application, if a first write command and a second write command that are combined together are received, in response to the data indicated by the first write command being written to the eighth cache unit and the data indicated by the second write command being written to the ninth cache unit, a combined elimination message is added to the elimination queue; the combined elimination message indicates that the eighth cache unit is associated with the eighth cache container, and indicates that the ninth cache unit is associated with the ninth cache container.

[0036] The twenty-second method for a storage device according to the first aspect of the present application also includes: writing the data of the tenth cache unit into the fourth data frame of the NVM chip according to the combined elimination message obtained from the elimination queue, and writing the data of the eleventh cache unit into the fifth data frame of the NVM chip, wherein the combined elimination message indicates that the tenth cache unit is associated with the tenth cache container, and indicates that the eleventh cache unit is associated with the eleventh cache container, and wherein the fourth data frame and the fifth data frame have consecutive physical addresses.

[0037] The twenty-third method for a storage device according to the first aspect of the present application also includes: updating the eighth entry in the FTL table recording the index of the tenth cache container with the address of the fourth data frame, and updating the ninth entry in the FTL table recording the index of the eleventh cache container with the address of the fifth data frame.

[0038] The twenty-fourth method for a storage device according to the first aspect of the present application also includes checking whether the association relationship between the tenth cache unit and the tenth cache container and the association relationship between the eleventh cache unit and the eleventh cache container recorded in the combined elimination message obtained from the elimination queue are valid; if the association relationship between the tenth cache unit and the tenth cache container and the association relationship between the eleventh cache unit and the eleventh cache container recorded in the combined elimination message obtained from the elimination queue are both valid, then writing the data of the tenth cache unit into the tenth data frame of the NVM chip, and writing the data of the eleventh cache unit into the eleventh data frame of the NVM chip.

[0039] According to the twenty-fifth method for a storage device of the first aspect of the present application, if one of the association relationships between the tenth cache unit and the tenth cache container and the association relationship between the eleventh cache unit and the eleventh cache container recorded in the combined elimination message obtained from the elimination queue is invalid, the data in the cache unit with a valid association relationship is written into the NVM chip.

[0040] According to the twenty-fifth method for a storage device of the first aspect of the present application, if the association relationship between the tenth cache unit and the tenth cache container and the association relationship between the eleventh cache unit and the eleventh cache container recorded in the combined elimination message obtained from the elimination queue are both invalid, the elimination message is discarded, and the data of the tenth cache unit is not written into the NVM chip, nor is the data of the eleventh cache unit written into the NVM chip.

[0041] According to the second aspect of the present application, a first information processing device according to the second aspect of the present application is provided, comprising a memory, a processor, and a program stored in the memory and executable on the processor, wherein when the processor executes the program, one of the above-mentioned methods for a storage device is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0043] Figure 1 shows a block diagram of a solid-state storage device;

[0044] Figure 2 is a schematic diagram of a storage space managed by an FTL according to an embodiment of the present application;

[0045] Figure 3 is a schematic diagram of a logical address (LBA) space of an embodiment of the present application;

[0046] Figure 4 The FTL table of the embodiment of the present application is shown;

[0047] Figure 5 A schematic diagram showing a cache provided by FTL in an embodiment of the present application is shown;

[0048] Fig. 6A A flowchart of writing data to a storage device according to an embodiment of the present application is shown;

[0049] Figure 6B A flowchart of writing data to a storage device according to another embodiment of the present application is shown;

[0050] Figure 6C A flowchart of reading data from a storage device according to another embodiment of the present application is shown;

[0051] Figure 7 A schematic diagram showing a technical solution for cache elimination according to an embodiment of the present application is shown;

[0052] FIG. 8A to FIG. 8D A schematic diagram of processing a write command according to an embodiment of the present application is shown;

[0053] FIG. 9A to FIG. 9E A schematic diagram of processing a write command according to another embodiment of the present application is shown;

[0054] Fig.10 A schematic diagram showing a technical solution for cache elimination according to another embodiment of the present application is shown;

[0055] FIG. 11A to FIG. 11C A schematic diagram showing a read command according to another embodiment of the present application is shown;

[0056] FIG. 12A to FIG. 12D A schematic diagram showing a pre-read command and a subsequent read command according to another embodiment of the present application is shown;

[0057] FIG. 13A to FIG. 13E A schematic diagram of processing a write command according to yet another embodiment of the present application is shown. DETAILED DESCRIPTION

[0058] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0059] Figure 2 It is a schematic diagram of the storage space managed by the FTL according to an embodiment of the present application.

[0060] According to an embodiment of the present application, the control unit 204 of the storage device 102 provides an FTL. The storage device provides a logical address (called LBA) space to the host. The host uses the logical address to access the storage device. The FTL maps the logical address provided by the host to a physical address.

[0061] According to an embodiment of the present application, the physical address obtained by FTL mapping is partially a physical address for accessing NVM chip 105, and partially a physical address for accessing DRAM 110. Figure 2 , the NVM chip 105 and part of the DRAM 110 provide a storage space 200 managed by the FTL.

[0062] Optionally, in addition to DRAM 110, other types of memory such as SRAM are also used to provide storage space managed by the FTL.

[0063] It can be understood that the FTL according to another embodiment of the present application is provided by a host coupled to the storage device, or by a storage management apparatus arranged between the host and the storage device.

[0064] The FTL is implemented by, for example, software running in the CPU of the control component 204, firmware, and / or hardware as part of an ASIC.

[0065] Figure 3 FIG. 1 is a schematic diagram of a logical address (LBA) space of an embodiment of the present application. As an example, the logical address space is a continuous address space. The FTL maintains the logical address space.

[0066] Figure 3 The direction from top to bottom is the increasing direction of the logical address space. The logical address space includes multiple areas of the same size, each of which is called a small block. Each entry in the FTL table (called an FTL entry) records the mapping of a small block of the logical address space to a physical address. Figure 3, multiple entries of the FTL table are shown, including FTL entry 0, FTL entry 1, ..., FTL entry 5. For example, the size of the logical address space corresponding to each FTL entry may be, for example, 512 bytes, 1KB, or 4KB. The FTL entry is indexed according to the address of the logical address space. For example, the address of the logical address space is divided by the size of the logical address space corresponding to the FTL entry, and the quotient obtained is the index of the FTL entry.

[0067] Figure 4 The FTL table of the embodiment of the present application is shown.

[0068] The FTL table includes a plurality of FTL entries, each of which corresponds to one of the small blocks, and the value of the FTL entry records the NVM data frame address or cache container index that provides storage space for the small block. Optionally, according to the value of the FTL entry, it is identified whether the value indicates the NVM data frame address or the cache container index. For example, the FTL entry value greater than the threshold is mapped to the NVM data frame address, and the FTL entry value not greater than the threshold is mapped to the cache container index. As another example, a flag is recorded in the FTL entry to indicate whether the value of the FTL entry indicates the NVM data frame address or the cache container index.

[0069] The FTL table is stored in, for example, DRAM 110 (see also Figure 2 ) or SRAM. The FTL calculates the index of the corresponding FTL entry according to the accessed logical address, and obtains the NVM data frame or cache container that provides storage space for the small block from the FTL entry.

[0070] The NVM data frame address is, for example, a physical address for accessing a physical page of an NVM chip, a physical address for accessing a plurality of combined physical pages of an NVM chip (a combined physical page is, for example, a physical page with the same physical page number on a plurality of planes of the same logical unit (LUN)), or a physical address for accessing a portion of a data unit within a physical page of an NVM chip. The cache container index is, for example, an address of a cache unit in a DRAM or an address of a descriptor of a cache unit. A cache unit is, for example, a section of storage space in a DRAM or SRAM. A cache unit descriptor is used to describe a cache unit. A cache container is used to record a cache unit descriptor.

[0071] Figure 5 The schematic diagram of the FTL providing cache in the embodiment of the present application is shown. As an example, the FTL maps the logical address space to a portion of one or more NVM chips 105 (represented as NVM chips 510) and a portion of the DRAM 110 (represented as unified cache 520).

[0072] The storage space of NVM chip 510 includes multiple physical blocks. The storage space of NVM chip 510 is organized into NVM data frames (see block 512). Large block 512 includes multiple NVM data frames. The size of the NVM data frame is the same as the size of the small block, so that the data stored in the logical address space corresponding to a small block can be recorded in one NVM data frame.

[0073] Continue to view Figure 5 , the storage space of the unified cache 520 is organized into cache units. A cache unit is, for example, a section of storage space of the unified cache 520. The size of a cache unit is the same as the size of a small block, so that data stored in a logical address space corresponding to a small block can be recorded in one cache unit.

[0074] Return to view Figure 4 The index of the cache container recorded by the value of the FTL entry indicates the cache container. According to the cache container, the cache unit associated with the cache container can be accessed.

[0075] A cache container describes one or more cache units associated with it. A cache unit can be assigned to a cache container, or a cache unit has a specified association with a cache container. For example, a cache container records the cache unit descriptors of one or more cache units associated with the cache container, and the cache unit descriptors record the addresses of the cache units and the working status of the cache units.

[0076] Continue to view Figure 5 The values ​​of FTL entry 0, FTL entry 2, FTL entry 3 and FTL entry 4 indicate the NVM data frame address located in NVM chip 510, and the values ​​of FTL entry 1 and FTL entry 5 indicate the index of the cache container located in unified cache 520. Thus, FTL obtains the FTL entry according to the logical address, and provides the physical address of the storage space for the small block of the logical address space according to the value of the FTL entry.

[0077] Fig. 6A A flow chart of writing data to a storage device according to an embodiment of the present application is shown.

[0078] The storage device obtains a write command provided by the host, the write command indicating a logical address (610). The control component of the storage device queries the FTL table (612) according to the logical address to obtain a physical address corresponding to the logical address.

[0079] Optionally, the write command indicates multiple small blocks of the logical address space, and accordingly, the FTL table is queried according to the logical address of each small block to obtain the corresponding physical address. For the purpose of clarity, in one or more examples below, an embodiment according to the present application is described by taking a write command accessing a single small block as an example.

[0080] Identify whether the obtained physical address corresponding to the logical address indicates a cache container index (614). If the physical address provided by the FTL and the logical address accessed by the write command is a cache container index, then use the cache container index to access the cache unit of the corresponding cache container to carry the data to be written by the write command (616). Optionally, after the data to be written by the write command is written into the cache unit, indicate to the host that issued the write command that the write command has been processed.

[0081] If the physical address corresponding to the logical address accessed by the write command provided by the FTL is not a cache container index (614) (for example, it is an NVM data frame address, or other content), a new cache container is allocated for the logical address (618), and the data to be written by the write command is written into the cache unit of the newly allocated cache container (620). The index of the newly allocated cache container is also recorded in the FTL entry corresponding to the logical address (622).

[0082] According to an embodiment of the present application, optionally, when necessary or periodically, the data stored in the cache unit of the cache container indicated by one or more FTL entries is written to the NVM chip. In response to the data stored in the cache unit being written to the NVM chip, the cache container index in the FTL entry is replaced with the NVM data frame address of the NVM chip. Thus, until the cache container index recorded in the FTL table entry is modified to indicate the physical address of the data unit of the NVM chip, the FTL table entry always records the cache container index, which means that during this period, if a read command or write command accessing these FTL table entries is received, the unified cache will be hit, and the cache unit recorded with the cache container index will be used to respond to the read command or write command.

[0083] Figure 6B A flowchart of writing data to a storage device according to another embodiment of the present application is shown.

[0084] The storage device obtains a write command provided by the host, the write command indicating a logical address (630). The control component of the storage device queries the FTL table (632) according to the logical address to obtain a physical address corresponding to the logical address.

[0085] Identify whether the obtained physical address corresponding to the logical address indicates a cache container index (634). If the physical address of the logical address accessed by the write command provided by the FTL is a cache container index, further identify whether the cache unit of the cache container corresponding to the cache container index is being used (636). The cache unit is being used, for example, data is being written to the cache unit according to other write commands, data is being read from the cache unit, or the control component is writing data of the cache unit to the NVM chip. If the cache unit is not currently in use, use the cache unit to carry the data to be written by the write command (638). If the cache unit is currently in use, allocate a new cache unit for the cache container (640), and use the new cache unit to carry the data to be written by the write command (642).

[0086] If the physical address of the logical address accessed by the write command provided by the FTL is not a cache container index (634) (for example, it is an NVM data frame address, or other content), a new cache container is allocated for the logical address (644), and the data to be written by the write command is written into the cache unit of the newly allocated cache container (646). The index of the newly allocated cache container is also recorded in the FTL entry corresponding to the logical address (648).

[0087] Figure 6C A flow chart of reading data from a storage device according to another embodiment of the present application is shown.

[0088] The storage device obtains a read command provided by the host, the read command indicating a logical address (650). The control component of the storage device queries the FTL table (652) according to the logical address to obtain a physical address corresponding to the logical address.

[0089] Identify whether the obtained physical address corresponding to the logical address indicates a cache container index, an NVM data frame address, or another type of physical address (654). If the physical address provided by the FTL and the logical address accessed by the read command is a cache container index, then access the cache unit of the cache container and obtain data from the cache unit as a response to the read command (656). If the physical address provided by the FTL is an NVM data frame address, then send a read command to the NVM chip to read out the data (658). Optionally, other types of addresses are recorded in the FTL entry, such as indicating that the read logical address has not been written to data, indicating to the host that the read command processing error occurs, or using a specified value (e.g., all 0s) as a response to the read command.

[0090] Figure 7 A schematic diagram of a technical solution for cache elimination according to an embodiment of the present application is shown.

[0091] Storage device control unit (see also Figure 1) includes a host interface 760, a command processing unit 765 and a medium interface 770. The host interface 760, the command processing unit 765 and the medium interface 770 can all be implemented by a CPU, dedicated hardware or a combination thereof.

[0092] The host interface 760 receives a command to access the storage device. The command processing unit 765 obtains the command to be processed from the host interface 760, and instructs the medium interface 770 to generate one or more commands to operate the NVM chip 740 according to the address to be accessed by the command. As an example, the command processing unit 765 accesses the FTL table 750 with the logical address indicated by the obtained command to obtain the physical address corresponding to the logical address, and accesses the NVM chip 740 with the physical address.

[0093] Those skilled in the art can understand that the command received by the host interface 760 may access the logical address space corresponding to one or more FTL entries. And the command processing unit 765 may change the form of the command received from the host interface 760 (for example, split the command according to the size of the logical address space corresponding to the FTL entry) and process the command with the changed form. For the purpose of clarity, the embodiment according to the present application is described by taking the IO command received by the host interface 760 accessing a single FTL entry as an example.

[0094] The entries of FTL table 750 record NVM data frame addresses or cache container indexes. Figure 7 In , FTL entry 1 and FTL entry 5 record the cache container index, and other FTL entries record the NVM data frame address.

[0095] The unified cache 710 includes multiple cache containers. The cache container index recorded in the FTL entry of the FTL table 750 indicates the cache container of the unified cache 710. Figure 7 The cache container index recorded in FTL entry 1 indicates cache container 712 of unified cache 710, and the cache container index recorded in FTL entry 5 indicates cache container 716. Cache container 714 is not indexed by any FTL entry and is an unused free cache container.

[0096] Unified cache 710 also includes multiple cache units. A cache container is associated with one or more cache units. For example, cache container 712 is associated with cache unit 722, cache container 716 is associated with cache unit 726 and cache unit 727, and cache unit 724 is not associated with any cache container and is an unused free cache unit.

[0097] According to an embodiment of the present application, an elimination queue 780 is further included. The elimination queue 780 accommodates elimination messages for the unified cache 710. As an example, in response to the cache unit 727 carrying data to be written to the storage device indicated by the write command, an elimination message 787 is added to the end of the elimination queue 780. The elimination message 787 indicates that the data carried by the cache unit 727 is to be written to the NVM chip 740. Optionally, the elimination message 787 also indicates that the cache unit 727 is associated with the cache container 716.

[0098] Elimination is the process of writing data in the cache unit of the unified cache 710 to the NVM chip. During the elimination process, the data in the cache unit is also assigned an NVM data frame address for the NVM chip, and the data in the cache unit is written to the NVM chip according to the NVM data frame address. The assigned NVM data frame address is also recorded in the entry of the FTL table. Thus, after the elimination process is completed, the FTL entry changes from recording the cache container address to recording the NVM data frame address.

[0099] The elimination message is added to the tail of the elimination queue 780, and the elimination message is taken out from the head of the elimination queue 780, and the data recorded in the cache unit is written to the NVM chip according to the elimination message.

[0100] It takes a while for the elimination message to change from the tail to the head in the elimination queue 780. During this period of time, the data of the cache unit indicated by the elimination message may become invalid (for example, because the cache container corresponding to the cache unit is updated by writing new data to the logical address). For the elimination message taken out from the head of the elimination queue 780, the elimination message taken out is checked by the checking unit 790. The checking unit 790 checks whether the cache unit indicated in the elimination message is currently associated with one of the cache containers, or whether the cache unit currently recorded by the cache container indicated by the elimination message is the same as the cache unit indicated by the elimination message. If the cache unit indicated by the elimination message is not currently recorded or associated with any cache container, the checking unit 790 discards the elimination message and instructs the unified cache 710 to release the cache unit indicated by the elimination message. If the cache unit indicated by the elimination message is currently recorded or associated with a cache container, the checking unit 790 instructs the medium interface 770 to write the data of the cache unit indicated by the elimination message into the NVM chip (for example, write the NVM data frame 742). The FTL entry (eg, FTL entry 2) of the cache container corresponding to the cache unit is also updated by using the NVM data frame address of the NVM data frame 742. The cache container is also released.

[0101] According to an embodiment of the present application, the operation of adding elimination messages to the elimination queue 780 by the unified cache 710 and the operation of taking out elimination messages from the elimination queue by the checking unit 790 are processed in parallel or concurrently. And the ratio of the number of elimination messages added to the elimination queue 780 to the number of elimination messages taken out from the elimination queue 780 can be set. For example, the ratio of the number of elimination messages added to the number of elimination messages taken out is set to be equal to 1, so that the number of elimination messages accommodated in the elimination queue is basically stable. Optionally, the ratio is also adjusted according to the number of elimination messages accommodated in the elimination queue. If there are too many elimination messages in the elimination queue or the growth rate is too fast, the ratio is reduced, otherwise the ratio is increased. Still optionally, within a period of time, only elimination messages are added to the elimination queue without taking out the elimination messages, so as to accommodate a certain number of elimination messages in the elimination queue, and to keep the elimination messages in the elimination queue at a certain number, for example, each time an elimination message is added to the elimination queue, an elimination message is taken out from the elimination queue accordingly.

[0102] Through the cache elimination scheme of the embodiment of the present application, the elimination operation of the unified cache 710 occurs continuously, rather than according to the usage of the cache container or cache unit of the unified cache 710, so that the elimination queue 780 always has space to accommodate the elimination message, so that under the specified IO command load, the unified cache 710 can always provide available cache containers and cache units to respond to write commands. When the command processing unit 765 processes a write command, all write commands (regardless of whether the FTL entry corresponding to the logical address accessed records the cache container index) are processed by the unified cache 710, which shortens the processing delay of the write command, and also makes the processing delay of all or most of the write commands basically consistent, thereby avoiding the jitter of the processing delay of multiple write commands.

[0103] Further, according to an embodiment of the present application, the number of cache containers is limited to meet the hardware resource limitations of the control component of the storage device, and the cache units are provided by, for example, a memory external to the control component, and the number of cache units is greater than the cache containers, thereby further enabling the unified cache to respond to more write commands than the cache capacity at the same time.

[0104] Still further, the write command processing capability of the media interface 770 is known, and the write command bandwidth of the unified cache 710 depends on the processing capability of the media interface 770. Therefore, the command processing unit 765 receives write commands according to the processing capability, and can always obtain an immediate response from the unified cache 710, and makes the processing delay of the storage device for all write commands basically consistent, thereby reducing the volatility of the processing delay and improving the service quality.

[0105] FIG. 8A to FIG. 8D A schematic diagram of processing a write command according to an embodiment of the present application is shown.

[0106] See also Fig. 8A , the command processing unit 865 receives a write command from the host interface 860. The command processing unit 865 accesses the FTL table 850 according to the logical address indicated by the write command. As an example, the logical address of the write command indexes FTL entry 2. FTL entry 2 records the NVM data frame address, which means that the write command does not hit any cache container of the unified cache 810. Cache container 812 and cache container 814 of the unified cache 810 are being used, and they are respectively associated with cache unit 822 and cache unit 824.

[0107] See also Figure 8B In response to a write command not hitting any cache container of the unified cache 810, an idle cache container 816 is allocated to it, and an idle cache unit 826 is allocated. The cache container 816 is associated with the cache unit 826, for example, the index of the cache unit 826 is recorded in the cache container 816. The data to be written to the storage device by the write command is moved to the cache unit 826 through the host interface 860, and the NVM data frame address recorded in the FTL entry 2 is updated to indicate the cache container index of the cache container 816. And optionally, the cache container 816 also records its reference count as 1 to indicate the number of cache units associated with it. At this point, the host is indicated that the write command processing is completed.

[0108] Furthermore, a elimination message 887 is added to the elimination queue 880 , and the added elimination message 887 indicates the cache unit 826 and the cache container 816 associated therewith.

[0109] Continue to view Figure 8C After a period of time, the elimination message 887 becomes the head of the elimination queue. The checking unit 890 takes out the elimination message 887 from the head of the elimination queue 880, and checks whether the association between the cache container 816 and the cache unit 826 recorded in the elimination message 887 is still valid. As an example, the checking unit 890 accesses the cache container 816, and recognizes that the cache unit currently recorded by the cache container 816 is still the cache unit 826, thereby recognizing that the association between the cache container 816 and the cache unit 826 recorded by the elimination message 887 is still valid. Based on this, the checking unit 890 instructs the medium interface 870 to write the data recorded in the cache unit 826 into the NVM chip 840. As an example, the data frame 842 of the NVM chip 840 is allocated to the data of the cache unit 826.

[0110] Continue to view Fig.8DIn response to the data of cache unit 826 being written into NVM data frame 842, FTL entry 2 is updated, and the NVM data frame address of NVM data frame 842 is recorded in FTL entry 2. And cache unit 826 is released, so that cache unit 826 can be allocated to other write commands or other cache containers. And in response to cache unit 826 being released, the reference count of cache container 816 originally associated with cache unit 826 is decremented, and the new reference count obtained is 0. The FTL entry 2 no longer indexes cache container 816, the reference count of cache container 816 is 0, and cache container 816 is released. The released cache container 816 can be allocated to other write commands or other cache containers.

[0111] FIG. 9A to FIG. 9E A schematic diagram of processing a write command according to another embodiment of the present application is shown.

[0112] See also Fig. 9A , the command processing unit 965 receives a write command from the host interface 960. The command processing unit 965 accesses the FTL table 950 according to the logical address indicated by the write command. As an example, the logical address of the write command indexes FTL entry 1. FTL entry 1 records the cache container index, which means that the write command hits the cache container 912 of the unified cache 910. The cache container 912 of the unified cache 910 is associated with the cache unit 922. The elimination message 982 for the cache unit 922 is already in the elimination queue 980. The elimination message 982 indicates that the cache unit 922 is associated with the cache container 912. The reference count of the cache container 912 is 1, and the cache unit 922 references the cache container 912.

[0113] See also Fig. 9B In response to the write command hitting the cache container 912 of the unified cache 910, an idle cache unit 926 is allocated to the cache container 912. The cache container 912 is associated with the cache unit 926, for example, the index of the cache unit 926 is recorded in the cache container 912. The data to be written to the storage device by the write command is moved to the cache unit 926 through the host interface 960. And the reference of the cache container 912 is incremented to 2 to indicate that there are two cache units (922 and 926). At this point, the host is indicated that the write command processing is completed.

[0114] Furthermore, a elimination message 984 is added to the elimination queue 980, and the added elimination message 984 indicates the cache unit 926 and the cache container 912 associated therewith. Since the FTL entry 1 still records the index of the cache container 912, there is no need to update the FTL entry 1.

[0115] According to an embodiment of the present application, in response to a write command hitting a cache container, an idle cache unit (eg, cache unit 926, see Fig. 9B) is used to carry the data to be written by the write command, while the data of other cache units (for example, cache unit 922) of the hit cache container are not updated, so that the access to the other cache units is not affected, and the data transmission of the read command or write command being processed by the cache unit does not need to be interrupted.

[0116] Continue to view Fig. 9C After a period of time, the elimination message 982 becomes the head of the elimination queue. The checking unit 990 takes out the elimination message 982 from the head of the elimination queue 980 and checks whether the association between the cache container 912 and the cache unit 922 recorded in the elimination message 982 is still valid. Fig. 9C In the example, the inspection unit 990 accesses the cache container 912, identifies that the cache unit currently recorded by the cache container 912 is the cache unit 926 rather than the cache unit 922 indicated by the elimination message 982, and thereby identifies that the association between the cache container 912 recorded by the elimination message 982 and the cache unit 922 has expired. Accordingly, the inspection unit 990 discards the elimination message 982 and does not write the data contained in the cache unit 922 indicated by the elimination message 982 to the NVM chip. And the inspection unit 990 also releases the cache unit 922 so that the cache unit 922 can be allocated to other cache containers. Further, in response to the cache unit 922 being released, the cache units that reference the cache container 912 are reduced, so that the reference count of the cache container 912 is decremented to 1.

[0117] Continue to view Fig.9D After a period of time, the elimination message 984 becomes the head of the elimination queue 980. The checking unit 990 takes out the elimination message 984 from the head of the elimination queue 980 and checks whether the association between the cache container 912 and the cache unit 926 recorded in the elimination message 984 is still valid. Fig.9D In the example, the inspection unit 990 accesses the cache container 912 and identifies that the cache unit currently recorded in the cache container 912 is the cache unit 926, thereby identifying that the association relationship between the cache container 912 and the cache unit 926 recorded in the elimination message 982 is valid. Accordingly, the inspection unit 990 instructs the medium interface 970 to write the data recorded in the cache unit 926 into the NVM chip 940. As an example, the data of the cache unit 926 is allocated with the data frame 942 of the NVM chip 940.

[0118] Continue to view Fig.9EIn response to the data of cache unit 926 being written into NVM data frame 942, FTL entry 1 is updated, and the NVM data frame address of NVM data frame 942 is recorded in FTL entry 1. And cache unit 926 is released, so that cache unit 926 can be allocated to other write commands or other cache containers. And in response to cache unit 926 being released, the reference count of cache container 912 originally associated with cache unit 926 is decremented, and the new reference count obtained is 0. The impact is that FTL entry 1 no longer indexes cache container 912, and no other FTL entry references cache container 912. The reference count of cache container 912 is 0, thereby releasing cache container 912. The released cache container 912 can be allocated to other write commands or other cache containers.

[0119] Fig.10 A schematic diagram of a cache elimination technical solution according to another embodiment of the present application is shown.

[0120] Storage device control unit (see also Figure 7 ) includes a host interface 760, a command processing unit 765 and a medium interface 770.

[0121] The unified cache 1010 includes a plurality of cache containers (1012, 1014, and 1016). Fig.10 The cache container index recorded in FTL entry 1 indicates cache container 1012 of unified cache 1010, and the cache container index recorded in FTL entry 5 indicates cache container 1016. Cache container 1014 is not indexed by any FTL entry and is an unused free cache container.

[0122] The unified cache 1010 includes a plurality of cache units. For example, the cache container 1012 is associated with the cache unit 1022, the cache container 1016 is associated with the cache unit 1026 and the cache unit 1027, and the cache unit 1024 is not associated with any cache container and is an unused free cache unit.

[0123] according to Fig.10The embodiment includes an elimination queue 1080, a pre-read queue 1082 and a hot data queue 1084. The elimination queue 1080 accommodates elimination messages for the unified cache 1010. The data accommodated by some cache units are hot data. Hot data is data that is likely to be accessed again in the near future, so it is desired to retain the hot data in the unified cache 1010. In response to writing hot data into a cache unit (e.g., cache unit 1024), in addition to associating the cache unit 1024 with one of the cache containers, the elimination message for the cache unit 1024 is not added to the elimination queue 1080, but is added to the hot data queue 1084. Therefore, what is carried in the hot data queue 1084 is the elimination message for the hot data. The inspection unit 1090 obtains the elimination message from the elimination queue 1080 and the hot data queue 1084 with different strategies. For example, the inspection unit 1090 obtains the elimination message from the elimination queue 1080 and the hot data queue 1084 respectively in a ratio of N:1, where N is a natural number much greater than 1. Thus, the hot data is retained in the cache unit for a longer time. For the elimination message taken out from the hot data queue 1084, the checking unit 1090 processes it in the same way as the elimination message obtained from the elimination queue. Still optionally, under normal circumstances, the checking unit only obtains the elimination message from the elimination queue 1080, but not from the hot data queue 1084, and only obtains the elimination message from the hot data queue 1084 under specified conditions (for example, receiving an instruction from the host, the storage device is powered off, or the number of elimination messages in the hot data queue is greater than a threshold).

[0124] Continue to view Fig.10 , the data contained in some cache units are not write commands from the host, but commands initiated by the control component to read data from the NVM chip, for example, commands to read data generated by the control component in a pre-fetch operation or a garbage collection operation. The data contained in these cache units are called pre-read data. The pre-read data does not need to be written into the NVM chip. Therefore, there is no need to perform an elimination process on the pre-read data. In response to writing the pre-read data into the cache unit, a pre-read data message is generated, and the pre-read data message is added to the pre-read queue 1082. As an example, the pre-read data message has the same structure or content as the elimination message. The inspection unit 1090 does not obtain the pre-read data message from the pre-read queue 1082. In some cases, the cache unit storing the pre-read data is released. For example, the pre-read data message is obtained from the pre-read queue 1082, and the cache unit storing the pre-read data is obtained according to the pre-read data message, and released. For example, in response to estimating that the pre-read data is no longer used, the storage device is powered off, etc., the cache unit storing the pre-read data is released.

[0125] It is understandable that, since the messages in the pre-read queue 1082 do not need to be taken out in order, the pre-read queue 1082 can be implemented with other data structures, such as arrays, linked lists, stacks, etc. It is still understandable that other data structures can be used to store eliminated messages.

[0126] Still optionally, other numbers or types of queues are provided to accommodate elimination messages corresponding to cache units being filled with data. The inspection unit 1090 provides different processing strategies for different queues. For example, the data filled into the cache unit is accompanied by a flow identifier, and a queue is selected according to the flow identifier, so that the elimination messages corresponding to the cache units carrying data from different flows are added to different queues. Still optionally, one or more flows are bound to one of the queues, and the other one or more flows are bound to another queue.

[0127] FIG. 11A to FIG. 11C A schematic diagram of a read command according to another embodiment of the present application is shown.

[0128] See also Fig.11A , the command processing unit 1165 receives a read command from the host interface 1160. The command processing unit 1165 accesses the FTL table 1150 according to the logical address indicated by the read command. As an example, the logical address of the read command indexes FTL entry 1. FTL entry 1 records the cache container index, which means that the read command hits the cache container 1112 of the unified cache 1110. The cache container 1112 of the unified cache 1110 is associated with the cache unit 1122. The reference count value of the current cache container 1112 is 1, and the cache unit 1122 references the cache container 1112.

[0129] See also Fig. 11B In response to a read command hitting the cache container 1112 of the unified cache 1110, although the cache unit 1122 associated with the cache container 1112 stores data that can respond to the read command, according to an embodiment of the present application, the cache unit 1122 is not used to directly respond to the read command, but an idle cache unit 1126 is allocated for the read command. The data of the cache unit 1122 is copied to the cache unit 1126. During the data copying, the reference count of the cache container 1112 is 2, indicating that the cache unit 1122 and the cache unit 1126 both reference the cache container 1112.

[0130] Continue to view Fig. 11CAfter the data of cache unit 1122 is copied to cache unit 1126, the data of cache unit 1126 is transmitted to the host through host interface 1160 as a response to the read command. And cache container 1112 is no longer associated with cache unit 1126, but is still associated with cache unit 1122, and the reference count of cache container 1112 becomes 1. In response to the data of cache unit 1126 being transmitted to the host, the host is indicated that the read command processing is completed, and cache unit 1126 is also released.

[0131] The cache unit 1126 is used to transmit data to the host, so that the response process to the read command does not affect other processing of the cache unit 1122. In the process of using the cache unit 1126 to respond to the read command, the cache unit 1122 can be eliminated or updated. And if multiple read commands continue to hit the cache container 1112, a new cache unit is allocated for each read command, and the data of the cache unit 1122 is copied to the new cache unit. This process also prevents the reference count of the cache container from becoming zero, so that the cache unit 1122 will not be used and can continue to respond to the read command.

[0132] According to one embodiment of the present application, if the command processing unit obtains an FTL entry that records the NVM data frame address based on the logical address of the received read command, it means that the read command does not hit any cache container. The command processing unit instructs the media interface to read data from the NVM chip based on the NVM data frame address recorded in the FTL entry. Optionally, an available cache unit is also allocated to the read command to accommodate the data read from the NVM chip. However, the allocated cache unit is not associated with any cache container. In response to providing the data in the cache unit to the host through the host interface, the cache unit is released.

[0133] According to an embodiment of the present application, if the read command does not hit any cache container, the media interface is instructed to read data from the NVM chip according to the NVM data frame address recorded in the FTL entry. And a cache unit and an associated cache container are allocated, the cache unit is used to carry the data read from the NVM chip, and the data in the cache unit is provided to the host, and the FTL table is also updated with the allocated cache container index. The address of the NVM data frame is recorded in the cache container. And in response to the cache container and the cache unit being released, the FTL table is updated again with the NVM data frame address recorded in the cache container.

[0134] FIG. 12A to FIG. 12D A schematic diagram showing a pre-read command and a subsequent read command according to yet another embodiment of the present application is shown.

[0135] See also Fig. 12A, the command processing unit 1265 processes the pre-read command. The pre-read command is not initiated by the host, but by the control unit of the storage device itself. As an example, the command processing unit 1265 accesses the FTL table 1250 with the logical address indicated by the pre-read command. The logical address of the pre-read command indexes FTL entry 2. FTL entry 2 records the NVM data frame address indicating the NVM data frame 1242. According to the NVM data frame address recorded by FTL entry 2, data is read from the NVM chip 1240. An idle cache unit 1224 is allocated in the unified cache 1210 to carry the data read from the NVM data frame 1242.

[0136] See also Fig. 12B , allocate an idle cache container 1214, associate the cache unit 1224 with the cache container 1214. And record the cache container index of the cache container 1214 in the FTL entry 2. Optionally, a pre-read data message is also generated and added to the pre-read queue 1282. The pre-read data message indicates that the cache unit 1224 is associated with the cache container 1214.

[0137] The pre-read queue 1282 records the cache units used to accommodate the pre-read data and the cache containers associated therewith. The cache units accommodating the pre-read data do not need to be eliminated.

[0138] Optionally, the cache container 1214 used for processing the pre-read command also records the NVM data frame address accessed by the pre-read command. In response to the cache container 1214 being released, the NVM data frame address recorded by the cache container 1214 is recorded in the FTL entry recording the index of the cache container 1214.

[0139] Continue to view Fig. 12C , the command processing unit 1265 receives a read command from the host interface 1260. The FTL table 1250 is accessed according to the logical address of the read command to obtain FTL entry 2. Currently, FTL entry 2 records the cache container index of cache container 1214, which means that the read command hits cache container 1214. The cache unit 1224 associated with cache container 1214 records the data previously read by the pre-read command. In response to the read command hitting cache container 1214, an idle cache unit 1226 is allocated for the read command. The data of cache unit 1224 is copied to cache unit 1226. In response to the start of data copying, the reference count of cache container 1214 is incremented.

[0140] Continue to view Fig.12D After the data of the cache unit 1224 is copied to the cache unit 1226, the data of the cache unit 1226 is transmitted to the host through the host interface 1260 as a response to the read command. And the reference count of the cache container 1214 is decremented.

[0141] Optionally, after a period of time, the cache unit 1224 accommodating the pre-read data is released. And in response, the reference count of the cache container 1214 is incremented. When the reference count of the cache container 1214 is 0, the cache container 1214 is released. And the FTL entry 2 is also updated with the NVM data frame address recorded by the cache container 1214.

[0142] FIG. 13A to FIG. 13E A schematic diagram of processing a write command according to yet another embodiment of the present application is shown.

[0143] See also Fig.13A , the command processing unit 1365 receives two write commands combined together from the host interface 1360. The command processing unit 1365 accesses the FTL table 1350 according to the logical address indicated by each of the two write commands. As an example, the logical addresses of the two write commands index FTL entry 1 and FTL entry 2 respectively. FTL entry 1 records the cache container index of cache container 1312, which means that the write command hits the cache container 1312 of the unified cache 1310. Cache container 1312 is associated with cache unit 1322. FTL entry 2 records the NVM data frame address, which means that the other write command does not hit the cache container index.

[0144] See also Fig. 13B In response to the write command hitting the cache container 1312, an idle cache unit 1223 is allocated to the cache container 1312. The cache container 1312 is associated with the cache unit 1223. The data to be written to the storage device by the write command is moved to the cache unit 1323 through the host interface 1360.

[0145] For the other write command accessing FTL entry 2, a free cache unit 1326 and a free cache container index 1316 are allocated, cache container 1316 is associated with cache unit 1326, and the data to be written to the storage device by the other write command is moved to cache unit 1326 through host interface 1360. The cache container index of cache container 1316 is also recorded in FTL entry 2.

[0146] Furthermore, a elimination message 1387 is added to the elimination queue 1380 , and the added elimination message 1387 indicates the cache unit 1323 and the cache container 1312 associated therewith, and also indicates the cache unit 1326 and the cache unit 1316 associated therewith.

[0147] See also Fig. 13B There is also an elimination message 1382 in the elimination message queue 1380, which indicates the cache unit 1322 and the cache container 1312 associated therewith.

[0148] Continue to view Fig. 13CAfter a period of time, the elimination message 1382 becomes the head of the elimination queue. The checking unit 1390 takes out the elimination message 1382 from the head of the elimination queue 1380 and checks whether the association between the cache container 1312 and the cache unit 1322 recorded in the elimination message 1382 is still valid. Fig. 13C In the example of FIG. 1 , the checking unit identifies that the association between the cache container 1312 and the cache unit 1322 recorded in the elimination message 1382 has expired. Accordingly, the checking unit 1390 discards the elimination message 1382 and does not write the data contained in the cache unit 1322 indicated by the elimination message 1382 into the NVM chip. And the checking unit 1390 also releases the cache unit 1322.

[0149] Continue to view Fig.13D After a period of time, the elimination message 1387 becomes the head of the elimination queue 1380. The checking unit 1390 takes the elimination message 1387 from the head of the elimination queue 1380 and checks whether the association between the cache container 1316 and the cache unit 1326 recorded in the elimination message 1387 is still valid, and whether the association between the cache container 1312 and the cache unit 1323 is still valid. Fig.13D In the example of , the inspection unit 1390 identifies that the association relationship between the cache container 1316 and the cache unit 1326, and the association relationship between the cache container 1312 and the cache unit 1323, are currently valid. Accordingly, the inspection unit 1390 instructs the medium interface 1370 to write the data recorded in the cache unit 1323 in the cache unit 1326 into the NVM chip 1340. As an example, the data frame 1342 of the NVM chip 1340 is allocated to the data of the cache unit 1326, and the data frame 1344 of the NVM chip 1340 is allocated to the data of the cache unit 1323, wherein the NVM data frame 1342 and the NVM data frame 1344 have consecutive addresses, and the data of the NVM data frame 1342 and the NVM data frame 1344 can be read out using a single read command.

[0150] Continue to view Fig.13E In response to the data of cache unit 1326 being written into NVM data frame 1342, FTL entry 1 is updated, and the NVM data frame address of NVM data frame 1342 is recorded in FTL entry 1. And cache unit 1326 is released. And in response to cache unit 1326 being released, cache container 1316 originally associated with cache unit 1326 is also released. In response to the data of cache unit 1323 being written into NVM data frame 1344, FTL entry 2 is updated, and the NVM data frame address of NVM data frame 1344 is recorded in FTL entry 2. And cache unit 1323 and cache container 1312 are also released.

[0151] According to an embodiment of the present application, a storage device is also provided to execute any one of the processing methods provided in the embodiments of the present application.

[0152] According to an embodiment of the present application, there is also provided a program stored on a readable medium, which, when executed by a controller of a storage device, enables the storage device to execute any one of the processing methods provided according to the embodiment of the present application.

[0153] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application. Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for storing a device, comprising: In response to receiving a read command, querying the FTL table through the logical address indicated by the read command, if the first FTL entry recording the first cache container index is obtained by querying the FTL table; Then, an idle second cache unit is allocated, and the second cache unit is associated with the first cache container; In response to associating the second cache unit with the first cache container, incrementing a reference count indicating a number of cache units associated with the first cache container; Furthermore, data of the first cache unit associated with the first cache container is copied to the second cache unit, a reference count of the first cache container is incremented, and both the first cache unit and the second cache unit reference the first cache container; The data in the second cache unit is read out in response to the read command.

2. The method for storing a device according to claim 1, wherein: In response to reading the data of the second cache unit, the association between the second cache unit and the first cache container is cancelled.

3. The method for storing a device according to claim 2, wherein: In response to revoking the association between the second cache unit and the first cache container, a reference count indicating the number of cache units associated with the first cache container is decremented.

4. The method for storing a device according to claim 3, wherein: In response to canceling the association between the second cache unit and the first cache container, the data of the first cache unit associated with the first cache container is the data read from the NVM data frame address through the pre-read command.

5. The method for a storage device according to claim 4, further comprising, in response to receiving a pre-read command, querying the FTL table through the logical address indicated by the pre-read command to obtain a second FTL entry recording an address of a second NVM data frame; Allocating an idle third cache unit, and storing the data read from the second NVM data frame address in the third cache unit; Allocating an idle second cache container and associating the third cache unit with the second cache container; The second FTL entry in the FTL table that records the address of the NVM data frame is updated with the third cache container index.

6. The method for storing a device according to claim 5, wherein: In response to updating the second FTL entry, the generated pre-read data message indicating that the third cache unit is associated with the second cache container is added to the pre-read queue.

7. The method for storing a device according to claim 6, further comprising: In response to querying the FTL table according to the received read command to obtain a second FTL entry recording the second cache container index, Then, an idle fourth cache unit is allocated, and the fourth cache unit is associated with the second cache container; And, copying the data of the third cache unit associated with the second cache container to the fourth cache unit; The data of the fourth cache unit is read out in response to the read command.

8. The method for storing a device according to claim 7, wherein: Under a specified condition, a third cache unit accommodating the data indicated by the pre-read command is released.

9. The method for storing a device according to claim 8, wherein: In response to releasing the third storage unit, a reference count indicating the number of cache units associated with the second cache container is decremented.

10. The method for storing a device according to claim 9, wherein: In response to the reference count of the second cache container being 0, the second cache container is released.

11. The method for storing a device according to claim 10, wherein: In response to releasing the second cache container, a second FTL entry recording the second cache container index is updated with the NVM data frame address recorded by the second cache container.

12. The method for storing a device according to any one of claims 5 to 11, wherein: The pre-read command is a read command generated inside the control unit.

13. The method for storing a device according to any one of claims 1 to 11, wherein: In response to receiving a read command, querying the FTL table through the logical address indicated by the read command, if the querying FTL table obtains a third FTL entry recording the address of the NVM data frame; Then, an idle fifth cache unit is allocated, and the data read out according to the NVM data frame address recorded in the third FTL entry is stored in the fifth cache unit; The data of the fifth cache unit is read out in response to the read command.

14. The method for storing a device according to claim 13, wherein: Allocating a third cache container, and associating the fifth cache unit with the third cache container; A third FTL entry in the FTL table that records the address of the NVM data frame is updated with the index of the third cache container.

15. The method for storing a device according to claim 14, wherein: The NVM data frame address is recorded in the third cache container, and in response to the fifth cache unit and the third cache container being released, a third FTL entry recording the third cache container index in the FTL table is updated with the NVM data frame address recorded in the third cache container.

16. The method for storing a device according to claim 13, wherein: In response to reading out all the data of the second cache unit or the fifth cache unit, a message indicating completion of the read command is sent to the host.

17. The method for storing a device according to claim 16, wherein: In response to the read command processing being completed, the second cache unit or the fifth cache unit is released.

18. The method for storing a device according to any one of claims 1 to 11, further comprising: In response to data indicated by the write command being written to a sixth cache unit of the cache, adding an elimination message indicating that the sixth cache unit is associated with a sixth cache container of the cache to the tail of the elimination queue; According to the elimination message of the elimination queue head, the data of the seventh cache unit is written into the seventh data frame of the NVM chip, and the seventh FTL entry recording the seventh cache container index in the FTL table is updated with the address of the seventh data frame, wherein the elimination message of the elimination queue head indicates that the seventh cache unit is associated with the seventh cache container.

19. The method for storing a device according to claim 18, further comprising: Check whether the association between the seventh cache unit and the seventh cache container recorded in the elimination message at the head of the elimination queue is valid. If valid, write the data of the seventh cache unit into the seventh data frame of the NVM chip, and use the address of the seventh data frame to update the seventh FTL entry recording the seventh cache container index in the FTL table.

20. The method for storing a device according to claim 18, wherein: Check whether the association between the seventh cache unit and the seventh cache container recorded in the elimination message at the head of the elimination queue is valid. If invalid, discard the elimination message at the head of the elimination queue, do not write the data of the seventh cache unit into the NVM chip, and do not update the FTL table with the address of the seventh data frame.

21. The method for storing a device according to claim 18, wherein: If a first write command and a second write command that are combined together are received, in response to the data indicated by the first write command being written into the eighth cache unit and the data indicated by the second write command being written into the ninth cache unit, adding a combined elimination message to the elimination queue; The combined elimination message indicates that the eighth cache unit is associated with the eighth cache container, and indicates that the ninth cache unit is associated with the ninth cache container.

22. The method for storing a device according to claim 21, further comprising: The data of the tenth cache unit is written into the fourth data frame of the NVM chip, and the data of the eleventh cache unit is written into the fifth data frame of the NVM chip according to the combined elimination message obtained from the elimination queue, wherein the combined elimination message indicates that the tenth cache unit is associated with the tenth cache container, and indicates that the eleventh cache unit is associated with the eleventh cache container, and wherein the fourth data frame and the fifth data frame have consecutive physical addresses.

23. The method for storing a device according to claim 22, further comprising: The eighth entry in the FTL table recording the index of the tenth cache container is updated with the address of the fourth data frame, and the ninth entry in the FTL table recording the index of the eleventh cache container is updated with the address of the fifth data frame.

24. The method for a storage device according to claim 21, further comprising: checking whether the association relationship between the tenth cache unit and the tenth cache container and the association relationship between the eleventh cache unit and the eleventh cache container recorded in the combined elimination message obtained from the elimination queue are valid; If the association relationship between the tenth cache unit and the tenth cache container and the association relationship between the eleventh cache unit and the eleventh cache container recorded in the combined elimination message obtained from the elimination queue are both valid, the data of the tenth cache unit is written into the tenth data frame of the NVM chip, and the data of the eleventh cache unit is written into the eleventh data frame of the NVM chip.

25. The method for storing a device according to claim 24, wherein: If one of the associations between the tenth cache unit and the tenth cache container and the association between the eleventh cache unit and the eleventh cache container recorded in the combined elimination message obtained from the elimination queue is invalid, the data in the cache unit with a valid association is written into the NVM chip.

26. The method for storing a device according to claim 24, wherein: If the association relationship between the tenth cache unit and the tenth cache container and the association relationship between the eleventh cache unit and the eleventh cache container recorded in the combined elimination message obtained from the elimination queue are both invalid, the elimination message is discarded, and the data of the tenth cache unit is not written into the NVM chip, nor is the data of the eleventh cache unit written into the NVM chip.

27. An information processing device, comprising a memory, a processor, and a program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the method for a storage device according to any one of claims 1 to 26 is implemented.

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