Pixel driving circuit, pixel structure and display panel

Abstract

The present invention relates to the field of display technology, and proposes a pixel driving circuit, a pixel structure and a display panel. The pixel driving circuit includes a plurality of driving transistors, each of which has a first end connected to a first power supply end, a second end connected to a first node, and a control end connected to a second node, and is used to input current to the first node under the action of a second node voltage. The pixel driving circuit can be applied to a low pixel density area of ​​a display panel, thereby avoiding a brightness difference between a low pixel density area and a high pixel density area.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel driving circuit, a pixel structure and a display panel. Background Art

[0002] In the related art, in order to realize the full-screen design of display devices such as mobile phones, the camera of display devices such as mobile phones is usually hidden in the display area of ​​the display panel. The display area where the camera is hidden needs to have its pixel density set to be smaller than the pixel density of the normal display area to improve its light transmittance, so as to facilitate the camera to collect light from the object to be photographed.

[0003] However, since the low pixel density area where the camera is hidden and the high pixel density area for normal display have different pixel densities, the high pixel density area and the low pixel density area will have different display brightness when the display panel displays the picture.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the invention

[0005] The object of the present invention is to provide a pixel driving circuit, a pixel structure and a display panel. The display panel can solve the technical problem of uneven brightness distribution of the display panel in the related art.

[0006] Other features and advantages of the present invention will become apparent from the following detailed description, or may be learned in part by practice of the present invention.

[0007] According to one aspect of the present invention, there is provided a pixel driving circuit, which includes a plurality of driving transistors, wherein a first end of each driving transistor is connected to a first power supply end, a second end is connected to a first node, and a control end is connected to a second node, and is used to input current to the first node under the action of a second node voltage.

[0008] In an exemplary embodiment of the present invention, the pixel driving circuit further includes: a first switching circuit, a data writing circuit, a compensation circuit, a second switching circuit, a storage circuit, a first reset circuit, a second reset circuit, and a light emitting unit. The first switch circuit is connected to the first power supply terminal, the first terminal of each driving transistor, and the enable signal terminal, and is used to respond to the signal of the enable signal terminal to conduct the first power supply terminal and the first terminal of each driving transistor; the data write circuit is connected to the first terminal of each driving transistor, the data signal terminal, and the gate signal terminal, and is used to respond to the signal of the gate signal terminal to transmit the signal of the data signal terminal to the first terminal of each driving transistor; the compensation circuit is connected to the first node, the second node, and the gate signal terminal, and is used to respond to the signal of the gate signal terminal to conduct the first node and the second node; the second switch circuit is connected to the first node, the enable signal terminal, and the third node, and is used to respond to the signal of the enable signal terminal to transmit the signal of the second node to the third node; the storage circuit is connected between the second node and the first power supply terminal, and is used to store the voltage of the second node; the first reset circuit is connected to the second node, the initial signal terminal, and the reset signal terminal, and is used to respond to the signal of the reset signal terminal to transmit the signal of the initial signal terminal to the second node; the second reset circuit is connected to the third node, the initial signal terminal, and the reset signal terminal, and is used to respond to the signal of the reset signal terminal to transmit the signal of the initial signal terminal to the third node; the light-emitting unit is connected between the third node and the second power supply terminal.

[0009] In an exemplary embodiment of the present invention, the first switch circuit includes a first transistor, the first end of the first transistor is connected to the first power supply terminal, the second end is connected to the first end of each of the driving transistors, and the control end is connected to the enable signal terminal; the data write circuit includes a second transistor, the first end of the second transistor is connected to the data signal terminal, the second end is connected to the first end of each of the driving transistors, and the control end is connected to the gate signal terminal; the compensation circuit includes a third transistor, the first end of the third transistor is connected to the first node, the second end is connected to the second node, and the control end is connected to the gate signal terminal; the second switch circuit includes a fourth transistor, the first end of the fourth transistor is connected to the first node, the second end is connected to the third node, and the control end is connected to the enable signal terminal; the storage circuit includes a capacitor, and the capacitor is connected between the second node and the first power supply terminal; the first reset circuit includes a fifth transistor, the first end of the fifth transistor is connected to the second node, the second end is connected to the initial signal terminal, and the control end is connected to the reset signal terminal; the second reset circuit includes a sixth transistor, the first end of the sixth transistor is connected to the third node, the second end is connected to the initial signal terminal, and the control end is connected to the reset signal terminal; the light-emitting unit includes a light-emitting diode, and the light-emitting diode is connected between the third node and the second power supply terminal.

[0010] In an exemplary embodiment of the present invention, the pixel driving circuit further includes a seventh transistor, an eighth transistor, a capacitor, and a light-emitting unit. The first end of the seventh transistor is connected to the data signal end, the second end is connected to the second node, and the control end is connected to the first gate signal end; the first end of the eighth transistor is connected to the sensing signal end, the second end is connected to the first node, and the control end is connected to the second gate signal end; the capacitor is connected between the first node and the second node; and the light-emitting unit is connected between the first node and the second power supply end.

[0011] According to one aspect of the present invention, a pixel structure is provided. The pixel structure includes the above-mentioned pixel driving circuit.

[0012] In an exemplary embodiment of the present invention, the pixel driving circuit includes a capacitor; each of the driving transistors includes a gate portion, and a plurality of the gate portions together form an electrode of the capacitor.

[0013] In an exemplary embodiment of the present invention, the pixel structure includes a gate layer, a source-drain layer, and a conductive layer located between the gate layer and the source-drain layer, and a portion of the conductive layer forms another electrode of the capacitor.

[0014] In an exemplary embodiment of the present invention, the pixel structure comprises a data line extending along a first direction; a plurality of driving transistors are sequentially arranged in parallel along the first direction.

[0015] According to one aspect of the present invention, there is provided a display panel, comprising a low pixel density area and a high pixel density area, wherein the low pixel density area is provided with the above-mentioned pixel driving circuit.

[0016] In an exemplary embodiment of the present invention, the display area of ​​the display panel includes a pixel density of the high pixel density area, which is n times the pixel density of the low pixel density area, and the pixel driving circuit in the high pixel density area has the same architecture as the pixel driving circuit in the low pixel density area; the pixel driving circuit in the high pixel density area includes m driving transistors, and the pixel driving circuit in the low pixel density area includes n driving transistors. 2 m driving transistors; in the high pixel density area, the capacitance value of the capacitor in the pixel driving circuit is p, and in the low pixel density area, the capacitance value of the capacitor in the pixel driving circuit is n 2 p; and, the sizes of the driving transistors in the high pixel density area and the low pixel density area are the same.

[0017] In an exemplary embodiment of the present invention, in the high pixel density area, the pixel driving circuit includes a driving transistor.

[0018] The present disclosure proposes a pixel driving circuit, a pixel structure and a display panel, wherein the pixel driving circuit includes a plurality of driving transistors, wherein the first end of each driving transistor is connected to a first power supply end, the second end is connected to a first node, and the control end is connected to a second node, and is used to input current to the first node under the action of a second node voltage. The first node is connected to a light-emitting unit. The pixel driving circuit increases the current input to the first node by setting a plurality of driving transistors without changing the size of the driving transistor and the voltage of the first power supply end of the pixel driving circuit, thereby improving the brightness of the light-emitting unit. The display panel provided by the present disclosure sets the above-mentioned pixel driving circuit in its low pixel density area, thereby avoiding the brightness difference between the low pixel density area and the high pixel density area.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0021] Figure 1 It is a structural schematic diagram of a pixel driving circuit in the related art;

[0022] Figure 2 for Figure 1 Timing diagram of some nodes in the pixel driving circuit;

[0023] Figure 3 A schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed in the present invention;

[0024] Figure 4 is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention;

[0025] Figure 5 is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention;

[0026] Figure 6 A schematic structural diagram of an exemplary embodiment of a pixel structure disclosed herein;

[0027] Figure 7 A schematic diagram of the structure of an active layer in an exemplary embodiment of a pixel structure disclosed herein;

[0028] Figure 8A schematic diagram of the structure of a gate layer in an exemplary embodiment of a pixel structure disclosed herein;

[0029] Fig. 9 It is a schematic structural diagram of a conductive layer in an exemplary embodiment of a pixel structure disclosed in the present invention;

[0030] Fig.10 A schematic diagram of the structure of a source-drain layer in an exemplary embodiment of a pixel structure disclosed herein;

[0031] Fig.11 A schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0032] Fig.12 for Figure 1 A pixel structure corresponding to the pixel driving circuit;

[0033] Fig.13 for Fig.12 Schematic diagram of the structure of the active layer in the pixel structure;

[0034] Fig.14 for Fig.12 A schematic diagram of the structure of the gate layer in the pixel structure;

[0035] Fig.15 for Fig.12 A schematic diagram of the structure of the conductive layer in the pixel structure;

[0036] Fig.16 for Fig.12 Schematic diagram of the structure with source and drain layers in the pixel structure. DETAILED DESCRIPTION

[0037] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present invention will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0038] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". Other relative terms, such as "high", "low", "top", "bottom", "left", "right", etc., also have similar meanings. When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0039] The terms "a", "an", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0040] In order to realize the full-screen design of display devices such as mobile phones, the related technology usually hides the camera of display devices such as mobile phones in the display area of ​​the display panel. The display area where the camera is hidden needs to set its pixel density to be lower than the pixel density of the normal display area to improve its light transmittance, so as to facilitate the camera to collect light from the object to be photographed. However, since the low pixel density area where the camera is hidden and the high pixel density area of ​​the normal display have different pixel densities, the high pixel density area and the low pixel density area of ​​the display panel will have different display brightness when displaying the picture.

[0041] like Figure 1 , 2 As shown, Figure 1 The figure is a schematic diagram of the structure of a pixel driving circuit in the related art. Figure 2 for Figure 1 Timing diagram of some nodes in the pixel driving circuit. The pixel driving circuit includes the first to sixth transistors T1-T6, a driving transistor DT, a capacitor C, and a light-emitting unit OLED, wherein the first to sixth transistors T1-T6 and the driving transistor DT can all be P-type transistors, and the light-emitting unit OLED is connected between the third node and the second power supply terminal VSS. The driving method of the pixel driving circuit includes three stages: a reset stage, a compensation stage, and a light-emitting stage. Figure 2As shown, in the reset stage T1: the enable signal terminal EM is a high-level signal, the reset signal terminal Reset is a low-level signal, the gate drive signal terminal Gate is a high-level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off, and the initialization signal terminal Vinit inputs a reset signal to the first node N1 and the third node N3. In the compensation stage T2: the enable signal terminal EM is a high-level signal, the reset signal terminal Reset is a high-level signal, the gate drive signal terminal Gate is a low-level signal, the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off, the second transistor T2 and the third transistor T3 are turned on, and the data signal terminal Vdata inputs a compensation voltage V to the first node N1, wherein the compensation voltage V=Vdata+Vth, Vdata is the signal voltage of the data signal terminal Vdata, and Vth is the threshold voltage of the third transistor T3. In the light-emitting stage: the enable signal terminal EM is a low-level signal, the reset signal terminal Reset is a high-level signal, the gate drive signal terminal Gate is a high-level signal, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned off, the first transistor T1 and the fourth transistor T4 are turned on, and the light-emitting unit OLED emits light under the control of the output current of the driving transistor DT. Among them, the output current of the driving transistor DT is I = 0.5*W / L*Cox*(Vgs-Vth) 2 , Vg is the gate voltage of the driving transistor DT, Vs is the source voltage of the driving transistor DT, Vth is the threshold voltage of the driving transistor DT, W is the channel width of the driving transistor DT, L is the channel length of the driving transistor DT, and Cox is the capacitance per unit area of ​​the gate of the driving transistor. Then the output current of the driving transistor DT is I = 0.5*W / L*Cox*(Vgs-Vth) 2 =0.5*W / L*Cox*(Vdata+Vth-VDD-Vth) 2 =0.5*W / L*Cox*(Vdata-VDD) 2 It can be seen from the formula that the light-emitting state of the light-emitting unit OLED is not related to the threshold voltage of the driving transistor, thereby avoiding the influence of the threshold voltage of the driving transistor DT on the light-emitting brightness.

[0042] Based on this, this exemplary embodiment provides a pixel driving circuit, such as Figure 3, which is a schematic diagram of an exemplary embodiment of a pixel driving circuit disclosed in the present invention. The pixel driving circuit includes a plurality of driving transistors DT1, DT2, DT3, and DT4, each of which has a first end connected to a first power supply end VDD, a second end connected to a first node N1, and a control end connected to a second node N2, for inputting current to the first node N1 under the action of a voltage at the second node N2.

[0043] In this exemplary embodiment, the first node can be connected to the light emitting unit to provide a driving current to the light emitting unit. The pixel driving circuit increases the current input to the first node N1 by setting a plurality of driving transistors without changing the size of the driving transistor and the voltage of the first power supply terminal VDD, thereby improving the brightness of the light emitting unit.

[0044] In this exemplary embodiment, Figure 3 As shown, four driving transistors are exemplarily drawn in this embodiment. It should be understood that in other exemplary embodiments, the pixel driving circuit may also be provided with other numbers of driving transistors. Figure 3 The middle driving transistor can be a P-type transistor or an N-type transistor.

[0045] like Figure 4As shown, it is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. In this exemplary embodiment, the pixel driving circuit may also include: a first switch circuit 1, a data writing circuit 2, a compensation circuit 3, a second switch circuit 4, a storage circuit 5, a first reset circuit 6, a second reset circuit 7, and a light-emitting unit 8. The first switch circuit 1 is connected to the first power supply terminal VDD, the first end of each of the driving transistors, and the enable signal terminal EM, and is used to respond to the signal of the enable signal terminal EM to turn on the first power supply terminal VDD and the first end of each of the driving transistors; the data writing circuit 2 is connected to the first end of each of the driving transistors, the data signal terminal Data, and the gate signal terminal Gate, and is used to respond to the signal of the gate signal terminal Gate to transmit the signal of the data signal terminal Data to the first end of each of the driving transistors; the compensation circuit 3 is connected to the first node N1, the second node N2, and the gate signal terminal Gate, and is used to respond to the signal of the gate signal terminal Gate to turn on the first node N1 and the second node N2; the second switch circuit 4 is connected to the first node N1, the enable signal terminal EM, and the third node N3, and is used to In response to the signal of the enable signal terminal EM, the signal of the first node N1 is transmitted to the third node N3; the storage circuit 5 is connected between the second node N2 and the first power supply terminal VDD, and is used to store the voltage of the second node N2; the first reset circuit 6 is connected to the second node N2, the initial signal terminal Vinit, and the reset signal terminal Reset, and is used to transmit the signal of the initial signal terminal Vinit to the second node N2 in response to the signal of the reset signal terminal Reset; the second reset circuit 7 is connected to the third node N3, the initial signal terminal Vinit, and the reset signal terminal Reset, and is used to transmit the signal of the initial signal terminal Vinit to the third node N3 in response to the signal of the reset signal terminal Reset; the light-emitting unit 8 is connected between the third node N3 and the second power supply terminal VSS.

[0046] In this exemplary embodiment, Figure 4As shown, the first switch circuit 1 may include a first transistor T1, the first end of the first transistor T1 is connected to the first power supply terminal VDD, the second end is connected to the first end of each of the driving transistors, and the control end is connected to the enable signal terminal EM; the data write circuit 2 may include a second transistor T2, the first end of the second transistor T2 is connected to the data signal terminal Data, the second end is connected to the first end of each of the driving transistors, and the control end is connected to the gate signal terminal Gate; the compensation circuit 3 may include a third transistor T3, the first end of the third transistor T3 is connected to the first node N1, the second end is connected to the second node N2, and the control end is connected to the gate signal terminal Gate; the second switch circuit 4 may include a fourth transistor T4, the first end of the fourth transistor T4 is connected to the first node N1, the second end The third node N3 is connected, and the control end is connected to the enable signal end EM; the storage circuit 5 may include a capacitor C, which is connected between the second node N2 and the first power supply end VDD; the first reset circuit 6 may include a fifth transistor T5, a first end of the fifth transistor T5 is connected to the second node N2, a second end is connected to the initial signal end Vinit, and a control end is connected to the reset signal end Reset; the second reset circuit 7 may include a sixth transistor T6, a first end of the sixth transistor T6 is connected to the third node N3, a second end is connected to the initial signal end Vinit, and a control end is connected to the reset signal end Reset; the light-emitting unit 8 may include a light-emitting diode OLED, which is connected between the third node N3 and the second power supply end VSS.

[0047] In the present exemplary embodiment, the first to sixth transistors T1 to T6 and the driving transistor may be P-type transistors. Figure 4 The pixel driving circuit shown is Figure 1 The driving method of the driving circuit shown is basically the same, the only difference is that Figure 4 The pixel driving circuit in the embodiment inputs current to the first node through four driving transistors, thereby Figure 4 The pixel driving circuit shown can improve the light emitting brightness of the pixel unit without changing the first power supply terminal VDD and the size of the driving transistor.

[0048] It should be understood that in other exemplary embodiments, the pixel driving circuit may have other structures to choose from. Figure 5 FIG. 1 is a schematic diagram of another exemplary embodiment of a pixel driving circuit disclosed in the present invention. Figure 3The pixel driving circuit shown in the figure may further include a seventh transistor T7, an eighth transistor T8, a capacitor C, and a light-emitting unit OLED. The first end of the seventh transistor T7 is connected to the data signal terminal Data, the second end is connected to the second node N2, and the control end is connected to the first gate signal terminal G1; the first end of the eighth transistor T8 is connected to the sensing signal terminal Sense, the second end is connected to the first node N1, and the control end is connected to the second gate signal terminal G2; the capacitor C is connected between the first node N1 and the second node N2; the light-emitting unit is connected between the first node N1 and the second power supply terminal VSS.

[0049] The sensing signal terminal Sense may be used to sense the output current of the driving transistor when the driving transistor is turned on, so as to detect the threshold voltage and mobility of the driving transistor. Figure 5 The driving method of the pixel driving circuit shown generally includes: a data writing stage and a light emitting stage. In the data writing stage: the data signal terminal Data inputs the data signal to the gate of the driving transistor through the seventh transistor T7 and stores it in the storage capacitor C. At the same time, the sensing signal terminal Sense can also input the initial signal to the source of each driving transistor through the eighth transistor T8. In the light emitting stage: each driving transistor is turned on under the action of the storage capacitor C to drive the light emitting unit OLED to emit light through the first power supply terminal VDD. Among them, each driving transistor outputs a current I = w (Vg-Vs-Vth) 2 , w is the mobility of the driving transistor, Vg is the gate voltage of the driving transistor, and Vs is the source voltage of the driving transistor. Since the source and gate of the driving transistor are connected to the two ends of the storage capacitor C, although the source voltage of the driving transistor rises during the light-emitting stage, the gate of the driving transistor will also rise by the same voltage under the bootstrap effect of the storage capacitor C, that is, the gate and source voltage difference of the driving transistor during the light-emitting stage is equal to the gate and source voltage difference during the data writing stage. Therefore, the brightness of the light-emitting unit can be controlled only by controlling the data signal terminal Data. Since the pixel driving circuit is provided with multiple driving transistors, the light-emitting brightness of the light-emitting unit during the light-emitting stage can be increased.

[0050] This exemplary embodiment also provides a pixel structure, which includes the above-mentioned pixel driving circuit.

[0051] like Figure 6 FIG. 1 is a schematic diagram of the structure of an exemplary embodiment of the pixel structure of the present disclosure. Figure 6 Specifically include Figure 4 The pixel driving circuit shown in the figure. The pixel structure includes an active layer ACT, a gate layer Gate, a conductive layer EC, and a source-drain layer SD, wherein the active layer ACT, the gate layer Gate, the conductive layer EC, and the source-drain layer SD are stacked in sequence, and an insulating layer is provided between adjacent film layers. Figure 6 The comments in Gate, Data, Vinit, Reset, VDD, T1, T2, T3, T4, T5, T6, DT1, DT2, DT3, DT4 and Figure 4 The comments Gate, Data, Vinit, Reset, VDD, T1, T2, T3, T4, T5, T6, DT1, DT2, DT3, and DT4 correspond to each other. Figure 6 The black box in the middle represents the via located on the insulating layer, and the via is used to connect the above four film layers.

[0052] like Figure 7 As shown, it is a schematic diagram of the structure of the active layer in an exemplary embodiment of the pixel structure of the present disclosure. The active layer ACT includes two first active parts 71, two second active parts 72, a third active part 73, a fourth active part 74, a fifth active part 75, a sixth active part 76, and four seventh active parts 77. Among them, the first active part 71 is used to form the channel layer of the first transistor, the second active part 72 is used to form the channel layer of the second transistor, the two third active parts 73 form the channel layer of the third transistor (dual gate structure), the fourth active part 74 is used to form the channel layer of the fourth transistor, the two fifth active parts 75 are used to form the channel layer of the fifth transistor (dual gate structure), the sixth active part 76 is used to form the channel layer of the sixth transistor, and the four seventh active parts 77 respectively form the channel layers of the driving transistors.

[0053] like Figure 8 As shown, it is a schematic diagram of the structure of the gate layer in an exemplary embodiment of the pixel structure of the present disclosure. The gate layer Gate includes a first gate portion 81, a second gate portion 82, a third gate portion 83, a fourth gate portion 84, and a fifth gate portion 85. Among them, the orthographic projection of a part of the first gate portion 81 covers the two fifth active portions 75 to form the gate layer of the fifth transistor T5, and the first gate portion 81 is connected to the reset signal terminal Reset; the orthographic projection of a part of the second gate portion 82 covers the second active portion 72 to form the gate layer of the second transistor; the orthographic projection of a part of the second gate portion 82 covers the third active portion 73 to form the gate layer of the third transistor, and the second gate portion 82 is connected to the gate drive signal terminal Gate; a part of the third gate portion 83 covers the four seventh active portions to form the gates of the four driving transistors, wherein the third gate portion 83 can be an integrated structure, and the third gate portion 83 can form Figure 4 an electrode of the middle capacitor C; a portion of the fourth gate portion 84 covers the fourth active portion 74 to form a gate of the fourth transistor, a portion of the fourth gate portion 84 covers the first active portion 71 to form a gate of the first transistor, and the fourth gate portion 84 is connected to the enable signal terminal EM; a portion of the fifth gate portion 85 covers the sixth active portion 76 to form a gate of the sixth transistor T6, and the fifth gate portion 85 is connected to the reset signal terminal Reset.

[0054] like Fig. 9 , which is a schematic diagram of the structure of the conductive layer in an exemplary embodiment of the pixel structure of the present disclosure. The conductive layer EC includes a first conductive portion 91, a second conductive portion 92, a third conductive portion 93, and a fourth conductive portion 94. The first conductive portion 91 and the third conductive portion 93 can be connected to the initial signal terminal Vinit; the second conductive portion 92 can form Figure 4 The fourth conductive portion is used to shield the channel layer of the third transistor T3 in the adjacent pixel structure on the right to prevent leakage of the third transistor.

[0055] like Fig.10 As shown, it is a schematic diagram of the structure of the source and drain layer in an exemplary embodiment of the pixel structure of the present disclosure. The source and drain layer may include a first source and drain portion 11, a second source and drain portion 12, a third source and drain portion 13, a fourth source and drain portion 14, a fifth source and drain portion 15, and a sixth source and drain portion 16. Among them, the first source and drain portion 11 is connected to the first conductive portion 91 through a via 21, and is connected to the active layer on one side of the fifth active portion 75 through a via 22 to connect the initial signal terminal Vinit and the second end of the fifth transistor. The second source and drain portion 12 is connected to the first power supply terminal VDD, and is connected to the fourth conductive portion 94 through a via 23 so that the fourth conductive portion maintains the voltage of the first power supply terminal VDD. The second source and drain portion 12 is also connected to the second conductive portion 92 through vias 27 and 28 so that the second conductive portion 92 forms an electrode of the capacitor C. The second source and drain portion 12 is also connected to the active layer on one side of the first active portion 71 through a via 29 so that the first end of the first transistor is connected to the first power supply terminal VDD. The third active portion 13 is connected to the data signal terminal Data, wherein the third active portion 13 is connected to the active layer on one side of the second active portion 72 through the via 24, so that the data signal terminal Data is connected to the first end of the second transistor. The fourth source-drain portion 14 is connected to the active layer on one side of the fourth active portion 74 through the via 33, so that the fourth source-drain portion 14 is connected to the second end of the fourth transistor, wherein the light-emitting diode OLED can be connected to the second end of the fourth transistor through the fourth source-drain portion 14. The fifth source-drain portion 15 is connected to the third conductive portion 93 through the via 31, and is connected to the active layer on one side of the sixth active portion 76 through the via 32, so that the second end of the sixth transistor is connected to the initial signal terminal Vinit. The sixth source-drain portion 16 is connected to the active layer on one side of the third active portion 73 through the via 25, and is connected to the third gate portion 83 through the via 26, so that the gate of each driving transistor is connected to the second end of the third transistor, wherein, as Fig. 9 As shown, the second conductive portion 92 is provided with a hollow hole 921 at the position where the via hole 26 is located at its orthographic projection, so that the sixth source-drain portion 16 can be connected to the third gate portion 83 through the via hole 26 and is not connected to the second conductive portion 92 .

[0056] In this exemplary embodiment, the active layer ACT may be indium gallium zinc oxide, and the active layer may be subjected to conductorization treatment after the gate layer is formed, so that the non-channel layer in the active layer forms a conductor. The conductorization treatment may be achieved by hydrogen ion implantation. In addition, the active layer ACT may also be a polysilicon layer, and the active layer may be subjected to semiconductor doping treatment after the gate layer is formed, so that the non-channel layer in the active layer forms a conductor, wherein the semiconductor doping may be N-type semiconductor doping or P-type semiconductor doping. In this exemplary embodiment, the conductive layer EC may also share other conductive film layers in the pixel structure, such as a light-shielding metal layer.

[0057] In this exemplary embodiment, Figure 6 , 10 As shown, the pixel structure includes a data line (third source-drain portion 13 ), and the data line extends along a first direction X; a plurality of driving transistors are sequentially arranged in parallel along the first direction X.

[0058] This exemplary embodiment also provides a display panel such as Fig.11 , which is a schematic diagram of the structure of an exemplary embodiment of a display panel of the present disclosure. The display area of ​​the display panel includes a low pixel density area 111 and a high pixel density area 112, and the low pixel density area is provided with the above-mentioned pixel driving circuit.

[0059] In this exemplary embodiment, the pixel density in the high pixel density area is twice that in the low pixel density area. Figure 1 The pixel driving circuit shown in the figure can be set to a low pixel density area. Figure 4 The pixel driving circuit shown in FIG. Figure 4 In the pixel driving circuit shown in FIG. 1 , in order to satisfy the gate conduction voltage of the four driving transistors, Figure 4 The capacitor should be Figure 1 Four times the capacitance of the capacitor. Figure 4 The number of driving transistors in the pixel driving circuit is Figure 1 Four times of Figure 4 The luminous intensity of the luminous unit is also approximately Figure 1 The experiment shows that at this time, the luminance of the high pixel density area and the low pixel density area is similar, and the bright and dark boundary line is not easy to appear in the display area of ​​the display panel.

[0060] This exemplary embodiment enhances the luminous brightness of the pixel units in the low pixel density area by setting the above-mentioned pixel driving circuit in the low pixel density area without changing the size of the driving transistor and the voltage of the first power supply terminal of the pixel driving circuit, thereby avoiding the phenomenon of inconsistent display brightness between the high pixel density area and the low pixel density area of ​​the display panel.

[0061] In this exemplary embodiment, Figure 12-16 As shown, Fig.12 for Figure 1 The pixel structure corresponding to the pixel driving circuit, Fig.13 for Fig.12 Schematic diagram of the structure of the active layer in the pixel structure; Fig.14 for Fig.12 A schematic diagram of the structure of the gate layer in the pixel structure; Fig.15 for Fig.12 A schematic diagram of the structure of the conductive layer in the pixel structure; Fig.16 for Fig.12 Schematic diagram of the structure with source and drain layers in the pixel structure. Fig.12 The pixel structure shown is similar to Figure 6 The pixel structure shown is similar, and the pixel structure also includes an active layer ACT, a gate layer Gate, a conductive layer EC, and a source-drain layer SD. The active layer ACT, the gate layer Gate, the conductive layer EC, and the source-drain layer SD are stacked in sequence, and an insulating layer is arranged between adjacent film layers. Fig.12 The comments in Gate, Data, Vinit, Reset, VDD, T1, T2, T3, T4, T5, T6, DT and Figure 1 The comments Gate, Data, Vinit, Reset, VDD, T1, T2, T3, T4, T5, T6, and DT correspond to each other. Fig.12 The black box in the middle represents the via located on the insulating layer, and the via is used to connect the above four film layers. Fig.12 The pixel structure shown is similar to Figure 6 The pixel structure shown also has the same interlayer connection method, the only difference is that Fig.12 The pixel structure shown includes a driving transistor, Figure 6 The pixel structure shown includes four drive transistors.

[0062] In this exemplary embodiment, the pixel structure of the low pixel density area of ​​the display panel can be Figure 6 The pixel structure shown in the figure can be a pixel structure in a high pixel density area of ​​the display panel. Fig.12 The pixel structure shown in Figure 2. Fig.12 The light-transmitting area ratio of the pixel structure is 32.57%, and the transmittance is 9.77%. Figure 6 The light-transmitting area ratio of the pixel structure is 30.29%, and the transmittance is 9.09%. This shows that in the low pixel density area, Figure 6 The pixel structure shown has little effect on its transmittance and can fully meet the camera lighting requirements.

[0063] In other exemplary embodiments, the pixel density of the high pixel density area can be other multiples of the pixel density of the low pixel density area. For example, the pixel density of the high pixel density area is n times the pixel density of the low pixel density area, and the pixel driving circuit in the high pixel density area has the same architecture as the pixel driving circuit in the low pixel density area; the pixel driving circuit in the high pixel density area includes m driving transistors, and the pixel driving circuit in the low pixel density area includes n driving transistors. 2 m driving transistors; in the high pixel density area, the capacitance value of the capacitor in the pixel driving circuit is p, and in the low pixel density area, the capacitance value of the capacitor in the pixel driving circuit is n 2 p; and the sizes of the driving transistors in the high pixel density area and the low pixel density area are the same. Wherein, and the pixel driving circuit in the high pixel density area has the same architecture as the pixel driving circuit in the low pixel density area, indicating that: the two pixel driving circuits have the same structure except for the number of driving transistors and the capacitance value of the capacitor. Wherein, m can be an integer greater than or equal to 1.

[0064] The display panel provided by this exemplary embodiment can be applied to display devices such as mobile phones, VR, and tablet computers.

[0065] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are to be considered as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0066] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein a display area of ​​the display panel comprises a low pixel density area and a high pixel density area, characterized in that: The low pixel density area is provided with a pixel driving circuit, and the pixel driving circuit comprises: A plurality of driving transistors, each of which has a first end connected to a first power supply end, a second end connected to a first node, and a control end connected to a second node, and is used to input current to the first node under the action of a second node voltage; a storage circuit connected between the second node and the first power supply terminal and used to store the voltage of the first node, the storage circuit comprising: a capacitor connected between the second node and the first power supply terminal; The pixel density of the high pixel density area is n times that of the low pixel density area, and the pixel driving circuit in the high pixel density area has the same architecture as the pixel driving circuit in the low pixel density area; The pixel driving circuit in the high pixel density area includes m driving transistors, and the pixel driving circuit in the low pixel density area includes n 2 m driving transistors; In the high pixel density area, the capacitance value of the capacitor in the pixel driving circuit is p, and in the low pixel density area, the capacitance value of the capacitor in the pixel driving circuit is n 2 p; Furthermore, the sizes of the driving transistors in the high pixel density area and the low pixel density area are the same; The pixel driving circuit further includes: a first switch circuit, connected to the first power supply terminal, the first terminal of each of the driving transistors, and an enable signal terminal, and configured to conduct the first power supply terminal and the first terminal of each of the driving transistors in response to a signal at the enable signal terminal; A data writing circuit, connected to the first terminal, the data signal terminal, and the gate signal terminal of each of the driving transistors, and used for transmitting the signal of the data signal terminal to the first terminal of each of the driving transistors in response to the signal of the gate signal terminal; A compensation circuit, connected to the first node, the second node, and a gate signal terminal, and configured to conduct the first node and the second node in response to a signal from the gate signal terminal; a second switch circuit, connected to the first node, the enable signal terminal, and the third node, and configured to transmit the signal of the first node to the third node in response to the signal of the enable signal terminal; The first switch circuit comprises: A first transistor, a first end of which is connected to the first power supply end, a second end of which is connected to the first end of each of the driving transistors, and a control end of which is connected to an enable signal end; The data writing circuit comprises: A second transistor, a first end of which is connected to the data signal end, a second end of which is connected to the first end of each of the driving transistors, and a control end of which is connected to the gate signal end; The compensation circuit comprises: a third transistor, a first end connected to the first node, a second end connected to the second node, and a control end connected to the gate signal end; The second switch circuit comprises: a fourth transistor, a first end connected to the first node, a second end connected to the third node, and a control end connected to the enable signal end; The display panel further includes: an active layer, a gate layer, and a conductive layer which are sequentially stacked in the Z direction; In the low pixel density area: The active layer includes a first active portion, a second active portion, a third active portion, a fourth active portion, and a plurality of seventh active portions, wherein the first active portion is used to form a channel layer of a first transistor, the second active portion is used to form a channel layer of a second transistor, the third active portion is used to form a channel layer of a third transistor, the fourth active portion is used to form a channel layer of a fourth transistor, and the plurality of seventh active portions are respectively used to form channel layers of a plurality of driving transistors; Wherein, the first end of each of the seventh active parts is connected between the third active part and the fourth active part in the same layer, and the other end of each of the seventh active parts is connected between the first active part and the second active part in the same layer; The gate layer includes a second gate portion, a third gate portion, and a fourth gate portion; The projection of the second gate portion in the Z direction covers the projection of the second active portion in the Z direction and the projection of the third active portion in the Z direction, a portion of the second gate portion is used to form a gate layer of the second transistor, and a portion of the second gate portion is used to form a gate layer of the third transistor; The projection of the third gate portion in the Z direction covers the projections of the plurality of seventh active portions in the Z direction, and the third gate portion is used to form gates of the plurality of driving transistors, wherein the third gate portion is an integrated structure, and the third gate portion is reused as an electrode of the capacitor; The projection of the fourth gate portion in the Z direction covers the projection of the fourth active portion in the Z direction and the projection of the first active portion in the Z direction, a portion of the fourth gate portion is used to form a gate of the fourth transistor, and a portion of the fourth gate portion is used to form a gate of the first transistor; The projections of the plurality of seventh active portions in the Z direction are located between the projection of the fourth gate portion in the Z direction and the projection of the second gate portion in the Z direction, and the projections of the plurality of seventh active portions in the Z direction are spaced apart and distributed along the first direction; The conductive layer includes a second conductive portion, and the second conductive portion is used to form another electrode of the capacitor.

2. The display panel according to claim 1, characterized in that: The pixel driving circuit further includes: A first reset circuit is connected to the second node, the initial signal terminal, and the reset signal terminal, and is used to transmit the signal of the initial signal terminal to the second node in response to the signal of the reset signal terminal; a second reset circuit, connected to the third node, the initial signal terminal, and the reset signal terminal, and configured to transmit the signal of the initial signal terminal to the third node in response to the signal of the reset signal terminal; The light emitting unit is connected between the third node and the second power supply terminal.

3. The display panel according to claim 2, characterized in that: The first reset circuit comprises: a fifth transistor, a first end connected to the second node, a second end connected to the initial signal end, and a control end connected to the reset signal end; The second reset circuit comprises: a sixth transistor, a first end connected to the third node, a second end connected to the initial signal end, and a control end connected to the reset signal end; The light emitting unit comprises: The light emitting diode is connected between the third node and the second power supply terminal.

4. The display panel according to claim 1, characterized in that: The display panel comprises a data line, and the data line extends along a first direction; The plurality of driving transistors are sequentially and parallelly distributed along the first direction.

5. The display panel according to claim 1, characterized in that: In the high pixel density area, the pixel driving circuit includes a driving transistor.

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