Computer readable storage medium, computer implemented method and computer program product

Abstract

Various aspects of the present invention include a high-precision log1p() computation logic section of a computing machine that uses an estimated function E(x) to approximate a function F(x)=log1p(x)=ln(x+1) and performs at least the following operations: (i) receiving an input x, (ii) computing (x+1) using only native precision, (iii) computing an integer N such that: (4 / 3)2 N‑1 ≤(x+1)≤(4 / 3)2 N , (iv) Calculate f N (x) = Sx + (S-1), where S = 2 ‑N , (v) Calculate E(f N (x)), and (vi) return value v = E(f N (x)+Nln(2)) as an approximation to F(x)=log1p(x). A computer-readable storage medium and a computer-implemented method are also provided.

Description

Technical Field

[0001] The present disclosure relates to high-precision computing, and more particularly to a device and method for high-precision computing of log1p(). Background Art

[0002] Today's computing machines are more powerful and efficient than ever before. For example, a graphics processing unit (GPU) can perform billions of calculations per second. The processing speeds of embedded memory and processors included in other devices such as smartphones, tablets, laptops, and personal computers continue to increase. However, some types of calculations are resource intensive and therefore use approximations instead, or rely on lookup tables, which take up area on the silicon chip, increase access latency, increase memory bandwidth, and lead to an overall increase in the device's memory footprint.

[0003] One way to implement a transcendental function (e.g., a logarithm) is to implement a different non-transcendental mathematical function that approximates the desired function to sufficient accuracy within a finite domain, but is simpler to compute. Such approximating functions are typically simple polynomials, ratios of polynomials, Taylor series, splines (i.e., a piecewise collection of simpler approximations within a subdomain), Chebyshez polynomials, or some combination thereof. When an input value is outside the finite domain of the approximation, the implementation utilizes mathematical identities to derive another value that is within the domain of the approximation, and uses the identity formula to derive the correct result. This is referred to in the industry as "range reduction," but in reality "domain reduction" would be more accurate.

[0004] For simple logarithmic functions such as ln(x), the range reduction identity is ln(x) = ln(S*x) – ln(S), where S is some scale factor, usually a power of two, and the domain of the approximation function is usually a power of two, including x = 1.0. For example: sqrt(0.5) <= x <= sqrt(2).

[0005] For log1p(x)=ln(1+x), the range reduction identity is log1p(x)=log1p(S*(1+x)–1)–ln(S), where S is some scaling factor, usually a power of 2, and the domain of the approximation function is some range including x=0. Difficulties arise when the input x is of small magnitude (i.e., absolute value). Combining the term "x+1" with native precision arithmetic can result in an unacceptable loss of precision. For example, if x is O(2 -10 ), this operation will lose 10 bits of precision. Therefore, the current practice is to use extended precision arithmetic to perform the calculation of “S*(1+x)–1”, which is typically expensive in terms of computational resources (e.g., time, space, energy). Summary of the invention

[0006] Various aspects of the present invention include a high precision log1p() calculation logic section that uses an estimated function E(x) to approximate a function F(x)=log1p(x)=ln(x+1) and performs at least the following operations: (i) receiving an input x, (ii) calculating (x+1) using only native precision, (iii) calculating an integer N such that: (4 / 3)2 N-1 ≤(x+1)≤(4 / 3)2 N , (iv) Calculate f N (x) = Sx + (S-1), where S = 2 -N , (v) Calculate E(f N (x)), and (vi) return value v = E(f N (x)+Nln(2)) as an approximation to F(x)=log1p(x).

[0007] Some embodiments include a computer-implemented method for high-precision calculation of log1p(). The method may include: using an estimated function E(x) to approximate a function F(x)=log1p(x)=ln(x+1) by a high-precision log1p() calculation logic section of a computing machine; receiving an input x by the high-precision log1p() calculation logic section of the computing machine; calculating (x+1) by the high-precision log1p() calculation logic section of the computing machine using only native precision; calculating an integer N by the high-precision log1p() calculation logic section of the computing machine such that: (4 / 3)2 N-1 ≤(x+1)≤(4 / 3)2 N ; The high-precision log1p() calculation logic section of the computing machine calculates f N (x) = Sx + (S-1), where S = 2 -N; E(f N (x)); and the high-precision log1p() calculation logic section of the computing machine returns a value v=E(f N (x)+Nln(2)) as an approximation to F(x)=log1p(x).

[0008] Some of the features of the present invention may be best realized by implementation in a graphics processing unit (GPU) or in an ARM processor core. Other types of processors or application specific integrated circuits (ASICs) may implement the inventive principles disclosed herein. The inventive concepts may be implemented in processors and / or memory modules of various mobile devices (e.g., smartphones, tablet computers, notebook computers, etc.) or in various fixed devices (e.g., desktop computers, routers, etc.). BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and additional features and advantages of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings, in which:

[0010] Figure 1A is an exemplary block diagram of a computing machine including a high-precision log1p() calculation logic section according to embodiments disclosed herein.

[0011] Figure 1B is an exemplary block diagram of another computing machine including a high precision log1p() calculation logic section embedded in one or more microprocessors according to embodiments disclosed herein.

[0012] Figure 1C is an exemplary flow chart illustrating a technique for performing high-precision log1p() calculations according to embodiments disclosed herein.

[0013] Figure 1D is a diagram showing a function set f according to an embodiment disclosed herein N Every function of is a linear graph.

[0014] Figure 2 is an exemplary flow chart illustrating another technique for performing high-precision log1p() calculations according to embodiments disclosed herein.

[0015] Figure 3 is an exemplary block diagram of a graphics processing unit (GPU) including a high-precision log1p() calculation logic section according to embodiments disclosed herein.

[0016] Figure 4is an exemplary block diagram of a smartphone including a high-precision log1p() calculation logic section according to embodiments disclosed herein.

[0017] Figure 5 is an exemplary block diagram of a tablet computer including a high-precision log1p() calculation logic section according to embodiments disclosed herein.

[0018] Figure 6 is an exemplary block diagram of a computer including a high precision log1p() calculation logic section according to embodiments disclosed herein.

[0019] Figure 7 is an exemplary block diagram of a computing system including a high-precision log1p() calculation logic section according to embodiments disclosed herein.

[0020] [Explanation of Symbols]

[0021] 105, 108: Calculating machinery;

[0022] 110: High-precision log1p() calculation logic section;

[0023] 115, 118: microprocessor;

[0024] 120: memory devices;

[0025] 125: storage unit;

[0026] 130: Display;

[0027] 135: Input / output (I / O) interface chip;

[0028] 140: log1p() function input;

[0029] 145: log1p() range reduction technique;

[0030] 150: log1p() function output;

[0031] 180, 200: Flowchart;

[0032] 182, 184, 186, 188, 190, 192, 205, 210, 215, 220, 225, 230, 235, 240, 245: steps;

[0033] 195: Figure;

[0034] 305: Graphics processing unit (GPU);

[0035] 405: Smartphone;

[0036] 505: Tablet computer;

[0037] 605: Computer;

[0038] 700: Computing systems;

[0039] 705: system bus;

[0040] 710: Clock;

[0041] 715: Random access memory (RAM) and / or flash memory;

[0042] 720: user interface;

[0043] 725: Modem;

[0044] 740: Battery;

[0045] 745: Memory controller. DETAILED DESCRIPTION

[0046] Reference will now be made in detail to embodiments of the inventive concept, which are illustrated in the accompanying drawings. In the following detailed description, many specific details are set forth to achieve a thorough understanding of the inventive concept. However, it should be understood that those of ordinary skill in the art can practice the inventive concept without these specific details. In other cases, well-known methods, procedures, components, circuits, and networks are not set forth in detail to avoid obscuring various aspects of the embodiments.

[0047] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first logic segment may be referred to as a second logic segment, and similarly, a second logic segment may be referred to as a first logic segment without departing from the scope of the present inventive concept.

[0048] The terms used in the description of the inventive concept herein are only used to illustrate specific embodiments and are not intended to limit the inventive concept. Unless the context clearly indicates otherwise, the singular forms "a, an" and "the" used in the description of the inventive concept and the appended claims are intended to also include plural forms. It should also be understood that the terms "and / or" used herein refer to and encompass all possible combinations of any of the related listed items and one or more of the related listed items. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, it is to indicate the presence of the features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. The components and features of the accompanying drawings are not necessarily drawn to scale.

[0049] The present invention discloses a more efficient system and method for implementing the log1p() function using fewer computing resources. The improved metrics obtained include: number of instructions, execution time, number of registers, and power consumption.

[0050] The embodiments disclosed herein enable the range reduction of the input values ​​implemented by the computer to be automatically performed using only native precision arithmetic operations (i.e., without using extended precision arithmetic or constant storage tables), thereby eliminating the need for more expensive extended precision arithmetic operations. In other words, the embodiments disclosed herein enable the range reduction portion of the log1p() function implemented by the computer to be automatically performed without using extended precision arithmetic or constant storage tables. On the contrary, only relatively few native precision computer instructions can be used. The log1p() function is used by OpenCL and other computer architecture standards. The range reduction technology implemented by the computer that is automatically performed disclosed herein is more efficient, has fewer instructions, fewer clock cycles, shorter execution time, and achieves lower power consumption. In addition, less silicon area is required, access latency, memory bandwidth, and memory footprint are improved. No lookup table or extended precision arithmetic is required.

[0051] Figure 1A is an exemplary block diagram of a computing machine 105 including a high precision log1p() calculation logic section 110 according to embodiments disclosed herein. Figure 1B is an exemplary block diagram of another computing machine 108 including a high precision log1p() calculation logic section 110 embedded in one or more microprocessors 118 according to embodiments disclosed herein. Figure 1C is an exemplary flow chart 180 illustrating a technique for performing high-precision log1p() calculations according to embodiments disclosed herein. Figure 1A , Figure 1B and Figure 1C .

[0052] Figure 1A The illustrated computing machine 105 may include a high precision log1p() calculation logic section 110 which will be described in further detail below. The computing machine 105 may also include a microprocessor 115, a memory device 120, a storage unit 125, a display 130 and / or an input / output (I / O) interface chip 135. Figure 1B The computing machine 108 is similar to Figure 1A The computing machine 108 may include one or more microprocessors 118, with the notable difference that the computing machine 108 may include one or more microprocessors 118 and the high precision log1p() calculation logic section may be embedded within the one or more microprocessors 118 or otherwise be part of the hardware section of the one or more microprocessors 118. The embodiments disclosed herein are capable of performing range reduction of log1p(x) using only a small number of native precision arithmetic operations.

[0053] like Figure 1C As shown at 182 of FIG. 1 , the high-precision log1p() calculation logic section 110 may receive a log1p() function input 140 ( Figure 1A and Figure 1B Next, the high precision log1p() calculation logic section 110 may perform range reduction at 145 according to the embodiments disclosed herein. Specifically, at 184, the high precision log1p() calculation logic section 110 may calculate (x+1) using only native precision. At 186, the high precision log1p() calculation logic section 110 may use the result from 184 and calculate the integer N such that: (4 / 3)2 N-1 ≤(x+1)≤(4 / 3)2 N At 188, the high precision log1p() calculation logic section 110 may calculate f N (x) = Sx-(1-S) or Sx+(S-1), where S = 2 -N .

[0054] After performing the above range reduction technique, the following holds: -1 / 3 ≤ f N (x) ≤ 1 / 3. Thereafter, a post-range-reduction computation associated with the log1p(x) function may be performed at 190 using standard techniques. For example, log1p(f N (x)). In addition, we can calculate log1p(x)=log1p(f N (x))-ln(S) or log1p(fN (x))+Nln(2) and returns log1p(x)=log1p(f N (x))-ln(S) or log1p(f N (x))+Nln(2) outputs 150 as the log1p() function.

[0055] The value of (x+1) calculated at 184 is only used in step 186 to calculate the integer N. In other words, the value of (x+1) does not need to be used in any subsequent stages. When x has a very small magnitude, this combination may lose precision, as described above. However, for these values, despite the loss of significant digits, the calculated integer N will be clear and unambiguous. Without departing from the inventive concepts disclosed herein, there may be alternative methods for implementing step 186, which will depend on the instruction set architecture and / or programming language of the computer used.

[0056] At 188, 2 -N and 2 -N The computation of x is an exact operation in which only the exponent of the floating point number is modified, not the significand. The combination of (S-1) is exact for small values ​​of N, but is rounded with a slight loss of precision for larger values ​​of N. However, for these values, the final result is dominated by the +Nln(2) term, so the effect of this rounding on the final result, if any, is negligible. The final addition of combining Sx+(S-1) in this step will be an exact operation, with no rounding for most inputs. For a small subset of the inputs, rounding may occur, but in the worst case the result is equivalent to losing 1 bit of the input value or 1 unit in the last place (ULP) or unit of least precision (ULP). The order of precedence of operators in this step is important; for example, evaluating (Sx+S)-1 will produce a completely different and less accurate result.

[0057] The following is pseudocode for one possible scheme to implement this range reduction using the conventions of the C++ computer programming language:

[0058]

[0059] In the process of designing an approximation function, there is always a trade-off between the size of the domain of the approximation and the computational complexity (i.e., cost) of the approximation. The reduction values ​​produced by this method are guaranteed to be in the limited range -1 / 3≤f N(x)≤1 / 3. This may be a smaller domain than supported by the approximation function used in some implementations of log1p(), and thus additional improvement may be achieved by simplifying the approximation function.

[0060] In some embodiments, a non-transitory computer-readable storage medium is provided, on which instructions are stored, which, when executed by a computer processor, cause a high-precision log1p() calculation logic section 110 to use an estimated function E(x) to approximate a function F(x)=log1p(x)=ln(x+1) and perform at least the following operations: (i) receive an input x, (ii) calculate (x+1) using only native precision, (iii) calculate an integer N such that: (4 / 3)2 N-1 ≤(x+1)≤(4 / 3)2 N , (iv) Calculate f N (x) = Sx + (S-1), where S = 2 -N , (v) Calculate E(f N (x)), and (vi) return value v = E(f N (x)+Nln(2)) as an approximation to F(x)=log1p(x).

[0061] Figure 1D is a diagram showing a function set f according to an embodiment disclosed herein N Every function of is linear in Figure 195. If and only if N is correctly chosen so that f N When the magnitude of (x) is minimized, there is little or no loss of precision at step 188. In other words, if N satisfies the inequality, then the magnitude of the range reduction value calculated at 188 must be minimized. Figure 1D As shown in , each function of the set is linear in 2 N It intersects the X-axis at -1 and has a slope of 2 N The preferred value of N is the index of the nearby zero crossing. The cusp point for selecting between consecutive integers is determined by making f N (x) and f N+1 (x) are defined by points with the same magnitude. For example:

[0062] │f N (y)│=│f N+1 (y)│or f N (y)= -f N+1 (y)

[0063] 2 -N (1+y)-1=-2 -(N+1) (1+y)+1

[0064] (1+y)(2-N +2 -(N+1) )=2

[0065] (1+y)(3 / 2)2 -N =2

[0066] (1+y)=(4 / 3)2 N

[0067] For Institute of Electrical and Electronics Engineers (IEEE)-754 base-2 floating point numbers (i.e., not denormal floating point numbers), the distinction between two consecutive integer values ​​of N will always depend only on the significand of (1+x), not on the exponent bits. The above pseudocode treats the bits of the value as a fixed point number and adds a specific bit pattern to it, and therefore works by moving one from the significand field to the exponent bit field - incrementing the exponent - if and only if the significand is greater than the tangent point value. For IEEE-754 floating point arithmetic, (1.0+x) cannot be denormal.

[0068] For any choice of N: f N (y) = 2 -N (4 / 3)(2 N )-1=1 / 3.

[0069] Therefore, for a properly chosen value of N, the reduction is: -1 / 3 ≤ f N (x)≤1 / 3.

[0070] The range reduction techniques disclosed herein can be implemented in various high-level computer languages, assembly languages, machine code, or hardware. The disclosed techniques can be implemented for different types of floating point numbers. The above pseudo code shows one possible implementation for IEEE 754 single precision floating point, but this can also be implemented for IEEE 754 double precision, or even for base-10 decimal floating point format, formats not covered by IEEE 754, etc. For bases other than 2, the equations in steps 186 and 188 must be modified accordingly.

[0071] There may be alternative ways to implement step 2. The pseudocode example given above is just one possibility. Another variation includes the following:

[0072]

[0073]

[0074] The log1p() function input 140 and / or the log1p() function output 150 may be temporarily stored in the memory device 120. The memory device 120 may be, for example, a volatile memory device, such as a dynamic random access memory (DRAM). The computing machine 105 or 108 may more permanently store the log1p() function output 150 in the storage unit 125, display the log1p() function output 150 on the display 130, and / or transmit the log1p() function output 150 through the input / output interface chip 135. The storage unit 125 may be, for example, a non-volatile memory, such as a solid state drive (SSD), a magnetic storage device, etc.

[0075] Figure 2 is an exemplary flow chart 200 illustrating a technique for performing high precision log1p() calculations according to embodiments disclosed herein. Flow chart 200 illustrates another possible implementation of range reduction for IEEE-754 single precision arithmetic.

[0076] At 140, a log1p() function input may be received. At 145, the high precision log1p() calculation logic section 110 may perform a range reduction operation. Specifically, at 205, the high precision log1p() calculation logic section 110 may perform a single precision floating point addition to calculate (1.0f+x). At 210, the high precision log1p() calculation logic section 110 may perform a 32-bit fixed point subtraction and a bit field extraction in combination, which subtracts the result of step 205 from the constant value. No type conversion is required for the input. The 32 bits generated at 205 may be reinterpreted as a fixed point number. This operation adds the value 2 / 3 to the significant bit field of the input, so if the significant bit number of the floating point value is >4 / 2, the exponent bit field is carried, thereby incrementing the exponent. In addition, an exponent bias term in IEEE-754 format may be subtracted from the exponent. The resulting exponent bit field is extracted (e.g., the resulting exponent bit field may be sign-extended) and output as a two's complement fixed-point value. The significand and sign bits may be discarded. The entire operation may be negated so that the output value is –N.

[0077] Steps 215 and 220 perform a load exponent (LDEXP) operation. A fixed-point input value can be added to the exponent of a floating-point value to effectively multiply the floating-point value by 2^(-N). Since the number of significant digits of the floating-point value is not modified, this is an exact operation without loss of precision. Step 220 takes a constant input of 1.0f and calculates S=2^(-N). Step 215 takes an x ​​input and calculates S*x.

[0078] At 225 , the high precision log1p() logic section 110 may perform a conversion operation to convert the value of N from fixed point to floating point.

[0079] At 230, the high precision log1p() calculation logic section 110 may perform a single precision floating point subtraction to calculate (1.0f - S). Rounding is only performed in this step to obtain extreme values ​​of N, and even then, the loss of precision due to such rounding is generally negligible.

[0080] At 235, the high precision log1p() calculation logic section 110 may perform a single precision floating point subtraction to calculate f_N(x)=(S*x-(1.0f-S)). Since this is calculating the difference between two values ​​of comparable magnitude, for most input values, there is no rounding and this is an accurate operation. There are some exceptions for input values ​​where the calculated N is +1, and in these cases some rounding will occur, but this small loss of precision is generally negligible.

[0081] At 240, the high precision log1p() calculation logic section 110 may calculate the log1p() function of the range-reduced floating point result of step 235 using any of the standard techniques. For example, this may be the calculation of a minmax polynomial. At 245, the high precision log1p() calculation logic section 110 may calculate the final result log1 p(f_N(x))+N ln(2) using a single precision fused-multiply-add operation. The log1p() function output may be returned at 150.

[0082] Figure 3 is an exemplary block diagram of a graphics processing unit (GPU) 305 including a high precision log1p() calculation logic section 110 according to embodiments disclosed herein. The GPU 305 may perform the log1p() range reduction technique 145 described in detail herein. The GPU 305 may perform the log1p() range reduction technique 145 using at least one of the microprocessor 115, the high precision log1p() calculation logic section 110, or the memory device 120.

[0083] Figure 4 is an exemplary block diagram of a smartphone 405 including a high precision log1p() calculation logic section 110 according to embodiments disclosed herein. The smartphone 405 can perform the log1p() range reduction technique 145 described in detail herein. The smartphone 405 can use at least one of the microprocessor 115, the high precision log1p() calculation logic section 110, the memory device 120, or the storage unit 125 to perform the log1p() range reduction technique 145.

[0084] Figure 5 is an exemplary block diagram of a tablet computer 505 including a high precision log1p() calculation logic section 110 according to embodiments disclosed herein. The tablet computer 505 can perform the log1p() range reduction technique 145 described in detail herein. The tablet computer 505 can use at least one of the microprocessor 115, the high precision log1p() calculation logic section 110, the memory device 120, or the storage unit 125 to perform the log1p() range reduction technique 145.

[0085] Figure 6 is an exemplary block diagram of a computer 605 including a high precision log1p() calculation logic section 110 according to embodiments disclosed herein. The computer 605 may perform the log1p() range reduction technique 145 described in detail herein. The computer 605 may use at least one of a microprocessor 115, a high precision log1p() calculation logic section 110, a memory device 120, or a storage unit 125 to perform the log1p() range reduction technique 145.

[0086] Figure 7 is an exemplary block diagram of a computing system 700 including a high precision log1p() calculation logic section 110 according to embodiments disclosed herein. The high precision log1p() calculation logic section 110 may be the same as the high precision log1p() calculation logic section 110 described herein and may be electrically connected to a system bus 705. The computing system 700 may also include a clock 710, a random access memory (RAM) and / or flash memory 715, a memory controller 745, a user interface 720, a modem 725 (e.g., a baseband chipset), and / or automated test equipment (ATE), any one or all of which may be electrically coupled to the system bus 705.

[0087] If the computing system 700 is a mobile device, the computing system 700 may further include a battery 740 for powering the computing system 700. Figure 7 Although not shown, the computing system 700 may further include an application chipset, a camera image processor (CIS), a mobile dynamic random access memory (DRAM), etc. The memory controller 745 and the flash memory 715 may constitute a solid state drive / disk (SSD) that uses non-volatile memory to store data.

[0088] In an exemplary embodiment, the computing system 700 may be used as a computer, a portable computer, an ultra-mobile personal computer (UMPC), a workstation, a net-book, a personal digital assistant (PDA), a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a digital camera, a digital audio recorder / player, a digital photo / video recorder / player, a portable game machine, a navigation system, a black box, a three-dimensional television, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a remote processing network, a radio frequency identification device (RFID), or one of various electronic devices constituting a computing system.

[0089] The various operations of the above-described methods may be performed by any suitable means capable of performing the operations (eg, various hardware components, circuits and / or modules, and / or software components, circuits and / or modules).

[0090] The blocks or steps of the methods or algorithms and functions described in conjunction with the embodiments disclosed herein may be implemented directly in hardware, in software modules executed by a processor, or in a combination of the two. If implemented in software, the functions may be stored as one or more instructions or codes on a tangible, non-transitory computer-readable medium or transmitted via a tangible, non-transitory computer-readable medium. The software module may reside in a random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, compact disk read-only memory (CD ROM), or any other form of storage medium known in the art.

[0091] The following discussion is intended to provide a brief general description of one or more suitable machines in which certain aspects of the inventive concepts may be implemented. Typically, the one or more machines include a system bus with a processor, memory (e.g., RAM, ROM or other state preservation media), storage devices, video interfaces, and input / output interface ports attached. The one or more machines may be controlled at least in part by: input from traditional input devices such as keyboards, mice, etc.; and instructions received from another machine, interaction with a virtual reality (VR) environment, biometric feedback, or other input signals. The term "machine" as used herein is intended to broadly encompass a single machine, a virtual machine, or a system formed by machines, virtual machines, or devices operating together and coupled in a communicative manner. Exemplary machines include computing devices (e.g., personal computers, workstations, servers, portable computers, handheld devices, phones, tablet computers, etc.) and transportation devices (e.g., private or public transportation (e.g., cars, trains, taxis, etc.)).

[0092] The one or more machines may include embedded controllers, such as programmable or non-programmable logic devices or arrays, application specific integrated circuits (ASICs), embedded computers, smart cards, etc. The one or more machines may utilize one or more connections to one or more remote machines (e.g., via a network interface, a modem, or other communicative coupling). The machines may be interconnected through physical networks and / or logical networks such as intranets, the Internet, local area networks, and wide area networks. It should be understood by those skilled in the art that network communications may utilize various wired and / or wireless short-range or long-range carriers and protocols, including radiofrequency (RF), satellite, microwave, Institute of Electrical and Electronics Engineers (IEEE) 545.11, Optical, infrared, cable, laser, etc.

[0093] Embodiments of the inventive concept may be described by reference to or in conjunction with associated data, including functions, procedures, data structures, applications, etc., that when accessed by a machine cause the machine to perform a task or define an abstract data type or low-level hardware context. The associated data may be stored, for example, in volatile and / or non-volatile memory (e.g., RAM, ROM, etc.) or other storage devices and their associated storage media (including hard drives, floppy disks, optical storage, magnetic tapes, flash memory, memory sticks, digital video disks, bio-storage, etc.). The associated data may be delivered in the form of packets, serial data, parallel data, propagated signals, etc., through a transmission environment (including a physical network and / or a logical network), and may be used in a compressed or encrypted format. The associated data may be used in a distributed environment and may be stored locally and / or remotely for machine access.

[0094] The principles of the inventive concept have been described and illustrated with reference to the illustrated embodiments, and it will be appreciated that the illustrated embodiments may be arranged and modified in detail and may be combined in any desired manner without departing from these principles. And although the above discussion focuses on specific embodiments, other configurations are also contemplated. Specifically, even though expressions such as "embodiments according to the inventive concept" are used herein, these phrases are intended to refer generally to the possibility of embodiments and are not intended to limit the inventive concept to a specific embodiment configuration. These terms used herein may refer to the same or different embodiments that may be combined into other embodiments.

[0095] Embodiments of the inventive concepts may include a non-transitory machine-readable medium including instructions executable by one or more processors, including instructions to perform elements of the inventive concepts as described herein.

[0096] The above exemplary embodiments should not be considered as limiting the inventive concepts of the exemplary embodiments. Although several exemplary embodiments have been described, it will be readily understood by those skilled in the art that many modifications may be made to these embodiments without substantially departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the inventive concepts defined by the claims.

Claims

1. A non-transitory computer-readable storage medium having instructions stored thereon, which when executed by a computer processor causes a high-precision log1p() calculation logic section to approximate a function F(x)=log1p(x)=ln(x+1) using an estimated function E(x) and perform at least the following operations: (i) receiving input x, (ii) Calculate (x+1) using only native precision, (iii) Compute an integer N such that: (4 / 3)2 N-1 ≤(x+1)≤(4 / 3)2 N (iv) Calculate f N (x) = Sx + (S-1), where S = 2 -N (v) Calculate E(f N (x)), and (vi) Return value v = E(f N (x)+Nln(2)) as an approximation to F(x)=log1p(x).

2. The non-transitory computer-readable storage medium of claim 1 , wherein instructions are stored on the non-transitory computer-readable storage medium, and when the instructions are executed by the computer processor, the high-precision log1p() calculation logic section stores the returned value in a non-volatile storage unit.

3. The non-transitory computer-readable storage medium of claim 1 , having instructions stored thereon which, when executed by the computer processor, cause the high-precision log1p() calculation logic section to store the returned value in a volatile memory device.

4. The non-transitory computer-readable storage medium of claim 1 , wherein instructions are stored on the non-transitory computer-readable storage medium, and when the instructions are executed by the computer processor, the high-precision log1p() calculation logic section transmits the returned value through an input / output interface chip.

5. The non-transitory computer-readable storage medium of claim 1, having instructions stored thereon, which, when executed by the computer processor, cause the high-precision log1p() calculation logic section to display the returned value on a display device.

6. A computer-implemented method for high-precision calculation of log1p(), the method comprising: The high-precision log1p() calculation logic section of the computing machine uses the estimated function E(x) to approximate the function F(x)=log1p(x)=ln(x+1), The high precision log1p() calculation logic section of the computing machine receives an input x, The high precision log1p() calculation logic section of the computing machine calculates (x+1) using only native precision, The high precision log1p() calculation logic section of the computing machine calculates an integer N such that: (4 / 3)2 N-1 ≤(x+1)≤(4 / 3)2 N The high-precision log1p() calculation logic section of the computing machine calculates f N (x) = Sx + (S-1), where S = 2 -N The high-precision log1p() calculation logic section of the computing machine calculates E(f N (x)), and The high-precision log1p() calculation logic section of the computing machine returns a value v=E(f N (x)+Nln(2)) as an approximation to F(x)=log1p(x).

7. The computer-implemented method of claim 6, further comprising: The value returned by the high-precision log1p() calculation logic section is stored in a non-volatile storage unit.

8. The computer-implemented method of claim 6, further comprising: The value returned by the high precision log1p() calculation logic section is stored in a volatile memory device.

9. The computer-implemented method of claim 6, further comprising: The value returned by the high-precision log1p() calculation logic section is transmitted through the input / output interface chip.

10. The computer-implemented method of claim 6, further comprising: The high-precision log1p() calculation logic section causes the returned value to be displayed on a display device.

11. A computing machine comprising: Storage unit; microprocessor; High-precision log1p() calculation logic section; Wherein, the microprocessor and the high-precision log1p() calculation logic section are configured as follows: Use the estimated function E(x) to approximate the function F(x)=log1p(x)=ln(x+1); Receive input x; Calculate (x+1) using only native precision; Calculate the integer N such that: (4 / 3)2 N-1 ≤(x+1)≤(4 / 3)2 N ; Calculate f N (x) = Sx + (S-1), where S = 2 -N ; Calculate E(f N (x)); Return value v = E(f N (x)+Nln(2)) as an approximation to F(x)=log1p(x); Perform automatic range reduction of the function F(x) without using extended precision arithmetic or constant storage tables; Storing the returned value in the storage unit; displaying the returned value on a display device; and The returned value is transmitted through the input / output interface chip.

12. The computing machine of claim 11, wherein the storage unit is a non-volatile storage unit, and wherein the high-precision log1p() calculation logic section is further configured to store the returned value in the non-volatile storage unit.

13. The computing machine of claim 11, wherein the storage unit is a volatile memory device, and wherein the high precision log1p() calculation logic section is further configured to store the returned value in the volatile memory device.

14. The computing machine of claim 11, wherein the high precision log1p() calculation logic section is further configured to transmit the returned value through an input / output interface chip.

15. The computing machine of claim 11, wherein the high precision log1p() calculation logic section is further configured to display the returned value on a display device.

16. The computing machine of claim 11, wherein the computing machine is a graphics processing unit.

17. The computing machine of claim 11, wherein the computing machine is a smartphone.

18. The computing machine of claim 11, wherein the computing machine is a tablet computer.

19. The computing machine of claim 11, wherein the computing machine is a computer server.

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