Semiconductor component and method for identifying semiconductor component

Abstract

Provided are a semiconductor element and a method for identifying a semiconductor element whose characteristics can be easily identified during assembly. The semiconductor element comprises: a first external connection electrode (5a) disposed on the upper surface side of a chip; a second external connection electrode (5b) disposed in a manner separated from and parallel to the first external connection electrode; and a protective film (7) covering the first external connection electrode and the second external connection electrode, wherein a portion of the protective film has a first opening (8a) exposing a portion of the upper surface of the first external connection electrode and a second opening (8b) exposing a portion of the upper surface of the second external connection electrode. The planar pattern of the first opening and the planar pattern of the second opening are twice rotationally symmetric about the center point of the region including the first external connection electrode and the second external connection electrode, and are asymmetric about the center line between the first external connection electrode and the second external connection electrode.

Description

Technical Field

[0001] The present invention relates to a semiconductor element whose characteristics are easily distinguished and a method for distinguishing the semiconductor element. Background Art

[0002] In semiconductor integrated circuits (ICs) and the like, there is known a semiconductor element having a resistance layer having a polysilicon thin film (see Patent Document 1). In the semiconductor element described in Patent Document 1, two electrodes on the upper surface side of the resistance layer are connected to both ends of the resistance layer, and bonding wires are bonded to the two electrodes, respectively. Therefore, the chip size becomes larger and two bonding wires are required.

[0003] Therefore, the following vertical semiconductor element can be conceived: a structure in which one end of the resistance layer is connected to an electrode on the upper surface side of the resistance layer, and the other end of the resistance layer is ohmically connected to the semiconductor substrate via a relay wiring, so that the current flows vertically. By setting it as a vertical semiconductor element, the chip size can be reduced compared to a horizontal semiconductor element, and the number of bonding wires connected to the electrode can be reduced.

[0004] In order to suppress the increase in resistance value when the semiconductor element is operated at high temperature, it is preferable to set the temperature coefficient to a negative value below 0 ppm / °C. The resistance layer of the semiconductor element is formed by ion implantation of impurities into polysilicon. The temperature coefficient of the semiconductor element is controlled by adjusting the impurity dose or acceleration voltage of the ion implantation, and the temperature or time of the activation heat treatment of the implanted impurities. The resistance value of the semiconductor element is controlled by adjusting the length and width of the resistance layer.

[0005] In mounting a semiconductor element, a portion of the electrode on the upper surface side of the resistor layer is exposed to form a pad, and a bonding wire is bonded to the pad. Patent document 2 proposes the following scheme: by providing design standards such as the size of the chip and the bonding pad, human errors in the assembly process are reduced.

[0006] However, there is the following situation: the size of the chip and pad of the semiconductor element with different resistance values ​​is the same, so the semiconductor element with different resistance values ​​is manufactured by the same process. A plurality of semiconductor elements with different resistance values ​​are respectively stored in a tray, etc., and are installed by the same assembly process. As mentioned above, the resistance value is adjusted by the length and width of the pattern on the plane of the resistance layer, so it is difficult to identify even if other chips are mixed in. In addition, it is also possible to be mistaken for other chips. Therefore, in the assembly process, it is difficult to confirm whether it is the desired semiconductor element, and problems may occur.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Laid-Open No. 8-306861

[0010] Patent Document 2: Japanese Patent Application Publication No. 2003-282603 Summary of the invention

[0011] Problem that the invention aims to solve

[0012] In view of the above problems, an object of the present invention is to provide a semiconductor device having different characteristics that can be easily identified during assembly and a method for identifying the semiconductor device.

[0013] Solutions for solving problems

[0014] The main purpose of one embodiment of the present invention is a semiconductor element, which comprises: (a) a first external connection electrode, which is arranged on the upper surface side of a chip; (b) a second external connection electrode, which is separated from the first external connection electrode and arranged side by side with the first external connection electrode; and (c) a protective film, which covers the first external connection electrode and the second external connection electrode, and has a first opening portion that exposes a portion of the upper surface of the first external connection electrode and a second opening portion that exposes a portion of the upper surface of the second external connection electrode in a portion of the protective film, wherein the planar pattern of the first opening portion and the planar pattern of the second opening portion are rotationally symmetric about the center point of the area including the first external connection electrode and the second external connection electrode, and are asymmetric about the center line between the first external connection electrode and the second external connection electrode.

[0015] The main purpose of another embodiment of the present invention is a method for identifying a semiconductor element, which includes the following steps: (a) obtaining a planar image of a reference semiconductor element, and registering the length between the following first reference intersection and the following second reference intersection as a reference diagonal length, wherein the reference semiconductor element comprises: a first reference external connection electrode, which is arranged on the upper surface of a reference chip; a second reference external connection electrode, which has the same shape as the first reference external connection electrode and is arranged on the upper surface of the reference chip in a manner separated from the first reference external connection electrode and side by side with the first reference external connection electrode; and a reference protective film, which has a rectangular shape The first reference opening and the second reference opening are configured such that a portion of the first reference external connection electrode is exposed in the first reference opening, and a portion of the second reference external connection electrode is exposed in the second reference opening, and the first reference opening and the second reference opening are symmetrical about a center line between the first reference external connection electrode and the second reference external connection electrode, the reference protection film covers the upper surface of the reference chip, and in the planar patterns of the first reference opening and the second reference opening, the first reference intersection and the second reference intersection are located on opposite sides of the first opening and the second opening facing each other, and the first reference intersection and the second reference intersection are located about a center line including the first reference external connection electrode. (a) obtaining a planar image of a target semiconductor element, and registering a length between the first intersection and the second intersection as the target diagonal length, wherein the target semiconductor element comprises: a first external connection electrode, which is disposed on the upper surface of the target chip; a second external connection electrode, which has the same shape as the first external connection electrode and is disposed on the upper surface of the target chip in a manner separated from the first external connection electrode and arranged side by side with the first external connection electrode; and a protective film, which has a first opening portion that exposes a portion of the first external connection electrode and a second opening portion that exposes a portion of the second external connection electrode. A second opening portion through which a portion of the electrode is exposed, a protective film covers the upper surface of the target chip, in a planar pattern, the first opening portion and the second opening portion are point symmetrical about the center point of the region including the first external connection electrode and the second external connection electrode, and are asymmetrical about the center line between the first external connection electrode and the second external connection electrode, the first intersection point and the second intersection point are intersection points where the long sides and short sides of the first opening portion and the second opening portion intersect on the opposite side of the face-to-face side of the first opening portion and the second opening portion; and (c) if the difference between the target diagonal length and the reference diagonal length is greater than a pre-registered specified value, the target semiconductor element is determined to be a qualified product.

[0016] Effects of the Invention

[0017] According to the present invention, it is possible to provide a semiconductor device having different characteristics that can be easily identified during assembly and a method for identifying the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a plan view showing an example of a semiconductor element according to an embodiment of the present invention.

[0019] Figure 2 is shown as Figure 1 Schematic diagram of an enlarged cross section of a portion of a semiconductor element taken along line AA.

[0020] Figure 3 is from Figure 1 A schematic cross-sectional view of a semiconductor element obtained by cutting vertically along line BB.

[0021] Figure 4 is from Figure 1 A schematic cross-sectional view of a semiconductor element obtained by cutting vertically along line CC.

[0022] Figure 5 This is a plan view showing an example of a conventional semiconductor element used in describing the embodiment of the present invention.

[0023] Figure 6 This is a schematic diagram of a bonding apparatus used to describe an example of an assembly process of a semiconductor element according to an embodiment of the present invention.

[0024] Figure 7 This is a flowchart showing an example of a method for identifying a semiconductor element according to an embodiment of the present invention.

[0025] Figure 8 This is a flowchart showing an example of a modification of the semiconductor element identification method according to the embodiment of the present invention.

[0026] Fig. 9 This is a flowchart showing another example of a modification of the semiconductor element identification method according to the embodiment of the present invention.

[0027] Fig.10 It is a plan view showing an example of a semiconductor element according to another embodiment of the present invention.

[0028] Fig.11 It is a plan view showing another example of a semiconductor element according to another embodiment of the present invention.

[0029] Fig.12 is from Fig.11 A schematic cross-sectional view of a semiconductor element obtained by cutting vertically along line DD.

[0030] Description of Reference Numerals

[0031] 1: semiconductor substrate; 2a, 2b: lower insulating film; 3a: first resistance layer; 3b: second resistance layer; 4: interlayer insulating film; 5a: first external connection electrode; 5b: second external connection electrode; 5c: relay wiring; 6a, 6b, 6c, 6d, 6e: contact area; 7a: first protective film; 7b: second protective film; 8a, 8c, 8e: first opening; 8b, 8d, 8f: second opening; 9: facing electrodes; 10a, 10b: effective connection area; 11a, 11c, 11e: first intersection; 11b, 11d, 11f: second intersection; 30: position adjustment unit; 31: camera unit; 32: image processing unit; 33: recognition unit; 34: storage unit; 40: joining unit; 41: holding unit; 42: head; 45: input device; 46: output device. DETAILED DESCRIPTION

[0032] The following describes an embodiment of the present invention with reference to the accompanying drawings. In the description of the accompanying drawings, the same or similar parts are marked with the same or similar symbols and repeated descriptions are omitted. However, the drawings are schematic, and sometimes the relationship between thickness and plane size, the ratio of thickness of each layer, etc. are different from the actual ones. In addition, the drawings may also include parts with different dimensional relationships and ratios. In addition, the embodiments shown below are used to illustrate the devices and methods for concretizing the technical ideas of the present invention. The technical ideas of the present invention do not specify the material, shape, structure, configuration, etc. of the structural components as the following materials, shapes, structures, configurations, etc.

[0033] In addition, the definitions of up and down directions in the following description are simply selected for convenience of description and do not limit the technical concept of the present invention. For example, if the object is rotated 90° to observe, the up and down is converted to left and right for reading, and if the object is rotated 180° to observe, the up and down is reversed for reading, which is self-evident. The relationship between "front" and "back" is the same. If it is rotated 180°, the opposite terms are defined.

[0034] (Implementation Method)

[0035] <Semiconductor Components>

[0036] like Figure 1 As shown, the semiconductor element involved in the embodiment of the present invention is a resistor element having a rectangular plane pattern with a pair of first external connection electrodes 5a and second external connection electrodes 5b and relay wiring 5c ​​arranged side by side as the long side direction. As a plane pattern, the relay wiring 5c ​​is arranged between the first external connection electrode 5a and the second external connection electrode 5b. The chip size of the semiconductor element involved in the embodiment is, for example, about 2.8 mm×2.5 mm. Figure 1As shown, the first external connection electrode 5a arranged on the left side and the second external connection electrode 5b arranged on the right side are substantially similar in shape to each other. The first external connection electrode 5a and the second external connection electrode 5b are separated and arranged side by side. For example, a pair of the first external connection electrode 5a and the second external connection electrode 5b have Figure 1 The rectangular plane pattern is in the long-side direction of the vertical direction, with a length of about 2.1 mm, a width of about 1.0 mm, and a spacing of about 0.5 mm or more. Figure 1 As shown, the first resistance layer 3a, the second resistance layer 3b and the relay wiring 5c ​​also have Figure 1 A rectangular plane pattern with the up-down direction as the long side direction.

[0037] Based on the focus Figure 2 As can be seen from the partially enlarged cross-sectional view of the area of ​​the relay wiring 5c, a protective film (passivation film) 7 is disposed on a pair of first external connection electrodes 5a and second external connection electrodes 5b and the relay wiring 5c. The protective film 7 is provided with a first opening 8a for exposing a portion of the upper surface of the first external connection electrode 5a and a second opening 8b for exposing a portion of the upper surface of the second external connection electrode 5b. Figure 1 As shown, the first opening 8a and the second opening 8b are rectangular planar patterns with a length of L and a width of W. For example, the length L of the first opening 8a and the second opening 8b is about 1.9 mm, and the width W is about 0.9 mm. The portions of a pair of first external connection electrodes 5a and the second external connection electrodes 5b exposed from the first opening 8a and the second opening 8b become effective connection areas 10a and 10b that can be bonded to external connection members such as bonding wires and bonding ribbons. For example, the effective connection areas 10a and 10b are less than about 1.3 mm × 0.74 mm.

[0038] The rectangular plane pattern of the relay wiring 5c ​​is arranged on the center line CL passing through the center point CP of the chip. Moreover, the first resistor layer 3a, the second resistor layer 3b, the first external connection electrode 5a, the second external connection electrode 5b and the relay wiring 5c ​​are arranged on the plane pattern to be line symmetrical about the center line CL passing through the center point CP of the chip. That is, the plane pattern of the first resistor layer 3a, the second resistor layer 3b, the first external connection electrode 5a, the second external connection electrode 5b and the relay wiring 5c ​​is rotationally symmetrical twice about the center point CP of the chip. By having rotational symmetry, it can also be used by rotating 180° when installing the semiconductor element involved in the embodiment, thereby expanding the degree of freedom of configuration during assembly operation.

[0039] like Figure 1As shown in FIG. 1 , the first opening 8a and the second opening 8b are arranged in a plane pattern at positions that are asymmetric with respect to the center line CL passing through the center point CP of the chip and are symmetrical with respect to the center point CP of the chip. Figure 1 As shown, the upper end of the first opening 8a arranged on the left side is shifted downward by a shortened length R relative to the upper end of the second opening 8b arranged on the right side. In addition, the lower end of the first opening 8a is shifted downward by a shortened length R relative to the lower end of the second opening 8b. In the first opening 8a, the intersection of the upper side of the first opening 8a located on the side opposite to the face-to-face second opening 8b is defined as the first intersection 11a. In the second opening 8b, the intersection of the lower side of the second opening 8b located on the side opposite to the face-to-face first opening 8a is defined as the second intersection 11b. The length between the first intersection 11a and the second intersection 11b is defined as the diagonal length DL. For example, the diagonal length DL of the semiconductor element involved in the embodiment can be selected to be about 2.96 mm.

[0040] like Figure 2 to Figure 4 As shown, the semiconductor element according to the embodiment includes a first conductivity type (n - The semiconductor substrate 1 of the present invention is a semiconductor substrate 1 of the present invention, a lower insulating film (2a, 2b), a first resistance layer 3a and a second resistance layer 3b. The lower insulating film (2a, 2b) is arranged on the semiconductor substrate 1. The first resistance layer 3a and the second resistance layer 3b of the thin film are arranged on the lower insulating film (2a, 2b). The semiconductor element involved in the embodiment is preferably a resistance element as follows: for example, an insulated gate type semiconductor element such as an insulated gate bipolar transistor (IGBT) and a MIS transistor is used as a main semiconductor element, and the resistance element is used as a gate resistor of the main semiconductor element. Therefore, when used as a resistance element such as a gate resistor, although it depends on the specifications required as the resistance element, the thickness of the semiconductor substrate 1 is, for example, about 250μm to 450μm, and the resistivity of the semiconductor substrate 1 is usually selected to be a relatively low value. As the semiconductor substrate 1, for example, a silicon (Si) substrate can be used.

[0041] The following description will focus on the case where the semiconductor element according to the embodiment is used as a resistor element, but the present invention is not limited to a resistor element. Figure 2 to Figure 4 In the cross-sectional view of FIG. 1 , different symbols are marked as the lower insulating films (2a, 2b), but the lower insulating films (2a, 2b) may also be continuous and integrated components such as the back side of the drawing. Although not shown in the figure, a first conductive type (n) having a resistivity lower than that of the semiconductor substrate 1 is provided between the lower insulating films 2a and 2b on the upper part of the semiconductor substrate 1. + In addition, a second conductivity type (p -A second conductive type (p type) semiconductor substrate 1 having a resistivity lower than that of the semiconductor substrate 1 is provided on the upper portion of the semiconductor substrate 1. + Type) semiconductor region is used as the contact region.

[0042] The lower insulating film (2a, 2b) can be, for example, a field insulating film having a thickness of about 600nm to 1000nm. As the lower insulating film (2a, 2b), a silicon oxide film (SiO2 film), a silicon nitride film (Si3N4 film) or a composite film thereof can be used. As the lower insulating film (2a, 2b), an insulating film formed by a chemical vapor deposition (CVD) method using a gas of an organic silicon compound such as tetraethyl orthosilicate (TEOS) can also be used. By making the lower insulating film (2a, 2b) thicker, parasitic capacitance can be reduced.

[0043] The thickness of the first resistance layer 3a and the second resistance layer 3b is, for example, about 400nm to 600nm, and the sheet resistance of the first resistance layer 3a and the second resistance layer 3b is, for example, about 100Ω / □ to 200Ω / □. The thickness and width of the first resistance layer 3a and the second resistance layer 3b can be adjusted. Figure 1 Depth direction) and length ( Figure 1 The resistance value of the first resistance layer 3a and the second resistance layer 3b can be controlled by the material of the first resistance layer 3a and the second resistance layer 3b. As the first resistance layer 3a and the second resistance layer 3b, for example, polysilicon to which n-type impurities are added (doped polysilicon: DOPOS) can be used. The n-type DOPOS can be formed by adding impurity elements such as phosphorus (P) and boron (B) to the polysilicon by ion implantation, or by depositing polysilicon by CVD while adding impurity elements from the gas phase using a doping gas. In the case of using DOPOS for the first resistance layer 3a and the second resistance layer 3b, the resistance value of the first resistance layer 3a and the second resistance layer 3b can also be controlled by adjusting the amount of impurity elements added to the polysilicon.

[0044] Preferably, the temperature coefficient of the first resistance layer 3a and the second resistance layer 3b is 0 ppm / °C, or the first resistance layer 3a and the second resistance layer 3b have a negative temperature coefficient. Thus, the increase in resistance value during high temperature operation can be suppressed. For example, when the semiconductor element involved in the embodiment is applied to the gate resistor of an IGBT, the loss when the IGBT is turned on can be suppressed. The temperature coefficient of DOPOS can be controlled by adjusting the dose when ion implantation of impurities into polysilicon. For example, if the dose is set to 7.0×10 15 cm -2The temperature coefficient of DOPOS can be made below 0 ppm / ° C. Furthermore, the temperature coefficients of the first and second resistor layers 3a and 3b do not necessarily need to be limited to below 0 ppm / ° C. The first and second resistor layers 3a and 3b may also have positive temperature coefficients.

[0045] The first resistance layer 3a and the second resistance layer 3b are not limited to DOPOS, but may also be tantalum nitride (TaN x ) or a laminated film of a high melting point metal film laminated in the order of chromium (Cr)-nickel (Ni)-manganese (Mn). The first resistor layer 3a and the second resistor layer 3b may also use a thin film of silver palladium (AgPd), ruthenium oxide (RuO2), etc. In addition, although different from Figure 2 to Figure 4 Although the configuration shown is not limited to the configuration shown in the figure, the first resistance layer 3a and the second resistance layer 3b can also be realized by using a p-type diffusion layer or an n-type diffusion layer formed on the surface of the semiconductor.

[0046] An interlayer insulating film 4 is arranged to cover the lower insulating film (2a, 2b), the first resistance layer 3a and the second resistance layer 3b. The thickness of the interlayer insulating film 4 is, for example, about 1000nm to 2000nm. As the interlayer insulating film 4, a silicon oxide film (SiO2 film) containing no impurities, which is called "NSG film", a silicon oxide film (PSG film) to which phosphorus is added, a silicon oxide film (BSG film) to which boron is added, etc. can be used. In addition, a single layer of a silicon oxide film (BPSG film) or a silicon nitride film (Si3N4 film) to which phosphorus and boron are added, or a composite film in which a plurality of types thereof are selected and combined can be used as the interlayer insulating film 4. For example, the interlayer insulating film 4 can be composed of a composite film in which an NSG film of about 500nm to 800nm ​​and a PSG film of about 400nm to 800nm ​​are stacked. The NSG film has the function of suppressing resistance deviation. In addition, the PSG film has the function of ensuring the strength of wire bonding.

[0047] like Figure 2 As shown in the partially enlarged cross-sectional view, a pair of first external connection electrodes 5a and second external connection electrodes 5b and a relay wiring 5c ​​are arranged on the interlayer insulating film 4. The first external connection electrode 5a is located above the lower insulating film 2a, and the horizontal position of the end of the first external connection electrode 5a overlaps with one end of the first resistor layer 3a in the depth direction. The second external connection electrode 5b is located above the lower insulating film 2b, and the horizontal position of the end of the second external connection electrode 5b overlaps with one end of the second resistor layer 3b in the depth direction. The relay wiring 5c ​​is extended from above the lower insulating film 2a to above the lower insulating film 2b in a manner sandwiched by a pair of first external connection electrodes 5a and second external connection electrodes 5b, and is arranged as follows: Figure 2 The cross-sectional structure shown is a shape close to a T-shape.

[0048] The first external connection electrode 5a is connected to one end of the first resistor layer 3a via the contact region 6a. At the other end of the first resistor layer 3a, a resistor layer connection terminal as one end of the relay wiring 5c ​​is connected via the contact region 6b. The second external connection electrode 5b is connected to one end of the second resistor layer 3b via the contact region 6c. At the other end of the second resistor layer 3b, a resistor layer connection terminal as the other end of the relay wiring 5c ​​is connected via the contact region 6d. The substrate connection terminal as the central end of the T-shaped relay wiring 5c ​​is connected to the n-type terminal provided on the upper part of the semiconductor substrate 1 via the contact region 6e. + The type contact area (not shown) is ohmically connected with low contact resistance. An opposing electrode 9 is provided on the back of the semiconductor substrate 1. That is, the first resistance layer 3a and the second resistance layer 3b are connected in series with the semiconductor substrate 1 via the relay wiring 5c, realizing a longitudinal semiconductor element with the first external connection electrode 5a and the opposing electrode 9 and the second external connection electrode 5b and the opposing electrode 9 as resistors.

[0049] The thickness of a pair of first external connection electrodes 5a, second external connection electrodes 5b and relay wiring 5c ​​is, for example, about 3 μm. The first external connection electrode 5a, second external connection electrode 5b and relay wiring 5c ​​can be composed of a stacked film of titanium / titanium nitride (Ti / TiN) of about 100nm to 130nm as a barrier metal, aluminum-silicon (Al-Si) of about 3μm, and TiN / Ti of about 35nm to 55nm as an anti-reflection film. Instead of Al-Si, Al alloys such as Al, Al-Cu-Si, and Al-Cu can also be used. A pair of first external connection electrodes 5a and second external connection electrodes 5b respectively constitute electrode pads for output (mounting). A bonding wire with a diameter of about 200μm to 400μm formed of a metal such as aluminum (Al) is connected to the first external connection electrode 5a and the second external connection electrode 5b.

[0050] Although not shown in the figure, a guard ring layer may be arranged on the interlayer insulating film 4. The guard ring layer is formed of the same material as the first external connection electrode 5a, the second external connection electrode 5b and the relay wiring 5c. The guard ring layer is arranged in a ring shape, for example, on the outer peripheral portion of the chip constituting the semiconductor element involved in the embodiment. The guard ring layer is ohmically connected to the semiconductor substrate 1 via the contact area.

[0051] like Figure 2 to Figure 4As shown, a protective film (passivation film) 7 is arranged on the first external connection electrode 5a, the second external connection electrode 5b and the relay wiring 5c. As the protective film 7, for example, it can be composed of a composite film in which a first protective film 7a such as a TEOS film or a Si3N4 film and a second protective film 7b such as a polyimide film are stacked. A first opening 8a and a second opening 8b are respectively provided in the protective film 7. For example, a Si3N4 film is deposited by a plasma CVD method and a polyimide film is applied, thereby forming a protective film 7 including a first protective film 7a and a second protective film 7b. Next, the polyimide film is selectively removed by photolithography technology and wet etching technology, thereby forming an opening that exposes the surface of the Si3N4 film. Next, the Si3N4 film is selectively removed at the opening that exposes the Si3N4 film by photolithography technology and dry etching technology, thereby forming an opening that exposes the surface of the first external connection electrode 5a and the second external connection electrode 5b. As a result, as shown in FIG. Figure 2 to Figure 4 As shown, the first opening 8a and the second opening 8b are formed as follows: at the ends of the first opening 8a and the second opening 8b, the second protective film 7b formed of the polyimide film is retreated, and the first protective film 7a formed of the Si3N4 film is protruded. The portion of the first external connection electrode 5a exposed from the first opening 8a and the portion of the second external connection electrode 5b exposed from the second opening 8b respectively become the pad area for mounting that can be connected to the bonding wire.

[0052] like Figure 2 to Figure 4 As shown, an opposing electrode 9 is disposed on the lower surface of the semiconductor substrate 1. The opposing electrode 9 can be formed of, for example, a single-layer film formed of gold (Au), or a metal film stacked in the order of titanium (Ti), nickel (Ni), and gold (Au). The outermost layer of the opposing electrode 9 can be formed of a material that can be welded. The opposing electrode 9 is fixed to a metal plate or the like by welding or the like.

[0053] When the semiconductor element according to the embodiment is a resistor element, Figure 2 As shown, the following structure is used as the basis: the resistor layer connection terminals at both ends of the T-shaped relay wiring 5c ​​are connected to the first resistor layer 3a and the second resistor layer 3b. In addition, the substrate connection terminal as the terminal on the central side of the T-shaped relay wiring 5c ​​is connected to the n-type resistor layer 3a provided on the semiconductor substrate 1. +The type contact area (not shown) is ohmically connected with low contact resistance to form a vertical semiconductor element. Therefore, an external connection area (pad area) for installation composed of a first external connection electrode 5a connected to the first resistor layer 3a is allocated to the first resistor layer 3a. An external connection area (pad area) for installation composed of a second external connection electrode 5b connected to the second resistor layer 3b is allocated to the second resistor layer 3b. Therefore, according to the semiconductor element involved in the embodiment, the number of bonding wires for each of the first resistor layer 3a and the second resistor layer 3b is 1, and the number of bonding wires can be reduced compared to the horizontal semiconductor element. In addition, compared to the horizontal semiconductor element, the area occupied by the external connection area (pad area) for installation on the upper surface side can be reduced, so the chip size can be reduced.

[0054] Figure 5 The plane pattern of a common semiconductor element is shown in FIG. The length and width of the first resistance layer 3c and the second resistance layer 3d of a common semiconductor element are different from the length and width of the first resistance layer 3a and the second resistance layer 3b, so the resistance values ​​are different. Figure 5 As shown, a pair of first openings 8c and second openings 8d are provided in the protective film 7 to partially expose the first external connection electrode 5a and the second external connection electrode 5b. The first opening 8c and the second opening 8d are rectangular plane patterns with a length of Lx and a width of W, and are similar in shape. The first opening 8c and the second opening 8d are arranged in the plane pattern at positions that are linearly symmetrical about the center line CL passing through the center point CP of the chip and are rotationally symmetrical twice about the center point CP of the chip. In the first opening 8c, the intersection of the upper corner of the first opening 8c located on the side opposite to the face-to-face second opening 8d is set as the first intersection 11c. In the second opening 8d, the intersection of the lower corner of the second opening 8d located on the side opposite to the face-to-face first opening 8c is set as the second intersection 11d. The length between the first intersection 11c and the second intersection 11d is the diagonal length DLx. For example, the length Lx of the first opening 8c and the second opening 8d is about 2.0 mm, the width W is about 0.9 mm, and the diagonal length DLx is about 3.08 mm.

[0055] On the other hand, Figure 1In the semiconductor element involved in the embodiment shown, the first opening 8a and the second opening 8b are arranged in a plane pattern at positions that are twice rotationally symmetrical about the center point CP of the chip. However, the first opening 8a and the second opening 8b are asymmetrical about the center line CL passing through the center point CP of the chip. In this way, the plane pattern of the semiconductor element involved in the embodiment is different from the plane pattern of the conventional semiconductor element. The first opening 8a and the second opening 8b of the semiconductor element involved in the embodiment each have a length L, while the first opening 8c and the second opening 8d of the conventional semiconductor element each have a length Lx, which is different in this point. That is, the length L of each of the first opening 8a and the second opening 8b is shortened by a shortened length R compared to the length Lx of each of the first opening 8c and the second opening 8d.

[0056] For example, in a semiconductor element assembled into a semiconductor device such as a power module, the resistance value varies depending on the use of the semiconductor device. In order to produce a target semiconductor element with a different resistance value, the width and length of the resistance layer are adjusted relative to the previous reference semiconductor element, but the chip size, manufacturing process, assembly process, etc. are the same. The target semiconductor element and the reference semiconductor element are manufactured using different wafers, so they are not mixed in the manufacturing process. However, the following situation is also considered: in the assembly process, for example, when the tray providing the semiconductor element is wrong or the management is poor, the reference semiconductor element is mixed into the target semiconductor element as a defective product. Therefore, it is desired to detect the mixed defective products at the stage of the assembly process.

[0057] For example, in the assembly process, a wafer having a large number of semiconductor elements formed thereon is cut into a large number of chips by dicing or the like. A circuit substrate such as an insulating circuit board on which the chips having semiconductor elements are arranged is provided to a bonding device. Figure 6 As shown in FIG. 1 , the bonding device includes a bonding unit 40, a position adjustment unit 30, an input device 45, and an output device 46. The bonding unit 40 includes a holding unit 41 for holding a chip and a head 42 for performing wire bonding. The position adjustment unit 30 includes an imaging unit 31 for capturing a chip image, an image processing unit 32 for performing image processing on the chip image, an identification unit 33 for identifying the chip, and a storage unit 34 for storing the results of image processing and identification. The input device 45 transmits the input operation performed by the operator to the position adjustment unit. The output device 46 displays the image obtained by the position adjustment unit 30, the data to be processed, and the like.

[0058] The camera device used in the camera section 31 of the position adjustment unit 30 is a low-resolution camera device. Although it is not suitable for reliably identifying the difference in plane patterns through images of about hundreds of μm, it is possible to identify the difference in image contrast. In addition, it is possible to obtain images of a range of about hundreds of μm in diameter, register base points and measure the distance between base points. In addition, when a semiconductor element is bonded to a wiring substrate or the like using a bonding member, the semiconductor element sometimes tilts due to the uneven thickness of the bonding member. In the case where the semiconductor element is tilted like this, an error occurs in the measurement. Although it varies depending on the bonding device, for example, if the difference in the distance between the base points of two plane patterns is 50 μm or more, the two plane patterns can be identified as different plane patterns.

[0059] As described above, in the chip of the semiconductor element, the first opening 8a and the second opening 8b as the effective connection area are surrounded by the first protective film 7a formed of the Si3N4 film. The contrast difference between the metal surface of the first opening 8a and the second opening 8b and the surrounding Si3N4 film can be identified by the camera unit 31. In the embodiment, the image is obtained respectively including Figure 1 The images of the first intersection 11a and the second intersection 11b are shown, and the first intersection 11a and the second intersection 11b are registered as base points. Then, the distance between the first intersection 11a and the second intersection 11b is registered as the diagonal length DL. In addition, the diagonal length DL of the semiconductor element involved in the embodiment is about 2.96mm. The diagonal length DLx of the conventional semiconductor element is about 3.08mm. The difference in diagonal length is about 120μm, which can be identified as different chips.

[0060] In the semiconductor element involved in the embodiment, the first opening 8a and the second opening 8b having similar shapes are arranged at positions that are non-line symmetrical about the center line CL of the chip and are twice rotationally symmetrical about the center point CP of the chip. The first opening 8a and the second opening 8b are arranged so that the positions in the long-side direction are staggered from each other. The diagonal length DL between the first intersection 11a and the second intersection 11b of the plane image pattern of the first opening 8a and the second opening 8b is changed according to the resistance value. Therefore, it becomes easy to recognize the difference in the characteristics of the semiconductor element.

[0061] In order to recognize the three plane patterns as different plane patterns, all (three) distances between base points of two plane patterns selected from the three plane patterns need to be set to be larger than 50 μm.

[0062] <Method of Identifying Semiconductor Components>

[0063] Reference Figure 7An example of a method for identifying a semiconductor element according to an embodiment of the present invention is described with reference to the flowchart shown in FIG. Figure 6 The illustrated engagement device implements Figure 5 The conventional semiconductor element assembly process of the planar pattern is shown in FIG. Figure 1 The semiconductor element according to the embodiment of the planar pattern is shown as a new semiconductor element having a resistance value different from that of a conventional semiconductor element.

[0064] exist Figure 7 In step S100, a conventional semiconductor device chip is provided to the bonding device and placed on the holding portion 41 of the bonding unit 40. The image processing portion 32 specifies the position of the semiconductor device using the image acquired by the imaging portion 31 of the position adjustment unit 30. Figure 5 The positions of the first intersection point 11c and the second intersection point 11d are detected and registered in the storage unit 34. The distance between the registered first intersection point 11c and the second intersection point 11d is detected and registered in the storage unit 34 as a reference diagonal length DLx.

[0065] In step S101, the semiconductor element according to the embodiment is provided as a target chip to the bonding device. In step S102, the target chip is placed on the holding portion 41 of the bonding unit 40. The image processing unit 32 specifies the target chip using the image acquired by the imaging unit 31 of the position adjustment unit 30. Figure 1 The positions of the first intersection 11a and the second intersection 11b are detected and registered in the storage unit 34. In step S103, the distance between the registered first intersection 11a and the second intersection 11b is detected and registered in the storage unit 34 as the target diagonal length DL.

[0066] In step S104, the diagonal length difference between the object diagonal length DL and the reference diagonal length DLx is calculated by the recognition unit 33 of the position adjustment unit 30. If the diagonal length difference is greater than the specified value, it is recognized as a qualified product in step S105 and bonding is performed. As the specified value for the diagonal length difference, 50 μm is used. If the diagonal length difference is less than the specified value, it is recognized as a chip that was mixed in by mistake in step S106.

[0067] In the identification method of the semiconductor element involved in the embodiment, the first intersection 11a and the second intersection 11b of the plane image pattern of the first opening 8a and the second opening 8b of the bonding pad with a large difference in contrast are specified. In addition, the first opening 8a and the second opening 8b of similar shape are arranged at a position that is non-linearly symmetrical about the center line CL of the chip and is twice rotationally symmetrical about the center point CP of the chip. The first opening 8a and the second opening 8b are arranged so that the positions in the long side direction are staggered from each other. Therefore, compared with the conventional semiconductor element, the diagonal length DL can be easily shortened, and it becomes easy to identify the difference in characteristics.

[0068] <Modification of the method for identifying a semiconductor element>

[0069] In the above, a case is shown in which the resistance value of a new semiconductor element having a resistance value different from that of a conventional semiconductor element is 1. However, there is also a case in which the resistance value of the new semiconductor element is 2 or more. In the case of distinguishing a new semiconductor element from other new semiconductor elements and conventional semiconductor elements, for example, in the case of 3 types of resistance values, the new semiconductor element is manufactured in such a manner that the diagonal length DL of each semiconductor element differs from the diagonal length DL of other semiconductor elements by more than 50 μm. For example, the diagonal length DL of a new semiconductor element differs from the diagonal length of conventional semiconductor elements by 100 μm, and the diagonal length DL of other new semiconductor elements differs from the diagonal length of conventional semiconductor elements by 200 μm. Below, refer to Figure 8 and Fig. 9 The flowchart shown is used to illustrate two modified examples of the identification method.

[0070] First, explain Figure 8 In step S200, three types of semiconductor elements with different resistance values, namely, two new semiconductor elements and a conventional semiconductor element, are placed on the chip. Figure 6 The holding portion 41 of the bonding unit 40. For each chip of the semiconductor element with different resistance values, Figure 7 Similarly, in step S100, the image processing unit 32 detects the reference diagonal length DLx using the image acquired by the imaging unit 31 of the position adjustment unit 30. Each detected reference diagonal length DLx is registered in the storage unit 34.

[0071] Next, in step S201, one semiconductor element to be identified among three types of semiconductor elements having different resistance values, for example Figure 1 The semiconductor element shown in FIG. 1 is taken as the target chip, and the reference diagonal length of the target chip is registered. Then, in step S202, the chip of the semiconductor element as the identification target is provided to Figure 6 In step S203, Figure 7 Similarly, in step S102, specify Figure 1 The positions of the first intersection 11a and the second intersection 11b are registered in the storage unit 34. In step S204, Figure 7 Similarly, in step S103 , the distance between the registered first intersection point 11 a and the second intersection point 11 b is detected and registered in the storage unit 34 as the target diagonal length DL.

[0072] In step S205, the recognition unit 33 of the position adjustment unit 30 calculates the diagonal length difference between the target diagonal length DL and the reference diagonal length DLx other than the reference diagonal length of the target semiconductor element. If all the calculated diagonal length differences are greater than the specified value, they are identified as qualified products in step S206 and bonded by the bonding device. As the specified value for the diagonal length difference, 50 μm is used. Even if there is one diagonal length difference less than the specified value, it is identified as a chip that was mis-taken and mixed in in step S207.

[0073] Next, explain Fig. 9 The semiconductor component identification method shown. Fig. 9 Steps S210 to S214 shown are similar to Figure 8 Steps S200 to S204 shown are the same, so their description is omitted.

[0074] In step S215, the recognition unit 33 of the position adjustment unit 30 calculates the diagonal length difference between the target diagonal length DL and the reference diagonal length DLx of the target semiconductor element. If the diagonal length difference is less than a predetermined value, the semiconductor element is identified as a qualified product in step S216. Figure 6 The bonding is performed by a bonding apparatus. 50 μm is used as a predetermined value for the diagonal length difference. If the diagonal length difference is greater than the predetermined value, the chip is identified as a chip that has been mixed in by mistake in step S217.

[0075] In a variation of the embodiment, Figure 8 and Fig. 9 As shown in the figure, the identification method of three types of semiconductor elements with different characteristics is exemplified, but it can also be applied to the identification method of two types of semiconductor elements or four or more types of semiconductor elements.

[0076] (Other embodiments)

[0077] As described above, the present invention is described by citing a resistor element as an example, but it should not be understood that the discussion and drawings of the embodiments and the like constituting a part of the specification are used to limit the present invention. Those skilled in the art should be able to clearly understand various alternative embodiments, examples, and application technologies based on the disclosure of the specification and drawings of the present invention.

[0078] In the embodiment, a case where a new semiconductor element is added to a conventional semiconductor element assembly line is described. However, sometimes multiple types of semiconductor elements having the same chip size but different resistance values ​​are added. Figure 1 As shown, the length L of the long side of each of the rectangular first opening 8a and the second opening 8b is shortened by the shortened length R to achieve a diagonal length DL shorter than the diagonal length DLx of the conventional semiconductor element. Figure 1 The effective connection areas 10a, 10b shown in the figure, therefore, the shortening of the length L of the long side of the opening is limited. In this case, for example, Fig.10 As shown, as a plane pattern, a concave portion facing the inside of the first opening 8e is provided at the upper left corner of the first opening 8e, the length of the concave portion in the long side direction is Lz, the width in the short side direction is Wz, and there is a first intersection 11e. Similarly, as a plane pattern, a concave portion facing the inside of the second opening 8f is provided at the lower right corner of the second opening 8f, the length of the concave portion in the long side direction is Lz, the width in the short side direction is Wz, and there is a second intersection 11f. The distance between the first intersection 11e and the second intersection 11f is set as the diagonal length DLy. Figure 5 The diagonal length DLx of the semiconductor element shown is about 3.08 mm. Figure 1 The diagonal length DL of the semiconductor element shown is about 2.96 mm. Figure 8 The diagonal length DLy of the semiconductor element shown is 2.29 mm, so that the semiconductor element described above can be identified.

[0079] In addition, as the semiconductor element involved in the embodiment, the following is exemplified. Figure 1 and Figure 2 As shown in FIG. 1 , the resistor element is a vertical structure connected to the semiconductor substrate 1 via the relay wiring 5c, but it can also be a horizontal structure in which the relay wiring 5c ​​is omitted. Fig.11 and Fig.12 As shown in FIG. 1 , the length of each long side Ly of the rectangular first opening 8g and the second opening 8h is shortened by the shortened length Ry to realize a lateral structure having a diagonal length DLz shorter than the diagonal length DLx of a conventional semiconductor element. In a lateral structure resistor element, Fig.12 As shown in the cross-sectional view of FIG. 1 , not only the relay wiring 5c ​​is omitted, but also no Figure 2 The structure shown includes the lower insulating film 2b and the second resistance layer 3b. In the case of a lateral structure, when the lower surface of the semiconductor substrate 1 is bonded and mounted on a circuit board or the like using an adhesive or the like, the counter electrode 9 can be omitted.

[0080] Thus, as long as the purpose of the disclosure of the above-mentioned embodiments is understood, those skilled in the art should be able to clearly understand that the present invention can include various alternative embodiments, examples, and application technologies. Alternatively, it is self-evident that the present invention includes various embodiments that are not described herein, such as structures obtained by arbitrarily applying the structures described in the above-mentioned embodiments and various modifications. Therefore, the technical scope of the present invention is determined only by the technical features of the invention involved in the claims that are appropriate based on the above-mentioned illustrative description.

Claims

1. A semiconductor element, characterized in that: have: a first external connection electrode disposed on the upper surface side of the chip; a second external connection electrode, which is separated from the first external connection electrode and arranged side by side with the first external connection electrode; as well as a protective film covering the first external connection electrode and the second external connection electrode, wherein a portion of the protective film has a first opening portion exposing a portion of the upper surface of the first external connection electrode and a second opening portion exposing a portion of the upper surface of the second external connection electrode, wherein the planar pattern of the first opening and the planar pattern of the second opening are twice rotationally symmetric about the center point of the region including the first external connection electrode and the second external connection electrode, and are asymmetric about the center line between the first external connection electrode and the second external connection electrode, In the first opening portion, the intersection point on the upper side of the first opening portion located on the opposite side to the second opening portion facing each other is defined as a first intersection point; in the second opening portion, the intersection point on the lower side of the second opening portion located on the opposite side to the first opening portion facing each other is defined as a second intersection point; the length between the first intersection point and the second intersection point is defined as a diagonal length; wherein the difference in characteristics of the semiconductor element can be identified based on the diagonal length.

2. The semiconductor device according to claim 1, characterized in that The first opening and the second opening are rectangular in shape, and positions of ends of the first opening and the second opening are different in the longitudinal direction of the first opening and the second opening.

3. The semiconductor device according to claim 1, wherein: Inwardly directed recessed portions are provided at corners of the planar patterns of the first opening and the second opening.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: Also available: a semiconductor substrate forming a part of the chip; a lower insulating film disposed on the semiconductor substrate; a first resistance layer disposed on the lower insulating film; a second resistance layer, which is disposed on the lower insulating film, separated from the first resistance layer and arranged side by side with the first resistance layer; an interlayer insulating film covering the first resistance layer and the second resistance layer; a relay wiring connected to the first resistance layer and the second resistance layer respectively, and ohmically connected to the semiconductor substrate; as well as an opposite electrode disposed under the semiconductor substrate, wherein the first external connection electrode is arranged on the interlayer insulating film in a manner connected to the first resistance layer, The second external connection electrode is arranged on the interlayer insulating film so as to be connected to the second resistance layer.

5. A method for identifying a semiconductor component, characterized in that: The following steps are involved: A planar image of a reference semiconductor element is acquired, and a length between the first reference intersection and the second reference intersection is registered as a reference diagonal length, wherein the reference semiconductor element comprises: a first reference external connection electrode, which is arranged on the upper surface of a reference chip; a second reference external connection electrode, which has the same shape as the first reference external connection electrode and is arranged on the upper surface of the reference chip in a manner separated from the first reference external connection electrode and side by side with the first reference external connection electrode; and a reference protective film, which has a first reference opening portion and a second reference opening portion in a rectangular shape, wherein the first reference opening portion exposes a portion of the first reference external connection electrode, and the second reference opening portion exposes a portion of the first reference external connection electrode. The opening exposes a portion of the second reference external connection electrode, and the first reference opening is symmetrical to the second reference opening about a center line between the first reference external connection electrode and the second reference external connection electrode, the reference protection film covers the upper surface of the reference chip, and in a planar pattern of the first reference opening and the second reference opening, the first reference intersection and the second reference intersection are located on opposite sides of a side facing each other of the first reference opening and the second reference opening, and the first reference intersection and the second reference intersection are rotationally symmetrical twice about a center point of a region including the first reference external connection electrode and the second reference external connection electrode; Acquire a planar image of a target semiconductor element, and register a length between the following first intersection and the following second intersection as the target diagonal length, wherein the target semiconductor element comprises: a first external connection electrode, which is arranged on the upper surface of the target chip; a second external connection electrode, which has the same shape as the first external connection electrode and is arranged on the upper surface of the target chip in a manner separated from the first external connection electrode and parallel to the first external connection electrode; and a protective film, which has a first opening portion that exposes a portion of the first external connection electrode and a second opening portion that exposes a portion of the second external connection electrode, the protective film covering the upper surface of the target chip, in which, in a planar pattern, the first opening portion and the second opening portion are point-symmetrical about a center point of a region including the first external connection electrode and the second external connection electrode, and are asymmetrical about a center line between the first external connection electrode and the second external connection electrode, and the first intersection point and the second intersection point are intersection points where the long sides and short sides of the first opening portion and the second opening portion intersect on the opposite side of the face-to-face sides of the first opening portion and the second opening portion; and If the difference between the target diagonal length and the reference diagonal length is equal to or larger than a predetermined value registered in advance, it is determined that the target semiconductor element is a non-defective product.

6. A method for identifying a semiconductor element, which is a method for identifying a plurality of semiconductor elements having different characteristics and having different diagonal lengths between the first intersection and the second intersection, wherein the plurality of semiconductor elements respectively include: a first external connection electrode provided on an upper surface of each of the plurality of semiconductor elements; a second external connection electrode having the same shape as that of the first external connection electrode and disposed on the upper surface of each of the plurality of semiconductor elements in a manner separated from and arranged in parallel with the first external connection electrode; and a protective film having a first opening portion exposing a portion of the first external connection electrode and a second opening portion exposing a portion of the second external connection electrode, the protective film covering the upper surface of the semiconductor element, wherein, in a planar pattern of the first opening portion and the second opening portion, the first intersection and the second intersection are located on the opposite side of the first opening portion and the second opening portion facing each other, and are rotationally symmetrical twice about a center point of a region including the first external connection electrode and the second external connection electrode, the identification method of the semiconductor element is characterized in that it includes the following steps: Acquire planar images for each of the plurality of semiconductor elements, and pre-register the diagonal length as a reference diagonal length; registering one semiconductor element among the plurality of semiconductor elements as a target semiconductor element; providing a new chip of the target semiconductor element, acquiring a planar image of the chip, and registering the diagonal length as the target diagonal length; and If the difference between the reference diagonal length other than the reference diagonal length of the target semiconductor element and the target diagonal length is greater than a predetermined value registered in advance, the target semiconductor element is determined to be a non-defective product.

7. A method for identifying a semiconductor element, which is a method for identifying a plurality of semiconductor elements having different characteristics and having different diagonal lengths between the first intersection and the second intersection, wherein the plurality of semiconductor elements respectively include: a first external connection electrode provided on an upper surface of each of the plurality of semiconductor elements; a second external connection electrode having the same shape as that of the first external connection electrode and disposed on the upper surface of each of the plurality of semiconductor elements in a manner separated from and arranged in parallel with the first external connection electrode; and a protective film having a first opening portion exposing a portion of the first external connection electrode and a second opening portion exposing a portion of the second external connection electrode, the protective film covering the upper surface of the semiconductor element, wherein, in a planar pattern of the first opening portion and the second opening portion, the first intersection and the second intersection are located on the opposite side of the first opening portion and the second opening portion facing each other, and are rotationally symmetrical twice about a center point of a region including the first external connection electrode and the second external connection electrode, the identification method of the semiconductor element is characterized in that it includes the following steps: Acquire planar images for each of the plurality of semiconductor elements, and pre-register the diagonal length as a reference diagonal length; registering one semiconductor element among the plurality of semiconductor elements as a target semiconductor element; providing a new chip of the target semiconductor element, acquiring a planar image of the chip, and registering the diagonal length as the target diagonal length; and If the difference between the target diagonal length and the reference diagonal length of the target semiconductor element is smaller than a predetermined value registered in advance, it is determined that the target semiconductor element is a non-defective product.

8. The semiconductor device identification method according to any one of claims 5 to 7, characterized in that: The first opening and the second opening are rectangular in shape, and positions of ends of the first opening and the second opening are different in the longitudinal direction of the first opening and the second opening.

9. The semiconductor device identification method according to any one of claims 5 to 7, characterized in that: The first intersection point and the second intersection point are respectively provided at positions in the planar pattern where corners of the first opening and the second opening face inward to form recessed portions.

10. The semiconductor device identification method according to any one of claims 5 to 7, characterized in that: The prescribed value is 50 μm.

Images