Semiconductor Devices

Abstract

A semiconductor package is disclosed, comprising: a substrate; a semiconductor chip on the substrate; a molding layer on the substrate, covering the semiconductor chip; and a shielding layer on the molding layer. The shielding layer comprises a polymer, in which a plurality of conductive structures and a plurality of nanostructures are distributed, wherein at least some of the conductive structures are connected to each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0163464 filed in the Korean Intellectual Property Office on December 17, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a shielding layer. Background Art

[0004] Semiconductor packages are provided to implement integrated circuit chips that are qualified for use in electronic products. Semiconductor packages are generally configured such that the semiconductor chip is mounted on a printed circuit board (PCB), and bonding wires or bump pads are used to electrically connect the semiconductor chip to the PCB. When inspecting a semiconductor package including a semiconductor chip, electromagnetic interference may occur between the semiconductor package and other electronic devices. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide a semiconductor package having improved reliability.

[0006] The objects of the inventive concept are not limited to the above contents, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0007] According to some example embodiments, a semiconductor package is provided, which may include: a substrate; a memory chip on the substrate; a molding layer on the substrate, covering the semiconductor chip; and a shielding layer on the molding layer. The shielding layer may include a polymer, in which a plurality of conductive structures and a plurality of nanostructures are distributed, wherein at least some of the conductive structures are connected to each other.

[0008] According to some example embodiments, a semiconductor package is provided, which may include: a substrate; a memory chip on the substrate; a molding layer on the substrate, covering the semiconductor chip; and a shielding layer on the molding layer. The shielding layer may include a plurality of electromagnetic wave shielding structures and a plurality of X-ray shielding structures.

[0009] According to some example embodiments, a semiconductor package is provided, which may include: a substrate; a memory chip on the substrate; a molding layer on the substrate and covering the semiconductor chip; and a shielding layer on the molding layer. The shielding layer may include: a plurality of conductive structures connected to each other; and a plurality of first nanostructures in the shielding layer. The first nanostructure may include a semiconductor material. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1AIllustrated is a plan view showing a semiconductor package according to some example embodiments.

[0011] Figure 1B The diagram shows Figure 1A A cross-sectional view taken along line AB.

[0012] Figure 1C The diagram shows Figure 1B An enlarged view of portion C of FIG.

[0013] Figure 1D Illustrated are cross-sectional views showing a shielding layer according to some example embodiments.

[0014] Figure 1E Illustrated are cross-sectional views showing a shielding layer according to some example embodiments.

[0015] Figure 2A Illustrated are cross-sectional views showing a shielding layer according to some example embodiments.

[0016] Figure 2B Illustrated are cross-sectional views showing a shielding layer according to some example embodiments.

[0017] Figure 2C Illustrated are cross-sectional views showing a shielding layer according to some example embodiments.

[0018] FIG. 3A to FIG. 3B Illustrated is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to some example embodiments.

[0019] Figure 3C The diagram shows Figure 3B An enlarged view of portion C of FIG.

[0020] Figure 4A Illustrated is a cross-sectional view showing a semiconductor package according to some example embodiments.

[0021] Figure 4B Illustrated is a cross-sectional view showing a semiconductor package according to some example embodiments. DETAILED DESCRIPTION

[0022] It will be understood that when an element or layer is referred to as being "above," "over," "on," "connected to," or "coupled to" another element or layer, it may be directly above, above, on, directly connected to, or coupled to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly above," "over," "on," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. Throughout the accompanying drawings, the same reference numerals represent the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] In this specification, the same reference numerals may denote the same components. A semiconductor package and a method of manufacturing the same according to some example embodiments will be described below.

[0024] Figure 1A Illustrated is a plan view showing a semiconductor package according to some example embodiments. Figure 1B The diagram shows Figure 1A A cross-sectional view taken along line AB.

[0025] refer to Figure 1A and Figure 1B , the semiconductor package 1 may include a substrate 100, a semiconductor chip 200, a molding layer 300, and a shielding layer 400. The substrate 100 may be a printed circuit board (PCB), a semiconductor substrate, a redistribution layer, or a flexible substrate. The substrate 100 may include a dielectric layer 110, substrate pads 140S and 140G, a ground structure 120G, a signal structure 120S, and terminals 130G and 130S. The dielectric layer 110 may include a silicon-based dielectric material or a polymer. Although not shown, the dielectric layer 110 may include a plurality of layers.

[0026] Substrate pads 140G and 140S may be disposed on a top surface of dielectric layer 110. The top surface of dielectric layer 110 may correspond to top surface 100a of substrate 100. Substrate pads 140G and 140S may include ground substrate pads 140G and signal substrate pads 140S spaced apart from each other. Signal substrate pads 140S may be insulated from ground substrate pads 140G. Substrate pads 140G and 140S may include a conductive material, such as metal.

[0027] The terminals 130G and 130S may be disposed on the bottom surface of the dielectric layer 110. The bottom surface of the dielectric layer 110 may correspond to the bottom surface of the substrate 100. The terminals 130G and 130S may include a conductive material and have a solder ball shape. The terminals 130G and 130S may include a ground terminal 130G and a signal terminal 130S spaced apart from each other. The ground terminal 130G may be insulated from the signal terminal 130S. The ground terminal 130G may be configured to receive a ground voltage.

[0028] The ground structure 120G may be disposed in the dielectric layer 110. The ground structure 120G may include a lower ground via 121G, a ground pattern 123G, and an upper ground via 125G. The dielectric layer 110 may include a plurality of layers, and the ground pattern 123G may be inserted between the plurality of layers. A portion of the ground pattern 123G may be exposed on one surface of the substrate 100. For example, the ground pattern 123G may be exposed on the side surface 100c of the substrate 100. The upper ground via 125G may be inserted between the ground pattern 123G and the ground substrate pad 140G, and coupled to the ground pattern 123G and the ground substrate pad 140G. The lower ground via 121G may be inserted between the ground pattern 123G and the ground terminal 130G, and coupled to the ground pattern 123G and the ground terminal 130G. Therefore, the ground substrate pad 140G may be coupled to the ground terminal 130G through the ground structure 120G. The lower ground via 121G may not be aligned with the upper ground via 125G in the vertical direction. The vertical direction may indicate a direction perpendicular to the top surface 100a of the substrate 100. The number, shape, and arrangement of the lower ground via 121G, the ground pattern 123G, and the upper ground via 125G may not be limited to the number, shape, and arrangement shown. The ground structure 120G may include a conductive material, such as a metal.

[0029] The signal structure 120S may be disposed in the dielectric layer 110. The signal structure 120S may include a lower signal via 121S, a signal pattern 123S, and an upper signal via 125S. The dielectric layer 110 may include a plurality of layers, and the signal pattern 123S may be inserted between the plurality of layers. The signal pattern 123S may not be exposed on the side surface 100c of the substrate 100. The upper signal via 125S may be inserted between the signal pattern 123S and the signal substrate pad 140S, and coupled to the signal pattern 123S and the signal substrate pad 140S. The lower signal via 121S may be inserted between the signal pattern 123S and the signal terminal 130S, and coupled to the signal pattern 123S and the signal terminal 130S. Therefore, the signal substrate pad 140S may be coupled to the signal terminal 130S through the signal structure 120S. The dielectric layer 110 may be inserted between the signal structure 120S and the ground structure 120G. The signal structure 120S may be spaced apart from and insulated from the ground structure 120G. The signal structure 120S may include a conductive material, such as a metal.

[0030] The semiconductor chip 200 may be mounted on the top surface 100a of the substrate 100. The semiconductor chip 200 may include an integrated circuit therein, and the integrated circuit may include a memory circuit, a logic circuit, or a combination thereof. The integrated circuit may include a transistor. The semiconductor chip 200 may be used as a memory chip. For example, the memory chip may include a dynamic random access memory (DRAM). For another example, the memory chip may include a static random access memory (SRAM), a magnetic random access memory (MRAM), or a NAND flash memory. For another example, the semiconductor chip 200 may be a logic chip. In this specification, the phrase "electrically connected to the semiconductor chip 200" may mean "electrically connected to the integrated circuit in the semiconductor chip 200".

[0031] Chip pads 240G and 240S may be provided on the top surface of semiconductor chip 200. Chip pads 240G and 240S may be electrically connected to an integrated circuit in semiconductor chip 200. Chip pads 240G and 240S may include ground chip pads 240G and signal chip pads 240S. Substrate 100 may be provided with connection terminals 500 on its top surface 100a, and connection terminals 500 electrically connect semiconductor chip 200 to substrate 100. Connection terminals 500 may include bonding wires. Ground chip pad 240G may be electrically connected to ground substrate pad 140G through one of connection terminals 500. In this configuration, ground voltage may be applied to semiconductor chip 200 through ground terminal 130G and ground structure 120G. Signal chip pad 240S may be electrically connected to signal substrate pad 140S through another connection terminal 500. Therefore, when the semiconductor chip 200 operates, the semiconductor chip 200 can communicate electrical signals with an external device (not shown) through the connection terminal 500, the signal structure 120S and the signal terminal 130S. Different from what is shown, the semiconductor chip 200 can be flip-chip mounted. In this case, the chip pads 240G and 240S can be arranged on the bottom surface of the semiconductor chip 200, and the connection terminal 500 can be inserted between the substrate 100 and the semiconductor chip 200. The connection terminal 500 may include one or more of a solder ball, a bump pad or a column.

[0032] The substrate 100 may be provided thereon with a molding layer 300 covering the semiconductor chip 200. The molding layer 300 may include a dielectric polymer material, such as an epoxy molding compound.

[0033] The shielding layer 400 may be disposed on the top surface of the molding layer 300, at least one side surface of the molding layer 300, and at least one surface of the substrate 100. One surface of the substrate 100 may be a side surface 100c. The shielding layer 400 may have conductivity to shield the electromagnetic interference (EMI) of the semiconductor package 1. Electromagnetic interference may mean that the communication operation of the electronic component is subject to interference caused by the electromagnetic wave 700 emitted or sent from other electronic components. The electromagnetic wave 700 may have a frequency ranging from about 1 Ghz to about 6 GHz. In some embodiments, the semiconductor package 1 may include the shielding layer 400 and prevent the outward radiation of the electromagnetic wave 700 generated from the semiconductor chip 200. Therefore, the semiconductor chip 200 may not interrupt the operation of other electronic devices. Other electronic devices may include a transmitter, a receiver, a passive device, and another semiconductor chip disposed outside the semiconductor package 1.

[0034] The shielding layer 400 may reflect or absorb electromagnetic waves 700 generated from the integrated circuit of the semiconductor chip 200, the connection terminal 500, or the substrate 100. Because the ground pattern 123G is exposed on the side surface 100c of the substrate 100, the shielding layer 400 may be electrically connected to the ground pattern 123G. Therefore, the shielding layer 400 may be electrically grounded. The arrows shown in the shielding layer 400 may schematically indicate the radiation path of the electromagnetic wave 700 in the shielding layer 400. The electromagnetic wave 700 absorbed in the shielding layer 400 may be radiated outward through the ground pattern 123G and the ground terminal 130G. The signal pattern 123S may not be exposed on the side surface 100c of the substrate 100. The signal pattern 123S may not be electrically connected to the shielding layer 400.

[0035] In some embodiments, the semiconductor package 1 may be irradiated with an X-ray 600 to inspect defects of the semiconductor package 1 when manufacturing and inspecting the semiconductor chip 200. The X-ray 600 may be, for example, a soft X-ray. The soft X-ray may have an energy ranging from about 0.12 keV to about 12 keV. The soft X-ray may have an energy ranging from about 2.9×10 16 Hz to about 2.9×10 18 Hz. The irradiation of soft X-rays can inspect transistors in the semiconductor chip 200. The inspection of the semiconductor chip 200 can be repeatedly performed. When the semiconductor chip 200 is over-irradiated with X-rays 600, the semiconductor chip 200 may be damaged. For example, the integrated circuit in the semiconductor chip 200 may be degraded. In some embodiments, the shielding layer 400 can partially shield the X-rays 600 irradiated to the semiconductor chip 200. The shielding layer 400 can reduce the intensity and / or amount of the X-rays 600 irradiated to the semiconductor chip 200. Therefore, the semiconductor chip 200 can be prevented from being damaged during the inspection of the semiconductor chip 200. As a result, the semiconductor chip 200 can improve reliability. The shielding layer 400 will be discussed further below.

[0036] Figure 1C The diagram shows Figure 1B An enlarged view of portion C of FIG.

[0037] refer to Figure 1C as well as Figure 1B, the shielding layer 400 may include a conductive structure 410, a nanostructure 420, and a polymer 430. Because the shielding layer 400 includes the conductive structure 410, the shielding layer 400 may be conductive. The conductive structure 410 may be used as an electromagnetic wave shielding particle to shield the electromagnetic wave 700 generated from the semiconductor chip 200. For example, the conductive structure 410 may absorb the electromagnetic wave 700. The conductive structure 410 may include a metal or a metal oxide. For example, the conductive structure 410 may include silver (Ag) or silver oxide. For another example, the conductive structure 410 may include one or more of gold (Au), copper (Cu), nickel (Ni), iron (Fe), aluminum (Al) and its oxide. When the conductive structures 410 are spaced apart from each other, electrons may migrate slowly or hardly migrate between the conductive structures 410. The conductive structures 410 may be physically connected and / or electrically connected to each other. For example, at least two of the conductive structures 410 may be in physical contact with each other. For another example, at least two of the conductive structures 410 may be chemically bonded into an agglomerate. For ease of description, the conductive structures 410 are shown as having boundaries therebetween, but are not Figure 1B and Figure 1C Unlike the one shown in , the conductive structures 410 can be connected to each other so that there is no visible boundary between them. Because the conductive structures 410 are connected to each other, electrons can migrate at high speed between the conductive structures 410, and as a result, the shielding layer 400 can have a reduced resistance. As the resistance of the shielding layer 400 is reduced, the electromagnetic wave 700 adsorbed in the shielding layer 400 can be quickly transmitted to the outside of the semiconductor package 1.

[0038] Conductive structure 410 may have a relatively high aspect ratio. In this specification, the aspect ratio of a component may mean the ratio of the maximum diameter to the minimum diameter of a component. The average value of the maximum diameter of conductive structure 410 may fall within the range of about 1 μm to about 5 μm. The average value of the minimum diameter of conductive structure 410 may fall within the range of about 150 nm to about 500 nm. Because conductive structure 410 has its high aspect ratio, electrons may be sent / migrated between conductive structures 410 more quickly, resulting in shielding layer 400 having a lower resistance. Conductive structure 410 may be shaped, for example, as a sheet or plate.

[0039] The conductive structure 410 may be coupled to the ground pattern 123G, and thus the shielding layer 400 may be electrically connected to the ground structure 120G. Figure 1B As shown by the arrows in , the conductive structure 410 may form a radiation path for the electromagnetic wave 700 in the shielding layer 400. In this specification, the phrase "coupled to / electrically connected to the shielding layer 400" may include "electrically connected to the conductive structure 410 in the shielding layer 400".

[0040] In some embodiments, the conductive structure 410 may be stacked on the mold layer 300. When the conductive structure 410 is disposed on the top surface of the mold layer 300, the conductive structure 410 may have its main axis substantially parallel to the top surface of the mold layer 300. When the conductive structure 410 is disposed on the side surface of the mold layer 300, the conductive structure 410 may have its main axis substantially parallel to the side surface of the mold layer 300. However, the arrangement of the main axis of the conductive structure 410 is not limited to the above.

[0041] The nanostructure 420 may include a first nanostructure 421 and a second nanostructure 422. The first nanostructure 421 may include a semiconductor material. For example, the first nanostructure 421 may include silicon or silicon oxide. The first nanostructure 421 may include nanoparticles. The nanoparticles may have a spherical shape. The nanoparticles may also have an elliptical shape. The first nanostructure 421 may be used as an X-ray shielding structure. The X-ray shielding structure may be a soft X-ray shielding structure. For example, the first nanostructure 421 may absorb and shield an X-ray 600 having a first energy. The first energy may fall within a range of about 0.12 keV to about 12 keV.

[0042] The second nanostructure 422 may include a material different from that of the first nanostructure 421. The second nanostructure 422 may include a metal or a metal oxide. For example, the second nanostructure 422 may include zinc or zinc oxide. For another example, the second nanostructure 422 may include one or more of gold (Au), copper (Cu), nickel (Ni), iron (Fe), aluminum (Al) and oxides thereof. The second nanostructure 422 may include a metal material different from that of the conductive structure 410. The second nanostructure 422 may be an X-ray shielding structure. For example, the second nanostructure 422 may be a soft X-ray shielding structure. The second nanostructure 422 may absorb and shield X-rays 600 having a second energy. The second energy may be different from the first energy. The second energy may fall within a range of about 0.12 keV to about 12 keV. In some embodiments, because the shielding layer 400 includes the first nanostructure 421 and the second nanostructure 422, the shielding layer 400 may shield X-rays 600 having a relatively wide energy band. For example, the shielding layer 400 may shield first energy X-rays and second energy X-rays. The second nanostructure 422 may include nanoparticles. The nanoparticles may have a spherical or elliptical shape.

[0043] The polymer 430 may be disposed in gaps between the conductive structure 410 and the nanostructure 420, between the conductive structure 410 and the mold layer 300, and between the nanostructure 420 and the mold layer 300. The polymer 430 may encapsulate the conductive structure 410. The polymer 430 may be used as a binder. For example, the polymer 430 may attach the conductive structure 410 and the nanostructure 420 to the mold layer 300. The polymer 430 may include, for example, one or more of an epoxy polymer and a polyurethane.

[0044] In some embodiments, the first nanostructure 421 and the second nanostructure 422 may be distributed in the shielding layer 400. For example, each of the first nanostructure 421 and the second nanostructure 422 may be distributed in the polymer 430 and encapsulated by the polymer 430. The first nanostructures 421 may be spaced apart from each other. The second nanostructures 422 may be spaced apart from each other. The first nanostructure 421 and the second nanostructure 422 may be spaced apart from the conductive pad 410. The polymer 430 may be disposed between the nanostructures 420.

[0045] Each of the first nanostructure 421 and the second nanostructure 422 may have a lower conductivity than that of the conductive structure 410 and a higher resistance than that of the conductive structure 410. Since the first nanostructure 421 and the second nanostructure 422 are distributed, the first nanostructure 421 and the second nanostructure 422 may have no influence on the electrical connection between the conductive structures 410. The shielding layer 400 may have a low resistance characteristic.

[0046] In some embodiments, the amount of the nanostructure 420 may be less than the amount of the conductive structure 410. For example, the amount of the nanostructure 420 may be about 0.01% to about 10% of the amount of the conductive structure 410. The amount may be by weight, but the inventive concept is not limited thereto. The amount of the nanostructure 420 may mean the sum of the amount of the first nanostructure 421 and the amount of the second nanostructure 422. When the amount of the nanostructure 420 is less than 0.01% of the amount of the conductive structure 410, the shielding layer 400 may be difficult to fully shield the X-ray 600. When the amount of the nanostructure 420 is greater than about 10% of the amount of the conductive structure 410, the nanostructure 420 may be difficult to distribute. In this case, the shielding layer 400 may have increased resistance and reduced electromagnetic wave shielding properties. In some embodiments, because the amount of the nanostructure 420 is about 0.01% to about 10% of the amount of the conductive structure 410, the shielding layer 400 may satisfactorily shield the electromagnetic wave 700 and the X-ray 600.

[0047] In the case where the nanostructure 420 has an excessively large average diameter (e.g., greater than about 100 nm), when the nanostructure 420 is disposed between the conductive structures 410, the nanostructure 420 may interrupt the electrical connection between the conductive structures 410. In this case, the shielding layer 400 may have increased resistance and reduced electromagnetic wave shielding properties. In some embodiments, the average diameter of each of the first nanostructure 421 and the second nanostructure 422 may be less than the average value of the minimum diameter of the conductive structure 410. The average diameter of the first nanostructure 421 may be from about 0.01 nm to about 100 nm, for example, from about 0.01 nm to about 10 nm. The average diameter of the second nanostructure 422 may be from about 0.01 nm to about 100 nm, for example, from about 0.01 nm to about 10 nm. Therefore, even when the conductive structure 410 has the nanostructure 420 inserted therebetween, the conductive structures 410 may be satisfactorily electrically connected to each other. As a result, the shielding layer 400 may have low resistance properties and exhibit improved electromagnetic wave shielding properties.

[0048] Figure 1D and Figure 1E Pictured Figure 1B FIG. 1 is an enlarged view of the portion C shown in FIG. 1 , thereby illustrating the shielding layer according to some example embodiments. The repeated description will be omitted below. Reference will also be made to FIG. Figure 1A and Figure 1B Describe the following references Figure 1D and Figure 1E Embodiment of the invention.

[0049] refer to Figure 1D , the shielding layer 400 may include a polymer 430, a conductive structure 410, and a first nanostructure 421. The shielding layer 400 may not include the second nanostructure 422. The polymer 430, the conductive structure 410, and the first nanostructure 421 may be the same as the reference Figure 1C The ones discussed are essentially the same.

[0050] refer to Figure 1E , the shielding layer 400 may include the polymer 430 , the conductive structure 410 , and the second nanostructure 422 . The shielding layer 400 may not include the first nanostructure 421 .

[0051] FIG. 2A to FIG. 2C Pictured Figure 1B FIG. 1 is an enlarged view of the portion C shown in FIG. 1 , thereby illustrating the shielding layer according to some example embodiments. The repeated description will be omitted below. Reference will also be made to FIG. Figure 1B Description Reference FIG. 2A to FIG. 2C The following examples.

[0052] refer to FIG. 2A to FIG. 2C, the shielding layer 400 may include a conductive structure 410, a nanostructure 420, and a polymer 430. The conductive structure 410 and the nanostructure 420 may be disposed in the polymer 430. The nanostructure 420 may include a first nanostructure 421 and a second nanostructure 422. The shape of the nanostructure 420 may be changed variously. For example, the first nanostructure 421 or the second nanostructure 422 may include a nanowire. The nanowire may have a relatively high aspect ratio. For example, the nanowire may have a higher aspect ratio than the nanoparticle. Figure 2A As shown, the first nanostructure 421 may include nanowires, and the second nanostructure 422 may include nanoparticles. Figure 2B As shown, the first nanostructure 421 may include nanoparticles, and the second nanostructure 422 may include nanowires. Figure 2C As shown, the first nanostructure 421 may include a nanowire, and the second nanostructure 422 may include a nanowire. In some embodiments, the average diameter of the nanowires may be smaller than the average of the smallest diameters of the conductive structure 410. For example, the average diameter of the nanowires may be about 0.01 nm to about 100 nm, for example, about 0.01 nm to about 10 nm. Because the nanostructure 420 includes nanowires with relatively small diameters, the shielding layer 400 may have a low resistance characteristic.

[0053] The first nanostructure 421 may include silicon or silicon oxide, such as Figure 1C The second nanostructure 422 may include a metal or a metal oxide. However, the metal included in the second nanostructure 422 may be different from the metal included in the conductive structure 410. The amount of the nanostructure 420 may be about 0.01% to about 10% of the amount of the conductive structure 410.

[0054] Alternatively, in FIG. 2A to FIG. 2C In the illustrated embodiment, the shielding layer 400 may not include the first nanostructure 421 or the second nanostructure 422 .

[0055] Figure 3A and Figure 3B The diagram shows Figure 1A 8 is a cross-sectional view taken along line AB of FIG. 1 , thereby illustrating a method of manufacturing a semiconductor package according to some example embodiments. Figure 3C The diagram shows an enlarged view of portion C of FIG. 3B .

[0056] refer to Figure 3A, the semiconductor chip 200 may be mounted on the substrate 100. For example, the connection terminal 500 may be formed on the semiconductor chip 200 to connect with the corresponding chip pads 240G and 240S and the corresponding substrate pads 140G and 140S. The mold layer 300 may be formed on the substrate 100 so as to cover the semiconductor chip 200. The mounting of the semiconductor chip 200 and the formation of the mold layer 300 may be performed at the chip level or the wafer level.

[0057] refer to Figure 3B , the coating solution may be coated on the top surface and side surface of the mold layer 300 and on the side surface 100c of the substrate 100, thereby forming a preliminary shielding layer 400P. The preliminary shielding layer 400P may physically contact the ground pattern 123G of the substrate 100. The coating solution may include a polymer 430, a conductive structure 410, a nanostructure 420, and a solvent. The solvent may include one or more of propylene glycol methyl ether acetate (PGMEA), water, and ethanol. The coating solution may be coated on the mold layer 300 by a spray coating technique. The nanostructure 420 may be Figure 1C , Figure 1D , Figure 1E , Figure 2A , Figure 2B or Figure 2C For simplicity, the following will describe the nanostructures discussed in the example Figure 1C The nanostructure 420 is discussed in the example of FIG. 1 , but the inventive concept is not limited thereto.

[0058] The preliminary shielding layer 400P may include the same material as that of the coating solution. Figure 3B As shown, some of the conductive structures 410 may not be joined to each other. The conductive structures 410 may not be physically connected to each other.

[0059] A curing process may be performed on the preliminary shielding layer 400P to cure the polymer 430 in the preliminary shielding layer 400P. The curing process of the preliminary shielding layer 400P may be performed at a temperature of about 90° C. to about 190° C. The solvent may be volatilized in the curing process of the preliminary shielding layer 400P.

[0060] Return to reference Figures 1A to 1C , the preliminary shielding layer 400P may be heat-treated to form the shielding layer 400. The heat treatment of the preliminary shielding layer 400P may be achieved by an infrared reflow process using an infrared heater. For another example, the preliminary shielding layer 400P may be heat-treated using plasma or high-temperature nitrogen. For another example, the preliminary shielding layer 400P may be heat-treated using a halogen lamp under vacuum conditions.

[0061] Annealing may be performed so that the conductive structures 410 may be polymerized / aggregated and physically connected to each other. Thus, the shielding layer 400 may have a reduced resistance. When the preliminary shielding layer 400P is annealed at a temperature below about 150°C, the conductive structures 410 may not be satisfactorily connected to each other. When the preliminary shielding layer 400P is annealed at a temperature greater than about 300°C, the mold layer 300 may be damaged. In some embodiments, the preliminary shielding layer 400P may be annealed at a temperature equal to or greater than about 150°C, for example, at a temperature of about 150°C to about 300°C. As a result, the shielding layer 400 may have a low resistance and damage to the mold layer 300 may be prevented.

[0062] Figure 4A A cross-sectional view illustrating a semiconductor package according to some example embodiments is illustrated. Repeated descriptions will be omitted below.

[0063] refer to Figure 4A , the semiconductor package 2 may include a substrate 100, a semiconductor chip 200, a molding layer 300 and a shielding layer 400. The semiconductor chip 200 and the molding layer 300 may be connected to the reference Figure 1A and Figure 1B The substrate 100 may have a top surface 100a and a bottom surface 100b opposite to each other. The ground structure 120G may include a plurality of lower ground vias 121G, a ground pattern 123G, an upper ground via 125G, and a lower ground pad 127G.

[0064] The lower ground pad 127G may be exposed on one surface of the substrate 100, and the one surface may correspond to the bottom surface 100b of the substrate 100. For example, the lower ground pad 127G may be exposed on the bottom surface 100b of the edge region of the substrate 100. One of the lower ground vias 121G may be inserted between the lower ground pad 127G and the ground pattern 123G, and coupled to the lower ground pad 127G and the ground pattern 123G. The ground terminal 130G may be disposed on the bottom surface of another lower ground via 121G. The lower ground vias 121G may be electrically connected to each other through the ground pattern 123G. Therefore, the lower ground pad 127G may be coupled to the ground terminal 130G through the lower ground via 121G and the ground pattern 123G.

[0065] The shielding layer 400 may extend onto the bottom surface 100b of the substrate 100, thereby coupling to the exposed ground structure 120G. For example, the shielding layer 400 may include a conductive structure 410 coupled to the lower ground pad 127G. The shielding layer 400 may be electrically grounded through the lower ground pad 127G, the lower ground via 121G, the ground pattern 123G, and the ground terminal 130G.

[0066] For another example, the lower ground pad 127G may not be provided. In this case, one of the lower ground vias 121G may be exposed on the bottom surface 100 b of the substrate 100 , and the shielding layer 400 may be coupled to one of the lower ground vias 121G.

[0067] The ground pattern 123G may be spaced apart from the side surface 100c of the substrate 100. For another example, the ground pattern 123G may further extend onto the side surface 100c of the substrate 100 and be electrically connected to the shielding layer 400. The shielding layer 400 may be spaced apart from the ground terminal 130G and the signal terminal 130S.

[0068] Figure 4B A cross-sectional view illustrating a semiconductor package according to some example embodiments is illustrated. Repeated descriptions will be omitted below.

[0069] refer to Figure 4B , the semiconductor package 3 may include a substrate 100, a semiconductor chip 200, a molding layer 300, and a shielding layer 400. The grounding structure 120G may include a lower grounding via 121G, a grounding pattern 123G, an upper grounding via 125G, and an upper grounding pad 129G. A plurality of upper grounding vias 125G may be provided. The upper grounding pad 129G may be disposed on one of the upper grounding vias 125G and coupled to one of the upper grounding vias 125G. The upper grounding pad 129G may be exposed on one surface of the substrate 100, and the one surface may be the top surface 100a of the substrate 100. For example, the upper grounding pad 129G may be exposed on the top surface 100a of the edge region of the substrate 100.

[0070] The mold layer 300 may be disposed on the top surface 100a of the substrate 100. The width of the mold layer 300 may be smaller than the width of the substrate 100. The mold layer 300 may expose the top surface 100a of the edge region of the substrate 100. The mold layer 300 may expose at least a portion of the ground structure 120G (eg, the upper ground pad 129G).

[0071] The shielding layer 400 may be disposed on the mold layer 300. The shielding layer 400 may extend onto the top surface 100a of the substrate 100 exposed by the mold layer 300, and may be connected to the upper ground pad 129G. The shielding layer 400 may be electrically grounded through the upper ground pad 129G, one of the upper ground vias 125G, the ground pattern 123G, the lower ground via 121G, and the ground terminal 130G. The shielding layer 400 may further extend onto the side surface 100c of the substrate 100, but the inventive concept is not limited thereto.

[0072] Unlike shown, the upper ground pad 129G may not be provided. In this case, one of the upper ground vias 125G may be exposed on the top surface 100a of the substrate 100. One of the upper ground vias 125G may be spaced apart from the mold layer 300. The shielding layer 400 may directly contact one of the upper ground vias 125G.

[0073] According to the inventive concept, the shielding layer may include a conductive structure and a nanostructure. The conductive structure of the shielding layer may shield electromagnetic waves. The nanostructure of the shielding layer may shield X-rays. When manufacturing a semiconductor package, the semiconductor chip may be prevented from being damaged by X-rays. The nanostructure may be distributed in the shielding layer, and therefore, the shielding layer may have a low resistance characteristic. The semiconductor package may improve reliability.

[0074] This detailed description of the exemplary embodiments should not be interpreted as limiting the inventive concept, and it is intended that the inventive concept covers various combinations, modifications and variations of the above embodiments without departing from the spirit and scope of the inventive concept. The appended claims should be interpreted to include other embodiments.

Claims

1. A semiconductor package, comprising: substrate; a semiconductor chip on the substrate; The molding layer on the substrate covers the semiconductor chip; as well as The shielding layer on the molded layer, The shielding layer comprises a polymer, in which a plurality of conductive structures and a plurality of nanostructures are distributed, and wherein at least some of the conductive structures are connected to each other, The amount of the plurality of nanostructures is 0.01% to 10% of the amount of the plurality of conductive structures.

2. The semiconductor package according to claim 1, wherein The conductive structure is configured to shield electromagnetic waves, and Wherein, the nanostructure is configured to shield X-rays.

3. The semiconductor package according to claim 1, wherein: The nanostructure includes a semiconductor material.

4. The semiconductor package according to claim 1, wherein: The nanostructure is spaced apart from the conductive structure.

5. The semiconductor package according to claim 1, wherein The average diameter of the nanostructures is smaller than the average of the smallest diameters of the conductive structures.

6. The semiconductor package according to claim 1, wherein The nanostructures include nanoparticles and / or nanowires.

7. The semiconductor package according to claim 1, wherein: The substrate includes a ground structure exposed on one surface of the substrate, wherein at least a portion of the one surface of the substrate is covered by the shielding layer, and Wherein, the shielding layer is connected to the grounding structure.

8. A semiconductor package, comprising: substrate; a semiconductor chip on the substrate; The molding layer on the substrate covers the semiconductor chip; as well as The shielding layer on the molded layer, Wherein, the shielding layer includes a plurality of electromagnetic wave shielding structures and a plurality of X-ray shielding structures, Wherein, the amount of the plurality of X-ray shielding structures is 0.01% to 10% of the amount of the plurality of electromagnetic wave shielding structures.

9. The semiconductor package according to claim 8, wherein: The electromagnetic wave shielding structures are connected to each other, and Wherein, the X-ray shielding structure is distributed in the shielding layer.

10. The semiconductor package according to claim 8, wherein The electromagnetic wave shielding structure includes metal or metal oxide, and Wherein, the X-ray shielding structure comprises semiconductor material.

11. The semiconductor package according to claim 8, wherein The X-ray shielding structure comprises: a plurality of first nanostructures configured to shield X-rays having a first energy; and A plurality of second nanostructures are configured to shield X-rays having a second energy different from the first energy.

12. The semiconductor package according to claim 8, wherein The average diameter of the X-ray shielding structure is smaller than the average value of the minimum diameters of the electromagnetic wave shielding structure.

13. The semiconductor package according to claim 12, wherein: The resistance of the X-ray shielding structure is greater than the resistance of the electromagnetic wave shielding structure.

14. The semiconductor package according to claim 8, wherein: The X-ray shielding structure includes nanoparticles and / or nanowires.

15. The semiconductor package according to claim 8, wherein The X-ray shielding structure includes metal or metal oxide.

16. A semiconductor package, comprising: substrate; a semiconductor chip on the substrate; The molding layer on the substrate covers the semiconductor chip; as well as The shielding layer on the molding layer comprises: a plurality of conductive structures connected to each other; and The plurality of first nanostructures in the shielding layer include semiconductor materials, The amount of the plurality of first nanostructures is 0.01% to 10% of the amount of the plurality of conductive structures.

17. The semiconductor package according to claim 16, wherein: The shielding layer further comprises a plurality of second nanostructures, Wherein, the second nanostructure includes metal or metal oxide.

18. The semiconductor package according to claim 16, wherein: The conductive structure is configured to shield electromagnetic waves having a frequency of 1 GHz to 6 GHz, and Wherein, the first nanostructure is configured to shield soft X-rays.

19. The semiconductor package according to claim 16, wherein: The amount of the first nanostructure is less than the amount of the conductive structure, and The average diameter of the first nanostructure is smaller than the average value of the minimum diameter of the conductive structure.

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