Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region; a stack structure including a lower stack structure and an upper stack structure stacked in sequence on the substrate, wherein the stack structure includes insulating layers and electrodes alternately and vertically stacked on the substrate; a vertical structure located in a channel hole of the lower stack structure and the upper stack structure that penetrates the cell array region; and a dummy structure located in a dummy hole of at least one of the lower stack structure and the upper stack structure that penetrates the connection region. The connection region includes a second connection region located at one side of the cell array region and a first connection region located at one side of the second connection region. A surface pattern shape of the dummy hole in the second connection region is different from a shape of the dummy hole in the first connection region.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0165466, filed on December 19, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor memory device, and more specifically, to a 3D semiconductor memory device. Background Technology

[0004] The integration density of semiconductor memory devices has increased to meet consumer demands for superior performance and low cost. In the case of 2D or planar semiconductor devices, the integration density is primarily determined by the area occupied by a single memory cell, and therefore is heavily influenced by the level of fine patterning technology.

[0005] However, the integration density of 2D semiconductor devices remains limited, despite the increase, because miniaturization of patterns requires extremely expensive manufacturing equipment. Therefore, a 3D semiconductor memory device with 3D arranged memory cells has been proposed. Furthermore, the proposed 3D semiconductor memory device needs to be reliably manufactured with high design freedom. Summary of the Invention

[0006] The present invention provides a 3D semiconductor memory device with improved integration, greater design freedom, and enhanced reliability.

[0007] According to some examples, this disclosure relates to a 3D semiconductor memory device comprising: a substrate including a cell array region and a connection region; a stacked structure including an insulating layer and electrodes alternately and vertically stacked on the substrate, and including a stepped structure located in the connection region, and including a lower stacked structure and an upper stacked structure sequentially stacked on the substrate; a vertical structure located in a channel via penetrating the lower stacked structure and the upper stacked structure on the cell array region; and a pseudo-structure located in a pseudo-via penetrating at least one of the lower stacked structure and the upper stacked structure on the connection region, wherein the connection region includes a second connection region located on one side of the cell array region and a first connection region located on one side of the second connection region, and the second connection region is located between the first connection region and the cell array region, and wherein the pseudo-via includes a first pseudo-via in the first connection region and a second pseudo-via in the second connection region, and the surface pattern shape of the first pseudo-via is different from the surface pattern shape of the second pseudo-via.

[0008] According to some examples, this disclosure relates to a 3D semiconductor memory device, the 3D semiconductor memory device comprising: a substrate including a cell array region and a connection region; a stacked structure including an insulating layer and electrodes alternately and vertically stacked on the substrate, and including a stepped structure located in the connection region, and including a lower stacked structure and an upper stacked structure sequentially stacked on the substrate; a vertical structure penetrating the lower stacked structure and the upper stacked structure on the cell array region; and a pseudo-structure penetrating at least one of the lower stacked structure and the upper stacked structure on the connection region, wherein the connection region includes a second connection region located on one side of the cell array region and a second connection region located on the other side of the cell array region. A first connection region on one side of the connection region, and a second connection region between the first connection region and the cell array region, wherein the pseudo-structure includes a first pseudo-structure and a second pseudo-structure, wherein the second pseudo-structure includes a second lower pseudo-structure and a second upper pseudo-structure that respectively penetrate the lower stacked structure and the upper stacked structure of the second connection region and are connected to each other, and the first pseudo-structure includes a first lower pseudo-structure and a first upper pseudo-structure that respectively penetrate the lower stacked structure and the insulating layer of the first connection region and are connected to each other, and wherein the second pseudo-structure includes a discontinuous portion in which the diameters of the second lower pseudo-structure and the second upper pseudo-structure change discontinuously in the boundary region between the second lower pseudo-structure and the second upper pseudo-structure.

[0009] According to some examples, this disclosure relates to a 3D semiconductor memory device, the 3D semiconductor memory device comprising: a substrate including a cell array region and a connection region; a stacked structure including an insulating layer and electrodes alternately and vertically stacked on the substrate, and including a stepped structure located in the connection region, and including a lower stacked structure and an upper stacked structure sequentially stacked on the substrate; a vertical structure penetrating the lower stacked structure and the upper stacked structure on the cell array region; and a pseudo-structure penetrating at least one of the lower stacked structure and the upper stacked structure on the connection region, wherein the connection region includes a second connection region located on one side of the cell array region and a second connection region located in the second connection region. A first connection region on one side, and a second connection region between the first connection region and the cell array region, wherein the pseudo-structure includes a first pseudo-structure and a second pseudo-structure, wherein the second pseudo-structure includes a second lower pseudo-structure and a second upper pseudo-structure that respectively penetrate the lower stacked structure and the upper stacked structure of the second connection region and are connected to each other, and the first pseudo-structure includes a first lower pseudo-structure that penetrates the lower stacked structure of the first connection region, wherein the second pseudo-structure includes a discontinuous portion in which the diameters of the second lower pseudo-structure and the second upper pseudo-structure change discontinuously at the boundary region of the second lower pseudo-structure and the second upper pseudo-structure, and wherein an insulating layer covering the lower stacked structure is formed in the first connection region. Attached Figure Description

[0010] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1This is a schematic block diagram illustrating a 3D semiconductor memory device according to an example embodiment;

[0012] Figure 2 This is a schematic diagram illustrating the cell array region of a 3D semiconductor memory device according to an example embodiment;

[0013] Figure 3 This is a layout diagram of a 3D semiconductor memory device according to an example embodiment;

[0014] Figure 4 and Figure 5 They are along Figure 3 The sectional views taken by lines I-I' and II-II';

[0015] Figure 6A and Figure 6B They are Figure 4 Enlarged sectional views of the M and N regions;

[0016] Figure 7A and Figure 7B They are Figure 5 Enlarged sectional views of regions O and P;

[0017] Figure 8 This is a planar layout diagram of the channel holes and pseudo-holes of a 3D semiconductor memory device according to an example embodiment;

[0018] Figures 9 to 15 This is a cross-sectional view illustrating a method for manufacturing a 3D semiconductor memory device according to an example embodiment;

[0019] Figure 16 This is a conceptual diagram used to describe the sequence of manufacturing a 3D semiconductor memory device according to an example embodiment;

[0020] Figure 17 This is a layout diagram of a 3D semiconductor memory device according to an example embodiment;

[0021] Figure 18 and Figure 19 They are along Figure 17 The sectional views taken by lines I-I' and II-II';

[0022] Figure 20 This is a planar layout diagram of the channel holes and pseudo-holes of a 3D semiconductor memory device according to an example embodiment;

[0023] Figures 21 to 26 This is a cross-sectional view used to describe a method of manufacturing a 3D semiconductor memory device according to an example embodiment; and

[0024] Figure 27 This is a conceptual diagram used to describe the sequence of manufacturing a 3D semiconductor memory device according to an example embodiment. Detailed Implementation

[0025] Figure 1 This is a block diagram schematically illustrating a 3D semiconductor memory device according to an example embodiment.

[0026] exist Figure 1 In this context, a 3D semiconductor memory device may include a cell array region (CAR) and a peripheral circuit region (not shown). The planar structure of the 3D semiconductor memory device can be modified, and the inventive concept is not limited to this. Figure 1 As shown. The 3D semiconductor memory device can be a non-volatile semiconductor memory device. The peripheral circuit area may include a row decoder area (ROW DCR), a page buffer area (PBR), a column decoder area (COL DCR), and a control circuit area (not shown).

[0027] In some embodiments, the connection region CTR may be arranged between the cell array region CAR and the row decoder region ROW DCR. The connection region CTR may be formed by extending a component included in the cell array region CAR and may be referred to as an extension region.

[0028] A memory cell array comprising multiple memory cells is arranged in a cell array region (CAR). In some embodiments, the memory cell array includes memory cells arranged in a three-dimensional manner and multiple word lines and multiple bit lines electrically connected to the memory cells.

[0029] The row decoder for selecting word lines of the memory cell array can be arranged in the row decoder area ROW DCR, and the wiring structure for electrically connecting the memory cell array to the row decoder can be arranged in the connection area CTR.

[0030] The row decoder selects one of the word lines in the memory cell array based on the address information. The row decoder can then supply word line voltages to the selected and unselected word lines in response to control signals from the control circuitry.

[0031] Page buffers used for reading information stored in memory cells can be arranged in the page buffer area (PBR). The page buffer can temporarily store data to be stored in the memory cell or detect data stored in the memory cell, depending on the operating mode. In programming mode, the page buffer operates as a write driver circuit, and in read mode, it operates as a read amplifier circuit.

[0032] In the column decoder area (COL DCR), column decoders are arranged to connect to the bit lines of the memory cell array. The column decoders provide a data transfer path between the page buffer and external devices (e.g., the memory controller).

[0033] Figure 2This is a schematic diagram illustrating the cell array region of a 3D semiconductor memory device according to an example embodiment.

[0034] In detail, the cell array region CAR may include multiple cell array blocks BLK1, BLK2, ... and BLKn (n is a positive integer). Each of the cell array blocks BLK1, BLK2, ... and BLKn may include a stacked structure comprising electrodes stacked on a plane in a third direction (Z-direction), the plane extending in a first direction (X-direction) and a second direction (Y-direction).

[0035] The stacked structure can be combined with multiple vertical structures (e.g., semiconductor pillars) and can form memory cells arranged in a 3D shape. Each of the cell array blocks BLK1, BLK2, ..., and BLKn may include bit lines electrically connected to the memory cells. The memory cells of the 3D memory cell array can be non-volatile memory cells, wherein multiple vertically aligned groups of memory cells are connected in series to form a string of memory cells, which can form a 3D NAND flash non-volatile memory.

[0036] Figure 3 This is a layout diagram of a 3D semiconductor memory device according to an example embodiment. Figure 4 and Figure 5 They are along Figure 3 The sectional view taken by lines I-I' and II-II'. Figure 6A and Figure 6B They are Figure 4 Enlarged sectional views of the M and N regions. Figure 7A and Figure 7B They are Figure 5 Enlarged sectional views of areas O and P.

[0037] Reference Figures 3 to 5 , Figure 6A , Figure 6B , Figure 7A and Figure 7B The 3D semiconductor memory device 10 may include a substrate 100, which includes a cell array region (CAR) and a connection region (CTR). For example, the substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In one embodiment, the substrate 100 may include a substrate of a first conductivity type, such as a p-type substrate.

[0038] Cell array block ( Figure 2 The cell array block (BLK) can be arranged on the substrate 100. The cell array block BLK may include a stacked structure ST, which includes an insulating layer IL and an electrode EL stacked alternately and vertically. Each of the stacked structures ST may include a lower stacked structure SS1 and an upper stacked structure SS2.

[0039] The upper stack structure SS2 can be arranged on the lower stack structure SS1. The stack structure ST can extend longitudinally from the cell array region CAR to the connection region CTR in a first direction (X-direction). The stack structure ST can be arranged in a second direction (Y-direction) intersecting the first direction (X-direction). An item, layer, or part of an item or layer described as extending "longitudinally" in a particular direction has a length in that particular direction and a width perpendicular to that direction, wherein the length is greater than the width.

[0040] A common-source electrode region (CSR) may be disposed within the cell array region (CAR). The CSR may be arranged in portions of the substrate 100 between horizontally adjacent stacked structures (ST). The CSR may extend longitudinally parallel to the stacked structures (ST) in a first direction (X-direction). The CSR may be arranged in a second direction (Y-direction). The CSR may be doped with impurities to have a second conductivity type. For example, the CSR may be doped with impurities such as arsenic (As) or phosphorus (P) to have n-type conductivity.

[0041] A common-source plug CSP can be connected to a common-source region CSR. The common-source plug CSP can extend longitudinally parallel to the stack structure ST in a first direction (X-direction). An insulating spacer SP can be located between the common-source plug CSP and the stack structure ST.

[0042] The electrodes EL of the stacked structure ST can be stacked in a third direction (Z-direction) perpendicular to the top surface of the substrate 100. The electrodes EL can be separated from each other perpendicularly by the insulating layer IL between them. The electrodes EL can form a stepped structure in the connection region CTR. For example, the height of the stacked structure ST on the connection region CTR can decrease as the distance from the cell array region CAR in the first direction (X-direction) increases. For example, the length of each electrode EL in the vertically stacked electrodes EL in the x-direction can decrease from the bottommost electrode EL to the topmost electrode EL, so that the length of each electrode EL gradually decreases as the electrode EL is closer to the top of the stacked structure ST.

[0043] One or more of the bottommost electrodes EL of the lower stack structure SS1 may include a lower select line. One or more of the topmost electrodes EL of the upper stack structure SS2 may include an upper select line. In addition to the lower and upper select lines, the electrodes EL may be word lines. In the connection area CTR with a stepped structure, a portion of the electrodes EL is exposed on one side, that is, the portion connected to the contact plug CP may be referred to as a word line pad.

[0044] In some embodiments, the etch stop layer ESL may be disposed on top of the lower stack structure SS1. The etch stop layer ESL may be in direct contact with the bottommost insulating layer IL of the upper stack structure SS2.

[0045] For example, the electrode EL may include at least one selected from doped semiconductors (e.g., doped silicon), metals (e.g., tungsten, copper, aluminum, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), and transition metals (e.g., titanium, tantalum, etc.). The insulating layer IL may include a silicon oxide layer. The etch stop layer ESL may include a polycrystalline silicon film.

[0046] The etch stop layer (ESL) can be formed only when needed, and in some embodiments, it can be omitted. When the etch stop layer (ESL) is not formed, the bottom insulating layer (IL) of the upper stacked structure SS2 can directly contact the horizontal insulating layer (HP).

[0047] The connection region CTR may include a second connection region CTR2 disposed on one side of the cell array region CAR and a first connection region CTR1 disposed on one side of the second connection region CTR2. The second connection region CTR2 may include a region disposed on one side of the cell array region CAR where a second circuit line CL2 electrically connected to the electrode EL of the upper stacked structure SS2 is disposed. The first connection region CTR1 may include a region disposed on one side of the second connection region CTR2 where a first circuit line CL1 electrically connected to the electrode EL of the lower stacked structure SS1 is disposed.

[0048] The planar area of ​​the electrode EL on the connection region CTR can decrease as the distance from the top surface of the substrate 100 increases in the third direction (Z-direction). The bottom electrode EL (lower select line) of the stacked structure ST can have the largest planar area. The top electrode EL (upper select line) of the stacked structure ST can have the smallest planar area.

[0049] In the cell array region CAR, multiple channel holes CH can be formed that penetrate the stacked structure ST. Vertical structures VS can be disposed in the channel holes CH. When viewed from above, the vertical structures VS can be arranged in a first direction (X-direction). For example, the vertical structures VS can be arranged in a zigzag pattern in the first direction (X-direction). In another example, although not shown, the vertical structures VS can be arranged in a straight line in the first direction (X-direction).

[0050] Each of the vertical structures VS may include a vertical insulating layer VP, an upper semiconductor pattern USP, a lower semiconductor pattern LSP, and an insulating pattern VI. The insulating pattern VI may be referred to herein as the buried insulating pattern VI. The vertical insulating layer VP may extend toward the substrate 100 along the inner wall of the channel via CH. The upper semiconductor pattern USP may cover the inner wall of the vertical insulating layer VP and may also extend toward the substrate 100 together with the vertical insulating layer VP.

[0051] Return to reference Figure 6A The lower semiconductor pattern LSP can be disposed below the channel via CH and directly contact the substrate 100. The lower semiconductor pattern LSP can penetrate the bottom electrode EL (lower select line) of the stacked structure ST. The oxide pattern 103 can be disposed between the lower semiconductor pattern LSP and the bottom electrode EL (lower select line).

[0052] The upper semiconductor pattern USP may include a first semiconductor pattern SL1 and a second semiconductor pattern SL2. The second semiconductor pattern SL2 may be directly connected to the lower semiconductor pattern LSP. The second semiconductor pattern SL2 may have a bottom-closed tubular shape or a hollow powder shape. The interior of the second semiconductor pattern SL2 may be filled with an embedded insulating pattern VI. The second semiconductor pattern SL2 may contact the inner wall of the first semiconductor pattern SL1.

[0053] A second semiconductor pattern SL2 can electrically connect a first semiconductor pattern SL1 to a lower semiconductor pattern LSP. The first semiconductor pattern SL1 can have a tubular shape or a hollow powder shape with openings at both the top and bottom. The first semiconductor pattern SL1 can be spaced apart from the lower semiconductor pattern LSP and can not be in direct contact with the lower semiconductor pattern LSP. The lower semiconductor pattern LSP and the upper semiconductor pattern USP can be used as a channel in a 3D memory device according to an example embodiment.

[0054] In one example embodiment, the lower semiconductor pattern LSP and the upper semiconductor pattern USP may comprise silicon (Si), germanium (Ge), or mixtures thereof, and may have different crystal structures. The lower semiconductor pattern LSP and the upper semiconductor pattern USP may have a crystal structure including at least one selected from single-crystal, amorphous, and polycrystalline structures. The lower semiconductor pattern LSP and the upper semiconductor pattern USP may be undoped, or may be doped with impurities to have a first conductivity type identical to that of the substrate 100.

[0055] Return to reference Figure 3 , Figure 4 and Figure 5The diameter of the vertical structure VS in the lower stacked structure SS1 may gradually decrease in the direction toward the substrate 100. The diameter of the vertical structure VS in the upper stacked structure SS2 may also gradually decrease in the direction toward the substrate 100. In the region between the lower stacked structure SS1 and the upper stacked structure SS2, the diameter of the vertical structure VS may vary discontinuously. For example, the diameter of the lower portion of the vertical structure VS in the upper stacked structure SS2 may be smaller than the diameter of the upper portion of the vertical structure VS in the lower stacked structure SS1. In some embodiments, the diameters of the upper portions of the vertical structures VS in the upper stacked structure SS2 and the lower stacked structure SS1 may be substantially the same, and the diameters of the lower portions of the vertical structures VS in the upper stacked structure SS2 and the lower stacked structure SS1 may also be substantially the same.

[0056] When referring to orientation, layer, location, shape, size, quantity, or other measures, terms such as “identical,” “equal,” “flat,” or “coplanar” as used herein do not necessarily refer to exactly identical orientation, layer, location, shape, size, quantity, or other measures, but are intended to cover substantially identical orientation, layer, location, shape, size, quantity, or other measures, for example, those that may be subject to acceptable variation due to manufacturing processes. Unless the context or other description clearly indicates otherwise, the term “substantially” may be used herein to emphasize this meaning.

[0057] Return to reference Figure 6B The vertical structure VS may include at least one discontinuous portion NCP1. The discontinuous portion NCP1 may be located between the lower stacked structure SS1 and the upper stacked structure SS2. The etch stop layer ESL may be adjacent to the discontinuous portion NCP1. The etch stop layer ESL may be in substantially the same plane as the discontinuous portion NCP1. For example, the discontinuous portion NCP1 may include a horizontal surface that is substantially flat and parallel to the top surface of the substrate 100, and the top surface of the etch stop layer ESL may be substantially coplanar with the top surface of the horizontal surface.

[0058] The upper portion of the discontinuous portion NCP1 may have a first diameter M1, and the lower portion of the discontinuous portion NCP1 may have a second diameter M2. The diameter of the discontinuous portion NCP1 at the junction or boundary region between the lower stacked structure SS1 and the upper stacked structure SS2 may increase discontinuously. Therefore, the second diameter M2 may be larger than the first diameter M1. The sidewall SW1 of the vertical structure VS may have a discontinuous profile. For example, the sidewall SW1 of the vertical structure VS may have a stepped profile at the discontinuous portion NCP1. In some example embodiments, the stepped profile of the sidewall SW1 of the vertical structure VS may include: a lower inclined sidewall inclined relative to the top surface of the substrate 100, a substantially horizontal upper surface parallel to the top surface of the substrate 100, and an upper inclined sidewall inclined relative to the top surface of the substrate 100.

[0059] Return to reference Figure 6A The horizontal insulating layer HP can be located between the electrode EL and the insulating layer IL. The horizontal insulating layer HP and the vertical insulating layer VP between the electrode EL and the upper semiconductor pattern USP can form a data storage layer.

[0060] The 3D semiconductor memory device according to the example embodiment can be a NAND flash memory device. For example, the data storage layer between the electrode EL and the upper semiconductor pattern USP may include a tunnel insulating layer, a charge storage layer, and a barrier insulating layer. The tunnel insulating layer may be in direct contact with the upper semiconductor pattern USP.

[0061] The barrier insulating layer can be in direct contact with the electrode EL. The charge storage layer can be located between the tunnel insulating layer and the barrier insulating layer. Data stored in the data storage layer can be altered by utilizing the Fowler-Nordheim tunneling effect caused by the voltage difference between the electrode EL and the upper semiconductor pattern USP.

[0062] The tunneling insulation layer may include a material with a band gap larger than that of the charge storage layer. The tunneling insulation layer may include a high-k film, such as an alumina film, a hafnium oxide film, etc., or may include a silicon oxide film. The charge storage layer may include a silicon nitride layer, a silicon oxynitride layer, or a silicon-rich nitride layer. The barrier insulation layer may include a silicon oxide layer.

[0063] Return to reference Figure 3 , Figure 4 and Figure 5 On the connection area CTR, contact plugs CP can be connected to electrodes EL of the stacked structure ST. For example, the number of contact plugs CP connected to the stacked structure ST can be equal to the number of electrodes EL constituting the stacked structure ST.

[0064] The contact plugs CP can be spaced apart from each other in the first direction (X-direction). Since the electrodes EL form a stepped structure in the connection region CTR, the bottom surface of the contact plugs CP can be located at different heights relative to the substrate 100. The plane of the bottom surface of the contact plugs CP can be lower as the distance from the cell array region CAR increases. The vertical length of the contact plugs CP in the third direction (Z-direction) can correspond to the length of each electrode EL in the vertically stacked electrodes in the first direction (X-direction). For example, at the furthest point from the cell array region CAR, the longest contact plug CP can be electrically connected to the longest electrode EL, and at the closest point to the cell array region CAR, the shortest contact plug CP can be electrically connected to the shortest electrode EL.

[0065] In the connection region CTR, multiple pseudo-vias DH can be formed, penetrating the insulating layer 110 and the stacked structure ST. The insulating layer 110 may be referred to herein as the buried insulating layer 110. The pseudo-vias DH can penetrate at least one of the lower stacked structure SS1 and the upper stacked structure SS2 on the connection region CTR. The pseudo-vias DH can penetrate the insulating layer 110 on a portion of the first connection region CTR1, such as... Figure 5 As shown.

[0066] The pseudo-structure DS can be located within the pseudo-via DH. The pseudo-structure DS can selectively be located only on the connection region CTR and not on the cell array region CAR. The pseudo-structure DS can be arranged adjacent to the contact plug CP, but can also be located away from the contact plug CP. As used herein, the term "pseudo" is used to refer to a component that has the same or similar structure and shape as other components but does not have the basic function and exists only as a pattern in the device. Here, the pseudo-structure DS is ineffective for read or write operations. For example, the pseudo-structure DS may not be electrically connected to the bit line contact and therefore cannot be connected to the bit line.

[0067] The pseudo-structure DS can be a stacked structure ST on the physical support connection area CTR. In one embodiment, such as a vertical structure VS, each of the pseudo-structures DS may include a vertical insulating layer VP, an upper semiconductor pattern USP, a lower semiconductor pattern LSP, and an embedded insulating pattern VI.

[0068] The diameter of the pseudo-structure DS can gradually decrease as the distance from the substrate 100 increases. The diameter of the pseudo-structure DS can continuously decrease in the direction from the upper stacked structure SS2 to the lower stacked structure SS1.

[0069] like Figure 5 As shown, the pseudo-structure DS may include a lower pseudo-structure DSL and an upper pseudo-structure DSU. The lower pseudo-structure DSL may include a second lower pseudo-structure DSL2 and a first lower pseudo-structure DSL1 formed in the second connection area CTR2 and the first connection area CTR1. The upper pseudo-structure DSU may include a second upper pseudo-structure DSU2 and a first upper pseudo-structure DSU1 formed in the second connection area CTR2 and the first connection area CTR1, respectively.

[0070] In the second connection region CTR2, the second upper pseudo-structure DSU2 and the second lower pseudo-structure DSL2 can be connected vertically. In the first connection region CTR1, the first upper pseudo-structure DSU1 and the first lower pseudo-structure DSL1 can be vertically connected and form a single body. For example, the first upper pseudo-structure DSU1 and the first lower pseudo-structure DSL1 can be formed in a single process. In the first connection region CTR1, some pseudo-structures DS do not penetrate the stacked structure ST but penetrate the insulating layer 110, such as... Figure 5 As shown.

[0071] Return to reference Figure 7AThe second connection region CTR2 may include a lower pseudo-via DHL and an upper pseudo-via DHU that penetrate the lower stacked structure SS1 and the upper stacked structure SS2, respectively. The lower pseudo-via DHL and the upper pseudo-via DHU formed in the second connection region CTR2 may be referred to as the second lower pseudo-via DHL2 and the second upper pseudo-via DHU2, respectively.

[0072] The pseudo-structure DS of the second connection region CTR2 may include at least one discontinuous portion NCP2. The discontinuous portion NCP2 may be located in the boundary region or intermediate region between the lower stacked structure SS1 and the upper stacked structure SS2. The etch stop layer ESL may be adjacent to the discontinuous portion NCP2. The etch stop layer ESL may be in substantially the same plane as the discontinuous portion NCP2. For example, the discontinuous portion NCP2 may include a horizontal surface that is substantially flat and parallel to the top surface of the substrate 100, and the top surface of the etch stop layer ESL may be substantially coplanar with the top surface of that horizontal surface.

[0073] The upper part of the discontinuous portion NCP2 may have a third diameter M3, and the lower part of the discontinuous portion NCP2 may have a fourth diameter M4. The diameter of the discontinuous portion NCP2 at the interface between the lower stacked structure SS1 and the upper stacked structure SS2 may increase discontinuously (abruptly). Therefore, the fourth diameter M4 may be larger than the third diameter M3.

[0074] The sidewall SW2 of the pseudostructure DS may have a discontinuous profile. For example, the sidewall SW2 of the pseudostructure DS may have a stepped profile at the discontinuous portion NCP2. In some example embodiments, the stepped profile of the sidewall SW2 of the pseudostructure DS may include: a downwardly inclined sidewall inclined relative to the top surface of the substrate 100, a substantially horizontal upper surface parallel to the top surface of the substrate 100, and an upwardly inclined sidewall inclined relative to the top surface of the substrate 100.

[0075] Return to reference Figure 7B The first connection region CTR1 may include a lower pseudo-via DHL and an upper pseudo-via DHU that penetrate the lower stacked structure SS1 and the upper stacked structure SS2, respectively. The boundary line between the lower stacked structure SS1 and the upper stacked structure SS2 is indicated by a dashed line and reference numeral 112. The lower pseudo-via DHL and the upper pseudo-via DHU formed in the first connection region CTR1 may be referred to as the first lower pseudo-via DHL1 and the first upper pseudo-via DHU1, respectively.

[0076] Unlike the pseudo-structure DS of the second connection region CTR2 described above, the diameter of the pseudo-structure DS of the first connection region CTR1 may have a continuous portion CPP, and the continuous portion CPP does not have a discontinuous change. The sidewalls of the pseudo-structure DS of the first connection region CTR1 may have a continuous profile. In some embodiments, the diameter of the pseudo-structure DS may gradually increase as the pseudo-structure DS extends in a direction away from the substrate 100, and the sidewalls of the pseudo-structure DS of the first connection region CTR1 may be inclined relative to the top surface of the substrate 100.

[0077] For example, the sidewall SW3 of the pseudostructure DS in the first connection region CTR1 may not have a stepped profile. For example, the maximum diameter M3 of the first upper pseudostructure DSU1 in the first connection region CTR1 may be substantially equal to the maximum diameter M3' of the first lower pseudostructure DSL1 in the first connection region CTR1. For example, the maximum diameter M3 of the pseudostructure DS in the first connection region CTR1 may be substantially equal to the maximum diameter M3 of the pseudostructure DS in the second connection region CTR2.

[0078] Return to reference Figure 3 , Figure 4 and Figure 5 On the substrate 100, a buried insulating layer 110 covering the stacked structure ST can be provided. The buried insulating layer 110 may have a planarized top surface. The vertical thickness of the buried insulating layer 110 may increase in the direction from the cell array region CAR to the connection region CTR.

[0079] The first interlayer insulating layer 120 and the second interlayer insulating layer 130 may be disposed on the buried insulating layer 110. A bit line BL extending longitudinally in a second direction (Y-direction) across the stacked structure ST may be arranged on the second interlayer insulating layer 130. The bit line BL may be electrically connected to the vertical structure VS via bit line contact plugs BPLG and bit line contact pads 111.

[0080] The first circuit line CL1 and the second circuit line CL2 connected to the contact plug CP can be disposed on the second interlayer insulating layer 130. In one embodiment, the pseudo-structure DS may not be electrically connected to either the bit line BL, the first circuit line CL1, or the second circuit line CL2.

[0081] Figure 8 This is a planar layout diagram of the channel holes and pseudo-holes of a 3D semiconductor memory device according to an example embodiment.

[0082] In detail, Figure 8 It shows the formation in Figure 3The example planar layout of the channel vias CH and dummy vias DH in the cell array region CAR, the first connection region CTR1, and the second connection region CTR2 of the 3D semiconductor memory device 10 shown in Figure 7. The number of channel vias CH and dummy vias DH formed in the cell array region CAR, the first connection region CTR1, and the second connection region CTR2 is merely an example, and the inventive concept is not limited thereto. Vertical structure ( Figure 3 To the VS in Figure 7) and pseudostructure ( Figure 3 The DS shown in Figure 7 can be formed in the channel hole CH and the pseudo hole DH.

[0083] Figure 8 The planar layout diagram can correspond to the surface pattern shape of the vias CH and dummy vias DH in a given stacked structure. In some embodiments, when viewed from top to bottom, the surface pattern shape can reflect the cross-sectional shape of the vias CH and dummy vias DH when the given stacked structure is formed. For example, the surface pattern shape of the lower stacked structure SS1 shows the layout and cross-sectional appearance of the vias CH and dummy vias DH when they are formed in the lower stacked structure SS1 and before the formation of the second stacked structure SS2. Similarly, the surface pattern shape of the upper stacked structure SS2 shows the layout and cross-sectional appearance of the vias CH and dummy vias DH when they are formed in the upper stacked structure SS2. Thus, for example, the dummy vias DH in the first connection region CTR1 are not shown in the surface pattern shape of the lower stacked structure SS1 because these dummy vias were not formed before the formation of the upper stacked structure SS2.

[0084] In some embodiments, the surface pattern shape of the lower channel hole CHL formed in the lower stacked structure SS1 in the cell array region CAR may be the same as the surface pattern shape of the upper channel hole CHU formed in the upper stacked structure SS2. The surface pattern shapes of the lower channel hole CHL and the upper channel hole CHU may be circular or elliptical. The diameter of the lower channel hole CHL may be larger than the diameter of the upper channel hole CHU.

[0085] In some embodiments, the surface pattern shape of the dummy via DH formed in the second connection region CTR2 may differ from the surface pattern shape of the dummy via DH formed in the first connection region CTR1. Each of the dummy via DH formed in the second connection region CTR2 and the first connection region CTR1 may include multiple sub-vias. Each of the dummy via DH formed in the second connection region CTR2 and the first connection region CTR1 may include multiple sub-vias, including circular sub-vias, elliptical sub-vias, or combinations thereof.

[0086] In some embodiments, a dummy via DH may include a lower dummy via DHL penetrating the lower stacked structure SS1 and an upper dummy via DHU penetrating the upper stacked structure SS2. The surface pattern shape of the lower dummy via DHL may be different from the surface pattern shape of the upper dummy via DHU.

[0087] In some embodiments, the surface pattern shape of the second lower pseudo-hole DHL2 of the lower stacked structure SS1 penetrating the second connection region CTR2 may be different from the surface pattern shape of the second upper pseudo-hole DHU2 of the upper stacked structure SS2 penetrating the second connection region CTR2.

[0088] In some embodiments, the surface pattern shape of the second lower dummy hole DHL2 penetrating the lower stacked structure SS1 of the second connection region CTR2 may be the same as that of the insulating layer penetrating the first connection region CTR1. Figure 4 and Figure 5 The surface pattern shape of the first upper pseudo-hole DHU1 in 110 is different.

[0089] In some embodiments, the surface pattern shape of the second upper dummy hole DHU2 penetrating the upper stacked structure SS2 of the second connection region CTR2 may be the same as that of the insulating layer penetrating the first connection region CTR1. Figure 4 and Figure 5 The surface pattern shape of the first upper pseudo-hole DHU1 in 110 is different.

[0090] In some embodiments, the insulating layer penetrating the second connection region CTR2 ( Figure 4 and Figure 5 The surface pattern shape of the first upper pseudo-via DHU1 in 110) may be different from the surface pattern shape of the first lower pseudo-via DHL1 of the lower stacked structure SS1 that penetrates the first connection area CTR1.

[0091] As described above, according to the present invention, the surface pattern shapes of the channel holes CH and pseudo-holes DH formed in the cell array region CAR, the first connection region CTR1 and the second connection region CTR2 can be formed differently, thereby improving integration and design freedom, and manufacturing a reliable 3D semiconductor memory device.

[0092] Furthermore, according to the present invention, the pseudo-vias DH formed in the second connection region CTR2 and the first connection region CTR1 are formed differently, thereby manufacturing a reliable 3D semiconductor memory device with high design freedom.

[0093] Figures 9 to 15 This is a cross-sectional view illustrating a method for manufacturing a 3D semiconductor memory device according to an example embodiment.

[0094] In detail, Figures 9 to 15 It is along Figure 3 A sectional view taken from line II-II', showing the manufacturing process. Figure 5 The method for creating a 3D semiconductor memory device is shown.

[0095] First, refer to Figure 9An insulating layer IL and a first sacrificial layer HL1 are stacked vertically and alternately on the surface of substrate 100 to form a lower stack structure SS1. The insulating layer IL and the first sacrificial layer HL1 may be referred to as the lower molding layer. Substrate 100 may include a cell array region CAR and a connection region CTR. In embodiments, substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0096] The connection region CTR may include a second connection region CTR2 adjacent to the cell array region CAR and a first connection region CTR1 adjacent to the second connection region CTR2. For example, the second connection region CTR2 may be horizontally adjacent to the cell array region CAR and located between the cell array region CAR and the first connection region CTR1. An etch stop layer ESL may be formed on the topmost first sacrificial layer HL1. The etch stop layer ESL may be formed only if necessary, and in some embodiments, it may be omitted.

[0097] The insulating layer IL, the first sacrificial layer HL1, and the etch stop layer ESL can be formed by a thermochemical vapor deposition (CVD) process, a plasma-enhanced CVD process, a physical CVD process, or an atomic layer deposition (ALD) process. The insulating layer IL may comprise a silicon oxide film, and the first sacrificial layer HL1 may comprise a silicon nitride film or a silicon oxynitride film. The etch stop layer ESL may comprise a polycrystalline silicon film.

[0098] Reference Figure 10 A lower channel via (CHL) penetrating the lower stacked structure (SS1) is formed on the cell array region (CAR) to expose the substrate 100. The diameter of the lower channel via (CHL) can gradually decrease as the distance from the substrate 100 decreases. For example, the diameter of the lower channel via (CHL) can be smaller near the substrate 100 and larger near the etch stop layer (ESL).

[0099] The operations for forming the lower channel hole CHL may include operations for forming a mask pattern including an opening and operations for etching the lower stack structure SS1 using the mask pattern as an etching mask, wherein the opening is used to define the area on the lower stack structure SS1 where the lower channel hole CHL is formed.

[0100] The mask pattern can then be removed. During the operation of etching the lower stacked structure SS1, the top surface of the substrate 100 may be over-etched. As a result, the top of the substrate 100 may be recessed into the area below the lower channel via CHL.

[0101] A sacrificial insulating pattern SIP can be formed to fill the lower channel via CHL. Operations for forming the sacrificial insulating pattern SIP may include operations for forming a sacrificial insulating layer to fill the lower channel via CHL on the lower stack structure SS1 and operations for planarizing the sacrificial insulating layer until the top surface of the etch stop layer ESL is exposed.

[0102] Additionally, a second lower dummy via DHL2 may be formed in the lower stacked structure SS1 that penetrates the second connection region CTR2. The diameter of the second lower dummy via DHL2 may gradually decrease as the distance from the substrate 100 decreases. For example, the diameter of the second lower dummy via DHL2 may be smaller near the substrate 100 and larger near the etch stop layer ESL. The formation of the second lower dummy via DHL2 may be substantially similar to the formation of the lower channel via CHL. In some embodiments, the second lower dummy via DHL2 may be filled with a sacrificial insulating pattern SIP.

[0103] In one example embodiment, the operations for forming the lower channel via CHL and the operations for forming the second lower dummy via DHL2 can be performed simultaneously. In some embodiments, the operations for forming the lower channel via CHL and the operations for forming the second lower dummy via DHL2 can be performed separately.

[0104] Reference Figure 11 The upper stacked structure SS2 can be formed by vertically and alternately stacking an insulating layer IL and a second sacrificial layer HL2 on the lower stacked structure SS1. The insulating layer IL and the second sacrificial layer HL2 can be referred to as the upper molding layer. The lower stacked structure SS1 and the upper stacked structure SS2 can constitute the stacked structure ST. The insulating layer IL and the second sacrificial layer HL2 can be formed by essentially the same operation as described above with respect to the lower stacked structure SS1.

[0105] An upper channel via (CHU) can be formed on the cell array region (CAR) to penetrate the upper stacked structure (SS2) and expose the sacrificial insulating pattern (SIP). The diameter of the upper channel via (CHU) can gradually decrease with decreasing distance from the substrate 100. For example, the diameter of the upper channel via (CHU) can be smaller closer to the substrate 100 and larger further away from the substrate 100. The upper channel via (CHU) can be formed to perpendicularly overlap with the lower channel via (CHL).

[0106] The operation for forming the upper channel via CHU can be the same as the operation for forming the lower channel via CHL described above. For example, when forming the upper channel via CHU, misalignment with the lower channel via CHL may occur. In this case, the etch stop layer ESL can prevent the lower stack structure SS1 from being etched.

[0107] During the formation of the upper via CHU, the sacrificial insulation pattern SIP exposed through the upper via CHU can be selectively removed. Therefore, the lower via CHL and the upper via CHU are interconnected and form a single via. Figure 3 CH in (the text).

[0108] Because the lower channel hole CHL and the upper channel hole CHU are formed in different operations, the diameter of the channel hole CH can change discontinuously. For example, the diameter of the channel hole CH at the junction or boundary region between the lower stack structure SS1 and the upper stack structure SS2 can increase discontinuously (suddenly). The sidewalls of the channel hole CH can have a discontinuous profile (i.e., a stepped profile).

[0109] Reference Figure 12 A stepped structure can be formed in the stacked structure ST on the connection region CTR. The stepped structure can be formed by repeatedly performing the following operations: operations for forming a mask pattern on the stacked structure ST, operations for etching a portion of the stacked structure ST by using the mask pattern as an etching mask, and clipping operations for reducing the size of the mask pattern.

[0110] The etching operation of a portion of the stacked structure ST may include etching multiple sacrificial layers HL1 and HL2 exposed by the mask pattern. The clipping operation may be used to reduce the area of ​​the mask pattern by horizontally moving the sidewalls of the mask pattern a specific distance.

[0111] Reference Figure 13 A buried insulating layer 110 covering the stacked structure ST can be formed on the top surface of the substrate 100. A second upper pseudo-via DHU2 penetrating the upper stacked structure SS2 in the second connection region CTR2 and the buried insulating layer 110 can be formed, as well as a first upper pseudo-via DHU1 and a first lower pseudo-via DHL1 penetrating the lower stacked structure SS1 in the first connection region CTR1 and the buried insulating layer 110.

[0112] The diameters of the second upper dummy via DHU2, the first upper dummy via DHU1, and the first lower dummy via DHL1 can gradually decrease as the distance from the substrate 100 decreases. The formation of the second upper dummy via DHU2, the first upper dummy via DHU1, and the first lower dummy via DHL1 can be basically similar to the formation of the aforementioned channel via CH.

[0113] The second upper dummy hole DHU2, the first upper dummy hole DHU1, and the first lower dummy hole DHL1 can be formed by the same operation. In one example embodiment, since the first upper dummy hole DHU1 and the first lower dummy hole DHL1 are formed by the same operation, the diameters of the first upper dummy hole DHU1 and the first lower dummy hole DHL1 can be continuously changed.

[0114] For example, the diameters of the first upper dummy hole DHU1 and the first lower dummy hole DHL1 in the junction or boundary region between the lower stacked structure SS1 and the upper stacked structure SS2 can change continuously. The inner sidewalls of the first upper dummy hole DHU1 and the first lower dummy hole DHL1 can have a continuous profile.

[0115] In one embodiment, since the second upper pseudo-hole DHU2 and the second lower pseudo-hole DHL2 are formed through different operations, the diameters of the second upper pseudo-hole DHU2 and the second lower pseudo-hole DHL2 can be changed discontinuously.

[0116] For example, the diameters of the second upper pseudo-hole DHU2 and the second lower pseudo-hole DHL2 at the junction or boundary region between the lower stacked structure SS1 and the upper stacked structure SS2 may increase discontinuously (suddenly). The inner walls of the second upper pseudo-hole DHU2 and the second lower pseudo-hole DHL2 may have discontinuous profiles (i.e., stepped profiles).

[0117] Reference Figure 14 A vertical structure VS can be formed in the channel hole CH, and a pseudo structure DS can be formed in the pseudo hole DH. In the current embodiment, the vertical structure VS and the pseudo structure DS can be formed simultaneously.

[0118] Specifically, a lower semiconductor pattern (LSP) can be formed on the portion of substrate 100 exposed through the channel vias CH and dummy vias DH. The lower semiconductor pattern (LSP) can fill the lower portion of the channel vias CH and dummy vias DH. The portion of substrate 100 exposed through the channel vias CH and dummy vias DH can be used as a seed layer to form the lower semiconductor pattern (LSP) through a selective epitaxial growth operation.

[0119] A vertical insulating layer VP and an upper semiconductor pattern USP can be formed, sequentially covering the inner walls of the channel via CH and the dummy via DH. Each of the vertical insulating layer VP and the upper semiconductor pattern USP can be formed by an ALD process or a CVD process. Then, a buried insulating pattern VI that completely fills the channel via CH and the dummy via DH can be formed.

[0120] Reference Figure 15 A first interlayer insulation layer 120 can be formed on the embedded insulation layer 110. Stacked structures ST spaced horizontally from each other can be formed by patterning the stacked structures ST. The stacked structures ST can be arranged in a second direction (Y-direction) while extending in a first direction (X-direction).

[0121] A trench TR may be defined between adjacent stacked structures ST. The trench TR may expose a portion of the substrate 100. The trench TR may extend along the stacked structures ST in a first direction (X-direction).

[0122] Return to reference Figure 4 and Figure 5 The first sacrificial layer HL1 and the second sacrificial layer HL2 can be replaced by the electrode EL. Specifically, the first sacrificial layer HL1 and the second sacrificial layer HL2 exposed through the trench TR are selectively removed, and the electrode EL can be formed in the space where the first sacrificial layer HL1 and the second sacrificial layer HL2 have been removed.

[0123] In one example embodiment, it is possible to Figure 12 Following the manufacturing process, an operation is performed to replace the first sacrificial layer HL1 and the second sacrificial layer HL2 with the electrode EL. For example, as... Figure 12 As shown, the first sacrificial layer HL1 and the second sacrificial layer HL2 exposed through the lower channel hole CHL, the upper channel hole CHU, and the second lower pseudo-via DHL2 can be selectively removed, and the electrode EL can be formed in the space where the first sacrificial layer HL1 and the second sacrificial layer HL2 have been removed.

[0124] A common-source region (CSR) can be formed by doping the portion of the substrate 100 exposed through the trench TR. An insulating spacer SP and a common-source plug CSP can be formed sequentially filling the trench TR. The common-source plug CSP can be connected to the common-source region (CSR).

[0125] A second interlayer insulating layer 130 may be formed on the first interlayer insulating layer 120. A bit line contact plug BPLG may be formed that penetrates the first interlayer insulating layer 120 and the second interlayer insulating layer 130 and is connected to the vertical structure VS. A contact plug CP may be formed that penetrates the first interlayer insulating layer 120, the second interlayer insulating layer 130, penetrates the buried insulating layer 110, and is connected to the electrode EL. Each of the contact plugs CP may have a substantially vertical sidewall that extends continuously from the top surface of the second interlayer insulating layer 130 to the electrode EL to which the contact plug CP is connected.

[0126] A bit line BL electrically connected to the bit line contact plug BPLG and a first circuit line CL1 and a second circuit line CL2 electrically connected to the contact plug CP can be formed on the second interlayer insulation layer 13.

[0127] Based on the example method for manufacturing a 3D semiconductor memory device according to the example embodiment, a lower stacked structure SS1 and a lower channel via CHL can be formed, and then an upper stacked structure SS2 and an upper channel via CHU can be formed. A channel via CH formed by the interconnection of the lower channel via CHL and the upper channel via CHU can completely penetrate the multi-layered stacked structure ST. Therefore, both the integration density and reliability of the 3D semiconductor memory device can be improved.

[0128] In an example method for manufacturing a 3D semiconductor memory device according to the present invention, a second lower pseudo-via DHL2 is formed in the second connection region CTR2 during the formation of the lower channel via CHL. Additionally, based on the example method for manufacturing a 3D semiconductor memory device according to the present invention, after forming the upper stacked structure SS2, a second upper pseudo-via DHU2 can be formed in the second connection region CTR2 by an etching operation, and a first lower pseudo-via DHL1 and a first upper pseudo-via DHU1 can be formed in the first connection region CTR1.

[0129] Through the above manufacturing process, the second lower pseudo-hole DHL2, the second upper pseudo-hole DHU2, the first lower pseudo-hole DHL1, and the first upper pseudo-hole DHU1 can have various surface pattern shapes, thus increasing the degree of design freedom.

[0130] According to an example method for manufacturing a 3D semiconductor memory device conceived in this invention, the manufacturing process can be simplified by forming a lower stacked structure SS1 and an upper stacked structure SS2 and then immediately forming a stepped structure on the connection region CTR.

[0131] Figure 16 This is a conceptual diagram used to describe the sequence of manufacturing a 3D semiconductor memory device according to an example embodiment.

[0132] In detail, Figure 16 This may include manufacturing the above references Figures 3 to 15 The sequence of the aforementioned 3D semiconductor memory device. Figure 16 In the description, with Figures 3 to 15 The same label indicates the same element.

[0133] First, a lower molding layer is formed on the cell array region CAR and the connection region CTR to form a lower stack structure SS1 (operation S1). The lower molding layer may be a structure with the aforementioned insulating layer IL and the first sacrificial layer HL1 stacked on top of each other.

[0134] Next, operation S2 is performed to form a lower channel via CHL through the lower stack structure SS1 of the cell array region CAR. Then, operation S3 is performed to form a second lower pseudo-via DHL2 through the lower stack structure SS1 of the second connection region CTR2. Operation S2 for forming the lower channel via CHL and operation S3 for forming the second lower pseudo-via DHL2 are performed simultaneously.

[0135] Next, an operation is performed to form an upper molding layer on the cell array region CAR and the connection region CTR to form an upper stacked structure SS2 (operation S4). The upper molding layer may be a structure with the aforementioned insulating layer IL and the second sacrificial layer HL2 stacked on top. Next, an operation is performed to form an upper channel via CHU through the upper stacked structure SS2 of the cell array region CAR (operation S5).

[0136] Next, an operation (operation S6) is performed to form a stepped structure by patterning one side of the lower stacked structure SS1 in the connection region CTR and one side of the upper stacked structure SS2 in the connection region CTR. When necessary, an operation can be performed to replace the first sacrificial layer HL1 and the second sacrificial layer HL2 included in the lower molding layer and the upper molding layer with the electrode EL.

[0137] Next, the operation of embedding the insulating layer 110 for forming the upper stack structure SS2 and the lower stack structure SS1 for forming the coverage cell array region CAR and the connection region CTR is performed (operation S7).

[0138] Next, the operation of forming a second upper pseudo-via DHU2 for the upper stacked structure SS2 penetrating the second connection region CTR2 is performed (operation S8). Next, the operation of forming a first upper pseudo-via DHU1 and a first lower pseudo-via DHL1 for the upper stacked structure SS2 and the lower stacked structure SS1 penetrating the first connection region CTR1 is performed (operation S9). Operation S8 for forming the second upper pseudo-via DHU2 and operation S9 for forming the first upper pseudo-via DHU1 and the first lower pseudo-via DHL1 can be performed simultaneously.

[0139] Figure 17 This is a layout diagram of a 3D semiconductor memory device according to an example embodiment. Figure 18 and Figure 19 They are along Figure 17 The sectional view taken by lines I-I' and II-II'.

[0140] In detail, apart from the embedded insulating layer 110 formed in the first connection region CTR1 which does not have a contact plug CP, Figures 17 to 19 3D semiconductor memory device 20 can be used with Figure 3 It is the same as the 3D semiconductor memory device 10 in Figure 7. Figure 18 The M and N regions in the text can be respectively connected with... Figure 6A and Figure 6B The M and N regions shown are the same. Figure 19 O area in Figure 7A The O region shown is the same, so a detailed description of it will be omitted.

[0141] exist Figures 17 to 19 In the text, the references above will be simply provided or omitted. Figure 3 The description provided in the figure is the same. Figures 17 to 19 In, with Figure 3 The same labels as those in Figure 7 indicate the same components.

[0142] like Figures 17 to 19 As shown, no contact plug CP is formed in the first connection area CTR1 of the connection area CTR. Figure 17 As shown, only the first lower pseudo-structure DSL1 can be formed in the first connection area CTR1.

[0143] like Figure 18 and Figure 19 As shown, a second upper pseudo-structure DSU2 and a second lower pseudo-structure DSL2 can be formed in the second connection area CTR2. Furthermore, a first lower pseudo-structure DSL1 can be formed in the first connection area CTR1.

[0144] Unlike the cell array region CAR and the second connection region CTR2, the first lower pseudo-structure DSL1 may include a buried insulating layer 110. Only the buried insulating layer 110 may be formed in the first connection region CTR1, without forming the upper stacked structure SS2.

[0145] Figures 17 to 19 The 3D semiconductor memory device 20 can be formed with connection regions CTRs of various structures, so that a stacked structure SS2 is not formed in the first connection region CTR1. Therefore, the degree of design freedom can be improved.

[0146] Figure 20 This is a planar layout diagram of the channel holes and pseudo-holes of a 3D semiconductor memory device according to an example embodiment.

[0147] In detail, Figure 20 It shows the formation in Figures 17 to 19 An example planar layout of the cell array region CAR, the first connection region CTR1, and the second connection region CTR2 in a 3D semiconductor memory device 20, showing the channel via CH and the pseudo-via DH. Figure 20 In the following text, references to the above will be provided or omitted. Figure 8 The provided description is the same as the description.

[0148] The number of channel vias CH and pseudo-vias DH formed in the cell array region CAR, the first connection region CTR1, and the second connection region CTR2 is merely an example, and the inventive concept is not limited thereto. Vertical structures (e.g., Figures 17 to 19 Vertical structures (VS) and pseudo-structures (e.g., in the context of vertical structures) and pseudo-structures. Figures 17 to 19 The pseudo-structure DS can be formed in the channel hole CH and the pseudo-hole DH.

[0149] In some embodiments, the surface pattern shape of the lower channel hole CHL formed in the lower stacked structure SS1 in the cell array region CAR may be the same as the surface pattern shape of the upper channel hole CHU formed in the upper stacked structure SS2.

[0150] In some embodiments, a dummy via DH may include a lower dummy via DHL penetrating the lower stacked structure SS1 and an upper dummy via DHU penetrating the upper stacked structure SS2. The surface pattern shape of the lower dummy via DHL may be different from the surface pattern shape of the upper dummy via DHU.

[0151] In some embodiments, the surface pattern shape of the lower channel hole CHL formed in the lower stacked structure SS1 in the cell array region CAR may be the same as the surface pattern shape of the upper channel hole CHU formed in the upper stacked structure SS2. The surface pattern shapes of the lower channel hole CHL and the upper channel hole CHU may be circular or elliptical. The diameter of the lower channel hole CHL may be larger than the diameter of the upper channel hole CHU.

[0152] In some embodiments, the surface pattern shape of the first lower pseudo-hole DHL1 penetrating the lower stacked structure SS1 of the first connection area CTR1 may be different from the surface pattern shape of the second upper pseudo-hole DHU2 penetrating the upper stacked structure SS2 of the second connection area CTR2.

[0153] In some embodiments, the surface pattern shape of the second lower pseudo-hole DHL2 penetrating the lower stacked structure SS1 of the second connection region CTR2 and the surface pattern shape of the first lower pseudo-hole DHL1 penetrating the lower stacked structure SS1 of the first connection region CTR1 may be different from the surface pattern shape of the second upper pseudo-hole DHU2 penetrating the upper stacked structure SS2 of the second connection region CTR2.

[0154] In some embodiments, the surface pattern shape of the second lower pseudo-hole DHL2 penetrating the lower stacked structure SS1 of the second connection region CTR2 may be different from the surface pattern shape of the first lower pseudo-hole DHL1 penetrating the lower stacked structure SS1 of the first connection region CTR1.

[0155] In some embodiments, a second lower pseudo-via DHL2 penetrating the lower stacked structure SS1 and a second upper pseudo-via DHU2 penetrating the upper stacked structure SS2 may be formed in the second connection region CTR2. A first lower pseudo-via DHL1 penetrating the lower stacked structure SS1 and a buried insulating layer covering the lower stacked structure SS1 including the first lower pseudo-via DHL1 (e.g., Figure 18 and Figure 19 The buried insulating layer 110 can be formed in the first connection area CTR1.

[0156] As described above, according to the present invention, the pseudo-vias DH formed in the second connection region CTR2 and the first connection region CTR1 are formed differently, thereby manufacturing a reliable 3D semiconductor memory device.

[0157] Figures 21 to 26 This is a cross-sectional view used to describe a method of manufacturing a 3D semiconductor memory device according to an example embodiment.

[0158] In detail, Figures 21 to 26 It is along Figure 17 A sectional view taken from line II-II', showing the manufacturing process. Figure 19 The method for creating a 3D semiconductor memory device is shown. Figures 21 to 26 In, with Figures 9 to 15 The same labels in the text indicate the same element, and a detailed description of it will be provided or omitted.

[0159] First, as referenced above Figure 9As described, the insulating layer IL and the first sacrificial layer HL1 are stacked vertically and alternately on the surface of the substrate 100 to form a lower stack structure SS1. The insulating layer IL and the first sacrificial layer HL1 may be referred to as the lower molding layer. The substrate 100 may include a cell array region CAR and a connection region CTR.

[0160] The connection region CTR may include a second connection region CTR2 horizontally adjacent to the cell array region CAR and a first connection region CTR1 horizontally adjacent to the second connection region CTR2. An etch stop layer ESL may be formed on the topmost first sacrificial layer HL1. The etch stop layer ESL may be formed only when necessary, and in some embodiments, it may be omitted.

[0161] Reference Figure 21 A through-beam stacked structure SS1 is formed on the cell array region CAR, exposing the lower channel via CHL of the substrate 100. A sacrificial insulating pattern SIP that fills the lower channel via CHL can be formed.

[0162] Additionally, a second lower dummy via DHL2 can be formed in the lower stacked structure SS1 that penetrates the second connection region CTR2. A first lower dummy via DHL1 can be formed in the lower stacked structure SS1 that penetrates the first connection region CTR1. The diameters of the second lower dummy via DHL2 and the second lower dummy via DHL1 can gradually decrease as the distance from the substrate 100 decreases.

[0163] In one embodiment, the operations for forming the lower channel via CHL, the operations for forming the second lower dummy via DHL2, and the operations for forming the first lower dummy via DHL1 can be performed simultaneously. In some embodiments, the operations for forming the lower channel via CHL, the operations for forming the second lower dummy via DHL2, and the operations for forming the first lower dummy via DHL1 can be performed separately. In some embodiments, the operations for forming the lower dummy via DHL2 and the operations for forming the first lower dummy via DHL1 can be performed separately.

[0164] Reference Figure 22 The upper stacked structure SS2 can be formed by vertically and alternately stacking an insulating layer IL and a second sacrificial layer HL2 on the lower stacked structure SS1. The insulating layer IL and the second sacrificial layer HL2 can be referred to as the upper molding layer. The lower stacked structure SS1 and the upper stacked structure SS2 can constitute the stacked structure ST.

[0165] An upper channel via (CHU) can be formed on the cell array region (CAR) to penetrate the upper stacked structure (SS2) and expose the sacrificial insulating pattern (SIP). The diameter of the upper channel via (CHU) can gradually decrease as the distance from the substrate 100 decreases. The upper channel via (CHU) can be formed to overlap perpendicularly with the lower channel via (CHL).

[0166] The operation for forming the upper via CHU can be the same as the operation for forming the lower via CHL described above. During the formation of the upper via CHU, the sacrificial insulation pattern SIP exposed through the upper via CHU can be selectively removed. Therefore, the lower via CHU and the upper via CHU are interconnected and constitute a single via (e.g., Figure 19 The channel hole (CH) in the middle.

[0167] Because the lower channel hole CHL and the upper channel hole CHU are formed in different operations, the diameter of the channel hole CH can change discontinuously. For example, the diameter of the channel hole CH in the interface or boundary region between the lower stack structure SS1 and the upper stack structure SS2 can increase discontinuously (suddenly). The sidewalls of the channel hole CH can have a discontinuous profile (i.e., a stepped profile).

[0168] Reference Figure 23 A stepped structure can be formed in the stacked structure ST on the connection region CTR. The stepped structure can be formed by repeatedly performing the following operations: operations for forming a mask pattern on the stacked structure ST, operations for etching a portion of the stacked structure ST by using the mask pattern as an etching mask, and clipping operations for reducing the size of the mask pattern.

[0169] Operations for etching a portion of the stacked structure ST may include etching multiple sacrificial layers HL1 and HL2 exposed through a mask pattern. A clipping operation may be used to reduce the area of ​​the mask pattern by horizontally moving the sidewalls of the mask pattern a specific distance.

[0170] Reference Figure 24 A buried insulating layer 110 covering the stacked structure ST can be formed on the top surface of the substrate 100. An upper stacked structure SS2 penetrating the second connection region CTR2 and a second upper pseudo-via DHU2 penetrating the buried insulating layer 110 can be formed.

[0171] The diameter of the second upper dummy via DHU2 can gradually decrease as the distance from the substrate 100 decreases. The formation of the second upper dummy via DHU2 can be basically similar to the formation of the channel via CH described above.

[0172] In some embodiments, since the second upper pseudo-hole DHU2 and the second lower pseudo-hole DHL2 are formed through different operations, the diameters of the second upper pseudo-hole DHU2 and the second lower pseudo-hole DHL2 can be changed discontinuously.

[0173] For example, the diameter of the second upper pseudo-hole DHU2 and the second lower pseudo-hole DHL2 at the junction or boundary region between the lower stacked structure SS1 and the upper stacked structure SS2 may increase discontinuously (suddenly). The inner walls of the second upper pseudo-hole DHU2 and the second lower pseudo-hole DHL2 may have discontinuous profiles (i.e., stepped profiles).

[0174] Reference Figure 25 A vertical structure VS can be formed in the channel hole CH. A pseudo structure DS can be formed in the second lower pseudo hole DHL2 and the second upper pseudo hole DH2. The pseudo structure DS may include the lower pseudo structure DSL and the upper pseudo structure DSU.

[0175] The second lower pseudo-structure DSL2 and the second upper pseudo-structure DSU2 can be formed in the second lower pseudo-hole DHL2 and the second upper pseudo-hole DHL2, respectively. The first lower pseudo-structure DSL1 can be formed in the first lower pseudo-hole DHL1. In the current embodiment, the vertical structure VS and the pseudo-structure DS can be formed simultaneously.

[0176] Reference Figure 26 A first interlayer insulation layer 120 can be formed on the embedded insulation layer 110. The stacked structures ST can be formed by patterning the stacked structures ST to create horizontally separated stacked structures ST. The stacked structures ST can be arranged in a second direction (Y-direction) while extending in a first direction (X-direction).

[0177] A trench TR may be defined between adjacent stacked structures ST. The trench TR may expose a portion of the substrate 100. The trench TR may extend along the stacked structures ST in a first direction (X-direction).

[0178] Return to reference Figure 18 and Figure 19 The first sacrificial layer HL1 and the second sacrificial layer HL2 can be replaced by the electrode EL. Specifically, the first sacrificial layer HL1 and the second sacrificial layer HL2 exposed through the trench TR are selectively removed, and the electrode EL can be formed in the space where the first sacrificial layer HL1 and the second sacrificial layer HL2 have been removed.

[0179] In some embodiments, it is possible to Figure 23 Following the manufacturing process, an operation is performed to replace the first sacrificial layer HL1 and the second sacrificial layer HL2 with the electrode EL. For example, as... Figure 23 As shown, the first sacrificial layer HL1 and the second sacrificial layer HL2 exposed through the lower channel hole CHL, the upper channel hole CHU, and the second lower pseudo-via DHL2 can be selectively removed, and the electrode EL can be formed in the space where the first sacrificial layer HL1 and the second sacrificial layer HL2 have been removed.

[0180] A common-source region (CSR) can be formed by exposing a portion of the substrate 100 through a trench (TR) to doping. An insulating spacer (SP) and a common-source plug (CSP) can be formed sequentially filling the trench (TR). The common-source plug (CSP) can be connected to the common-source region (CSR).

[0181] A second interlayer insulating layer 130 may be formed on the first interlayer insulating layer 120. A bit line contact plug BPLG may be formed that penetrates the first interlayer insulating layer 120 and the second interlayer insulating layer 130 and is connected to the vertical structure VS. A contact plug CP may be formed that penetrates the first interlayer insulating layer 120, the second interlayer insulating layer 130, penetrates the buried insulating layer 110, and is connected to the electrode EL.

[0182] A bit line BL electrically connected to the bit line contact plug BPLG and a first circuit line CL1 and a second circuit line CL2 electrically connected to the contact plug CP can be formed on the second interlayer insulation layer 130.

[0183] In an example method for manufacturing a 3D semiconductor memory device according to the present invention, during the formation of the lower channel via CHL, a second lower pseudo-via DHL2 and a first lower pseudo-via DHL1 are formed in the second connection region CTR2 and the first connection region CTR1. Additionally, in another example method for manufacturing a 3D semiconductor memory device according to the present invention, after forming the upper stacked structure SS2, a second upper pseudo-via DHU2 is formed in the second connection region CTR2, and a buried insulating layer 110 is formed in the first connection region CTR1.

[0184] Through this manufacturing process, the pseudo-vias DH formed in the second connection region CTR2 and the first connection region CTR1 can have various surface pattern shapes, and by forming a buried insulating layer 110 on the first connection region CTR1, the degree of freedom of the 3D semiconductor memory device 20 can be improved.

[0185] Figure 27 This is a conceptual diagram used to explain the sequence of manufacturing a 3D semiconductor memory device according to an example embodiment.

[0186] In detail, Figure 27 This may include manufacturing the above references Figures 17 to 26 The order of the described 3D semiconductor memory device. Figure 27 In the description, with Figures 17 to 26 In the same way, the same labels indicate the same components. Additionally, in... Figure 27 In the description, with Figure 16 The same label indicates the same element.

[0187] First, a lower molding layer is formed on the cell array region CAR and the connection region CTR to form a lower stack structure SS1 (operation S1). The lower molding layer may be a structure with the aforementioned insulating layer IL and the first sacrificial layer HL1 stacked on top of each other.

[0188] Next, the operation of forming the lower channel via CHL of the lower stacked structure SS1 that penetrates the cell array region CAR is performed (operation S2). Next, the operation of forming the first lower pseudo-via DHL1 and the second lower pseudo-via DHL2 of the lower stacked structure SS1 that penetrates the first connection region CTR1 and the second connection region CTR2 is performed (operation S3). Operation S2 for forming the lower channel via CHL and operation S3 for forming the first lower pseudo-via DHL1 and the second lower pseudo-via DHL2 can be performed simultaneously.

[0189] Next, an operation is performed to form an upper molding layer on the cell array region CAR and the connection region CTR to form an upper stacked structure SS2 (operation S4). The upper molding layer may be a structure with the aforementioned insulating layer IL and the second sacrificial layer HL2 stacked on top. Next, an operation is performed to form an upper channel via CHU that penetrates the upper stacked structure SS2 of the cell array region CAR (operation S5).

[0190] Next, an operation (operation S6) is performed to form a stepped structure by patterning one side of the lower stacked structure SS1 in the connection region CTR and one side of the upper stacked structure SS2 in the connection region CTR. In some embodiments, an operation is performed to replace the first sacrificial layer HL1 and the second sacrificial layer HL2 included in the lower molding layer and the upper molding layer with the electrode EL.

[0191] Next, the operation of embedding the insulating layer 110 for forming the upper stacked structure SS2 and the lower stacked structure SS1 covering the cell array region CAR and the connection region CTR is performed (operation S7). Next, the operation of forming the second upper dummy via DHU2 of the upper stacked structure SS2 penetrating the second connection region CTR2 is performed (operation S8).

[0192] Although the inventive concept has been specifically shown and described with reference to it, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the claims.

Claims

1. A 3-dimensional semiconductor memory device comprising: a substrate including a cell array region and a connection region; a stack structure including insulating layers and electrodes which are alternately and vertically stacked on the substrate, and including a step structure located in the connection region, and including a lower stack structure and an upper stack structure which are sequentially stacked on the substrate; a vertical structure located in a channel hole which penetrates the lower stack structure and the upper stack structure on the cell array region; and a dummy structure located in a dummy hole which penetrates at least one of the lower stack structure and the upper stack structure on the connection region, wherein the connection region includes a second connection region located on a side of the cell array region and a first connection region located on a side of the second connection region, and the second connection region is located between the first connection region and the cell array region, and wherein the dummy hole includes a first dummy hole in the first connection region and a second dummy hole in the second connection region, and a surface pattern shape of the first dummy hole is different from a surface pattern shape of the second dummy hole.

2. The 3-dimensional semiconductor memory device according to claim 1, the first dummy hole includes a first lower dummy hole which penetrates the lower stack structure and a first upper dummy hole which penetrates the insulating layer, wherein wherein the surface pattern shape of the first lower dummy hole is different from the surface pattern shape of the first upper dummy hole, wherein the second dummy hole includes a second lower dummy hole which penetrates the lower stack structure and a second upper dummy hole which penetrates the upper stack structure, and wherein the surface pattern shape of the second lower dummy hole is different from the surface pattern shape of the second upper dummy hole.

3. The 3-dimensional semiconductor memory device according to claim 1, the second dummy hole includes a second lower dummy hole which penetrates the lower stack structure and a second upper dummy hole which penetrates the upper stack structure, and wherein wherein the surface pattern shape of the second lower dummy hole which penetrates the lower stack structure of the second connection region is different from the surface pattern shape of the second upper dummy hole which penetrates the upper stack structure of the second connection region.

4. The 3-dimensional semiconductor memory device according to claim 1, the second dummy hole includes a second lower dummy hole which penetrates the lower stack structure, and the first dummy hole includes a first upper dummy hole which penetrates the insulating layer, and wherein wherein the surface pattern shape of the second lower dummy hole which penetrates the lower stack structure of the second connection region is different from the surface pattern shape of the first upper dummy hole which penetrates the insulating layer in the first connection region.

5. The 3-dimensional semiconductor memory device according to claim 1, the second dummy hole includes a second upper dummy hole which penetrates the upper stack structure, and the first dummy hole includes a first lower dummy hole which penetrates the lower stack structure, and wherein, wherein the surface pattern shape of the second upper dummy hole which penetrates the upper stack structure of the second connection region is different from the surface pattern shape of the first lower dummy hole which penetrates the lower stack structure in the first connection region.

6. The 3-dimensional semiconductor memory device according to claim 1, the first dummy hole includes a first lower dummy hole which penetrates the lower stack structure and a first upper dummy hole which penetrates the insulating layer, and wherein wherein the surface pattern shape of the first upper dummy hole which penetrates the insulating layer in the first connection region is different from the surface pattern shape of the first lower dummy hole which penetrates the lower stack structure in the first connection region. ​ 7. The 3-dimensional semiconductor memory device according to claim 1, wherein, the first dummy hole includes a first upper dummy hole that penetrates the insulating layer, and the second dummy hole includes a second upper dummy hole that penetrates the upper stack structure, and wherein a surface pattern shape of the first upper dummy hole that penetrates the insulating layer in the first connection region is different from a surface pattern shape of the second upper dummy hole that penetrates the upper stack structure of the second connection region.

8. The 3-dimensional semiconductor memory device according to claim 1, wherein the second dummy hole includes a second lower dummy hole that penetrates the lower stack structure and a second upper dummy hole that penetrates the upper stack structure, and the first dummy hole includes a first lower dummy hole that penetrates the lower stack structure, and wherein a surface pattern shape of the second lower dummy hole that penetrates the lower stack structure of the second connection region and a surface pattern shape of the first lower dummy hole that penetrates the lower stack structure in the first connection region are different from a surface pattern shape of the second upper dummy hole that penetrates the upper stack structure of the second connection region.

9. The 3-dimensional semiconductor memory device according to claim 8, wherein, the channel hole includes an upper channel hole that penetrates the upper stack structure and a lower channel hole that penetrates the lower stack structure, and wherein a surface pattern shape of the upper channel hole is different from a surface pattern shape of the lower channel hole.

10. The 3-dimensional semiconductor memory device according to claim 1, wherein the second dummy hole includes a second lower dummy hole that penetrates the lower stack structure, and the first dummy hole includes a first lower dummy hole that penetrates the lower stack structure, and wherein a surface pattern shape of the second lower dummy hole that penetrates the lower stack structure of the second connection region is different from a surface pattern shape of the first lower dummy hole that penetrates the lower stack structure in the first connection region.

11. The 3-dimensional semiconductor memory device according to claim 1, wherein the second dummy hole includes a second lower dummy hole that penetrates the lower stack structure in the second connection region and a second upper dummy hole that penetrates the upper stack structure in the second connection region, wherein the first dummy hole includes a first lower dummy hole that penetrates the lower stack structure in the first connection region, and wherein an insulating layer covers the lower stack structure and the first lower dummy hole in the first connection region.

12. The 3-dimensional semiconductor memory device according to claim 1, wherein the second connection region includes a region on which a second circuit line electrically connected to an electrode of the upper stack structure is arranged on one side of the cell array region, and wherein the first connection region includes a region on which a first circuit line electrically connected to an electrode of the lower stack structure is arranged on one side of the second connection region.

13. A 3-dimensional semiconductor memory device comprising: a substrate including a cell array region and a connection region; a stack structure including insulating layers and electrodes that are alternately and vertically stacked on the substrate, and including a step structure in the connection region, and including a lower stack structure and an upper stack structure that are sequentially stacked on the substrate; a vertical structure that penetrates the lower stack structure and the upper stack structure on the cell array region; and a dummy structure that penetrates at least one of the lower stack structure and the upper stack structure on the connection region. ​ The connection region includes a second connection region on one side of the cell array region and a first connection region on one side of the second connection region, the second connection region is between the first connection region and the cell array region, The dummy structure includes a first dummy structure and a second dummy structure, The second dummy structure includes a second lower dummy structure and a second upper dummy structure that penetrate a lower stack structure and an upper stack structure of the second connection region and are connected to each other, and the first dummy structure includes a first lower dummy structure and a first upper dummy structure that penetrate a lower stack structure and an insulating layer of the first connection region and are connected to each other, The second dummy structure includes a second dummy hole that penetrates a lower stack structure and an upper stack structure of the second connection region, the first dummy structure includes a first dummy hole that penetrates a lower stack structure and an insulating layer of the first connection region, and a surface pattern shape of the first dummy hole is different from a surface pattern shape of the second dummy hole, and The second dummy structure includes a non-continuous portion in which diameters of the second lower dummy structure and the second upper dummy structure are discontinuously changed at a boundary region of the second lower dummy structure and the second upper dummy structure.

14. The 3-dimensional semiconductor memory device according to claim 13, wherein, The first upper dummy structure and the first lower dummy structure include a continuous portion in which diameters are gradually and continuously increased.

15. The 3-dimensional semiconductor memory device according to claim 13, wherein, The first upper dummy structure and the first lower dummy structure constitute the same body.

16. The 3-dimensional semiconductor memory device of claim 13, wherein, Each of the vertical structures includes a lower vertical structure and an upper vertical structure that penetrate a lower stack structure and an upper stack structure, respectively, and are connected to each other, and The vertical structure includes a non-continuous portion in which diameters of the lower vertical structure and the upper vertical structure are discontinuously changed at a boundary region of the upper vertical structure and the lower vertical structure.

17. The 3-dimensional semiconductor memory device according to claim 13, wherein, The second lower dummy structure and the second upper dummy structure are formed in a second lower dummy hole and a second upper dummy hole that penetrate a lower stack structure and an upper stack structure of the second connection region, respectively, and The first lower dummy structure and the first upper dummy structure are formed in a first lower dummy hole and a first upper dummy hole that penetrate a lower stack structure and an insulating layer in the first connection region, respectively.

18. The 3-dimensional semiconductor memory device according to claim 13, wherein, An etching stop layer is formed on a topmost portion of the lower stack structure in the second connection region, and An etching stop layer is not formed on a topmost portion of the lower stack structure in the first connection region.

19. A 3-dimensional semiconductor memory device, comprising: a substrate including a cell array region and a connection region; a stack structure including insulating layers and electrodes that are alternately and vertically stacked on the substrate, and including a step structure in the connection region, and including a lower stack structure and an upper stack structure that are sequentially stacked on the substrate; a vertical structure that penetrates the lower stack structure and the upper stack structure on the cell array region; and a dummy structure that penetrates at least one of the lower stack structure and the upper stack structure on the connection region, The connection region includes a second connection region on one side of the cell array region and a first connection region on one side of the second connection region, the second connection region is between the first connection region and the cell array region, The dummy structure includes a first dummy structure and a second dummy structure, The second dummy structure includes a second lower dummy structure and a second upper dummy structure which penetrate a lower stack structure and an upper stack structure of the second connection region and are connected to each other, and the first dummy structure includes a first lower dummy structure which penetrates a lower stack structure of the first connection region, The second dummy structure includes a second dummy hole which penetrates a lower stack structure and an upper stack structure of the second connection region, the first dummy structure includes a first dummy hole which penetrates a lower stack structure of the first connection region, and a surface pattern shape of the first dummy hole is different from a surface pattern shape of the second dummy hole, The second dummy structure includes a non-continuous portion in which diameters of the second lower dummy structure and the second upper dummy structure are discontinuously changed at a boundary region of the second lower dummy structure and the second upper dummy structure, and An insulating layer covering a lower stack structure is formed in the first connection region.

20. The 3-dimensional semiconductor memory device according to claim 19, wherein, Each of the vertical structures includes a lower vertical structure and an upper vertical structure which penetrate a lower stack structure and an upper stack structure, respectively, and are connected to each other, and The vertical structure includes a non-continuous portion in which diameters of the lower vertical structure and the upper vertical structure are discontinuously changed at a boundary region of the upper vertical structure and the lower vertical structure.

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