Device, system and method for target address encryption

Abstract

According to one general aspect, a device, system, and method for target address encryption are provided. The device may include a context-specific encryption key circuit, the context-specific encryption key circuit is configured to generate a key value, wherein the key value is specific to the context of an instruction set. The device may include a target address prediction circuit, the target address prediction circuit is configured to provide a target address for the next instruction in the instruction set. The device may include a target address memory, the target address memory is configured to store an encrypted version of the target address, wherein the target address is encrypted at least in part using the key value. The device may further include an instruction fetch circuit, the instruction fetch circuit is configured to decrypt the target address at least in part using the key value, and retrieve the target address.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Provisional Patent Application No. 62 / 786,327, entitled “SECURE BRANCH PREDICTOR WITH CONTEXT-SPECIFIC LEARNED INSTRUCTION TARGET ADDRESS ENCRYPTION,” filed on December 28, 2018. The subject matter of this previously filed application is incorporated herein by reference. Technical Field

[0003] The present description relates to computer security and, more particularly, to a secure branch predictor with context-specific learned instruction target address encryption. Background Art

[0004] In 2018, a class of security vulnerabilities known as Spectre was made public. Specifically, Spectre attacks branch predictor targets. This class of attacks has since expanded to use various forms of side-channel or timing attacks to leak sensitive data to attacking processes that do not have privileged access to said data.

[0005] Initially, attacks focused on the speculative behavior of branch predictors, where the branch predictor can run ahead of actual program execution and start pulling in cache lines it thinks will be accessed soon. When the execution portion of the processor catches up, the speculative path is declared a misprediction, and the speculative state is flushed. While software may not be able to see the results of speculation that was not executed in the program, the hardware still retains some state, such as cache lines that were speculatively brought in. This speculative state can be forced along a path through false target injection, and subsequently exploited by an attacker program, using a "timing attack" in privileged memory space and inferring which line was speculatively accessed based on the hit latency.

[0006] Other security vulnerabilities in this class exposed by branch predictors are that an attacker program trains the predictor target and returns a call in a shared processor to jump to the illegal target using shared software resources or libraries, then switches the program to a victim thread which uses the common resources to speculatively jump to the poisoned target.

[0007] Ultimately, the use of speculation and shared resources on public CPUs exposes major security vulnerabilities in branch predictors, allowing external programs to infer secrets discovered speculatively by injecting bad targets, or to be trained to jump to undesired locations. Summary of the invention

[0008] According to one general aspect, a device may include context-specific encryption key circuitry configured to generate a key value, wherein the key value is specific to a context of an instruction set. The device may include a target address prediction circuit configured to provide a target address for a next instruction in the instruction set. The device may include a target address memory configured to store an encrypted version of a target address, wherein the target address is encrypted at least in part using the key value. The device may further include an instruction fetch circuit configured to decrypt the target address at least in part using the key value and retrieve the target address.

[0009] According to another general aspect, a system may include execution unit circuitry to process instructions associated with a first program. The system may include instruction fetch circuitry configured to fetch instructions at a target address associated with the first program via branch prediction and provide the instructions to the execution unit, wherein the instruction fetch circuitry is further configured to encrypt the target address such that a malicious second program is unable to read a correctly decrypted version of the target address.

[0010] According to another general aspect, a method may include: in response to starting to fetch a first instruction stream, generating a context-specific encryption key value that is substantially unique to the first instruction stream and associated with the first instruction stream. The method may include determining an instruction address associated with the first instruction stream. The method may include storing an encrypted version of the instruction address in a target address memory, wherein the instruction address is encrypted at least in part using the context-specific encryption key value, and thus a second instruction stream not associated with the context-specific encryption key value is not able to read the unencrypted instruction address.

[0011] The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.

[0012] A system and / or method for computer security and more particularly for a secure branch predictor with context-specific learned instruction target address encryption, substantially as depicted in and / or described in conjunction with at least one of the accompanying drawings, as more fully set forth in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a block diagram of an example embodiment of a system in accordance with the disclosed subject matter.

[0014] Figure 2 is a block diagram of an example embodiment of a system in accordance with the disclosed subject matter.

[0015] Figure 3is a block diagram of an example embodiment of a circuit in accordance with the disclosed subject matter.

[0016] Figure 4 is a schematic block diagram of an information processing system that may include devices formed according to the principles of the disclosed subject matter.

[0017] Like reference numbers in the various drawings indicate like elements.

[0018] Description of Figure Numbers

[0019] 100, 200: system;

[0020] 101: instruction cache memory;

[0021] 102: instruction fetch unit circuit;

[0022] 103: Branch prediction circuit or system;

[0023] 104: instruction decoding unit;

[0024] 106: execution unit;

[0025] 108: branch predictor circuit;

[0026] 110: program counter;

[0027] 112: branch target buffer;

[0028] 114: return address stack;

[0029] 118: selector;

[0030] 122, 222: encryption circuit;

[0031] 124, 224: decryption circuit;

[0032] 182: first program / program / software block / instruction set;

[0033] 184: Second procedure;

[0034] 202: target address memory;

[0035] 203, 205: XOR gate;

[0036] 204: context-specific encryption key;

[0037] 212: new target address;

[0038] 213: encrypted address;

[0039] 214: Plain text destination address;

[0040] 300: Circuits / Systems;

[0041] 301: key generator;

[0042] 302: Logic or circuit;

[0043] 304: context key;

[0044] 306: selector circuit;

[0045] 308: Entropy expansion circuit;

[0046] 400: Information processing system;

[0047] 405: system bus;

[0048] 410: processor;

[0049] 415: Combinational logic block;

[0050] 420: Volatile memory;

[0051] 430: non-volatile memory;

[0052] 440: network interface;

[0053] 450: user interface unit;

[0054] 460: Hardware components;

[0055] 470: Software component. DETAILED DESCRIPTION

[0056] Various example embodiments will be described more fully below with reference to the accompanying drawings, some of which are depicted in the accompanying drawings. However, the subject matter disclosed in the present invention may be implemented in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that the present disclosure will be thorough and comprehensive, and will fully convey the scope of the subject matter disclosed in the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0057] It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or coupled to another element or layer, or there may be intermediate elements or layers. In contrast, when an element is referred to as being "directly" "on," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. Like reference numerals refer to like elements throughout. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0058] It will be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the subject matter disclosed in the present invention, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

[0059] For ease of description, spatially relative terms such as "below," "below," "lower," "above," "upper," and similar terms may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to the orientation depicted in the figures. For example, if the device in the figure is turned upside down, then the elements described as "below" or "below" other elements or features will be oriented "above" the other elements or features. Therefore, the exemplary term "below" can cover both the above and below orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0060] Likewise, for ease of description, electrical terms such as "high," "low," "pull up," "pull down," "1," "0," and similar terms may be used herein to describe voltage levels or currents relative to other voltage levels or currents of another element or feature as shown in the figures. It should be understood that the electrically relative terms are intended to encompass different reference voltages of the device in use or operation in addition to the voltages or currents depicted in the figures. For example, if the device or signal in the figure is reversed or uses other reference voltages, currents, or charges, then the element described as "high" or "pull up" will be "low" or "pull down" compared to the new reference voltage or current. Thus, the exemplary term "high" may encompass relatively lower or higher voltages or currents. Devices may be based on different electrical reference frames in other ways, and the electrically relative descriptors used herein are interpreted accordingly.

[0061] The terms used herein are for the purpose of describing specific example embodiments only and are not intended to limit the subject matter disclosed herein. As used herein, the singular forms "a", "an", and "the" are intended to also include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms "comprises and / or comprising" when used in this specification specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0062] Example embodiments are described herein with reference to schematic cross-sectional illustrations as idealized example embodiments (and intermediate structures). In this way, differences from the illustrated shapes will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, example embodiments should not be interpreted as being limited to the specific shapes of the regions shown herein, but should include deviations in shapes, for example, caused by manufacturing. For example, an implant region shown as a rectangle will typically have a circular feature or a curved feature and / or a gradient of implant concentration on its edge, rather than a binary change from an implant region to a non-implant region. Similarly, a buried region formed by implantation can produce some implantation in the region between the buried region and the surface where the implantation occurs. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to show the actual shape of the region of the device and is not intended to limit the scope of the subject matter disclosed in the present invention.

[0063] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which the subject matter of the present disclosure belongs. It should be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such.

[0064] Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

[0065] Figure 1 1 is a block diagram of an example embodiment of a system 100 according to the disclosed subject matter. In various embodiments, the system 100 may be part of a processor (e.g., a central processing unit, a graphical processing unit (GPU), a system-on-a-chip (SoC), a dedicated controller processor, etc.) or any pipeline architecture. In various embodiments, the system 100 may be included in a computing device such as a laptop computer, a desktop computer, a workstation, a personal digital assistant, a smart phone, a tablet computer, and other suitable computers or their virtual machines or virtual computing devices.

[0066] In various embodiments, system 100 may illustrate the beginning portion of a pipelined architecture, such as a conventional five-stage reduced instruction set computer (RISC) architecture. It should be understood that the above is merely an illustrative example and does not limit the disclosed subject matter.

[0067] In such embodiments, a program, piece of software, or set of instructions 182 may be executed by the system 100. The program 182 may include various instructions. Some of the instructions may flow sequentially. Other instructions that are fast may jump between points in the program (e.g., subroutine calls / returns, if / then decisions, etc.).

[0068] In the illustrated embodiment, system 100 may include instruction cache memory (I-CACHE) 101. I-CACHE 101 may store instructions for system 100 to process.

[0069] In various embodiments, system 100 may include an instruction fetch unit circuit (IFU) 102. IFU 102 may be configured to fetch instructions (associated with a target address) and begin the process of providing instructions to execution unit 106 for processing. In the illustrated embodiment, IFU 102 may fetch instructions pointed to by program counter 110 (e.g., at the target address).

[0070] The IFU 102 may then pass such instructions to an instruction decode unit (IDU) or circuit 104. The IDU 104 may be configured to decode the instructions and route them to the appropriate execution unit 106. In such embodiments, multiple execution units 106 may be present and process instructions in a variety of ways. For example, the execution units 106 may include load / store units, floating point units, integer units, etc.

[0071] As described above, program 182 may include out-of-sequence jumps, and system 100 may employ speculative execution to improve efficiency (compared to sitting idle while a jump instruction is resolved). To do this, system 100 may include a branch prediction circuit or system 103. In various embodiments, branch prediction system 103 may be included as part of IFU 102. Branch prediction circuit or system 103 may be configured to predict what the next target memory address of the next (predicted) instruction will be.

[0072] In the illustrated embodiment, the branch prediction circuit 103 may include a branch predictor circuit 108 that actually makes the prediction. The branch prediction circuit 103 may include a branch target buffer (BTB) 112. The BTB 112 may be a content addressable memory that stores predicted target addresses or previously encountered target addresses and is indexed by the source address. The branch prediction circuit 103 may include a return address stack (RAS) 114. The RAS 114 may be configured to store the target address to the point in the program 182 where a subroutine call is made or a subroutine return is expected to the point.

[0073] In the illustrated embodiment, the branch predictor circuit 108 may query the BTB 112 and RAS 114 or its own internal logic and circuitry to generate a predicted target address. A selector 118 (e.g., a multiplexer (MUX)) may then select which prediction source is being used and provide the target address to the program counter 110 or IFU 102. In various embodiments, when the jump instruction is actually resolved by the execution unit 106, the correctness of the prediction may be fed back to the branch predictor circuit 108. It should be understood that the above is only an illustrative example that does not limit the disclosed subject matter.

[0074] As described above, some security vulnerabilities (e.g., Spectre-class vulnerabilities) exploit weaknesses in branch prediction circuit 103. In a simplified description, these malicious programs (e.g., second program 184) attempt to access BTB 112 and RAS 114 to obtain target addresses associated with other programs (e.g., first program 182). This may allow the malicious program to access data that it should not access. In general, system 100 should only allow program 182 and program 184 to access their respective associated target addresses. For security reasons, there should be a certain degree of compartmentalization between program 182 and program 184. As described above, some security vulnerabilities (e.g., Spectre-class vulnerabilities) violate the compartmentalization.

[0075] In the illustrated embodiment, to prevent unauthorized access to the target address, the system 100 can encrypt the target address. Specifically, the system 100 can encrypt the target address when storing the target address in one or more memories, the one or more memories (i.e., target address memory) storing the target address and represented by BTB 112 and RAS 114.

[0076] In such embodiments, encryption circuit 122 may perform encryption before the target address is stored in BTB 112 and RAS 114. Likewise, decryption circuit 124 may perform decryption on any target address retrieved from BTB 112 and RAS 114. In various embodiments, other encryption circuits 122 and decryption circuits 124 may be used with other target address memories. In various embodiments, encryption circuit 122 and decryption circuit 124 may be integrated into BTB 112, RAS 114, or other memories.

[0077] In various embodiments, context-specific encryption keys may be used. Figure 2 and Figure 3 Each context-specific key or hash may be associated with and substantially unique to a program 182 that is associated with the target address.

[0078] In such embodiments, if the malicious program 184 attempts to read an unauthorized target address (e.g., a target address associated with the first program 182) from the BTB 112, the decryption circuit 124 will use the malicious program's context-specific key. Since the key (the malicious program's key) will be wrong, the decrypted value will not be the target address. The malicious program will only get meaningless garbage from the BTB 112 / decryption circuit 124, thereby preventing the vulnerability.

[0079] Figure 2 is a block diagram of an example embodiment of a system 200 in accordance with the disclosed subject matter. In various embodiments, the system 200 can emphasize aspects of encryption employed during memory accesses (reads and writes) to the target address memory 202.

[0080] In the illustrated embodiment, the system 200 may include a target address memory 202 (e.g., a BTB, a RAS, etc.). The system 200 may include a context-specific encryption key 204. The context-specific encryption key 204 may include a register, a table, or a data structure, wherein the table or other data structure may store multiple keys 204 each associated with a different program, instruction set, or instruction stream.

[0081] In various embodiments, the context-specific encryption key 204 may be based on a constant, entropy or random value associated with the program and / or a contextual value. In some embodiments, the contextual value may include, but is not limited to, items such as a process identifier (ID), a kernel ID, a security state, a hypervisor ID, etc. In various embodiments, the entropy or random value may be provided by software, or may be the result of a (substantially) random number generation circuit. In various embodiments, the constant value may be provided by a hardware component (e.g., a serial number, a timer, etc.), and may be provided based on a context (e.g., the time when the program was first started) or a security mode. It should be understood that the above are only some illustrative examples that do not limit the disclosed subject matter.

[0082] In the illustrated embodiment, key 204 may be used in a stream cipher. In such embodiments, encryption may be relatively light weight and may have minimal impact on the processing time and power consumption of the overall system 200. In another embodiment, the encryption system may be more involved and heavier weight, requiring more resources and time. It should be understood that the above are only some illustrative examples that do not limit the disclosed subject matter.

[0083] In the illustrated embodiment, a simple XOR (gate 203 and gate 205) and / or offset can ensure target address safety when reading / writing from / to target address memory 202. This can avoid adding multiple cycle safety loops to the critical latency of the branch predictor.

[0084] In the illustrated embodiment, system 200 may include XOR gate 203 and XOR gate 205. Encryption circuit 222 and decryption circuit 224 may include shift or replacement logic; however, it should be understood that the above is merely an illustrative example that does not limit the disclosed subject matter.

[0085] In the illustrated embodiment, when a new target address 212 is to be stored, the address 212 may be XORed with the key 204. The output of the XOR gate 203 may then be shifted, (partially) replaced or masked by the encryption circuit 222. In various embodiments, this may involve the use of the key 204.

[0086] Likewise, when retrieving the target address, the encrypted address 213 may be unshifted, (partially) replaced, or masked by the decryption circuit 224. In various embodiments, this may involve the use of the key 204. The address may be XORed with the key 204. The output of the XOR gate 205 may be unencrypted or the plaintext target address 214 (which may be the same as the address 212 in the case where the same address is both written and read in the example).

[0087] In such embodiments, system 200 may include barriers to common stream cipher attacks, such as new key 204 computation for each process or instruction stream, use of non-obvious or unexpected constants to scramble plaintext attacks, and / or entropy expanders on key 204.

[0088] In one embodiment, by scrambling or encrypting the stored target address, both cases of speculative execution and shared resource attacks (cross-training to a protected address) can be thwarted because only the process created or associated with the target address will have the correct key 204 to restore the target address. Any attacker program that injects a false target address or trains the program to jump to an undesired location will incorrectly decode or decrypt the target address and send the processor to an unknown location.

[0089] In such embodiments, any branch predictor training (e.g., shared library training) may react to an incorrectly decrypted target address by mispredicting and relearning the target address only once in a new context. In various embodiments, branch predictor biases, history, and / or training may not be lost in a context switch because they may be unencrypted internal values ​​or metadata associated with the target address. In such embodiments, encryption of the target address may have an almost negligible performance penalty, while performing an attack may be significantly more expensive.

[0090] Figure 3 3 is a block diagram of an example embodiment of a circuit 300 in accordance with the disclosed subject matter. In various embodiments, the system 300 may illustrate one embodiment of creating a context-specific hash or key 304. It should be understood that the above is merely an illustrative example and does not limit the disclosed subject matter.

[0091] In the illustrated embodiment, system 300 may include context key 304, as described above. System 300 may also include logic or circuit 302 to create an initial version of context key 304. In such embodiments, the initial version may be copied from key generator 301, which may include registers storing IDs (e.g., virtual machine IDs, process IDs, etc.) or hardware specific values ​​(e.g., series numbers, timers). System 300 may also include entropy expansion circuit 308 and selector circuit 306 (e.g., multiplexer). It should be understood that the above are only some illustrative examples that do not limit the disclosed subject matter.

[0092] In such embodiments, the initial context key 304 may be calculated (using circuit 302) based on one or more inputs or entropy sources (key generator 301). These inputs or entropy sources include, but are not limited to, hardware or software defined entropy sources, process IDs, virtual machine IDs, privilege levels, etc.

[0093] In the illustrated embodiment, context hash 304 may undergo one or more iterative cycles of entropy expansion (e.g., entropy expander circuit 308). In a specific embodiment, this may include deterministic nonlinear shifting and XOR operations based on bits of a fixed input set with an average per-bit randomness. In general, processor context changes are relatively unoptimized and heavy for storing and migrating machine state, so multiple levels of constant XOR hashing or encryption and iterative entropy expansion may have a low performance impact.

[0094] As described above, when the context key 304 has been selected and has undergone enough entropy expansion iterations, the key 304 can be used much like a stream cipher to be XORed with the target address, such as an indirect branch or return target, stored in the BTB or RAS. In various embodiments, a simple substitution cipher or bit shifting can be used to further obfuscate the actual storage address. When the branch predictor is trained and prepared to predict jump targets from these structures, the program's context key 304 can be suitable and reversible for converting the correct predicted target.

[0095] Figure 4 is a schematic block diagram of an information processing system 400 that may include a semiconductor device formed according to the principles of the disclosed subject matter.

[0096] refer to Figure 4 , information processing system 400 may include one or more of the devices constructed according to the principles of the disclosed subject matter. In another embodiment, information processing system 400 may employ or perform one or more techniques according to the principles of the disclosed subject matter.

[0097] In various embodiments, information handling system 400 may include a computing device such as a laptop computer, a desktop computer, a workstation, a server, a blade server, a personal digital assistant, a smart phone, a tablet computer, and other suitable computers or virtual machines or virtual computing devices thereof. In various embodiments, information handling system 400 may be used by a user (not shown).

[0098] The information processing system 400 according to the disclosed subject matter may further include a central processing unit (CPU), logic or processor 410. In some embodiments, the processor 410 may include one or more functional unit blocks (FUB) or combinatorial logic blocks (CLB) 415. In such embodiments, the combinatorial logic block may include various Boolean logic operations (e.g., NAND, NOR, NOT, XOR), stable logic devices (e.g., flip-flops, latches), other logic devices, or combinations thereof. These combinatorial logic operations may be configured in a simple or complex manner to process input signals to achieve a desired result. It should be understood that while several illustrative examples of synchronous combinatorial logic operations are described, the disclosed subject matter is not so limited and may include asynchronous operations or a mixture thereof. In one embodiment, the combinatorial logic operation may include a plurality of complementary metal oxide semiconductor (CMOS) transistors. In various embodiments, these CMOS transistors may be arranged into gates that perform logic operations; however, it should be understood that other techniques may be used and are within the scope of the disclosed subject matter.

[0099] The information processing system 400 according to the disclosed subject matter may further include a volatile memory 420 (e.g., a random access memory (RAM)). The information processing system 400 according to the disclosed subject matter may further include a non-volatile memory 430 (e.g., a hard disk drive, an optical memory, a NAND, or a flash memory). In some embodiments, the volatile memory 420, the non-volatile memory 430, or a combination or portion thereof may be referred to as a "storage medium". In various embodiments, the volatile memory 420 and / or the non-volatile memory 430 may be configured to store data in a semi-permanent or substantially permanent form.

[0100] In various embodiments, the information processing system 400 may include one or more network interfaces 440 configured to allow the information processing system 400 to be part of a communication network and communicate via the communication network. Examples of Wi-Fi protocols may include, but are not limited to, Institute of Electrical and Electronics Engineer (IEEE) 802.11g, IEEE 802.11n. Examples of cellular protocols may include, but are not limited to, IEEE 802.16m (also known as Wireless-Metropolitan Area Network (Wireless-MAN) Advanced), Long Term Evolution (LTE) Advanced, Enhanced Data rates for GSM Evolution (EDGE), Evolved High-Speed ​​Packet Access (HSPA+). Examples of wired protocols may include, but are not limited to, IEEE 802.3 (also known as Ethernet), Fibre Channel, Power Line communication (eg, HomePlug, IEEE 1901). It should be understood that the above are only some illustrative examples that do not limit the disclosed subject matter.

[0101] The information processing system 400 according to the disclosed subject matter may further include a user interface unit 450 (e.g., a display adapter, a tactile interface, a human-machine interface device). In various embodiments, this user interface unit 450 may be configured to receive input from a user and / or provide output to a user. Other types of devices may also be used to provide interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and the input from the user may be received in any form, including sound, voice, or tactile input.

[0102] In various embodiments, information handling system 400 may include one or more other devices or hardware components 460 (eg, display or monitor, keyboard, mouse, camera, fingerprint reader, video processor). It should be understood that the above are only some illustrative examples that do not limit the disclosed subject matter.

[0103] The information processing system 400 according to the disclosed subject matter may further include one or more system buses 405. In such embodiments, the system bus 405 may be configured to communicatively couple the processor 410, the volatile memory 420, the nonvolatile memory 430, the network interface 440, the user interface unit 450, and one or more hardware components 460. Data processed by the processor 410 or data externally input from the nonvolatile memory 430 may be stored in the nonvolatile memory 430 or the volatile memory 420.

[0104] In various embodiments, the information handling system 400 may include or execute one or more software components 470. In some embodiments, the software component 470 may include an operating system (OS) and / or an application. In some embodiments, the OS may be configured to provide one or more services to the application or to manage or act as an intermediary between the application of the information handling system 400 and various hardware components (e.g., the processor 410, the network interface 440). In such embodiments, the information handling system 400 may include one or more native applications, which may be installed locally (e.g., in the non-volatile memory 430) and configured to be directly executed by the processor 410 and directly interact with the OS. In such embodiments, the native application may include precompiled machine executable code. In some embodiments, the native application may include a script interpreter (e.g., C shell (csh), Apple Script (AppleScript), hot key script (AutoHotkey)) or a virtual execution machine (virtual execution machine, VM) (e.g., Java Virtual Machine (Java Virtual Machine), Microsoft Common Language Runtime (Microsoft Common Language Runtime)) configured to translate source code or object code into executable code that is subsequently executed by the processor 410.

[0105] The semiconductor devices described above may be packaged using various packaging techniques. For example, a semiconductor device constructed according to the principles of the disclosed subject matter may be packaged using any of the following technologies: package on package (POP) technology, ball grid array (BGA) technology, chip scale package (CSP) technology, plastic leaded chip carrier (PLCC) technology, plastic dual in-line package (PDIP) technology, die in waffle pack technology, die in wafer form technology, chip on board (COB) technology, ceramic dual in-line package (CERDIP) technology, plastic metric quad flat package (PMQFP) technology, plastic quad flat package (PQFP) technology, small outline integrated circuit package (SOIC) technology, shrink small outline package (SSOP) technology, thin small outline package (TSP) technology. The present invention relates to a semiconductor device comprising: a thin outline package (TSOP) technology, a thin quad flat package (TQFP) technology, a system in package (SIP) technology, a multi-chip package (MCP) technology, a wafer-level fabricated package (WFP) technology, a wafer-level processed stack package (WSP) technology, or other technologies as will be known to those skilled in the art.

[0106] The method steps may be performed by one or more programmable processors executing a computer program to perform functions by operating on input data and generating output. The method steps may also be performed by a dedicated logic circuit such as a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), and the device may be implemented as a dedicated logic circuit.

[0107] In various embodiments, the computer-readable medium may contain instructions that, when executed, cause the device to perform at least a portion of the method steps. In some embodiments, the computer-readable medium may be contained in magnetic media, optical media, other media, or a combination thereof (e.g., CD-ROM, hard drive, read-only memory, flash drive). In such embodiments, the computer-readable medium may be a tangible and non-transitory embodied article of manufacture.

[0108] While the principles of the disclosed subject matter have been described with reference to the exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of these disclosed concepts. Therefore, it should be understood that the above-described embodiments are not restrictive, but merely illustrative. Therefore, the scope of the disclosed concepts will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be restricted or limited by the foregoing description. Therefore, it should be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments.

Claims

1. A device for target address encryption, comprising: a context-specific encryption key circuit configured to generate a key value, wherein the key value is specific to a context of an instruction set; a target address prediction circuit configured to provide a target address for a next instruction in the instruction set; a target address memory configured to store an encrypted version of the target address, wherein the target address is encrypted at least in part using the key value; as well as instruction fetch circuitry configured to decrypt the target address using at least in part the key value and retrieve the target address, Wherein the context-specific encryption key circuit is further configured to generate a second key value specific to a context of a second instruction set different from the instruction set, wherein the second key value is different from the key value.

2. The apparatus of claim 1, wherein the target address memory comprises a branch target buffer.

3. The apparatus of claim 1 , wherein the context-specific encryption key circuit comprises: A random number generator circuit for generating random numbers; as well as An entropy expansion circuit is configured to combine the random number with an identifier associated with the instruction set to create the key value.

4. The apparatus of claim 3, wherein the identifier comprises a value selected from the set consisting of: a process identifier, a virtual machine identifier, a privilege level, a kernel identifier, and a security state value.

5. The apparatus of claim 3, wherein the entropy expansion circuit is configured to perform multiple iterations of combining to create the key value, wherein each of the iterations includes an output of a previous iteration as an input to the current iteration.

6. The apparatus of claim 1 , wherein the target address prediction circuit is configured to: encrypting the target address using, at least in part, a stream cipher and the key value, and The encrypted version of the target address is stored in the target address memory.

7. The apparatus of claim 1, wherein the target address is encrypted such that a false target address is recovered if an incorrect key value is employed to attempt to decrypt the encrypted target address.

8. The apparatus of claim 1, wherein the target address prediction circuit is configured to generate branch bias information associated with the target address, and wherein the branch bias information is not encrypted.

9. A system for target address encryption, comprising: an execution unit circuit for processing instructions associated with the first program; as well as instruction fetch circuitry configured to fetch the instruction at a target address associated with the first program via branch prediction and provide the instruction to the execution unit circuitry, wherein the instruction fetch circuitry is further configured to encrypt the target address with a key value so that a malicious second program is unable to read a correctly decrypted version of the target address, The instruction fetch circuit decrypts the target address with the key value for the first program, and decrypts the target address with a second key value different from the key value for the malicious second program.

10. The system of claim 9, wherein the instruction fetch circuit is configured to prevent the second program from correctly reading the target address if the second program attempts to exploit a ghost-class speculative execution flaw.

11. The system of claim 9, wherein the instruction fetch circuit comprises: a context-specific encryption key circuit configured to generate the key value, wherein the key value is specific to a context of an instruction set, and a target address memory configured to store an encrypted version of the target address, wherein the target address is encrypted at least in part using the key value; and Wherein the instruction fetch circuitry is configured to decrypt the target address using, at least in part, the key value.

12. The system of claim 11, wherein the target address memory includes a return address stack.

13. The system of claim 11, wherein the context-specific encryption key circuit comprises: A random number generator circuit for generating random numbers; as well as An entropy expansion circuit is configured to combine the random number with an identifier associated with the instruction set to create the key value.

14. The system of claim 13, wherein the identifier comprises a value selected from the set consisting of: a process identifier, a virtual machine identifier, a privilege level, a kernel identifier, and a security state value.

15. The system of claim 13, wherein the entropy expansion circuit is configured to perform multiple iterations of combining to create the key value, wherein each of the iterations includes an output of a previous iteration as an input to the current iteration.

16. The system of claim 11, wherein the instruction fetch circuitry comprises a target address prediction circuitry configured to: encrypting the target address using, at least in part, a stream cipher and the key value, and The encrypted version of the target address is stored in the target address memory.

17. A method for target address encryption, comprising: In response to initiating the fetching of a first instruction stream, generating a context-specific encryption key value unique to and associated with the first instruction stream; determining instruction addresses associated with the first instruction stream; as well as storing an encrypted version of the instruction address in a target address memory, wherein the instruction address is encrypted at least in part using the context-specific encryption key value and thus a second instruction stream not associated with the context-specific encryption key value is unable to read the unencrypted instruction address, Wherein a second context-specific encryption key value associated with the second instruction stream is different from the context-specific encryption key value.

18. The method according to claim 17, further comprising: The instruction address within the target address memory is read, wherein reading comprises decrypting the encrypted version of the instruction address using, at least in part, the context-specific encryption key value.

19. The method of claim 17, wherein the second instruction stream is configured to exploit a ghost-class speculative execution defect.

20. The method of claim 17, wherein generating a context-specific encryption key value comprises utilizing an identifier associated with the first instruction stream, wherein the identifier comprises a value selected from a set comprising: a process identifier, a virtual machine identifier, a privilege level, a kernel identifier, and a security state value.

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