Linear and nonlinear calibration for time-interleaved digital-to-analog converters

Abstract

A time-interleaved digital-to-analog converter system includes: a digital predistorter configured to receive an input digital signal and an error signal, and output a distorted digital signal based on the input digital signal and the error signal; a time-interleaved digital-to-analog converter having a first sampling rate, the time-interleaved digital-to-analog converter configured to convert the distorted digital signal into an analog signal; and a calibration system. The calibration system includes an analog-to-digital converter having a second sampling rate equal to or lower than the first sampling rate, the analog-to-digital converter configured to receive the analog signal and convert the analog signal into a downsampled digital signal; a discrete-time linear model configured to receive the input digital signal and the error signal and output a model signal; and a combiner to subtract the downsampled digital signal from the model signal to generate an error signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Provisional U.S. Patent Application No. 62 / 787,223, filed on December 31, 2018, the entire contents of which are hereby incorporated by reference into this application. Field of the Invention

[0003] The present disclosure relates to systems and methods for time-interleaved (TI) digital-to-analog converters (DACs), and in particular to calibrating pre-processing digital signal processing (DSP) filters for TI DACs. Background Art

[0004] DACs are used to convert digital signals into analog signals. However, the bandwidth of a DAC may be limited by the analog bandwidth or sampling rate of the DAC. To achieve an effective higher DAC sampling rate, a TIDAC system can be used instead of a single DAC, which includes many time-interleaved DAC channels. Each DAC channel receives an input signal and outputs an analog signal that is offset in time within a single DAC sampling period. These analog signals can then be summed or multiplexed together to effectively multiply the sampling rate of the entire DAC system.

[0005] However, in a TIDAC system, linear and nonlinear distortions and / or mismatches may exist between channels of the TIDAC system, resulting in analog output signals that may be inaccurate.

[0006] Embodiments of the present disclosure address these and other deficiencies of the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects, features and advantages of embodiments of the present disclosure will become apparent from the following description of embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 is a block diagram of a time-interleaved digital-to-analog converter system according to some embodiments of the present disclosure.

[0009] Figure 2 yes Figure 1 Block diagram of an example digital pre-distortion unit.

[0010] Figure 3 Is has Figure 2 Block diagram of an example delay line for a second-order product of .

[0011] Figure 4 Is has Figure 2 Block diagram of another example delay line for the second order product of .

[0012] Figure 5 is to use Figure 2 Block diagram of an example multiplication of an adaptive block.

[0013] Figure 6 yes Figure 5 Block diagram of an example coefficient adaptation block.

[0014] Figure 7 yes Figure 5 Block diagram of an example multiplication block.

[0015] Figure 8 is to use Figure 2 Block diagram of the replacement multiplication of the adaptive block.

[0016] Fig. 9 yes Figure 8 Block diagram of an example MIMO coefficient adaptation block.

[0017] Fig.10 yes Figure 8 An example block diagram of a multiple-input multiple-output block.

[0018] Fig.11 yes Figure 1 Block diagram of an example discrete-time linear model of a DAC and ADC.

[0019] Fig.12 is a block diagram of another time-interleaved digital-to-analog converter system according to some embodiments of the present disclosure.

[0020] Fig.13 is a block diagram of another time-interleaved digital-to-analog converter system according to some embodiments of the present disclosure.

[0021] Fig.14 is a block diagram of a test and measurement instrument according to other embodiments of the present disclosure. DETAILED DESCRIPTION

[0022] Embodiments of the present disclosure include background and / or foreground calibration for correcting linear and nonlinear distortion of a time interleaved (TI) digital-to-analog converter (DAC). As will be discussed in more detail below, correction is performed by digital predistortion (DPD) of the TI DAC input data using background or foreground calibration. That is, calibration can be performed in the foreground using a known signal, or in the background during normal operation of the TIDAC. The TIDAC output is captured by an analog-to-digital converter (ADC) and compared with a suitably processed DAC input to form an error signal, which is used for least mean square (LMS) adaptation of the DPD coefficients.

[0023] Figure 1An example TIDAC system 100 according to some embodiments of the present disclosure is illustrated. A digital input signal 102, shown as x, is received at the input and transmitted to a DPD unit 104 and a discrete time (DT) linear model of a DAC and ADC unit 106 (referred to herein as a DT linear model unit 106). The digital input signal processed by the DPD unit 104 is transmitted to M parallel TIDAC channels 109 of a TIDAC 108, where the index m=1, ..., M, where M is an integer greater than 1. The output of each DAC channel 109 is summed together by a summer 110, or selected sequentially by a multiplexer instead of the summer 110, and output as an analog signal 112. If the TIDAC system 100 is used as part of a test and measurement instrument, the analog signal 112 can be output to the device under test through a port of the test and measurement instrument. The analog signal 112 is also sent to an ADC 114, which is used to calibrate the DPD unit 104.

[0024] The sampling rate of ADC 114 is 1 / L of the rate of TIDAC 108. Figure 1 108 in order to capture the complete output spectrum. A pre-sampler component can be used before the lower bandwidth ADC to achieve the same result. The downsampling rate L is chosen to be prime relative to M so that all TI sampling phases can be covered in the error waveform and thus adaptive. That is, L and M have no other common factors except one.

[0025] The output of the DT linear model 106 is also downsampled by L via a downsampler 118. The output of the ADC 114 is then subtracted from the output of the downsampler 118 via a combiner 120 to generate an error signal 122. The error signal 122 is sent to both the DT model 106 and the DPD 104, as will be discussed in further detail below.

[0026] Since the entire system has been discussed, Figure 2-11 Individual components of system 100 will be illustrated. Figure 2 An example DPD 104 according to some embodiments of the present disclosure is illustrated. The DPD 104 receives a digital signal 102 and sends the digital signal to a number of delay lines. P delay lines are provided, where P is greater than 1. For example, in Figure 2 , a first-order delay line 200, a second-order delay line 202, and a P-order delay line 204 are illustrated.

[0027] Each delay line 200, 202, and 204 has a different order of product to create a different order of nonlinearity with memory. The delay lines 200, 202, and 204 are used in conjunction with multiplication using an adaptation block 208 to compensate for the corresponding order of nonlinearity and time interleaving linear and nonlinear mismatch between the TIDAC channels 109. Figure 2 108. A first-order delay line 200 is illustrated in FIG. Delay blocks 206 each indicate a delay of one clock cycle of the TIDAC 108 input data. The delay line 202 with a second-order product block and the delay line 204 with a P-order product block each consist of a product of exactly two terms or P terms of the delay line and delay line components, each component being derived by a summing or multiplying by a constant. The output of each delay line 200, 202, and 204 is sent to a multiplication using an adaptive block 208. The error signal 122 is also applied to each multiplication using an adaptive block 208. The output of each multiplication using the adaptive block 208 is summed together by a combiner 210 and output as a signal y sent to the TIDAC 108.

[0028] Figure 3 and 4 A possible example of a second-order delay line 204 is shown, which can also be modified for a p-order delay line 206. If all possible outputs of the delay line are used to form all possible p-order products, then a p-order Volterra model will be derived. However, the full Volterra model may be too complex for some implementations, so a p-order Volterra model may be used. Figure 3 and 4 A simpler version is shown in FIG. Suitable simplified nonlinear models with memory can be derived through analysis of a specific TIDAC 108 model and / or its simulation. These models do not need to be accurate, as they will be augmented with adaptive coefficients to compensate for the actual nonlinearity of the TIDAC 108.

[0029] Figure 5 is a block diagram of an example multiplication using adaptive block 208. Demultiplexer 500 receives signal u from one of delay lines 200, 202, and 204 and converts M consecutive scalar data u entering block 208 at a rate equal to the rate of TIDAC 108 into vector u m , where m is an integer value from 1 to M. The data vector u m is delayed by delay block 502 to match the delay introduced by the chain of TIDAC 108 and ADC 114 at combiner 120. The delayed data vector v mIt is also downsampled by L by downsampler 504 to match the undersampled ADC 114. The output of downsampler 504 is sent to coefficient adaptation block 506. Error signal 122 is also received at demultiplexer 508, which converts the error signal into a vector e m , where m is an integer value from 1 to M, the vector e m is also received at the coefficient adaptation block 506. The coefficient adaptation block 506 performs LMS adaptation on a single TIDAC channel 109 to output a vector t m In multiplier 510, vector t m With vector u m Multiply to determine the combined vector w m Multiplexer 512 combines the vector w m is converted into scalar data w, which is output to the combiner 210.

[0030] As described above, coefficient adaptation block 506 performs LMS adaptation, which Figure 6 , is illustrated for one of the TIDAC channels 109. The LMS operation can also be described by the following equation (1):

[0031] t m (Ln) = t m (Ln-L)+μv m (Ln)e m (Ln) (1)

[0032] Among them, t m (Ln) is the update coefficient value at the Lnth clock cycle relative to the sampling period of the single TIDAC channel 109, and t m (Ln–L) is its previous value extracted by L clock cycles. The variable v m (Ln) and e m (Ln) are the data and the mth component of the error corresponding to the nLth clock cycle respectively. The constant μ is the adaptive constant of the LMS algorithm. Figure 6 A standard LMS operation is shown in , but other types of LMS algorithms may also be used, such as normalized LMS, LMS with a time-varying adaptive step, leaky LMS, or others.

[0033] Figure 7 The vector t in the multiplier 510 is shown. m and the input data vector u m The multiplication of . Figure 7 In some embodiments shown in FIG. 5 , the multiplier 510 multiplies the coefficients t from the coefficient adaptation block 506 by point-by-point multiplication. m Applied to the input data vector u m .exist Figure 7 In the example, M is equal to 4. This point-by-point multiplication can also be described by the following equation (2):

[0034] w m (n) = t m u m (n), m = 1, 2, ..., M (2)

[0035] Figure 8 is a block diagram illustrating an alternative multiplication using adaptive block 800 that may be implemented in some embodiments. The circuit may be used to replace Figure 2 100 . Similar to the multiplication using the adaptive block 208, the demultiplexer 802 receives a signal u from one of the delay lines 200, 202, and 204 and converts M consecutive scalar data u entering the block 800 at a rate equal to the rate of the TIDAC 108 into a vector u m , where m is an integer value from 1 to M. The data vector u m is delayed by delay block 804 to match the delay introduced by the chain of DACs and ADCs at combiner 120. The delayed data vector v m is sent to a multiple-input multiple-output (MIMO) coefficient adaptation block 806, an example of which is shown in Fig. 9 MIMO coefficient adaptation block 806 also receives the error vector e k , the error vector e k Outputted by the demultiplexer 808 based on the received error signal 122, where k is an integer value from 1 to M. Each coefficient of the MIMO coefficient adaptation block 806 can be determined by implementing a standard LMS algorithm, which can be described by equation (3):

[0036] t (s) k m (Ln) = t (s) km (Ln-L)+μv m (Ln-s+1)e k (Ln), k, m=1,...,M; s=1,...,S(3)

[0037] Similar to the coefficient adaptation block 208, other LMS algorithms may also be used.

[0038] The output of the MIMO coefficient adaptation block 806 is (s) km is sent to MIMO block 810, Fig.10 8 shows a MIMO block 810 for the case when M is equal to 2. The MIMO block 810 has M inputs and M outputs and is composed of M 2The input / output relationship of the MIMO block 810 is given by equation (4):

[0039]

[0040] Among them, the operator represents convolution, u m (n) is the mth input data, and t km is an input m and a vector of S coefficients of the FIR output connected to the kth output of the MIMO block 810 structure. Similar to multiplexer 512, multiplexer 812 combines vector w k is converted into scalar data w, which is output to the combiner 210.

[0041] Because MIMO block 810 includes memory for delay lines through M FIR filters, when multiplication by adaptation block 208 is replaced with an alternative multiplication by adaptation block 800, some of the lines connecting delay lines 200, 202, and 204 to the multiplication by adaptation block 208 become redundant.

[0042] As mentioned above, the TIDAC system 100 can compensate for TIDAC linear and nonlinear mismatches so that the output of the TIDAC system 100 will look like a linear time-invariant (LTI) system. For such a case, the actual TIDAC output can be compared to the output of the expected LTI system, which can model the operation of the ideal TIDAC. In the TIDAC system 100, the DT linear model unit 106 can perform this comparison. Fig.11 The structure of the DT linear model unit 106 is illustrated in . The DT linear model unit 106 covers the linear aspects of both the TIDAC 108 and the ADC 114 , which are not intended to be corrected in the DPD unit 104 .

[0043] As in Fig.11 As can be seen in FIG, the DT linear model unit 106 includes an FIR filter with LMS adaptation of its coefficients. The adaptation of the DT linear model unit 106 can track changes in the linear part of the TIDAC channel 108 and the ADC 114. However, at least one tap of the FIR filter is set to be non-adaptive and frozen at a constant value to avoid the situation when the coefficients of all DPD units 104 converge to a zero value. Although in Fig.11A conventional direct form FIR filter implementation for the DT linear model unit 106 is shown in , but any other known structure may be used, such as transpose, cascade, fast FIR, lattice FIR, frequency domain, etc. Similarly, as discussed above, the LMS operation may be implemented in a variety of ways.

[0044] In some embodiments, the calibration described above can be performed in the background while the TIDAC system 100 is producing the desired output signal. However, there may be some input signal types that can result in error waveforms used by multiple adaptive blocks that have linear correlations between components of the error signal 122 attributable to different impairment types covered in the DPD unit 104 correction structure, thereby allowing multiple adaptive coefficient states that achieve the same LMS optimization for this particular input signal 102. Since these multiple adaptive states are not equivalent, when the characteristics of the input signal 102 change, the multiple adaptive states can produce significant errors until the TIDAC system 100 has time to respond to the new input and converge to coefficients suitable for the new input signal. A simple example of this is a constant non-zero input signal 102, where, for each DAC channel 109, a DC offset term, a gain term, and / or a nonlinear term can be used to correct the mismatch between the TIDAC channel 109 outputs.

[0045] For the static coefficient factors (i.e., the memoryless components of the DPD unit 104), after accounting for downsampling by the undersampling ADC 114, the key to good convergence in the background calibration is to have sufficient diversity (such as a sufficient number of unique amplitude values) in the input waveform amplitude values ​​to utilize parallel LMS adaptive functions to solve for multiple coefficients.

[0046] For the dynamic coefficient factors (i.e., frequency-dependent components covered by the delay lines in the DPD unit 104 structure), in addition to having sufficient diversity in amplitude values ​​after taking into account the downsampling by the undersampling ADC 114, it is also important for good convergence in the background calibration to utilize the parallel LMS adaptive function to solve multiple coefficients.

[0047] The criteria for good convergence in the background calibration mathematically involves being able to solve a system of equations across multiple TIDAC channel 109 input and ADC 114 output samples, for the various impairments modeled in the DPD unit 104, for all unknown coefficient values, such that the solution to the LMS minimizes the residual error between the estimated aggregate waveform (as determined based on the input waveform and the DPD unit 104 coefficient values) and the actual impairments in the waveform captured by the undersampled ADC 114.

[0048] Consider the following equation (5):

[0049]

[0050] in, is a vector of the aggregated residual error waveform used for estimation, after taking into account the effects of the current DPD unit 104 correction coefficients, which is the sum of the errors due to each impairment type at the output of the undersampled ADC 114 per cycle. The variable U is the input waveform impairment matrix before scaling by parallel multiplication with the adaptation block 208, which has the base impairment values ​​in the row dimension (which are the input to the multiplication with the adaptation block 208) and the consecutive sample values ​​in the column dimension that are downsampled to match the rate of the undersampled ADC 114. The variable c is a residual coefficient vector used to scale the magnitude of the impairment values ​​in the multiplication with the adaptation block 208 to cancel the impairments of the DAC channel 108, i.e., to minimize the residual error that can be added to the current DPD coefficient vector.

[0051] This system of equations will generally be overdetermined, and a least squares solution can be found to minimize the following expression: min c ||-Uc-e||, where e = the residual error vector of the waveform measured after undersampling the output of the ADC.

[0052] The least squares solution can be given by equation (6):

[0053] c=-(U T U) -1 U T e (6)

[0054] As long as U T The U matrix is ​​not singular (i.e. |U T U|≠0), we can find the solution.

[0055] For background calibration, the parallel LMS adaptation that occurs every cycle should converge to the solution of the above system of equations on a continuous value basis to minimize the residual error term. T If the U matrix is ​​not singular or not close to singular, the background calibration should have good performance. Having good amplitude and spectral component diversity in the input waveform applied to the TIDAC 108 can make the corresponding U T It is more likely that the U matrix is ​​not singular or not nearly singular.

[0056] If an input signal is applied to the TIDAC system 100, such that the corresponding U TIf the U matrix is ​​singular or nearly singular, background calibration of the DPD coefficients may be stopped to prevent the coefficient states from deviating from the appropriate hardware error model. Furthermore, foreground calibration may be recommended, where the TIDAC system 100 input signal is specifically selected to allow fast and accurate convergence of the DPD coefficients.

[0057] In some embodiments, a real-time digital signal processor (DSP) may be added to analyze the waveform data in the TIDAC system 100 to estimate |U for a given time span in the input waveform 102 before the DPD unit 104 performs any corrections. T U|. The DSP can determine whether the time span should allow background adaptation. The DSP can instruct the TIDAC system 100 to T Background calibration is disabled for time spans where |U is close to zero, and T Background calibration is enabled for time spans where |U| is not too close to zero. That is, an arbitrary threshold can be determined for the system, and if the corresponding |U T U| is greater than this threshold, background calibration is enabled, and if the corresponding |U T U|Below this threshold, background calibration is disabled.

[0058] In alternative embodiments, for example where the input waveform 102, x[n] is predetermined, such as by loading a known waveform into a pattern memory, then |U may also be pre-computed. T The U| value is compared with time to generate a flag that can be stored in memory with the pre-calculated waveform. The flag can enable background calibration for periods of the input waveform where the convergence of the DPD coefficients will have good performance, and disable background calibration for periods where the DPD coefficients may not converge well.

[0059] As an alternative to the real-time calibration via the LMS discussed above, in some embodiments, background and / or foreground calibration may be performed offline by capturing and processing data packets at a later time.

[0060] To this end, the DT equivalent linear model of the DAC and ADC is estimated. In order to minimize interference from the nonlinear portion of the channel 108, a low amplitude input waveform can be used to complete this estimation. The data captured at the output of the ADC 114 can be collected into a row vector d. A matrix X of N / L times P can be formed from the DPD input data x, where N is the length of the TI DAC 108 input data pattern, and P is the number of taps of the linear model, where the p-th column of the matrix X includes p-1 zeros connected to the first N-p+1 data, followed by a decimation by a factor of L. Then, equation (7) can be used to find the linear model FIR coefficients:

[0061] c=(dX)(X′X) -1 (7)

[0062] where the notation X' is used for the transposed matrix X.

[0063] Once the linear model FIR coefficients c are estimated from equation (7), new TIDAC 108 data with full amplitude can be captured and processed at the ADC 114. Using the same indices d for the data packets (row vectors) captured at the ADC 114 output, and corresponding indices x, u for the data packets (row vectors) at the DPD unit 104 and MIMO block 810 inputs, the MIMO coefficients t (M by T matrix) can be found as follows.

[0064] The error vector can be calculated by first convolving the input data with the linear model filter coefficients, as shown in equation (8):

[0065] q=conv(x,c) (8)

[0066] Second, by downsampling the convolution output by a factor of L and subtracting the data captured at the ADC 114 output:

[0067] e=downs(q,L)−d (9)

[0068] Then, the matrix B may be formed with T (S times M) columns and N / L rows (N being the data packet length), where the tth column includes t-1 zeros concatenated with the first N-t+1 data in the vector u input to the MIMO block 800, followed by decimation by a factor of L. The mth phase of the vector e decimated by M may be given by e (m) Specify, as shown in Equation 10:

[0069]

[0070] And similarly, B (m) It can be the extraction matrix according to equation (11):

[0071]

[0072] Then, equation (12) can be found:

[0073] t (m) =(e (m) B (m) )(B (m) 'B (m) ) -1 (12)

[0074] Among them, t (m)is a row vector with T (S times M) coefficients. Finally, the coefficients of MIMO block 810 can be derived as shown in equation (13):

[0075]

[0076] Fig.12 An alternative TIDAC system 1200 is illustrated in accordance with some embodiments of the present disclosure. Components similar to the TIDAC system 100 are given the same reference numerals and will not be discussed in detail. Fig.12 discuss them in more detail. Fig.12 In the TIDAC system 1200 of FIG. 1 , a tunable radio frequency (RF) bandpass filter 1202, a local oscillator 1204, a mixer 1206, and an RF low pass filter (LPF) 1208 may be used in combination to down-convert the signal content in the TIDAC 108 output to a narrowband range supported by the ADC 114 at a lower bandwidth and sampling rate associated with the TIDAC 108. Although a tunable RF bandpass filter 1202 is shown, in some embodiments, an array of filters may be used instead. The frequency range covered by each narrowband capture of a given error waveform data segment 122 may be given as: [f c :f c +BW ADC ], where f c is the LO frequency, and BW ADC is the effective bandwidth captured by ADC114.

[0077] Then, after taking into account the DT linear model 106, the DSP is then used to mirror the RF down-conversion topology to develop the [f c :f c +BW ADC ] is a model of the expected ideal output signal content within a given frequency span covered by the DT linear model 106. That is, the output of the DT linear model 106 is sent to a tunable DSP bandpass filter 1210, the output of which is mixed with a signal from a local oscillator 1214 by a mixer 1218. The tunable DSP bandpass filter 1210 and the local oscillator 1214 are set by a frequency sweep control 1216. The signal from the local oscillator 1214 is also sent to a phase aligner 1212 for use as a reference so that the phases of the local oscillator 1214 and the local oscillator 1204 can have a known phase relationship to ensure a coherent phase in the segment captured by the ADC 114 relative to the DT linear model 106 (as modified by the tunable DSP bandpass filter 1210, the mixer 1218, the local oscillator 1214 and the low pass filter 1220) to allow the waveform to be subtracted to generate the error signal 122.

[0078] A segment of the error signal 122 may be captured for each narrowband frequency span. The segment size used when capturing the error signal 122 determines the size of the segment that is captured by each narrowband segment [f c :f c +BW ADC ] The resulting segments may be subjected to a discrete Fourier transform (DFT) in the DPD unit 104 to generate a complex vector of estimated error, magnitude, and phase components versus frequency for the frequencies covered by each narrowband frequency span, as discussed below.

[0079] The frequency of the local oscillator 1204 is swept to cover the entire frequency range of interest for calibration of the TIDAC 108. The resulting estimated frequency domain error vectors are then combined after DFT of the error signal 122 captured for each narrowband frequency span to generate an aggregated complex frequency domain error vector e, as shown in equations (14)-(17):

[0080] f C =n·BW ADC , n∈[0,...N-1] (14)

[0081]

[0082] e=E(f) (17)

[0083] Where E n (f) is the DFT output sample for each narrowband error waveform segment (within the bandwidth captured by the narrowband ADC 114), f∈(0:BW ADC ), E(f) is the aggregated frequency domain error waveform, f is the vector of frequency values ​​used to solve the adaptive DPD coefficients, and e is the aggregated frequency domain error waveform vector used to solve the adaptive DPD coefficients.

[0084] The next iteration of the DPD coefficients determined by the DPD unit 104 may then be solved in the frequency domain. Successive DFTs of the input waveform using the parallel multiplications of the adaptation block 208 in the DPD unit 104 may be performed to generate a vector of input waveform impairments versus frequencies for each type of impairment modeled in the DPD unit 104 to match the frequencies covered by the frequency domain vector e. The input waveform using the parallel multiplications of the adaptation block 208 may be captured in segments that are time aligned with the segments captured by the narrowband ADC 114. A DFT may be performed on each segment to extract a complex vector (including magnitude and phase components) of frequency domain samples that are aligned with the frequency span covered by the corresponding error signal 122 captured by the narrowband ADC 114 in that segment within the frequency scan range sequence. An aggregate vector e used to estimate the frequency domain error waveform is then constructed in the frequency scan sequence by combining the frequency domain vectors captured for each segment across all consecutive segments to cover the entire frequency range used in the calibration.

[0085] Then, the estimated residual error in the frequency domain can be calculated using equation (18):

[0086]

[0087] in, is a vector of estimated aggregated frequency domain residual error waveforms after accounting for the effects of the current DPD correction coefficients, which is the sum of the errors due to each type of impairment at the output of the narrowband ADC 114 aggregated across the frequency range covered by the LO 1204 frequency sweep. W is the input waveform impairment matrix (in the frequency domain) before scaling by the parallel multiplication with the adaptation block 208 in the DPD unit 104, with elementary impairment values ​​(inputs to the multiplication with the adaptation block 208) in the row dimension and continuous values ​​in frequency in the column dimension. The variable c is a residual coefficient vector used to scale the magnitude of the impairment values ​​in the multiplication with the adaptation block 208 to offset the impairments of the DAC 108, i.e., to minimize the residual error, which can be added to the current DPD coefficient vector.

[0088] Equations (14)-(18) can be generally overdetermined, and a least squares solution can be found to minimize the following expression: min c ||-Wc-e||, where e is a vector of aggregated frequency domain residual error waveforms measured from a full scan across the frequency range captured with consecutive segments followed by a DFT.

[0089] Therefore, the least squares solution is given by equation (19):

[0090] c=-(W T W) -1 WT e (19)

[0091] As long as W T The W matrix is ​​not singular (i.e., |W T W|≠0)), we can find equation (19).

[0092] Adaptation of the DPD coefficients for background calibration (occurring while the arbitrary waveform is being generated for the DAC output) can be accomplished using equation (20):

[0093] d n =d n-1 +μc (20)

[0094] where d n is the next vector of DPD coefficients, d n-1 is the current vector of DPD coefficients, μ is the adaptation rate, which can be potentially adjusted dynamically, such as using a normalized LMS type approach, and c are the coefficients solved for from a frequency domain optimization of the residual error over the current frequency scan.

[0095] This method can also be applied to foreground calibration. In such an embodiment, a set of known input waveforms can be used, which are optimized for the needs of DAC calibration. Then, the coefficients of DPD unit 104 can be solved in the frequency domain according to equation (19).

[0096] Fig.13 Another alternative embodiment according to the embodiment of the present disclosure is illustrated. Fig.13 The embodiment is similar to the above Figure 1 and 12 The embodiments discussed in the foregoing, as such, like components are given the same reference numerals and are not related to Fig.13 Further discussion. In the TIDAC system 1300, the tunable RF bandpass filter 1202 and the tunable DSP bandpass filter 1210 are removed. Considering the complexity of the tunable RF bandpass filter 1202, this can simplify and reduce the system cost. Removing the bandpass filters 1202 and 1210 results in two mixer input images (except for ff) in the resulting narrowband spectrum captured by the ADC 114. c In addition, there is f+f c ).

[0097] Two mixer input images with narrowband spectrum (except ff c In addition, there is f+f c ) can be mitigated by additional processing of the estimated residual complex frequency domain error frequency.

[0098] Each narrowband ADC capture segment and the resulting residual error waveform will include the following signal content in equations (21) and (22):

[0099] f C =n·BW ADC , n∈[0,...,N-1] (21)

[0100]

[0101] Then you can extract the G n (f) Iteratively extract the desired residual error waveform, as shown in equation (23):

[0102]

[0103] The segments can then be aggregated to generate the residual error waveform as shown in equation (24):

[0104]

[0105] After obtaining the residual error waveform in the frequency domain, a similar process can be used to solve for the adaptive DPD coefficients for the narrowband frequency scanning option including a tunable bandpass filter as discussed above.

[0106] Other variations of narrowband ADCs utilizing down-conversion methods that are adaptive to the DPD coefficients are also possible. One such example is adapting this method to other RF down-conversion architectures, such as complex I / Q superheterodyne receiver topologies.

[0107] Fig.14 An example test and measurement instrument 1400 is illustrated having a TIDAC system 1402. The TIDAC system 1402 may be any of the TIDAC systems 100, 1200, or 1300 discussed above. The test and measurement instrument 1400 may be any test and measurement instrument such as an arbitrary waveform generator, an arbitrary function generator, or an output signal source.

[0108] The test and measurement instrument 1400 includes: one or more ports 1404, which can be any electrical or fiber optic signaling medium. The ports 1404 can include receivers, transmitters, and / or transceivers. The ports 1404 are coupled to the TIDAC system 1402 connected to one or more processors 1406. Although for ease of illustration, the Fig.14 Only one processor 1406 is shown in FIG. 1 , but as will be appreciated by those skilled in the art, multiple processors 1406 of different types may be used in combination rather than a single processor 1406 .

[0109] One or more processors 1406 may be configured to execute instructions from memory 1408, and may implement any method and / or associated steps indicated by such instructions. Memory 1408 may be implemented as a processor cache, random access memory (RAM), read-only memory (ROM), solid-state memory, (one or more) hard disk drives, or any other memory type. Memory 1408 acts as a medium for storing data, computer program products, and other instructions. For example, one or more processors 1406 may output a digital signal to the TIDAC system 1402, which is to be output to the device under test as an analog signal (such as described above) through port 1404.

[0110] A user input 1410 is coupled to the one or more processors 1406. The user input 1410 may include a keyboard, a mouse, a trackball, a touch screen, and / or any other control that may be employed by a user to work with a GUI on a display 1412. The display 1412 may be a digital screen, a cathode ray tube-based display, or any other monitor that displays waveforms, measurements, and other data to a user. Although the components of the test instrument 1400 are depicted as being integrated within the test and measurement instrument 1400, one of ordinary skill in the art will appreciate that any of these components may be external to the test instrument 1400 and may be coupled to the test instrument 1400 in any conventional manner (e.g., wired and / or wireless communication media and / or mechanisms). For example, in some embodiments, the display 1412 may be remote from the test and measurement instrument 1400.

[0111] Aspects of the present disclosure may be operated on specially created hardware, firmware, digital signal processors, or on a specifically programmed computer including a processor that operates according to programming instructions. The term controller or processor as used herein is intended to include a microprocessor, a microcomputer, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and a dedicated hardware controller. One or more aspects of the present disclosure may be embodied in computer-usable data and computer-executable instructions executed by one or more computers (including monitoring modules) or other devices, such as in one or more program modules. Typically, program modules include routines, programs, objects, components, data structures, etc., which perform specific tasks or implement specific abstract data types when executed by a processor in a computer or other device. Computer executable instructions may be stored on computer-readable storage media such as hard disks, optical disks, removable storage media, solid-state memory, random access memory (RAM), etc. As will be appreciated by those skilled in the art, the functions of program modules may be combined or distributed as needed in various aspects. In addition, the function may be embodied in firmware or hardware equivalents in whole or in part, such as integrated circuits, FPGAs, and the like. Certain data structures may be used to more efficiently implement one or more aspects of the present disclosure, and such data structures are contemplated within the scope of the computer-executable instructions and computer-usable data described herein.

[0112] In some cases, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried or stored on one or more computer-readable storage media, which may be read and executed by one or more processors. Such instructions may be referred to as computer program products. As discussed herein, computer-readable media refers to any medium that can be accessed by a computing device. As an example and not limitation, computer-readable media may include computer storage media and communication media.

[0113] Computer storage media refers to any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital video disk (DVD) or other optical disk storage, cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any volatile or non-volatile, removable or non-removable media implemented in any technology. Computer storage media does not include the signal itself and the temporary form of signal transmission.

[0114] Communication media refers to any medium that can be used for communication of computer-readable information. By way of example and not limitation, communication media may include coaxial cables, fiber optic cables, air, or any other medium suitable for communication of electrical signals, optical signals, radio frequency (RF) signals, infrared signals, acoustic signals, or other types of signals.

[0115] Example

[0116] Illustrative examples of the technology disclosed herein are provided below. Embodiments of the technology may include any one or more of the examples described below and any combination thereof.

[0117] Example 1 is a time-interleaved digital-to-analog converter system, comprising: a digital predistorter, which is configured to receive an input digital signal and an error signal, and output a distorted digital signal based on the input digital signal and the error signal; a time-interleaved digital-to-analog converter having a first sampling rate, which is configured to convert the distorted digital signal into an analog signal, and the distorted signal corrects the mismatch between time-interleaved channels of the time-interleaved digital-to-analog converter; and a calibration system, which comprises: an analog-to-digital converter having a second sampling rate equal to or lower than the first sampling rate, which is configured to receive the analog signal and convert the analog signal into a down-sampled digital signal; a discrete-time linear model, which is configured to receive an input digital signal and output a model signal; and a combiner, which is used to subtract the down-sampled digital signal from the model signal to generate an error signal.

[0118] Example 2 is the time-interleaved digital-to-analog converter system of Example 1, wherein the discrete-time linear model also receives the error signal and includes a finite impulse response filter having at least one adaptive tap and a constant tap.

[0119] Example 3 is the time-interleaved digital-to-analog converter system of any of Examples 1 and 2, wherein the calibration system is enabled during a pre-operation calibration using a known digital input signal.

[0120] Example 4 is the time-interleaved digital-to-analog converter system of Example 3, further comprising: a digital signal processor configured to determine, based on the digital input signal, whether to disable the calibration system during operation with an unknown digital input signal.

[0121] Example 5 is the time-interleaved digital-to-analog converter system of any of Examples 1-4, wherein the digital predistorter comprises: a plurality of delay lines having different order products, each delay line receiving a digital input signal.

[0122] Example 6 is the time-interleaved digital-to-analog converter system of Example 5, wherein the digital predistorter further includes: a plurality of first demultiplexers, each first demultiplexer for each output of a delay line having a different order product, each first demultiplexer receiving the output of each of the delay lines and outputting a parallel data stream having a number of signals equal to the number of channels of the time-interleaved digital-to-analog converter; a plurality of second demultiplexers, each second demultiplexer for receiving an error signal and outputting a parallel error data stream having a number of signals equal to the number of channels of the time-interleaved digital-to-analog converter; a plurality of coefficient adapters, each coefficient adapter for correlating a corresponding parallel data stream with a parallel error data stream and outputting a number of variable coefficients equal to the number of channels of the time-interleaved digital-to-analog converter; a plurality of first combiners, each first combiner for combining a corresponding variable coefficient with a parallel data stream into a parallel combined data stream; a plurality of multiplexers, each multiplexer being configured to combine a corresponding parallel combined data stream into a signal; and a second combiner configured to combine each signal from a plurality of multiplexers into a distorted digital signal.

[0123] Example 7 is the time-interleaved digital-to-analog converter system of Example 6, wherein the first combiner is a point-by-point multiplier to multiply the variable coefficient with the parallel data stream.

[0124] Example 8 is the time-interleaved digital-to-analog converter system of any one of Examples 6 and 7, wherein the first combiner is a multiple-input multiple-output unit having a number of finite impulse response filters.

[0125] Example 9 is the time-interleaved digital-to-analog converter system of Example 8, wherein the coefficient adapter is a multiple-input multiple-output coefficient adapter.

[0126] Example 10 is the time-interleaved digital-to-analog converter system of any of Examples 1-9, wherein the calibration system operates in real time.

[0127] Example 11 is a test and measurement instrument comprising a time-interleaved digital-to-analog converter system according to any of Examples 1-10; and a port configured to receive an analog signal and output the analog signal to an electrically coupled or fiber-optically coupled device under test.

[0128] Example 12 is a method for calibrating a time-interleaved digital-to-analog converter, comprising: generating a distorted digital signal by distorting an input digital signal based on an error signal; converting the distorted digital signal into an analog signal through the time-interleaved digital-to-analog converter; converting the analog signal into a downsampled digital signal; generating a model signal based on the input digital signal; and generating an error signal by subtracting the downsampled digital signal from the model signal.

[0129] Example 13 is the method of Example 12, wherein generating the model signal includes processing the digital input signal and the error signal through a finite impulse response filter having at least one adaptive tap and a constant tap.

[0130] Example 14 is the method of any of Examples 12 or 13, further comprising enabling the method during a pre-operational calibration using a known digital input signal.

[0131] Example 15 is the method of any of Examples 12-14, further comprising enabling the method during operation with an unknown digital input signal based on the digital input signal.

[0132] Example 16 is the method of any of Examples 12-15, further comprising delaying the digital input signal through a plurality of delay lines having different factorial products.

[0133] Example 17 is a method according to Example 16, further comprising: receiving the output of each delay line at a corresponding first demultiplexer, and outputting a parallel data stream from each corresponding first demultiplexer, the parallel data stream having a signal number equal to the channel number of the time-interleaved digital-to-analog converter; receiving an error signal, and outputting a parallel error data stream at each of a plurality of second demultiplexers, the parallel error data stream having a signal number equal to the channel number of the time-interleaved digital-to-analog converter; correlating the corresponding parallel data stream with the corresponding parallel error data stream, and outputting a number of variable coefficients equal to the channel number of the time-interleaved digital-to-analog converter at each coefficient adapter of a plurality of coefficient adapters; combining each variable coefficient with the corresponding parallel data stream into a corresponding parallel combined data stream; multiplexing the corresponding combined data into a corresponding signal at each multiplexer of a plurality of multiplexers; and combining each corresponding signal into a distorted digital signal.

[0134] Example 18 is the method of any of Examples 12-17, further comprising: mixing the analog signal with a signal from a local oscillator to generate a mixed signal; filtering the mixed signal through a low pass filter before converting the analog signal into a downsampled digital signal.

[0135] Example 19 is the method of any one of Examples 12-18, further comprising: mixing the model signal with a signal from a local oscillator to generate a mixed signal; filtering the mixed signal through a low-pass filter; and downsampling the filtered mixed signal before generating the error signal.

[0136] Example 20 is the method of Example 19, further comprising filtering the model signal through a tunable bandpass filter before mixing the model signal with the signal from the first local oscillator.

[0137] The previously described versions of the disclosed subject matter have many advantages that have been described or will be apparent to those skilled in the art. Even so, not all versions of the disclosed apparatus, system or method require these advantages or features.

[0138] Additionally, this written description also refers to specific features. It is to be understood that the disclosure in this specification includes all possible combinations of those specific features. Where a specific feature is disclosed in the context of a particular aspect or example, the feature may also be used as much as possible in the context of other aspects and examples.

[0139] Furthermore, when the present application refers to a method having two or more defined steps or operations, the defined steps or operations may be performed in any order or simultaneously, unless the context excludes those possibilities.

[0140] Although specific examples of the present invention have been illustrated and described for purposes of illustration, it will be appreciated that various modifications may be made without departing from the spirit and scope of the present invention. Accordingly, the present invention should not be limited, except as limited by the appended claims.

Claims

1. A time-interleaved digital-to-analog converter system, comprising: a digital predistorter configured to receive a digital input signal and an error signal and output a distorted digital signal based on the digital input signal and the error signal; a time-interleaved digital-to-analog converter having a first sampling rate, the time-interleaved digital-to-analog converter configured to convert the distorted digital signal into an analog signal, the distorted signal correcting for a mismatch between time-interleaved channels of the time-interleaved digital-to-analog converter; as well as Calibration system, including: an analog-to-digital converter having a second sampling rate equal to or lower than the first sampling rate, the analog-to-digital converter being configured to receive the analog signal and convert the analog signal into a downsampled digital signal, a discrete-time linear model configured to receive the digital input signal and output a model signal, and A combiner is configured to subtract the down-sampled digital signal from the model signal to generate the error signal.

2. The time-interleaved digital-to-analog converter system of claim 1, wherein the discrete-time linear model also receives the error signal and comprises a finite impulse response filter having at least one adaptive tap and a constant tap.

3. The time-interleaved digital-to-analog converter system of claim 1, wherein the calibration system is enabled during a pre-operation calibration using a known digital input signal.

4. The time-interleaved DAC system of claim 3, further comprising: A digital signal processor is configured to determine, based on the digital input signal, whether to disable the calibration system during operation with an unknown digital input signal.

5. The time-interleaved digital-to-analog converter system of claim 1 , wherein the digital predistorter comprises: A plurality of delay lines having different order products are provided, each delay line receiving the digital input signal.

6. The time-interleaved DAC system of claim 5, wherein the digital predistorter further comprises: a plurality of first demultiplexers, each first demultiplexer for each output of a delay line having a different order product, each first demultiplexer receiving the output of each of the delay lines and outputting a parallel data stream having a number of signals equal to the number of channels of the time-interleaved digital-to-analog converter; a plurality of second demultiplexers, each second demultiplexer being configured to receive the error signal and output a parallel error data stream, the parallel error data stream having a number of signals equal to the number of channels of the time-interleaved digital-to-analog converter; a plurality of coefficient adapters, each coefficient adapter being operable to correlate a corresponding parallel data stream with a parallel error data stream and output a number of variable coefficients equal to the number of channels of the time-interleaved digital-to-analog converter; a plurality of first combiners, each first combiner being used to combine a corresponding variable coefficient with the parallel data stream into a parallel combined data stream; a plurality of multiplexers, each multiplexer configured to combine a corresponding parallel combined data stream into a signal; as well as A second combiner is configured to combine each signal from the plurality of multiplexers into the distorted digital signal.

7. The time-interleaved DAC system of claim 6, wherein the first combiner is a point-by-point multiplier for multiplying the variable coefficients with the parallel data streams.

8. The time-interleaved DAC system of claim 6, wherein the first combiner is a multiple-input multiple-output unit having a number of finite impulse response filters.

9. The time-interleaved digital-to-analog converter system of claim 8, wherein the coefficient adapter is a multiple-input multiple-output coefficient adapter.

10. The time-interleaved digital-to-analog converter system of claim 1, wherein the calibration system operates in real time.

11. A test and measurement instrument comprising: The time-interleaved digital-to-analog converter system according to claim 1; as well as A port is configured to receive the analog signal and output the analog signal to the electrical coupling or fiber optical coupling device under test.

12. A method for calibrating a time-interleaved digital-to-analog converter, comprising: generating a distorted digital signal by distorting a digital input signal based on an error signal; converting the distorted digital signal into an analog signal by a time-interleaved digital-to-analog converter; Converting the analog signal into a downsampled digital signal; generating a model signal based on the digital input signal; and The error signal is generated by subtracting the downsampled digital signal from the model signal.

13. The method of claim 12, wherein generating the model signal comprises processing the digital input signal and the error signal through a finite impulse response filter having at least one adaptive tap and a constant tap.

14. The method of claim 12, further comprising enabling the method during a pre-operational calibration using a known digital input signal.

15. The method of claim 12, further comprising enabling the method during operation with an unknown digital input signal based on the digital input signal.

16. The method of claim 12, further comprising delaying the digital input signal through a plurality of delay lines having different factorial products.

17. The method according to claim 16, further comprising: receiving an output of each delay line at a respective first demultiplexer and outputting a parallel data stream from each respective first demultiplexer, the parallel data stream having a number of signals equal to the number of channels of the time-interleaved digital-to-analog converter; receiving the error signal and outputting a parallel error data stream at each of a plurality of second demultiplexers, the parallel error data stream having a number of signals equal to a number of channels of the time-interleaved digital-to-analog converter; correlating the respective parallel data streams with the respective parallel error data streams and outputting, at each coefficient adapter of a plurality of coefficient adapters, a number of variable coefficients equal to the number of channels of the time-interleaved digital-to-analog converter; combining each variable coefficient with the corresponding parallel data stream into a corresponding parallel combined data stream; multiplexing the respective combined data into respective signals at each multiplexer of a plurality of multiplexers; as well as Each corresponding signal is combined into the distorted digital signal.

18. The method according to claim 12, further comprising: mixing the analog signal with a signal from a local oscillator to generate a mixed signal; The mixed signal is filtered by a low pass filter before converting the analog signal into a down-sampled digital signal.

19. The method according to claim 12, further comprising: mixing the model signal with a signal from a local oscillator to generate a mixed signal; Filtering the mixed signal through a low-pass filter; Prior to generating the error signal, the filtered mixed signal is downsampled.

20. The method according to claim 19, further comprising: The model signal is filtered by a tunable bandpass filter before being mixed with the signal from the local oscillator.

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