One-time programmable (OTP) memory device and method for testing OTP memory device

Abstract

A one-time programmable (OTP) memory device and a method for testing the OTP memory device are provided. The OTP memory device includes: a cell array circuit including an OTP cell array and a dummy cell block, the OTP cell array including OTP storage cells coupled to a bit line, a read word line and a voltage word line, and the dummy cell block is coupled to the read word line and the voltage word line; a row decoder coupled to the dummy cell block and the OTP cell array through the read word line and the voltage word line; a column decoder coupled to the OTP cell array through the bit line; a write sensing circuit coupled to the column decoder; and a control circuit for controlling the cell array circuit, the row decoder and the write sensing circuit based on commands and addresses, the cell array circuit also including an isolation circuit, which cuts off the first and second voltages transmitted from the row decoder to the OTP cell array in response to a control code in a test mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0000608 filed on January 3, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Exemplary embodiments of the inventive concept relate to a One-Time Programmable (OTP) memory device and a method of testing the OTP memory device. Background Art

[0004] In a one-time programmable (OTP) memory device, multiple OTP cells may be used to store data. For example, each OTP cell may have an unprogrammed state and a programmed state. The data programmed in the OTP cell may be retained without power. In this case, the OTP cell may work like a non-volatile memory. An OTP cell that has been programmed for the first time cannot be programmed a second time. In other words, a programmed OTP cell is irreversible in state. In some examples, the OTP cell may include a fuse or an antifuse and may be electrically programmed. OTP memory is used in the electronics field to permanently store information in various applications.

[0005] Compared to testing of memory that can be reprogrammed multiple times, testing of OTP memory is inefficient because the cells of OTP memory cannot be reprogrammed. Summary of the invention

[0006] According to an exemplary embodiment of the present invention, a one-time programmable (OTP) memory device includes: a cell array circuit, including an OTP cell array and a dummy cell block, wherein the OTP cell array includes a plurality of OTP storage cells coupled to a plurality of bit lines, a plurality of read word lines, and a plurality of voltage word lines, and the dummy cell block is coupled to the plurality of read word lines and the plurality of voltage word lines; a row decoder, coupled to the dummy cell block and the OTP cell array through the plurality of read word lines and the plurality of voltage word lines; a column decoder, coupled to the OTP cell array through the plurality of bit lines; a write sensing circuit, coupled to the column decoder; and a control circuit, configured to control the cell array circuit, the row decoder, and the write sensing circuit based on a command and an address, wherein the cell array circuit further includes an isolation circuit, which cuts off a first voltage and a second voltage transmitted from the row decoder to the OTP cell array in response to a control code in a first test mode.

[0007] According to an exemplary embodiment of the present invention, a method for testing an OTP memory device is provided, the OTP memory device including an OTP cell array, a dummy cell block and an isolation circuit, the OTP cell array including a plurality of OTP storage cells coupled to a plurality of bit lines, a plurality of read word lines and a plurality of voltage word lines, the dummy cell block coupled to a plurality of read word lines and a plurality of voltage word lines, and the isolation circuit coupled to the OTP cell array and the dummy cell block. In the method, the connection between the dummy cell block and the OTP cell array is cut off by the isolation circuit in a first test mode, a read word line and a voltage word line pair are selected from the read word line and the voltage word line, a first test bit line signal and a second test bit line signal are generated by a test bit line signal generator coupled to the dummy cell block in response to a first test enable signal, and based on a comparison of a test result pattern outputted through the bit line with an expected pattern, it is determined whether a row decoder and a column decoder are defective. The row decoder is coupled to a plurality of read word lines and a plurality of voltage word lines, and the column decoder is coupled to a plurality of bit lines.

[0008] According to an exemplary embodiment of the present invention, a method for testing an OTP memory device is provided, the OTP memory device comprising: an OTP cell array, the OTP cell array comprising a plurality of OTP storage cells coupled to a plurality of bit lines, a plurality of read word lines, and a plurality of voltage word lines; a dummy cell block coupled to the plurality of read word lines and the plurality of voltage word lines; and an isolation circuit coupled to the OTP cell array and the dummy cell block. In the method, after the connection between the dummy cell block and the OTP cell array is cut off by the isolation circuit in a first test mode, a first test is performed on a row decoder coupled to the plurality of read word lines and the plurality of voltage word lines and a column decoder coupled to the plurality of bit lines, and if the row decoder and the column decoder are determined to be non-defective in the first test, a second test is performed on the OTP cell array in a second test mode, and based on the second test result, it is determined whether the OTP memory device is defective.

[0009] According to an exemplary embodiment of the present invention, an OTP memory device includes: a cell array circuit, including an OTP cell array, an isolation circuit and a dummy cell block, wherein the OTP cell array includes a plurality of OTP storage cells coupled to a plurality of bit lines, a plurality of first word lines and a plurality of second word lines; a row decoder, coupled to the dummy cell block through a plurality of first word lines and a plurality of second word lines; a column decoder, coupled to the OTP cell array through a plurality of bit lines; a control circuit, configured to control the cell array circuit and the row decoder, wherein the row decoder is configured to provide a control code to the isolation circuit in a test mode, the control code instructing the isolation circuit to cut off a first voltage and a second voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features of the present inventive concept will be more clearly understood by describing in detail exemplary embodiments of the present inventive concept with reference to the attached drawings.

[0011] Figure 1 is a block diagram illustrating a one-time programmable (OTP) memory device according to an exemplary embodiment of the inventive concept.

[0012] Figure 2 Shows Figure 1 The OTP storage unit in the OTP memory device.

[0013] Figure 3 Shows Figure 2 Cross-sectional view of an OTP memory cell.

[0014] Figure 4 Shows Figure 1 Another OTP storage unit in the OTP memory device.

[0015] Figure 5 It shows that the Figure 1 Circuit diagram of the OTP cell array in an OTP memory device.

[0016] Figure 6 It shows that the Figure 1 A circuit diagram of another OTP cell array in an OTP memory device.

[0017] Figure 7 is a diagram showing an exemplary embodiment of the present invention including Figure 1 Circuit diagram of the cell array circuit in an OTP memory device.

[0018] Figure 8 It is shown Figure 7 A circuit diagram of a unit isolation circuit included in an isolation circuit.

[0019] Fig. 9 shows the first test mode Figure 7 The operation of the cell array circuit.

[0020] Fig.10 It shows Figure 1 Block diagram of the control circuitry in an OTP memory device.

[0021] Fig.11 It shows Figure 1 Block diagram of a row decoder in an OTP memory device.

[0022] Fig.12 It shows Figure 1 Block diagram of the voltage generator in an OTP memory device.

[0023] Fig.13 and Fig.14 In the first test mode, Figure 1 The OTP memory devices provide test result patterns.

[0024] Fig.15 An exemplary embodiment according to the inventive concept is shown. Figure 1 The OTP cell array in the OTP memory device.

[0025] Fig.16 is a flowchart illustrating a method of testing an OTP memory device according to an exemplary embodiment of the inventive concept.

[0026] Fig.17 Shows Fig.16 The operation of the row decoder and column decoder is tested in .

[0027] Fig.18 Shows Fig.16 The operation of the OTP cell array is tested in

[0028] Fig.19 is a block diagram illustrating an OTP memory device according to an exemplary embodiment of the inventive concept.

[0029] Fig. 20 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A block diagram of another cell array circuit in an OTP memory device.

[0030] Fig.21 is a block diagram illustrating a memory device including an OTP memory device according to an exemplary embodiment of the inventive concept.

[0031] Fig. 22 is a block diagram illustrating a mobile system including an OTP memory device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0032] Exemplary embodiments of the inventive concept provide a One-Time Programmable (OTP) memory device capable of improving test reliability of a peripheral circuit in the OTP memory device.

[0033] Exemplary embodiments of the inventive concept also provide a method of testing an OTP memory device, which can improve the test reliability of a peripheral circuit in the OTP memory device.

[0034] Exemplary embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings.Throughout the application, like reference numerals may refer to like elements.

[0035] Figure 1 is a block diagram illustrating an OTP memory device according to an exemplary embodiment of the inventive concept.

[0036] Reference Figure 1 , the OTP memory device 50 includes a cell array circuit (CAC) 100 , a row decoder (RDEC) 230 , a column decoder (CDEC) 210 , a write sense circuit (WD-SA) 220 , a voltage generator (VGR) 250 , and a control circuit 300 .

[0037] The cell array circuit 100 includes at least an OTP cell array 110 , an isolation circuit (ISC) 160 , and a dummy cell block (DCB) 180 .

[0038] The OTP cell array 110 includes a plurality of OTP memory cells coupled to a plurality of bit lines BL and a plurality of word lines WL. Figure 2 As described, the plurality of word lines WL may include a plurality of read word lines WLR and a plurality of voltage word lines WLP. The dummy cell block 180 may be coupled between the row decoder 230 and the isolation circuit 160 through the word lines WL.

[0039] The isolation circuit 160 is coupled between the OTP cell array 110 and the dummy cell block 180. The isolation circuit 160 may cut off the first voltage and the second voltage transmitted from the row decoder 230 to the OTP cell array 110 in response to the control code CCD in the first test mode. In an exemplary embodiment of the inventive concept, the first voltage may be a read voltage applied to the read word line WLR, and the second voltage may be a program voltage applied to the voltage word line WLP.

[0040] The control circuit 300 controls the test operation, write operation, and read operation of the OTP memory device 50 based on the command CMD and the address ADDR received from the outside of the OTP memory device 50. The test operation may include a first test performed on the peripheral circuit in a first test mode and a second test performed on the OTP cell array 100 in a second test mode.

[0041] The control circuit 300 generates a first control signal CTL1 for controlling the OTP cell array 110, a second control signal CTL2 for controlling the row decoder 230, a third control signal CTL3 for controlling the voltage generator 250, and a fourth control signal CTL4 for controlling the write sensing circuit 220 based on the command CMD. In addition, the control circuit 300 generates a row address RADDR and a column address CADDR based on the address ADDR. The control circuit 300 provides the row address RADDR to the row decoder 230, and provides the column address CADDR to the column decoder 210.

[0042] The column decoder 210 is coupled to the OTP cell array 110 through the bit lines BL. The column decoder 210 selects some of the bit lines BL based on the column address CADDR.

[0043] The write sensing circuit 220 is coupled to the column decoder 210, writes the input data DI to the OTP cell array 110 through the column decoder 210, and reads the output data DO from the OTP cell array 110 through the column decoder 210 to provide the output data DO to the outside. In addition, the write sensing circuit 220 can provide a test result pattern TD to the control circuit 300 in the first test mode. The control circuit 300 compares the test result pattern TD with the expected pattern, and outputs a test result signal TRS indicating whether the peripheral circuit is defective based on the comparison of the test result pattern TD with the expected pattern.

[0044] The write sensing circuit 220 may include a write driver and a sense amplifier. The sense amplifier may perform a read operation to sense the data stored in the OTP memory cell and provide the read data as output data DO to the outside. The write driver may perform a write operation to store the write data in the OTP memory cell. The write driver and the sense amplifier SA may be formed in the same circuit or device, or may be formed in a separate circuit or device. Separate formed in a circuit or device.

[0045] The row decoder 230 is coupled to the cell array circuit 100 through the word lines WL. The row decoder 230 can determine one of the word lines WL as a selected word line, and can determine the remaining word lines WL other than the selected word line as unselected word lines based on the row address RADDR. In addition, the row decoder 230 can apply the control code CCD to the isolation circuit 160 based on the second control signal CTL2 and the row address RADDR in the first test mode.

[0046] The voltage generator 250 generates an operating voltage VO under the control of the control circuit 300 , and provides the operating voltage VO to the word line WL through the row decoder 230 .

[0047] Figure 2 Shows Figure 1 The OTP storage unit in the OTP memory device 50.

[0048] Reference Figure 2 , the OTP memory cell UCa may include an anti-fuse AF and a read transistor TR.

[0049] The anti-fuse AF may be connected between the corresponding voltage word line WLP and the intermediate node NI. The read transistor TR may be connected between the intermediate node NI and the corresponding bit line BL, and may have a gate coupled to the corresponding read word line WLR.

[0050] The anti-fuse AF may include, for example, a metal oxide semiconductor (MOS) transistor. Figure 2 As shown, the drain electrode of the MOS transistor AF may be floating, the source electrode of the MOS transistor AF may be connected to the intermediate node NI, and the gate electrode of the MOS transistor AF may be connected to the voltage word line WLP.

[0051] The anti-fuse AF is an example element of an OTP memory cell. In an embodiment of the inventive concept, the anti-fuse AF may have electrical characteristics opposite to those of a typical fuse, for example, the anti-fuse AF may have a higher resistance value in an unprogrammed state and a lower resistance value in a programmed state.

[0052] In another embodiment of the present invention, the anti-fuse AF may include a dielectric material between two conductors. The dielectric material may be broken and programmed by applying a high voltage between the two conductors for a sufficient time. When programmed in this manner, the two conductors may be electrically connected by the broken dielectric material. Therefore, the anti-fuse AF may have a lower resistance value. In an anti-fuse type OTP memory, a MOS capacitor may have a thin gate oxide used as an anti-fuse AF. A high voltage may be applied between the two electrodes of the MOS capacitor to program the MOS capacitor. An OTP memory cell using a MOS capacitor may have a small cell area and a low programming current. Therefore, low power and byte-width programming may be achieved.

[0053] A program voltage of a relatively high voltage level may be applied to the voltage word line WLP in the program mode. A read voltage having a voltage level lower than the program voltage may be applied to the voltage word line WLP in the read mode. A selection voltage having a voltage level sufficient to turn on the read transistor TR may be applied to the read word line WLR in the program mode and the read mode.

[0054] In the programming mode, a program permission voltage may be applied to a bit line connected to an OTP memory cell to be programmed, and a program inhibition voltage greater than the program permission voltage may be applied to a bit line connected to an OTP memory cell not to be programmed. For example, the program permission voltage may be set to a ground voltage, and / or the program inhibition voltage and the read voltage may be set to a power supply voltage. In other embodiments of the present inventive concept, the voltage levels of the program voltage, the read voltage, the program permission voltage, and / or the program inhibition voltage may be different, for example depending on the characteristics and / or configuration of the OTP memory.

[0055] Programming of the antifuse AF may be performed in a programming mode. For example, in the programming mode, a program voltage may be applied to the voltage word line WLP, a selection voltage may be applied to the read word line WLR to turn on the read transistor TR, and a program permission voltage may be applied to the bit line BL.

[0056] Figure 3 Shows Figure 2 Cross-sectional view of the OTP memory cell UCa.

[0057] Reference Figure 3 , the OTP memory cell UCa may include an anti-fuse AF and a read transistor TR on the same substrate P_SUB.

[0058] The read transistor TR may include a first gate 111 connected to a corresponding read word line WLR, a first gate insulating layer (GOX) 112 isolating the first gate 111 from a substrate P_SUB, a first source region 113 connected to a corresponding bit line BL, and a first drain region 114 .

[0059] The anti-fuse AF may include a second gate 121 connected to a corresponding voltage word line WLP, a second gate insulating layer 122 insulating the second gate 121 from the substrate P_SUB, a second source region 123 connected to the first drain region 114 of the read transistor TR, and a floating second drain region 124 .

[0060] The second source region 123 of the anti-fuse AF may be electrically connected to the first drain region 114 of the read transistor TR through a conductive path 127. The conductive path 127 may include a metal line in an upper space and an interlayer structure such as a via for connecting the metal line to the upper surface of the substrate P_SUB. For example, the via on the first side of the conductive path 127 may be connected to the second source region 123, and the via on the second side of the conductive path 127 may be connected to the first drain region 114. In some exemplary embodiments of the inventive concept, the second source region 123 of the anti-fuse AF and the first drain region 114 of the read transistor TR may be merged. In this case, the conductive path 127 may be omitted.

[0061] For example, the substrate P_SUB may be doped with p-type impurities, and the first and second source regions 113 and 123 and the first and second drain regions 114 and 124 may be doped with n-type impurities.

[0062] The read transistor TR may further include a first spacer 115 on sidewalls of the first gate 111 and the first gate isolation layer 112. The anti-fuse AF may further include a second spacer 125 on sidewalls of the second gate 121 and the second gate isolation layer 122.

[0063] Figure 4 Shows Figure 1 Another OTP storage unit in the OTP memory device 50.

[0064] Reference Figure 4 , the OTP memory cell UCb may include an anti-fuse AF and a read transistor TR. The anti-fuse AF may be connected between the corresponding voltage word line WLP and the intermediate node NI. The read transistor TR may be connected between the intermediate node NI and the corresponding bit line BL. The gate electrode of the read transistor TR may be connected to the corresponding read word line WLR.

[0065] The anti-fuse AF may include, for example, a MOS capacitor. Figure 4 As shown, a first electrode of the MOS capacitor may be connected to a voltage word line WLP, and a second electrode of the MOS capacitor may be connected to an intermediate node NI.

[0066] Figure 4 The structure and manufacturing process of the OTP memory cell UCb may be similar to Figure 3 To implement a MOS capacitor, a conducting path can be added to connect Figure 3 The second source region 123 and the second drain region 124 are formed in the embodiment of the present invention.

[0067] Figure 5 It shows that the Figure 1 A circuit diagram of an OTP cell array in an OTP memory device 50 is shown.

[0068] Reference Figure 5 The OTP cell array 110a may include a plurality of OTP memory cells UC11a and UC21a, which are respectively coupled to a plurality of bit lines BL1-BLm, a plurality of voltage word lines WLP1-WLPn, and a plurality of read word lines WLR1-WLRn, and are arranged in an n*m matrix. Here, n and m are positive integers.

[0069] A gate electrode of the read transistor TR may be connected to a corresponding read word line WLRx (x=1~n), and a source electrode of the read transistor TR may be connected to a corresponding bit line BLy (y=1~m).

[0070] A first electrode of the anti-fuse AF may be connected to the corresponding word line WLPx, and a second electrode of the anti-fuse AF may be connected to the drain electrode of the read transistor TR. Here, the first electrode of the anti-fuse AF may be a gate electrode, and the second electrode of the anti-fuse AF may be a source electrode.

[0071] As described above, the anti-fuse AF may be a MOS transistor, a gate electrode or a first electrode of which may be connected to a corresponding voltage word line WLPx, a source electrode or a second electrode of which may be connected to a drain electrode of the read transistor TR, and a drain electrode of the MOS transistor AF may be floating.

[0072] Each of the OTP memory cells UC11 a and UC21 a may include an anti-fuse AF and a read transistor TR.

[0073] Figure 6 It shows that the Figure 1 A circuit diagram of another OTP cell array in the OTP memory device 50 is shown.

[0074] Reference Figure 6 The OTP cell array 110b may include a plurality of OTP memory cells UC11b and UC21b, which are respectively coupled to a plurality of bit lines BL1-BLm, a plurality of voltage word lines WLP1-WLPn, and a plurality of read word lines WLR1-WLRn, and are arranged in an n*m matrix.

[0075] Figure 6 The OTP cell array 110b is Figure 5 The OTP cell array 110a is different in that two OTP memory cells UC11b and UC21b form a pair. In other words, the read transistors TR in two adjacent OTP memory cells are commonly coupled to the corresponding bit line BL at a common node.

[0076] Figure 7 is a diagram showing an exemplary embodiment of the present invention including Figure 1 A circuit diagram of a cell array circuit in an OTP memory device 50 is shown.

[0077] Reference Figure 7 , the cell array circuit 100 includes an OTP cell array 110 , an isolation circuit 160 , a dummy cell block 180 , a test bit line signal generator 130 , and a switch circuit 190 .

[0078] The OTP cell array 110 includes a plurality of OTP memory cells UC11 ˜UCnm, which are respectively coupled to a plurality of bit lines BL1 ˜BLm, a plurality of voltage word lines WLP1 ˜WLPn, and a plurality of read word lines WLR1 ˜WLRn, and are arranged in an n*m matrix.

[0079] The isolation circuit 160 includes a plurality of unit isolation circuits (UIS1-UISn) 161-16n coupled to a plurality of voltage word lines WLP1-WLPn and a plurality of read word lines WLR1-WLRn. The isolation circuit 160 may receive a control code CCD and a power supply voltage VDDIO.

[0080] The dummy cell block 180 includes a plurality of unit dummy cells 181 ˜ 18 n , and each unit dummy cell 181 ˜ 18 n is coupled to a corresponding read word line and voltage word line pair among read word lines WLR1 ˜WLRn and voltage word lines WLP1 ˜WLPn. The dummy cell block 180 may be coupled to the test bit line signal generator 130 .

[0081] The unit dummy cell 181 includes a first transistor 1811 and a second transistor 1812. The first transistor 1811 has a gate coupled to a read word line WLR1, and the second transistor 1812 has a gate coupled to a voltage word line WLP1. A first electrode of the first transistor 1811 and a first electrode of the second transistor 1812 may be coupled to each other. The unit dummy cell 18n includes a first transistor 18n1 and a second transistor 18n2. The first transistor 18n1 has a gate coupled to a read word line WLRn, and the second transistor 18n2 has a gate coupled to a voltage word line WLPn. A first electrode of the first transistor 18n1 and a first electrode of the second transistor 18n2 may be coupled to each other.

[0082] The unit dummy cells 181~18n may include: a first unit dummy cell set, which is coupled to a first read word line (e.g., odd read word line) and a voltage word line (e.g., odd voltage word line) group among the read word lines WLR1~WLRn and the voltage word lines WLP1~WLPn; and a second unit dummy cell set, which is coupled to a second read word line (e.g., even read word line) and a voltage word line (e.g., even voltage word line) group.

[0083] The test bit line signal generator 130 may include first, second, third, fourth, fifth, and sixth inverters 131 , 132 , 133 , 134 , 135 , and 136 .

[0084] The first inverter 131 includes an input terminal for receiving a programming control signal PGMENB and an output terminal, the output terminal being coupled to the second terminal of the second transistor of each unit dummy cell in the first unit dummy cell set and the second terminal of the second transistor of each unit dummy cell in the second unit dummy cell set. In other words, the output terminal of the first inverter 131 is coupled to the second terminal of each of the unit dummy cells 181 to 18n. The second inverter 132 includes an input terminal for receiving a first test enable signal TDECEN and an output terminal coupled to the first node N11. The third inverter 133 includes an input terminal coupled to the first node N11 and an output terminal coupled to the second terminal of the first transistor of each unit dummy cell in the first unit dummy cell set at a second node N12.

[0085] The fourth inverter 134 includes an input terminal coupled to the second node N12 and an output terminal for providing a first test bit line signal TBLS1. The fifth inverter 135 includes an input terminal coupled to the first node N11 and an output terminal coupled to the second terminal of the first transistor of each unit dummy cell in the second unit dummy cell set at a third node N13. The sixth inverter 136 includes an input terminal coupled to the third node N13 and an output terminal for providing a second test bit line signal TBLS2.

[0086] In the first test mode, the program control signal PGMENB and the first test enable signal TDECEN have logic high levels, respectively.

[0087] If the program control signal PGMENB and the first test enable signal TDECEN have a logic high level in the first test mode and the first read word line and voltage word line pair are selected from the first read word line and voltage word line group, a first current path is formed from the second node N12 to the first inverter 131 through the first unit dummy cell. Here, the first unit dummy cell included in the first unit dummy cell set is coupled to the selected first pair, and thus the logic levels of the first test bit line signal TBLS1 and the second test bit line signal TBLS2 may be determined.

[0088] In addition, if the second read word line and voltage word line pair is selected from the second read word line and voltage word line group in the first test mode, a second current path is formed from the third node N13 to the first inverter 131 through the first unit dummy cell. Here, the first unit dummy cell included in the second unit dummy cell set is coupled to the selected second pair, and thus the logic levels of the first test bit line signal TBLS1 and the second test bit line signal TBLS2 can be determined.

[0089] The switch circuit 190 includes a plurality of switches 191-19n coupled to the bit lines BL1-BLm, and the plurality of switches 191-19n transmit the first test bit line signal TBLS1 and the second test bit line signal TBLS2 to the bit lines BL1-BLm in response to the first test enable signal TDECEN. The bit lines BL1-BLm may include a first bit line group and a second bit line group. In an exemplary embodiment of the inventive concept, the first bit line group may correspond to odd bit lines, and the second bit line group may correspond to even bit lines.

[0090] In an exemplary embodiment of the inventive concept, the plurality of switches 191-19n transmit the first test bit line signal TBLS1 to the first bit line group and transmit the second test bit line signal TBLS2 to the second bit line group. Alternatively, the plurality of switches 191-19n transmit the first test bit line signal TBLS1 to the second bit line group and transmit the second test bit line signal TBLS2 to the first bit line group.

[0091] Figure 8 It is shown Figure 7 1 is a circuit diagram of a unit isolation circuit included in the isolation circuit 160.

[0092] exist Figure 8 , the configuration of the unit isolation circuit 161 is shown. However, each of the unit isolation circuits 162 to 61 n may have the same configuration as the unit isolation circuit 161 .

[0093] Reference Figure 8 The unit isolation circuit 161 includes a p-channel metal oxide semiconductor (PMOS) transistor 171 , n-channel metal oxide semiconductor (NMOS) transistors 172 , 173 , 174 , a PMOS transistor 175 , and NMOS transistors 176 , 177 .

[0094] The PMOS transistor 171 is coupled to the row decoder 230 at the first node N21 of the read word line WLR1, is coupled to the read transistor TR1 of the OTP memory cell UC11 at the second node N22 of the read word line WLR1, and has a gate for receiving the first control code CCD1. The NMOS transistor 172 is coupled in parallel with the PMOS transistor 171 between the first node N21 and the second node N22, and has a gate for receiving the second control code CCD2. The NMOS transistors 173 and 174 are coupled in series between the second node N22 and the ground voltage VSS. The NMOS transistor 173 has a gate coupled to the power supply voltage VDDIO, and the NMOS transistor 174 has a gate for receiving the first control code CCD1.

[0095] The PMOS transistor 175 is coupled to the row decoder 230 at the first node N31 of the voltage word line WLP1, is coupled to the anti-fuse AF of the OTP memory cell UC11 at the second node N32 of the voltage word line WLP1, and has a gate for receiving the third control code CCD3. The NMOS transistors 176 and 177 are coupled in series between the second node N32 and the ground voltage VSS. The NMOS transistor 176 has a gate coupled to the power supply voltage VDDIO, and the NMOS transistor 177 has a gate for receiving the fourth control code CCD4.

[0096] In the first test mode, the first to fourth control codes CCD1 to CCD4 may have a logic high level, respectively. Therefore, in the first test mode, the unit isolation circuit 161 cuts off the first voltage to be applied to the read word line WLR1 and the second voltage to be applied to the voltage word line WLP1 by discharging the first voltage (e.g., the read voltage VRD) to the ground voltage VSS and by discharging the second voltage (e.g., the program voltage VP) to the ground voltage VSS.

[0097] Fig. 9 shows the first test mode Figure 7 Example operation of the cell array circuit 100.

[0098] Reference Figures 7 to 9 , for the pair of read word line WLR1 and voltage word line WLP1 in the first test mode, the row decoder 230 provides the first voltage VRD to the read word line WLR1, provides the second voltage VP to the voltage word line WLP1, and provides a ground voltage (e.g., 0V) to the unselected word line. Here, the first voltage VRD may be 1.2V, and the second voltage VP may be 2.4V. The unit isolation circuit 161 cuts off the first voltage VRD and the second voltage VP provided to the OTP cell array 110, and the first transistor 1811 and the second transistor 1812 in the unit dummy cell 181 are turned on. Therefore, a current path CP is formed from the second node N12 to the first inverter 131 through the unit dummy cell 181.

[0099] By applying the ground voltage to the unselected read word line and voltage word line pair, the first and second transistors of each of the other unit dummy cells 182 to 18n are turned off. Therefore, the second node N12 is changed from a high level to a low level, and the third node N13 is kept at a high level. Therefore, the fourth inverter 134 provides the first test bit line signal TBLS1 having a high level to the first bit line group through the switch circuit 190, and the sixth inverter 136 provides the second test bit line signal TBLS2 having a low level to the second bit line group through the switch circuit 190.

[0100] Since the isolation circuit 160 cuts off the first voltage VRD and the second voltage VP provided to the OTP cell array 110, Figure 1 The write sensing circuit 220 in the embodiment outputs the test result pattern TD to the control circuit 300 , which responds to the first and second test bit line signals TBLS1 and TBLS2 , without regard to defects of the OTP memory cells of the OTP cell array 110 .

[0101] If the test result pattern TD corresponds to the first pattern or the second pattern in which "0" and "1" are alternately repeated, the test result pattern TD indicates that the row decoder 230 and the column decoder 210 are not defective. If the test result pattern TD does not correspond to the first pattern or the second pattern, the test result pattern TD indicates that at least one of the row decoder 230 and the column decoder 210 is defective.

[0102] The row decoder 230 may sequentially control the word lines WL, and the column decoder 210 may sequentially control the bit lines BL.

[0103] Therefore, the OTP memory device 50 including the isolation circuit 160 according to an exemplary embodiment of the inventive concept may perform the first test on the row decoder 230 and the column decoder 210 without being affected by the states of the OTP memory cells of the OTP cell array 110 .

[0104] Fig.10 It shows Figure 1 1 is a block diagram of a control circuit in an OTP memory device 50.

[0105] refer to Fig.10 , the control circuit 300 may include a command decoder 310 , an address buffer 320 , a control signal generator 330 , and a decision logic 340 .

[0106] The command decoder 310 decodes the command CMD and provides the decoded command D_CMD to the control signal generator 330. The address buffer 320 receives the address ADDR, provides the row address RADDR to the row decoder 230, and provides the column address CADDR to the column decoder 210.

[0107] The control signal generator 330 receives the decoded command D_CMD, generates control signals CTL1-CTL4 based on the operation indicated by the decoded command D_CMD, and provides the control signals CTL1-CTL4 to the corresponding components respectively. In the first test mode, the decision logic 340 receives the test result pattern TD, and outputs the test result signal TRS based on the comparison between the test result pattern TD and the expected pattern. The test result signal TRS can indicate whether the row decoder 230 and the column decoder 210 are defective.

[0108] Fig.11 It shows Figure 1 A block diagram of a row decoder in an OTP memory device 50 is shown.

[0109] Reference Fig.11 , the row decoder 230 may include a pre-decoder 231 , a word line driver 233 , and a code signal generator 235 .

[0110] The predecoder 231 receives the row address RADDR, decodes the row address RADDR, and provides the decoded row address DRA to the word line driver 233 and the code signal generator 235. The word line driver 233 receives the operation voltage VO, and in response to the decoded row address DRA, transmits at least some of the operation voltage VO to the word line as the word line voltage VWL. The code signal generator 235 receives the first test enable signal TDECEN and the decoded row address DRA in the first test mode, and provides the control code CCD to the unit isolation circuit coupled to the word line corresponding to the decoded row address DRA.

[0111] Fig.12 It shows Figure 1 Block diagram of a voltage generator in an OTP memory device 50.

[0112] Reference Fig.12 , the voltage generator 250 may include a bandgap reference circuit (BGR) 251 , an operational amplifier (AMP) 252 , a driving transistor TD, a voltage dividing resistor R, and a multiplexer (MUX) 253 .

[0113] The operational amplifier 252 can amplify the difference between the bandgap reference voltage VBGR and the feedback voltage VF to output the amplified voltage. The driving transistor TD is connected to the power supply voltage VDD to generate a driving current corresponding to the amplified voltage of the operational amplifier 252. The voltage-dividing resistor R is connected in series between the driving transistor TD and the ground voltage VSS to provide the divided voltages V1 to VQ through the division nodes N1 to NQ. The multiplexer 253 can select one of the divided voltages V1 to VQ based on the third control signal CTL3 to use the selected one of the divided voltages V1 to VQ as the feedback voltage VF. The operating voltage VO can be provided at one of the division nodes N1 to NQ.

[0114] Fig.13 and Fig.14 In the first test mode, Figure 1 The OTP memory device 50 provides a test result pattern.

[0115] Reference Figure 1 and Fig.13 If the row decoder 230 and the column decoder 210 are not defective in the first test performed on the OTP memory device 50, the write sensing circuit 220 may output test result patterns TD1 ˜ TD8 corresponding to the first pattern AA′h or the second pattern 55′h in which “0” and “1” are alternately repeated.

[0116] Reference Figure 1 and Fig.14If at least one of the row decoder 230 and the column decoder 210 has a defect in the first test performed on the OTP memory device 50, the write sensing circuit 220 may output test result patterns TD1 ˜ TD8 corresponding to the pattern FF′h in which “1” is alternately repeated.

[0117] Fig.15 An exemplary embodiment according to the inventive concept is shown. Figure 1 The OTP cell array in the OTP memory device 50 .

[0118] Reference Fig.15 The OTP cell array 110 c may include a main OTP cell array MOCA and a test cell array TCA. The main OTP cell array MOCA may include a plurality of unprogrammed OTP memory cells 1101 .

[0119] The test cell array TCA may include a first test row TCR1 including a first unprogrammed test cell 1102, and the first test row TCR1 is coupled to the word line WLn+1. The first test cell 1102 of the first test row TCR1 may have the same structure as the OTP memory cell 1101 and may be programmed during testing of the OTP memory device 50. The programming operation (or write operation) of the OTP memory device 50 may be tested by programming the first test cell 1102 and then reading data from the programmed first test cell 1102.

[0120] The test cell array TCA may include a second test row TCR2 including a mask-programmed second test cell 1103, and the second test row TCR2 is coupled to the word line WLn+2. During the manufacture of the OTP memory device 50, the second test cell 1103 may be processed to correspond to a programmed state or an unprogrammed state of the OTP memory cell 1101.

[0121] For example, the second test cell 1103 may have a layout having a structure corresponding to a programmed state of the OTP memory cell 1101, such as an anti-fuse AF type, whose terminals have a closed state or a low resistance state. In other words, the second test cell 1103 may have the same layout as the OTP memory cell 1101 except for the anti-fuse AF, and may include a conductor (e.g., metal) as a structure corresponding to the anti-fuse AF of the OTP memory cell 1101.

[0122] As another example, the second test cell 1103 may have a layout having a structure corresponding to an unprogrammed state of the OTP memory cell 1101, such as an anti-fuse AF, both ends of which have a disconnected state or a high resistance state. In other words, the second test cell 1103 may have the same layout as the OTP memory cell 1101 except for the anti-fuse AF, and may include an insulator as a structure corresponding to the anti-fuse AF of the OTP memory cell 1101. Therefore, the read operation of the OTP memory device 50 may be tested by reading the data stored in the second test cell 1103.

[0123] Fig.16 is a flowchart illustrating a method of testing an OTP memory device according to an exemplary embodiment of the inventive concept.

[0124] Reference Figures 1 to 16 In a method for testing an OTP memory device 50 including an OTP cell array 110, wherein the OTP cell array 110 includes a plurality of OTP memory cells coupled to a plurality of bit lines, a plurality of read word lines, and a plurality of voltage word lines, a dummy cell block 180 coupled to the plurality of read word lines and the plurality of voltage word lines, and an isolation circuit 160 coupled between the OTP cell array 110 and the dummy cell block 180, in operation S100, in a first test mode, the isolation circuit 160 cuts off the connection between the OTP cell array 110 and the dummy cell block 180, and performs a first test on a row decoder 230 coupled to the read word lines and the voltage word lines, and a column decoder 210 coupled to the bit lines.

[0125] In operation S210, it is determined whether the row decoder 230 and the column decoder 210 are not defective based on the result of the first test. When it is determined that at least one of the row decoder 230 and the column decoder 210 has a defect (No in S210), it is determined that the OTP memory device 50 is defective in operation S430.

[0126] When it is determined that the row decoder 230 and the column decoder 210 are not defective (Yes in S210), a second test is performed on the OTP cell array 110 in operation S300. Whether the OTP cell array 110 is not defective is determined based on a result of the second test in operation S410.

[0127] When it is determined that the OTP cell array 110 has no defects ("Yes" in S410), the OTP memory device 50 is determined to be normal in operation S420. When it is determined that the OTP cell array 110 has defects ("No" in S410), the OTP memory device 50 is determined to be defective in operation S430.

[0128] Fig.17 Shown in detail Fig.16 The operation of the row decoder and column decoder is tested in .

[0129] Reference Figures 1 to 14 as well as Fig.17 In order to perform a first test on the row decoder 230 and the column decoder 210, in operation S110, the isolation circuit 160 cuts off the connection between the OTP cell array 110 and the dummy cell block 180. In other words, the dummy cell block 180 and the OTP cell array 110 are isolated from each other. In operation S120, the row decoder 230 selects a pair of a read word line and a voltage word line in response to the row address RADDR.

[0130] In operation S130, the test bit line signal generator 130 connected to the dummy cell block 180 generates first and second test bit line signals TBLS1 and TBLS2 based on the first test enable signal TDECEN. In operation S140, the switch circuit 190 coupled to the bit line applies the first and second test bit line signals TBLS1 and TBLS2 to the bit line.

[0131] The write sensing circuit 220 outputs the test result pattern TD received through the bit lines. In operation S150, to output the test result signal TRS, the control circuit 300 determines whether the row decoder 230 and the column decoder 210 are defective based on comparison of the test result pattern TD output through the bit lines with an expected pattern.

[0132] Fig.18 Shows Fig.16 The operation of the OTP cell array is tested in

[0133] Reference Figures 1 to 15 as well as Fig.18 In operation S300, in order to perform a second test on the OTP cell array, in operation S310, the state of the second test cell 1103 of the second test row TCR2 may be read. For example, the second test cell 1103 may be mask programmed to correspond to an OTP memory cell programmed during manufacture of the OTP memory device 50, for example, to store a binary value "1".

[0134] In operation S320, it is determined whether the reading of the second test cell 1103 of the second test row TCR2 is successful or whether the reading fails. As described above, since the second test cell 1103 has been mask-programmed to a state known to the manufacturer of the OTP memory device 50, it is possible to determine whether the reading operation of the second test cell 1103 of the second test row TCR2 is successful based on the data output from the write sensing circuit 220 during the reading of data from the mask-programmed second test cell 1103. For example, if all of the second test cells 1103 are mask-programmed to store a binary value of "1", when the data output from the write sensing circuit 220 by accessing the second test cell 1103 includes a bit that is not a binary value of "1", it can be determined that the reading operation of the second test cell 1103 has failed.

[0135] In operation S430 , if the read operation of the second test unit 1103 fails, it may be determined that the OTP memory device 50 is defective.

[0136] Alternatively, if it is determined that the read operation of the second test cell 1103 is successful, the process continues to operation S330. In operation S330, if the read operation of the second test cell 1103 is successful, the first test cell 1102 of the first test row TCR1 may be programmed. Fig.15 As described, the first test cell 1102 may have the same structure, such as the same layout, as the unprogrammed OTP cell 1101. During testing of the OTP memory device 50, the first test cell 1102 may be programmed and thus correct programming of the OTP memory device 50 may be tested in conjunction with operation S340.

[0137] Therefore, the user can be provided with an OTP memory device 50 determined to be normal due to testing the OTP memory device 50 by programming the first test cell 1102 of the test cell array TCA, instead of programming at least one of the OTP memory cells 1101 in the main OTP cell array MOCA.

[0138] In operation S340, it is determined whether programming of the first test cell 1102 is successful. In other words, data obtained by reading the data stored in the first test cell 1102 is examined to determine whether programming of the first test cell 1102 is successful. For example, when all of the first test cells 1102 are programmed to store a binary value of "1" in operation S330, and the read data includes a bit that is not "1" in operation S340, it can be determined that programming of the first test cell 1102 is a failure.

[0139] When programming of the first test cell 1102 fails (No in S340), the OTP memory device 50 may be determined to be defective in conjunction with operation S430. Alternatively, in conjunction with operation S420, when programming of the first test cell 1102 succeeds, the OTP memory device 50 may be determined to be normal.

[0140] like Fig.18 As shown, by first reading the second test row TCR2 and determining whether its read operation is successful, the defect condition of the OTP memory device can be determined at an early stage.

[0141] Fig.19 is a block diagram illustrating an OTP memory device according to an exemplary embodiment of the inventive concept.

[0142] Reference Fig.19 , the OTP memory device 51 may include an OTP cell array BK1, BK2, BK3, and BK4, a row decoder XDEC1, XDEC2, XDEC3, and XDEC4, a voltage generator VDR, a column decoder CSEL, and write sensing circuits WD and SA.

[0143] As described above, the OTP cell arrays BK1-BK4 may include a plurality of OTP memory cells coupled to a plurality of bit lines and a plurality of word lines, respectively. The word lines may include voltage word lines and read word lines. The OTP memory cells in the OTP cell arrays BK1-BK4 may form a plurality of memory banks BK1-BK4.

[0144] The row decoders XDEC1 to XDEC4 can select a word line corresponding to the row address RADDR.

[0145] The column decoder CSEL may select a bit line corresponding to the column address CADDR.

[0146] The OTP memory device 51 includes an isolation circuit, and the isolation circuit may cut off a read voltage and a program voltage supplied to the OTP cell arrays BK1 ˜ BK4 in the first test mode.

[0147] The OTP memory device 51 can program multiple bits, in other words, multiple OTP memory cells in the memory banks BK1 to BK4 can be programmed simultaneously in the programming mode. In some exemplary embodiments of the present inventive concept, the OTP memory device 51 can select and enable one of the memory banks BK1 to BK4, and simultaneously program multiple OTP memory cells of a selected row in the selected memory bank. In other exemplary embodiments of the present inventive concept, the OTP memory device 51 can select and enable two or more memory banks in the memory banks BK1 to BK4, and simultaneously program multiple OTP memory cells of a selected row in the selected memory bank.

[0148] The write driver WD may program a plurality of OTP memory cells based on the program data DI including a plurality of bits with respect to the current program address. The sense amplifier SA may generate output data DO including the plurality of bits by sensing the storage values ​​of the programmed OTP memory cells.

[0149] Fig. 20 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 1 is a block diagram of another cell array circuit in the OTP memory device 50.

[0150] Reference Fig. 20 , the cell array circuit 100b may include an OTP cell array 110, a dummy cell block (DCB) 180b, a test bit line signal generator (TBSG) 130b, and a switch circuit (SC) 190b. The OTP cell array 110 includes a plurality of OTP memory cells coupled to a plurality of bit lines BL and a plurality of word lines WL.

[0151] The OTP cell array 110 can be coupled to a row decoder 230 ( Figure 1 The column decoder 210 is coupled to the write sensing circuit (WD-SA) 220, and the write sensing circuit 220 writes the input data DI to the OTP cell array 110 through the column decoder 210, and reads the output data DO from the OTP cell array 110 through the column decoder 210 to provide the output data DO to the outside.

[0152] The dummy cell block 180b is coupled to the OTP cell array 110 through the word line WL. The test bit line signal generator 130b provides the first test bit line signal TBLS1 and the second test bit line signal TBLS2 to the switch circuit 190b in the first test mode.

[0153] The switch circuit 190b includes a plurality of switches coupled to the bit line BL, and the plurality of switches transmit the first test bit line signal TBLS1 and the second test bit line signal TBLS2 to the bit line BL in the first test mode. Therefore, in the first test mode, even if data is not programmed into the OTP memory cells of the OTP cell array 110, the write sensing circuit 220 can output the test result pattern TD2 in response to the first test bit line signal TBLS1 and the second test bit line signal TBLS2.

[0154] Fig.21 is a block diagram illustrating a memory device including an OTP memory device according to an exemplary embodiment of the inventive concept.

[0155] Reference Fig.21, the memory device 500 may include a control logic 505 , an address decoder 530 , a memory cell array 540 , an address buffer unit 550 , an input / output (I / O) circuit 560 , and an OTP memory device 50 .

[0156] The control logic 505 receives the control signal 70 through the command pin 75, receives the address signal 80 through the address pin 85, and controls the address decoder 530 accessing the memory cell array 540 based on the command and address signal 80. The control signal 70 includes a chip select signal / CS, a write enable signal / WE, a column address strobe signal / CAS, and a row address strobe signal / RAS. The address signal 30 includes addresses ADDR1 to ADDRn. The combination of the control signals / CS, / WE, / CAS, and / RAS specifies the command. In addition, in some embodiments of the present invention, the control logic 505 may also receive a clock enable signal / CKE, a clock signal CK, and an inverted clock signal / CK.

[0157] The address buffer unit 550 receives the address signal 80 through the address pin 85 and provides the addresses ADDR1 ˜ADDRn to the control logic 505 and the address decoder 530 in synchronization with the clock signal CK or the inverted clock signal / CK.

[0158] The I / O circuit 560 provides data 90 to or receives data 90 from the memory cell array 540 through the data pin 95. The data 90 includes data DQ1DQk.

[0159] The control logic 505 includes a command decoder 510 and a mode register 520. The command decoder 510 decodes a command specified by the control signals / CS, / WE, / CAS, and / RAS to provide a mode register set (MRS) command MRS_CMD to the mode register 520. The mode register 520 sets the operation mode of the memory device 500 in response to the MRS command MRS_CMD. The operation mode of the memory device 500 may include a test mode, an MRS mode, a test MRS (TMRS) mode, and a normal operation mode.

[0160] In the test mode, the external tester ATE 40 may program data into the OTP memory device 50. The programmed data may be used to control the memory device 500.

[0161] Fig. 22 is a block diagram illustrating a mobile system including an OTP memory device according to an exemplary embodiment of the inventive concept.

[0162] refer to Fig. 22, the mobile system 1200 includes an application processor (AP) 1210 , a connection circuit 1220 , a volatile memory device (VM) 1230 , a nonvolatile memory device (NVM) 1240 , a user interface 1250 , and a power supply 1260 .

[0163] The application processor 1210 may execute applications such as a web browser, a game application, a video player, etc. The connection circuit 1220 may perform wired or wireless communication with an external device. The volatile memory device 1230 may store data processed by the application processor 1210, or may operate as a working memory. The non-volatile memory device 1240 may store a boot image for booting the mobile system 1200. The user interface 1250 may include at least one input device, such as a keyboard, a touch screen, etc., and at least one output device, such as a speaker, a display device, etc. The power supply 1260 may provide a power supply voltage to the mobile system 1200.

[0164] In some embodiments of the present inventive concept, the mobile system 1200 may further include a camera image processor (CIP) and / or a storage device such as a memory card, a solid state drive (SSD), a hard disk drive (HDD), a compact disc read-only memory (CD-ROM), etc.

[0165] The application processor 1210 and / or the volatile memory device 1230 may include an OTP memory device. As described above, the OTP memory device may include an isolation circuit, and the isolation circuit may cut off the read voltage and the program voltage supplied to the OTP cell array in the first test mode. Therefore, the OTP memory device may perform a test on the row decoder and the column decoder without being affected by the state of the OTP memory cell of the OTP cell array to accurately determine whether the row decoder and the column decoder have defects.

[0166] In an exemplary embodiment of the inventive concept, an OTP memory device and a method of testing the OTP memory device include an isolation circuit that cuts off a read voltage and a program voltage supplied to an OTP cell array in a first test mode, and thus performs a test on a row decoder and a column decoder without being affected by the state of an OTP memory cell of the OTP cell array. Therefore, the OTP memory device and the method of testing the OTP memory device can obtain accurate test results for the row decoder and the column decoder.

[0167] The inventive concept as described above can be applied to devices and systems that use OTP memory devices to store non-volatile data. For example, exemplary embodiments of the inventive concept can be applied to systems such as mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, video cameras, personal computers (PCs), server computers, workstations, laptop computers, digital televisions, set-top boxes, portable game consoles, etc.

[0168] While the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A one-time programmable (OTP) memory device, comprising: A cell array circuit, comprising an OTP cell array and a dummy cell block, wherein the OTP cell array comprises a plurality of OTP memory cells coupled to a plurality of bit lines, a plurality of read word lines and a plurality of voltage word lines, and the dummy cell block is coupled to the plurality of read word lines and the plurality of voltage word lines; a row decoder coupled to the dummy cell block and the OTP cell array through the plurality of read word lines and the plurality of voltage word lines; a column decoder coupled to the OTP cell array through the plurality of bit lines; a write sense circuit coupled to the column decoder; and a control circuit configured to control the cell array circuit, the row decoder, and the write sensing circuit based on a command and an address, The cell array circuit further includes an isolation circuit connected between the OTP cell array and the dummy cell block, wherein the isolation circuit is configured to cut off the first voltage and the second voltage transmitted from the row decoder to the OTP cell array in response to a control code in a first test mode, A first test is performed on the row decoder and the column decoder in the first test mode.

2. The OTP memory device according to claim 1 , wherein the isolation circuit comprises a plurality of unit isolation circuits, and each of the plurality of unit isolation circuits is coupled to a corresponding pair of the read word line and the voltage word line, A selected unit isolation circuit of the unit isolation circuit coupled to a selected read word line and a voltage word line pair selected by the row decoder is configured to discharge the first voltage and the second voltage to ground in response to the control code.

3. The OTP memory device according to claim 2, wherein a first unit isolation circuit of the plurality of unit isolation circuits comprises: a first p-channel metal oxide semiconductor (PMOS) transistor coupled to the row decoder at a first node of a first one of the read word lines and coupled to the OTP cell array at a second node of the first read word line; a first n-channel metal oxide semiconductor (NMOS) transistor coupled in parallel with the first PMOS transistor between a first node of the first read word line and a second node of the first read word line; a second NMOS transistor and a third NMOS transistor coupled in series between a second node of the first read word line and the ground; a second PMOS transistor coupled to the row decoder at a first node of a first voltage word line of the voltage word lines and coupled to the OTP cell array at a second node of the first voltage word line; and A fourth NMOS transistor and a fifth NMOS transistor are coupled in series between the second node of the first voltage word line and the ground.

4. The OTP memory device according to claim 3, wherein Each gate of the second NMOS transistor and the fourth NMOS transistor receives a power supply voltage, The row decoder is configured as: applying a first control code to a gate of the first PMOS transistor; applying a second control code to a gate of the first NMOS transistor; applying the first control code to the gate of the third NMOS transistor; applying a third control code to a gate of the second PMOS transistor; and A fourth control code is applied to the gate of the fifth NMOS transistor.

5. The OTP memory device according to claim 4, wherein in the first test mode: turning on the third NMOS transistor in response to the first control code to discharge the first voltage to the ground; and The fifth NMOS transistor is turned on in response to the fourth control code to discharge the second voltage to the ground.

6. The OTP memory device according to claim 1, further comprising: a voltage generator configured to generate a plurality of operating voltages under the control of the control circuit and to provide at least some of the operating voltages to the row decoder as the first voltage and the second voltage, The unit array circuit further comprises: a test bit line signal generator coupled to the dummy cell block and configured to generate a first test bit line signal and a second test bit line signal in response to a control signal in the first test mode; and a switch circuit configured to transmit the first test bit line signal and the second test bit line signal to the bit line in the first test mode, and The dummy cell block includes a plurality of unit dummy cells, and at least one of the plurality of unit dummy cells is coupled to a corresponding pair of the read word line and the voltage word line.

7. The OTP memory device according to claim 6, wherein in the first test mode, The write sensing circuit is configured to output a test result pattern to the control circuit in response to the first test bit line signal and the second test bit line signal, and The control circuit is configured to output a test result signal indicating whether the row decoder and the column decoder are defective based on a comparison of the test result pattern and an expected pattern.

8. The OTP memory device according to claim 6, wherein the plurality of single-bit dummy cells comprises: a first unit dummy cell set coupled to a first read word line and a voltage word line group of the read word line and the voltage word line and the test bit line signal generator; and a second unit dummy cell set coupled to a second read word line and voltage word line group of the read word line and the voltage word line and the test bit line signal generator, wherein at least one unit dummy cell in the first unit dummy cell set and at least one unit dummy cell in the second unit dummy cell set include a first transistor and a second transistor, the first transistor having a gate coupled to a corresponding read word line, and the second transistor having a gate coupled to a corresponding voltage word line, and A first terminal of the first transistor and a first terminal of the second transistor are coupled to each other.

9. The OTP memory device according to claim 8, wherein the test bit line signal generator comprises: a first inverter including an input terminal for receiving a programming control signal and an output terminal coupled to a second terminal of a second transistor of the at least one unit dummy cell in the first unit dummy cell set and coupled to a second terminal of a second transistor of the at least one unit dummy cell in the second unit dummy cell set; a second inverter including an input for receiving the first test enable signal and an output coupled to the first node; a third inverter including an input terminal coupled to the first node and an output terminal coupled at a second node to a second terminal of a first transistor of the at least one unit dummy cell in the first set of unit dummy cells; a fourth inverter comprising an input terminal coupled to the second node and an output terminal for providing the first test bit line signal; a fifth inverter including an input terminal coupled to the first node and an output terminal coupled at a third node to a second terminal of a first transistor of the at least one unit dummy cell in the second set of unit dummy cells; and A sixth inverter includes an input terminal coupled to the third node and an output terminal for providing the second test bit line signal.

10. The OTP memory device according to claim 9, wherein if a first read word line and voltage word line pair is selected in the first read word line and voltage word line group, a first current path from the second node to the first inverter is formed through a first unit dummy cell included in a first unit dummy cell set coupled to the first read word line and voltage word line pair, and If a second read word line and voltage word line pair is selected in the second read word line and voltage word line group, a second current path from the third node to the first inverter is formed through a second unit dummy cell included in the second unit dummy cell set coupled to the second read word line and voltage word line pair.

11. The OTP memory device according to claim 6, wherein the switch circuit comprises a plurality of switches configured to transmit the first test bit line signal and the second test bit line signal to the bit line in response to a first test enable signal, and The bit lines include a first bit line group and a second bit line group, the first bit line group corresponds to odd-numbered bit lines among the bit lines, and the second bit line group corresponds to even-numbered bit lines among the bit lines. 12 . The OTP memory device of claim 11 , wherein the plurality of switches are configured to transmit the first test bit line signal to the first bit line group and transmit the second test bit line signal to the second bit line group. 13 . The OTP memory device of claim 11 , wherein the plurality of switches are configured to transmit the first test bit line signal to the second bit line group and transmit the second test bit line signal to the first bit line group.

14. The OTP memory device of claim 1 , wherein the row decoder comprises a control code generator, wherein the control code generator is configured to generate a plurality of control codes to be provided to the isolation circuit based on a row address and a first test enable signal in the first test mode, and The row address specifies a corresponding pair of the read word line and the voltage word line.

15. The OTP memory device according to claim 1, wherein the cell array circuit further comprises: a test cell array including a first test row and a second test row, the first test row having unprogrammed first test cells and the second test row including mask-programmed second test cells, wherein the test cell array shares a bit line with the OTP cell array, The first test unit and the second test unit are accessible during testing of the OTP cell array.

16. The OTP memory device according to claim 15, wherein the first test cell has the same structure as the OTP memory cell, wherein the second test cell is mask programmed to a state corresponding to the programmed OTP memory cell, If the control circuit determines that the row decoder and the column decoder are not defective in the first test mode, the control circuit is configured to perform a second test on the OTP cell array in a second test mode by performing a read operation on the first test cell and by performing a program operation on the second test cell.

17. A method for testing a one-time programmable (OTP) memory device, wherein the OTP memory device comprises an OTP cell array, a dummy cell block and an isolation circuit, the OTP cell array comprising a plurality of OTP memory cells coupled to a plurality of bit lines, a plurality of read word lines and a plurality of voltage word lines, the dummy cell block being coupled to the plurality of read word lines and the plurality of voltage word lines, and the isolation circuit being coupled between the OTP cell array and the dummy cell block, the method comprising: In a first test mode, after the connection between the dummy cell block and the OTP cell array is cut off by the isolation circuit, a first test is performed on a row decoder and a column decoder, the row decoder being coupled to the plurality of read word lines and the plurality of voltage word lines, and the column decoder being coupled to the plurality of bit lines; If it is determined in the first test that the row decoder and the column decoder are not defective, performing a second test on the OTP cell array in a second test mode; and A determination is made based on a result of the second test whether the OTP memory device is defective.

18. The method of claim 17, wherein performing the first test comprises: selecting a pair of a read word line and a voltage word line among the read word line and the voltage word line; generating a first test bit line signal and a second test bit line signal by a test bit line signal generator coupled to the dummy cell block in response to a first test enable signal; applying the first test bit line signal and the second test bit line signal to the bit line; and Based on a comparison of a test result pattern output through the bit lines with an expected pattern, it is determined whether the row decoder and the column decoder are defective.

19. A one-time programmable (OTP) memory device, comprising: A cell array circuit, comprising an OTP cell array, an isolation circuit and a dummy cell block, wherein the OTP cell array comprises a plurality of OTP storage cells coupled to a plurality of bit lines, a plurality of first word lines and a plurality of second word lines, and the isolation circuit is connected between the OTP cell array and the dummy cell block; a row decoder coupled to the dummy cell block through the plurality of first word lines and the plurality of second word lines; a column decoder coupled to the OTP cell array through the plurality of bit lines; and a control circuit configured to control the cell array circuit and the row decoder, wherein the row decoder is configured to provide a control code to the isolation circuit, the control code instructing the isolation circuit to cut off the first voltage and the second voltage transmitted from the row decoder to the OTP cell array in a test mode, The row decoder and the column decoder are tested in the test mode.

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