Self-encapsulated laminated optoelectronic device and preparation method thereof

Abstract

The present application relates to the field of stacked optoelectronic devices, and more specifically, to a self-packaged stacked optoelectronic device, which includes buried-gate glass, a perovskite top cell, a silicon-based cell, and an encapsulation layer; the perovskite cell is deposited on the buried-gate glass with a top electrode; the perovskite cell is connected in series with a silicon-based cell of a different structure and then packaged to form a stacked optoelectronic device; the application also includes a preparation method thereof, which includes separately preparing a perovskite cell and a silicon-based cell; connecting the silicon-based cell and the perovskite cell through the front electrode of the silicon-based cell; compared with existing stacked optoelectronic devices, the present invention independently prepares two cells, connects the two cells in series through a metal electrode, avoids the influence of the interface and suede morphology of the top cell and the silicon-based cell, and simplifies the structure and preparation method.

Description

Technical Field

[0001] The present application relates to the technical field of laminated optoelectronic devices, and in particular to a self-encapsulated laminated optoelectronic device and a preparation method thereof. Background Art

[0002] Solar energy is a vast, clean, and efficient renewable energy source. Solar power generation technology is a key technology for addressing energy challenges. Perovskite solar cells are currently a hot research topic due to their low cost, simple fabrication, and high photoelectric conversion efficiency. Silicon solar cells have also made significant progress due to their low manufacturing temperatures, simple process flow, high open-circuit voltage, high conversion efficiency, low temperature coefficient, excellent high-temperature / low-light power generation characteristics, and low attenuation.

[0003] The energy distribution of the solar spectrum is relatively broad, and a solar cell device can only absorb a portion of this energy. The remaining energy cannot be utilized and is released as heat, resulting in relatively low photoelectric conversion efficiency for single-junction solar cells. Because the perovskite material of perovskite cells has a high bandgap, while the bandgap of silicon is relatively narrow, the perovskite cell is used as the first light-absorbing layer to absorb short-wavelength light, such as violet light, while long-wavelength light, such as red light, passes through the perovskite layer and is absorbed by the underlying silicon-based cell. This maximizes the conversion of solar energy into electrical energy and improves the conversion efficiency of solar cells.

[0004] The combination of perovskite cells and silicon-based cells can theoretically effectively improve the photoelectric conversion efficiency. Current stacked optoelectronic devices use perovskite cells prepared on silicon-based cells. Since the surface of silicon-based cells has an uneven velvet surface, if perovskite cells are prepared directly on its surface, first, each layer of the perovskite cell cannot be made very flat, and may even damage the perovskite layer, resulting in serious short-circuit current loss, which is not conducive to improving the photoelectric conversion efficiency of the stacked device; second, the short-circuit current of the perovskite cell and the silicon-based cell under the same light-receiving area does not match, resulting in low photoelectric conversion efficiency of the stacked device. There are difficulties in matching the current by adjusting the light-receiving area. For example, if the surface of the silicon-based cell is made into a smooth plane, the silicon-based cell does not have the light-trapping effect of the velvet, and the photoelectric conversion efficiency cannot be maximized. Therefore, the interface contact problem between the perovskite cell and the silicon-based cell in the stacked device has become the most difficult problem to overcome in the stacked device; third, the existing perovskite cell uses a method of depositing a functional layer on glass and peeling off part of the functional layer to make anode and cathode electrodes, resulting in poor fit at the connection, and ordinary anode and cathode electrodes are not conducive to collecting charges.

[0005] Therefore, the present invention proposes a self-encapsulated laminated optoelectronic device and a preparation method thereof to solve the above problems. Summary of the Invention

[0006] The purpose of the embodiments of the present application is to provide a self-packaged laminated optoelectronic device and a method for preparing the same to solve the above-mentioned problems.

[0007] In a first aspect, an embodiment of the present application provides a self-packaged laminated optoelectronic device, comprising:

[0008] The buried glass, perovskite cell, silicon-based cell and packaging layer are connected from top to bottom, a top electrode is arranged in the groove of the buried glass, a perovskite cell is arranged on the top electrode, the silicon-based cell is connected to the perovskite cell via the front electrode of the silicon-based cell, the back electrode of the silicon-based cell forms a current loop with the top electrode in the buried glass, and the back electrode of the silicon-based cell is bonded to the packaging layer.

[0009] Preferably, the silicon-based cell includes a PERC cell, a heterojunction cell, or an N-type PERT cell.

[0010] Preferably, the perovskite cell includes a first transparent conductive layer, a hole transport layer, a perovskite light absorption layer, an electron transport layer and a second transparent conductive layer arranged from top to bottom, and the second transparent conductive layer is connected to the front electrode of the silicon-based cell.

[0011] Preferably, the perovskite cell includes a first transparent conductive layer, an electron transport layer, a perovskite light absorbing layer, a hole transport layer and a second transparent conductive layer arranged from top to bottom, and the second transparent conductive layer is connected to the front electrode of the silicon-based cell.

[0012] Preferably, the top electrode, the front electrode of the silicon-based battery and the back electrode of the silicon-based battery are made of one or more of aluminum, silver, gold, titanium, bismuth, tin, palladium, nickel, chromium and copper, with a thickness of 1-2000 μm.

[0013] Preferably, the top electrode includes n main grid lines and m auxiliary grid lines that intersect vertically; n is 1-20; and m is in the range of 1-100.

[0014] Preferably, the top electrode has a depth ranging from 1 to 2000 μm, the main grid lines and the auxiliary grid lines have lengths equal to the buried grid glass, the main grid lines have a width ranging from 10 to 1000 μm, and the auxiliary grid lines have a width ranging from 10 to 500 μm.

[0015] Preferably, the ratio of the light-shielding area of the front electrode of the silicon-based cell to the light-shielding area of the top electrode of the perovskite cell is in the range of 0.5-2.

[0016] A method for preparing a self-encapsulated laminated optoelectronic device comprises the following steps:

[0017] Make perovskite cells and silicon-based cells respectively;

[0018] Connecting the front electrode of the silicon-based cell to the perovskite cell;

[0019] The connected perovskite cell is packaged with the silicon-based cell to obtain a stacked photovoltaic device.

[0020] Preferably, the manufacturing of the perovskite battery comprises the following steps:

[0021] preparing grooves on the buried gate glass, the grooves including main grooves and auxiliary grooves;

[0022] preparing a top electrode in the trench, wherein the top electrode includes a main gate line and a secondary gate line;

[0023] A first transparent conductive layer, a hole transport layer, a perovskite light absorbing layer, an electron transport layer, and a second transparent conductive layer are sequentially prepared on a buried gate glass having a top electrode, or a first transparent conductive layer, an electron transport layer, a perovskite light absorbing layer, a hole transport layer, and a second transparent conductive layer are sequentially prepared to obtain a perovskite cell;

[0024] The front electrode of the silicon-based cell is connected to the second transparent conductive layer of the perovskite cell.

[0025] This application has the following technical effects:

[0026] 1. The separately manufactured perovskite cell and silicon-based cell are connected by metal electrodes. The perovskite cell and the silicon-based cell have no direct contact, thus avoiding damage to the perovskite cell caused by the velvet surface of the silicon-based cell, thereby improving the photoelectric conversion efficiency. Since the perovskite cell and the silicon-based cell are prepared separately, the perovskite cell and the silicon-based cell with matching light-receiving areas can be selected to achieve current matching. Therefore, the stacked photovoltaic device avoids the problem of the velvet surface of the existing perovskite cell prepared on the silicon-based cell affecting the photoelectric conversion efficiency of the stacked photovoltaic device and the current matching problem of the two cells. At the same time, the current-matched perovskite cell and the silicon-based cell are directly stacked and connected in series through the metal electrodes, which is conducive to simplifying the structure of the stacked photovoltaic device.

[0027] 2. By grooving the buried gate glass to prepare the top electrode, the functional layer of the perovskite cell can be conveniently prepared on the top electrode, and the current can be drawn out, which is conducive to the bonding of the buried gate glass and the functional layer of the perovskite cell. The buried gate top electrode adopts the main and auxiliary gate line design, which is conducive to collecting charges on the entire device surface.

[0028] 3. The separately manufactured perovskite cell and silicon-based cell are connected through metal electrodes, where carriers recombine, effectively reducing heat loss.

[0029] 4. Since perovskite cells and silicon-based cells are prepared separately, silicon-based cells and perovskite cells with different structures can be easily superimposed according to needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 Schematic diagram of the structure of the stacked optoelectronic device of this application Figure 1 .

[0032] Figure 2 This is a schematic structural diagram of the buried grid glass in this application.

[0033] Figure 3 Schematic diagram of the structure of the stacked optoelectronic device of this application Figure 2 .

[0034] Reference numerals:

[0035] 101-Buried gate glass, 102-Top electrode, 103-Encapsulation layer, 110-Inverted perovskite cell, 120-Silicon-based heterojunction cell, 111-First transparent conductive layer, 112-Hole transport layer, 113-Perovskite light absorption layer, 114-Electron transport layer, 115-Second transparent conductive layer, 121-Front electrode of silicon-based cell, 122-First oxidized transparent conductive layer, 123-P-type hydrogenated amorphous silicon layer, 124 -First intrinsic type hydrogenated amorphous silicon layer, 125-n-type silicon substrate, 126-n-type hydrogenated amorphous silicon layer, 127-second intrinsic type hydrogenated amorphous silicon layer, 128-second oxide transparent conductive layer, 129-back electrode of silicon-based cell, 210-upright perovskite cell, 220-PERC cell, 222-antireflection layer, 223-n+ emitter, 224-p-type silicon substrate, 225-passivation layer, 226-aluminum back field. DETAILED DESCRIPTION

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings. In addition, it should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0037] In order to solve the problem that the uneven surface of silicon-based cells affects the performance of perovskite cells in the existing stacked photovoltaic devices,

[0038] A self-encapsulated laminated photovoltaic device includes: a buried glass 101, a perovskite cell, a silicon-based cell and an encapsulation layer 103 connected from top to bottom, a top electrode 102 is arranged in the groove of the buried glass 101, a perovskite cell is prepared on the top electrode 102, the perovskite cell is connected to the silicon-based cell through the front electrode 121 of the silicon-based cell, the back electrode 129 of the silicon-based cell forms a current loop with the top electrode 102 in the buried glass 101, and the back electrode 129 of the silicon-based cell is bonded to the encapsulation layer 103.

[0039] The separately manufactured perovskite cell and silicon-based cell are connected by metal electrodes. There is no direct contact between the perovskite cell and the silicon-based cell, which avoids the damage caused by the velvet surface of the silicon-based cell to the perovskite cell and improves the photoelectric conversion efficiency.

[0040] Example 1

[0041] like Figure 1 As shown, a self-encapsulated laminated photovoltaic device includes: a buried glass 101, a perovskite cell, a silicon-based cell and an encapsulation layer 103 connected from top to bottom, a top electrode 102 is set in the groove of the buried glass 101, a perovskite cell is prepared on the top electrode 102, the perovskite cell is connected to the silicon-based cell through the front electrode 121 of the silicon-based cell, the back electrode 129 of the silicon-based cell forms a current loop with the top electrode 102 in the buried glass 101, and the back electrode 129 of the silicon-based cell is bonded to the encapsulation layer 103.

[0042] The perovskite cell achieves current conduction through the top electrode 102 in the buried glass 101 groove. The perovskite cell is connected to the silicon-based cell through the front electrode 121 of the silicon-based cell. The back electrode 129 of the silicon-based cell and the top electrode 102 in the buried glass 101 constitute a current loop of the stacked device.

[0043] The perovskite cell adopts an inverted perovskite cell 110, which includes a first transparent conductive layer 111, a hole transport layer 112, a perovskite light absorption layer 113, an electron transport layer 114 and a second transparent conductive layer 115 arranged from top to bottom, and the second transparent conductive layer 115 is connected to the front electrode 121 of the silicon-based cell.

[0044] The silicon-based cell adopts a heterojunction cell, such as a silicon-based heterojunction cell 120, which includes a front electrode 121 of the silicon-based cell, a first transparent conductive oxide layer 122, a p-type hydrogenated amorphous silicon layer 123, a first intrinsic hydrogenated amorphous silicon layer 124, an n-type silicon substrate 125, a second intrinsic hydrogenated amorphous silicon layer 127, an n-type hydrogenated amorphous silicon layer 126, a second transparent conductive oxide layer 128, and a back electrode 129 of the silicon-based cell.

[0045] The second transparent conductive layer 115 is connected to the front electrode 121 of the silicon-based battery, so that the perovskite battery and the silicon-based battery are connected in series; the silicon-based battery is connected to the encapsulation layer 103 through the back electrode 129 of the silicon-based battery, and the connection includes bonding; the material of the electrode is one or more of aluminum, silver, gold, titanium, bismuth, tin, palladium, nickel, chromium, and copper, with a thickness of 1-2000μm; silver is used in this embodiment.

[0046] In this embodiment, the silicon-based cell is connected to the second transparent conductive layer 115 of the perovskite cell through the front electrode 121 of the silicon-based cell, so that the structure of the stacked optoelectronic device is simpler, and the interface defects caused by direct contact between the perovskite cell and the silicon-based cell are avoided. The separately manufactured perovskite cell and the silicon-based cell are connected through metal electrodes, and the carriers are recombined at the metal electrodes, which effectively reduces heat loss, improves the open circuit voltage and fill factor of the cell, and further reduces the preparation steps and saves production costs.

[0047] Example 2

[0048] The silicon-based cell includes a PERC cell 220 or a heterojunction cell or an N-type PERT cell. The difference between this embodiment and embodiment 1 is that the silicon-based cell is different, such as Figure 3 As shown, this embodiment adopts a PERC cell 220, and the corresponding perovskite cell adopts an upright perovskite cell 210. The perovskite cell includes a first transparent conductive layer 111, an electron transport layer 114, a perovskite light absorption layer 113, a hole transport layer 112, and a second transparent conductive layer 115 arranged from top to bottom. The second transparent conductive layer 115 is connected to the front electrode of the silicon-based cell;

[0049] The silicon-based cell includes a front electrode 121 of the silicon-based cell, an anti-reflection layer 222, an n+ emitter 223, a p-type silicon substrate 224, a passivation layer 225 and an aluminum back surface field 226;

[0050] The second transparent conductive layer 115 is connected to the front electrode 121 of the silicon-based battery, so that the perovskite battery and the silicon-based battery are connected in series; the silicon-based battery is connected to the encapsulation layer 103 through the aluminum back surface field 226; the material of the electrode is one or more of aluminum, silver, gold, titanium, bismuth, tin, palladium, nickel, chromium, and copper, with a thickness of 1-2000 μm; aluminum is selected in this embodiment.

[0051] Example 3

[0052] like Figure 1 、 2As shown in Figures 3 and 3, the difference between this embodiment and embodiment 1 or 2 is that the buried gate glass 101 and the perovskite cell are connected through a top electrode 102, the buried gate glass 101 is provided with a groove, the top electrode 102 is provided in the groove, and the top electrode 102 includes n main grid lines and m auxiliary grid lines that intersect vertically.

[0053] The depth of the top electrode 102 is in the range of 1-2000 μm, the lengths of the main grid lines and the auxiliary grid lines are equal to those of the buried grid glass 101, the width of the main grid lines is in the range of 100-1000 μm, and the width of the auxiliary grid lines is in the range of 50-500 μm; n is 1 to 20; and m is in the range of 1-100.

[0054] like Figure 2 As shown, in this embodiment, there are 2 main grid lines and 8 auxiliary grid lines;

[0055] To overcome the existing perovskite cell problem of first making the functional layer and then the anode and cathode, which requires peeling off a portion of the functional layer surface before connecting the anode and cathode, resulting in an uneven contact surface and material waste, the top electrode 102 is prepared by grooving the buried gate glass 101. The functional layer of the perovskite cell can be conveniently prepared on the buried gate top electrode 102, and current is drawn out, which is conducive to the bonding of the buried gate glass 101 and the perovskite cell functional layer. The buried gate top electrode 102 adopts a main and secondary grid line design, which is conducive to collecting charges on the entire device surface and further improving the photoelectric conversion efficiency. On the buried gate glass 101 with the top electrode 102 already made, the solution corresponding to the perovskite cell is spin-coated or sprayed on it, and the perovskite cell naturally adheres to the top electrode 102. Considering the light-receiving area, the light-receiving area needs to be guaranteed, so the number of main grid lines and secondary grid lines needs to be limited.

[0056] Example 4

[0057] The difference between this embodiment and embodiment 1, 2 or 3 is that there is a proportional limit on the ratio of the shading area of the front electrode 121 of the silicon-based battery to the shading area of the top electrode 102 of the perovskite battery. The short-circuit current of the perovskite battery and the silicon-based battery under the same light-receiving area do not match. Specifically, due to the properties of the perovskite device and the silicon-based device themselves, when tested separately under the same area and light, the short-circuit current of the perovskite device is lower than that of the silicon-based battery. For example, the current of the perovskite is 24mA / cm2, and that of the silicon-based battery can reach 38mA / cm2. Electrically speaking, when two power sources are connected in series, the current value depends on the smaller value, then the performance of the silicon-based battery cannot be fully utilized, and the battery life is reduced. If a stacked device is made, the perovskite cell will absorb some light, and the silicon-based cell will receive less light, and the short-circuit current will be lower. Therefore, in order to match the currents of the two, the shading area of the front electrode 121 of the silicon-based cell can be adjusted until it is consistent with the short-circuit current of the perovskite. For example, the ratio of the shading area of the front electrode 121 of the silicon-based cell to the shading area of the top electrode 102 of the perovskite cell is 0.5, 2, or 1.5. The currents of the two cells can be matched according to the above ratio.

[0058] Based on the above-mentioned stacked optoelectronic device, the present application provides a method for preparing the stacked optoelectronic device, which is specifically as follows:

[0059] A method for preparing a self-encapsulated laminated optoelectronic device comprises the following steps:

[0060] Make perovskite cells and silicon-based cells respectively;

[0061] Connecting the silicon-based cell and the perovskite cell via the front electrode 121 of the silicon-based cell;

[0062] The connected perovskite cell is packaged with the silicon-based cell to obtain a stacked photovoltaic device.

[0063] The manufacturing of the perovskite battery comprises the following steps:

[0064] Forming grooves on the buried gate glass 101, the grooves including main grooves and auxiliary grooves;

[0065] A top electrode 102 is formed in the groove, wherein the top electrode 102 includes a main gate line and a secondary gate line;

[0066] A first transparent conductive layer 111 , a hole transport layer 112 , a perovskite light absorption layer 113 , an electron transport layer 114 and a second transparent conductive layer 115 are sequentially formed on the buried gate glass 101 having the top electrode 102 .

[0067] Among them, the materials of the first transparent conductive layer 111 and the second transparent conductive layer 115 are selected from one or more of ITO, IZO, AZO, graphene, including but not limited to metal nanowires of Ag, Au, Cu or Al, and the thickness is 0 - 500 nm. The transparent conductive layer is fabricated by magnetron sputtering, reactive plasma deposition (RPD) or chemical vapor deposition, and the chemical vapor deposition method is selected from plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD) or metal organic chemical vapor deposition (MOCVD).

[0068] The material of the perovskite light absorbing layer 113 can be FA1-xCsxPb3 (where 0.l < x < 0.3) or FA1-xMAxPb3 (where 0.05 ≤ x ≤ 0.5). The preparation method of the perovskite light absorbing layer 113 is spin coating.

[0069] The material of the hole transport layer 112 is one or more of PTAA, NiOx, P3HT, V2O5, MoOx, PEDOT:PSS, WOx, Sprio-OMeTAD, CuSCN, Cu2O, CuI, Spiro-TTB, m-MTDATA or TAPC, and the thickness is 0 - 200 nm. The preparation method of the hole transport layer 112 is spin coating or sputtering.

[0070] The material of the electron transport layer 114 is one or more of SnO2, TiO2, ZnO, ZrO2, fullerene and derivatives (C60, C70, PCBM), TiSnOx or SnZnOx, and the thickness is 0 - 500 nm. The preparation method of the electron transport layer 114 is spin coating or sputtering.

[0071] The trenches of the buried grid glass 101 are prepared by emery grinding, laser etching or chemical etching, and the depth is 1 - 2000 μm. The pattern of the trenches is 1 - 20 main lines and 1 - 100 sub-lines.

[0072] The top electrode 102 is a grid line electrode, and the electrode height is 2 - 2000 μm. The length of the main grid line electrode is the same as the side length of the buried grid glass 101, the width is 100 - 1000 μm, and the number is 1 - 20. The length of the sub-grid line is the same as the side length of the buried grid glass 101, the width is 50 - 500 μm, and the number is 1 - 100. The position of the top electrode 102 is in the trenches of the buried grid glass 101. The top electrode 102 is deposited into the trenches of the buried grid glass 101 by one or more of screen printing, inkjet printing, steel plate printing, micro-nano metal imprinting methods to form a buried grid electrode.

[0073] The preparation of the silicon-based battery includes the following steps:

[0074] Depositing a first intrinsic type hydrogenated amorphous silicon layer 124 and a second intrinsic type hydrogenated amorphous silicon layer 127 on both sides of the silicon wafer respectively;

[0075] Depositing a p-type hydrogenated amorphous silicon layer 123 on the first intrinsic hydrogenated amorphous silicon layer 124 and depositing an n-type hydrogenated amorphous silicon layer 126 on the second intrinsic hydrogenated amorphous silicon layer 127;

[0076] Depositing a first transparent conductive oxide layer 122 and a second transparent conductive oxide layer 128 on the p-type hydrogenated amorphous silicon layer 123 and the n-type hydrogenated amorphous silicon layer 126 respectively;

[0077] The front electrode 121 of the silicon-based battery is deposited on the first transparent conductive oxide layer 122, and the back electrode 129 of the silicon-based battery is deposited on the second transparent conductive oxide layer 128. There are three methods for preparing the front electrode 121 of the silicon-based battery and the back electrode 129 of the silicon-based battery, namely screen printing, inkjet printing or electroplating.

[0078] The first transparent conductive oxide layer 122 is made of one or more of ITO, IZO, and AZO, and has a thickness of 10-200 nm.

[0079] The thickness of the p-type hydrogenated amorphous silicon layer 123 and the n-type hydrogenated amorphous silicon layer 126 is 2-200 nm;

[0080] The thickness of the first intrinsic type hydrogenated amorphous silicon layer 124 and the second intrinsic type hydrogenated amorphous silicon layer 127-126 is 2-50 nm.

[0081] The thickness of the n-type silicon substrate 125 is 150-250 μm.

[0082] The first intrinsic type hydrogenated amorphous silicon layer 124 , the second intrinsic type hydrogenated amorphous silicon layer 127 , the p-type hydrogenated amorphous silicon layer 123 and the n-type hydrogenated amorphous silicon layer 126 are formed by plasma enhanced chemical vapor deposition (PECVD).

[0083] The following examples are provided according to the above preparation method, which are as follows:

[0084] Example 5

[0085] The method for preparing a stacked photovoltaic device comprises the following steps:

[0086] The preparation of silicon-based batteries includes the following steps:

[0087] Step 1: Plasma-enhanced chemical vapor deposition (PECVD) is used to deposit a layer of intrinsic hydrogenated amorphous silicon (10 nm) and 8 nm thick on each surface of the cleaned and textured n-type silicon wafer.

[0088] Step 2: Then, a 10 nm thick n-type hydrogenated amorphous silicon layer 127 is deposited on the 8 nm thick second hydrogenated amorphous silicon layer, and a 15 nm thick p-type hydrogenated amorphous silicon layer 123 is deposited on the 10 nm thick hydrogenated intrinsic amorphous silicon layer.

[0089] Step 3: forming a first transparent conductive oxide layer 122 and a second transparent conductive oxide layer 128 on the back side of the n-type hydrogenated amorphous silicon layer 126 and the p-type hydrogenated amorphous silicon layer 123 by magnetron sputtering. The material is indium tin oxide (ITO) with a thickness of 120 nm.

[0090] Step 4: Prepare the front electrode 121 of the silicon-based battery and the back electrode 129 of the silicon-based battery by screen printing on the oxidized transparent conductive layer, with a thickness of 50 μm;

[0091] The preparation of perovskite cells includes the following steps:

[0092] Step 1: Prepare gate line grooves on the cleaned buried gate glass 101 by laser grooving, including two main gate line grooves with a width of 100 μm and a depth of 50 μm, and eight auxiliary gate line grooves with a width of 20 μm and a depth of 50 μm;

[0093] Step 2: Prepare a top electrode 102 in the groove of the buried gate glass 101. The electrode material is Ag and the preparation method is magnetron sputtering.

[0094] Step 3: a transparent conductive layer is prepared on the buried gate glass substrate 101 with the top electrode 102. The material is indium tin oxide (ITO). The deposition method is physical vapor deposition. The deposited film thickness is 80 nm.

[0095] Step 4: Prepare a hole transport layer 112 on the prepared transparent conductive layer. The material is spiro-OMeTAD. The preparation method is spin coating. The annealing temperature is 120° C. and the thickness is 80 nm.

[0096] Step 5: Prepare a perovskite light absorbing layer 113 on the prepared hole transport layer 112. The light absorbing layer material is FA0.9MA0.1Pb3, the deposition method is spin coating, the spin coating raw materials are sulfonated formamidine (FAI), methylamine (MAI), and PbI2, the annealing temperature is 80°C, and the thickness of the perovskite absorption layer is 400nm;

[0097] Step 6: Prepare an electron transport layer 114 on the prepared perovskite light absorbing layer 113. The material is tin dioxide SnO2. The preparation method is spin coating. The annealing temperature is 100°C and the film thickness is 50nm.

[0098] Step 7: A transparent conductive layer is prepared on the prepared electron transport layer 114. The material is indium tin oxide (ITO). The deposition method is physical vapor deposition. The deposited film thickness is 80 nm.

[0099] Connection and packaging of silicon-based cells and perovskite cells:

[0100] Step 1: Connecting the front electrode 121 of the silicon-based heterojunction cell 120 to the transparent conductive layer of the perovskite cell to complete the device stacking;

[0101] Step 2: Encapsulate the stacked optoelectronic device through the bottom encapsulation layer 103; the encapsulation layer 103 is made of glass.

[0102] The present invention independently prepares two batteries and connects the two batteries in series through metal electrodes, thereby avoiding the influence of the interface and suede morphology of the top battery and the silicon-based battery, and simplifying the structure and preparation method.

[0103] Example 6

[0104] This embodiment differs from Example 5 in that the silicon-based cell in this embodiment uses a PERC cell 220, and the perovskite cell has an upright structure. Therefore, the materials and preparation methods for each layer of the perovskite cell are exactly the same as those in Example 5. The functional layers are prepared in the following order: first transparent conductive layer 111, electron transport layer 114, perovskite light absorbing layer 113, hole transport layer 112, and second transparent conductive layer 115. The preparation order is reversed, allowing light to enter from the electron transport layer 114 side.

[0105] The silicon-based cell includes a front electrode 121 of the silicon-based cell, an anti-reflection layer 222 , an n+ emitter 223 , a p-type silicon substrate 224 , a passivation layer 225 and an aluminum back surface field 226 .

[0106] The thickness of the p-type silicon substrate 224 is 150-250 μm.

[0107] The thickness of the anti-reflection layer 222 and the n+ emitter 223 is 2-200 nm.

[0108] The thickness of the aluminum back surface field 226 is 2-2000 μm.

[0109] The preparation of the P-type silicon cell can adopt methods known to those skilled in the art, which will not be described in detail here.

[0110] In summary: the present invention independently prepares two batteries and connects the two batteries in series through metal electrodes, thereby avoiding the influence of the interface and suede morphology of the top battery and the silicon-based battery, and simplifying the structure and preparation method.

[0111] In the above-mentioned several embodiments provided in the present application, it should be understood that the disclosed structures and methods can also be implemented in other ways. The structural embodiments described above are merely illustrative; it should also be noted that in some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. The above description is only an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, the present application can have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

[0112] In addition, it should be noted that, in this document, relational terms such as "first," "second," "third," etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include," "comprise," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

Claims

1. A self-packaged laminated optoelectronic device, characterized in that: include: A buried grid glass (101), a perovskite cell, a silicon-based cell and an encapsulation layer (103) connected from top to bottom, a top electrode (102) being provided in a groove of the buried grid glass (101), a perovskite cell being provided on the top electrode (102), the silicon-based cell being connected to the perovskite cell via a front electrode (121) of the silicon-based cell, a back electrode (129) of the silicon-based cell forming a current loop with the top electrode (102) in the buried grid glass (101), and the back electrode (129) of the silicon-based cell being bonded to the encapsulation layer (103); The ratio of the light-shielding area of the front electrode (121) of the silicon-based cell to the light-shielding area of the top electrode (102) of the perovskite cell is in the range of 0.5-2, so that the short-circuit current of the perovskite cell is consistent with the short-circuit current of the silicon-based cell; The perovskite battery and silicon-based battery are separately prepared perovskite batteries and silicon-based batteries.

2. The self-encapsulated laminated optoelectronic device according to claim 1, characterized in that: The silicon-based cell includes a PERC cell (220) or a heterojunction cell or an N-type PERT cell.

3. The self-packaged laminated optoelectronic device according to claim 1, characterized in that: The perovskite cell comprises a first transparent conductive layer (111), a hole transport layer (112), a perovskite light absorption layer (113), an electron transport layer (114), and a second transparent conductive layer (115) arranged from top to bottom, wherein the second transparent conductive layer (115) is connected to the front electrode (121) of the silicon-based cell.

4. The self-packaged laminated optoelectronic device according to claim 1, characterized in that: The perovskite cell comprises a first transparent conductive layer (111), an electron transport layer (114), a perovskite light absorption layer (113), a hole transport layer (112), and a second transparent conductive layer (115) arranged from top to bottom, wherein the second transparent conductive layer (115) is connected to the front electrode (121) of the silicon-based cell.

5. The self-packaged laminated optoelectronic device according to claim 1, characterized in that: The top electrode (102), the front electrode (121) of the silicon-based battery and the back electrode (129) of the silicon-based battery are made of one or more of aluminum, silver, gold, titanium, bismuth, tin, palladium, nickel, chromium and copper, and have a thickness of 1-2000 μm.

6. The self-packaged laminated optoelectronic device according to claim 1, characterized in that: The top electrode (102) comprises n main grid lines and m auxiliary grid lines that intersect vertically; n is 1-20; and m has a value range of 1-100.

7. The self-packaged laminated optoelectronic device according to claim 6, characterized in that: The top electrode (102) has a depth range of 1-2000 μm, the main grid line and the auxiliary grid line have lengths equal to those of the buried grid glass (101), the main grid line has a width range of 10-1000 μm, and the auxiliary grid line has a width range of 10-500 μm.

8. A method for preparing a self-encapsulated laminated optoelectronic device according to any one of claims 1 to 7, characterized in that: The method comprises the following steps: separately manufacturing a perovskite battery and a silicon-based battery; Connecting the front electrode (121) of the silicon-based cell to the perovskite cell; The connected perovskite cell is packaged with the silicon-based cell to obtain a stacked photovoltaic device.

9. The method for preparing a self-encapsulated laminated optoelectronic device according to claim 8, characterized in that: The manufacturing of the perovskite battery comprises the following steps: preparing grooves on the buried gate glass (101), the grooves comprising a main groove and a sub-groove; A top electrode (102) is prepared in the groove, wherein the top electrode (102) comprises a main grid line and a secondary grid line; A first transparent conductive layer (111), a hole transport layer (112), a perovskite light absorbing layer (113), an electron transport layer (114), and a second transparent conductive layer (115) are sequentially prepared on a buried grid glass (101) having a top electrode (102), or a first transparent conductive layer (111), an electron transport layer (114), a perovskite light absorbing layer (113), a hole transport layer (112), and a second transparent conductive layer (115) are sequentially prepared to obtain a perovskite cell; The front electrode (121) of the silicon-based cell is connected to the second transparent conductive layer (115) of the perovskite cell.

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