Memory

Abstract

The present invention discloses a memory, specifically, it includes: storage units with different performances, each storage unit is provided with a fixed threshold value VTH, and the VTH is represented by at least three binary numbers; a reading module, reading the current value of the storage unit, and obtaining the current threshold state of the storage unit; a first judgment module, judging whether the storage unit needs to be operated according to the threshold state; a second judgment module, enabled when the judgment result of the first judgment module is "yes", and used to judge the distance between the threshold state and VTH; an execution module, controlling the storage unit to perform corresponding operations according to the judgment results of the first judgment module and the second judgment module. The memory provided by the present invention adopts differentiated programming conditions for storage units with different performances during the process of rewriting storage data, so that the inconsistent differences in the external performance of storage units with inconsistent performances are reduced, thereby effectively improving the programming efficiency and reliability of the memory.

Description

Technical Field

[0001] The present invention relates to the field of memory and control technology thereof, and in particular to a memory capable of alleviating operation differences between storage units with different performances. Background Art

[0002] Solid-state memory is a special integrated circuit used for caching, data storage, and code storage. It has a wide range of uses in embedded and stand-alone applications. Currently, it mainly includes traditional flash memories such as non-volatile flash memory (NOR FLASH) and data storage flash memory (NAND FLASH), as well as resistive random access memory (RRAM), magnetic random access memory (MRAM) and phase change memory (PRAM).

[0003] With the reduction of process nodes, the increase of chip area, and the significant improvement of chip capacity, the chip yield faces huge challenges. There are thousands to billions of storage cells in today's chips. Due to the inconsistency of the process, there are performance differences between the various storage cells. One manifestation is that when rewriting data, the speed of each storage cell is different. When the same rewriting operation conditions are used, the state changes of each storage cell are also different. After repeated many times, the distribution between the various states will be more discrete, which is reflected in the decline of chip performance.

[0004] In general, the above-mentioned prior art has the following technical defects when storing data:

[0005] (1) Since the same initial conditions (including programming time T and programming voltage VG) are used in the traditional operation algorithm, this set of conditions has a relatively weak programming capability, resulting in poor effects on the slow cells in the first few programmings;

[0006] (2) In the traditional operation algorithm, the same conditions are applied to all data in a page, which will waste a lot of time for memory cells with inconsistent performance. Some fast cells complete programming early, but in the repeated programming and verification cycle, they still have to wait during the period, resulting in the weakening of chip performance. Summary of the invention

[0007] In view of this, the present invention discloses a memory to at least partially solve the above technical problems.

[0008] The present invention provides a memory, comprising:

[0009] Memory cells of different performances, each memory cell is provided with a fixed threshold value VTH, and the VTH is represented by at least three binary numbers;

[0010] A reading module reads the current value of the storage unit to obtain the current threshold state of the storage unit;

[0011] A first judgment module, judging whether the storage unit needs to be operated according to a threshold state;

[0012] The second judgment module is enabled when the judgment result of the first judgment module is "yes", and is used to judge the distance between the threshold state and VTH;

[0013] The execution module controls the storage unit to perform corresponding operations according to the judgment results of the first judgment module and the second judgment module.

[0014] Further, among others:

[0015] In some embodiments, the threshold state of the memory cell includes: "all 0"-"all 1" represented by at least three binary bits.

[0016] In some embodiments, the threshold state of the memory cell is the same as the binary number of VTH.

[0017] In some embodiments, the first determination module includes:

[0018] When the threshold state is less than VTH, the judgment result of the first judgment module is "yes", and the second judgment module is entered;

[0019] When the threshold state is greater than or equal to VTH, the judgment result of the first judgment module is "no", and the execution module is entered.

[0020] In some embodiments, the second determination module includes:

[0021] When the threshold state is "all 0", the threshold state is farthest from VTH;

[0022] When the threshold state is smaller than the maximum value of the VTH value, the threshold state is closest to VTH.

[0023] In some embodiments, the execution module includes:

[0024] When the execution module receives the instruction from the first judgment module, the execution module controls the storage unit to terminate the relevant operation;

[0025] When the execution module receives the instruction from the second determination module, the execution module controls the storage unit to continue the related operation.

[0026] Furthermore, in some embodiments, when the execution module receives the instruction from the second determination module, it further includes:

[0027] The execution module uses operating conditions of different strengths to control the storage unit to continue related operations according to the distance between the threshold state and VTH obtained by the second judgment module, and when the distance between the threshold state and VTH gradually increases, the strength of the operating condition gradually weakens.

[0028] Furthermore, in some embodiments, the operating condition includes: a gate terminal voltage VG, and / or a drain terminal voltage VD, and / or an operating time T.

[0029] Furthermore, in some embodiments, the intensity control of the operating condition includes:

[0030] Enhanced gate voltage VG, and / or enhanced drain voltage VD, and / or increased operation time T to obtain enhanced operation conditions;

[0031] Weakening the gate terminal voltage VG, and / or weakening the drain terminal voltage VD, and / or reducing the operation time T obtains weakened operation conditions.

[0032] In some embodiments, the memory is a non-volatile flash memory, a data storage flash memory, a resistive random access memory, a magnetic memory and / or a phase change memory.

[0033] In other embodiments, the operation of the memory includes a programming operation and / or an erasing operation.

[0034] The memory provided by the present invention has the following beneficial effects:

[0035] (1) By adopting the solution of the present invention, differentiated programming conditions are adopted for storage cells with different performances during the storage data rewriting process, so that the inconsistency of the external performance of storage cells with inconsistent performances is reduced;

[0036] (2) Using a memory with the operating program of the present invention can reduce the time and number of repeated verifications, thereby speeding up programming;

[0037] (3) Using a memory with the operating program of the present invention can reduce the number of programming iterations and effectively improve chip reliability;

[0038] (4) The use of a memory having the operating program of the present invention can effectively save the power consumption required during the programming process. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1A-Figure 1C The operation method of the conventional memory;

[0040] Figure 2 is a structural block diagram of a memory in the present application provided by another embodiment of the present invention;

[0041] Figure 3 is based on Figure 2 Operation flow chart of the memory of the structure shown;

[0042] Figure 4A-4B The present invention is based on the improved memory operation process implementation. DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0044] In the traditional memory operation method, because the memory cells operated in parallel are usually in pages, the page capacity is very large, and considering the inconsistency of these memory cells, these operating conditions are usually selected conservatively, because the thresholds of some fast cells move quickly, while the thresholds of other slow cells move slowly. In the traditional operation method, data is read and verified immediately after programming. If the threshold value VTH has been exceeded, the current memory cell will be shielded from programming during the next programming, so that its threshold value will not be programmed too high. This is repeated many times to complete the programming of a whole page, such as Figure 1A However, on this basis, since some slow memory cells are still difficult to program even after repeated programming, it is necessary to change the operating voltage VG, such as increasing VG1 to VG2 or even VG3 (obviously VG3>VG2>VG1) before the next programming, which can increase the intensity of the next programming and make it easier to increase the threshold of the slow cell. Figure 1B Similarly, the programming time T1 can be modified to T2 or even T3 at the same time (it is obvious that T3>T2>T1), such as Figure 1C However, because the initial conditions used were the same, the first few programming times had very poor effects on the slow cells.

[0045] Therefore, the present invention provides a new memory that can reduce the operational differences between storage units with different performances, mainly by using the most suitable programming conditions for storage units with different performances, so as to achieve the purpose of improving programming ability. Specifically, in some embodiments, its structure and workflow are combined with reference to Figure 2 and Figure 3 ,include:

[0046] Step 1: A fixed threshold VTH is set for each memory cell with different performances, where the VTH is represented by at least three binary numbers.

[0047] Step 2: The reading module reads the current value of the storage unit to obtain the current threshold state of the storage unit;

[0048] In some embodiments, the threshold state of the memory cell includes: "all 0"-"all 1" represented by at least three binary digits, and the threshold state of the memory cell is the same as the binary digit number of VTH.

[0049] Step 3: The first judgment module judges whether the storage unit needs to be operated according to the threshold state, and the specific judgment method includes:

[0050] Step 3.1: When the threshold state is less than VTH, the judgment result of the first judgment module is "yes", and the second judgment module is entered to judge the distance between the threshold state and VTH;

[0051] Step 3.2: When the threshold state is greater than or equal to VTH, the judgment result of the first judgment module is "no", and the execution module is entered.

[0052] Wherein, step 3.1 further comprises:

[0053] Step 3.1.1: When the threshold state is "all 0", the threshold state is farthest from VTH;

[0054] Step 3.1.2: When the threshold state is less than the maximum value of the VTH value, the threshold state is closest to VTH.

[0055] Step 4: The execution module controls the storage unit to perform corresponding operations according to the judgment results of the first judgment module and the second judgment module, specifically including:

[0056] Step 4.1: When the execution module receives the instruction from the first judgment module, the execution module controls the storage unit to terminate the relevant operation;

[0057] Step 4.2: When the execution module receives the instruction from the second judgment module, the execution module controls the storage unit to continue the relevant operation.

[0058] Furthermore, in step 4.2, the execution module uses operating conditions of different strengths to control the storage unit to continue related operations according to the distance between the threshold state obtained by the second judgment module and VTH, and when the distance between the threshold state and VTH gradually increases, the strength of the operating conditions used gradually weakens.

[0059] In some embodiments, the operating conditions include: gate terminal voltage VG, and / or drain terminal voltage VD, and / or operating time T. Operating conditions of different intensities can be obtained by increasing or decreasing the intensity or size of the gate terminal voltage VG, and / or the drain terminal voltage VD, and / or the operating time T.

[0060] In particular, each operation has a set operation time, so each time the operation is performed, the above-mentioned process of step 1 to step 4 must be repeated until the operation is completed or the operation ends at step 4.1.

[0061] Based on the above-mentioned memory and its workflow, an embodiment of the present invention combines a specific memory device to describe the operation process in detail. The process is as follows:

[0062] In the traditional operation algorithm, after the first reading, a bit of data "1" or "0" will be obtained, and the conclusion drawn is whether the current storage unit needs to be programmed. For example, "0" means that programming is required. This information is obviously not enough. In this embodiment, the threshold VTH is represented by a multi-bit binary number. Taking NOR FLASH as an example, NOR FLASH realizes data distinction by changing the threshold voltage of the floating gate transistor. Assume that the initial threshold of the storage unit is VT1 (the same as the binary bit number of the threshold VTH), which is also the threshold of the erase state, representing that the data is "erasable". The threshold for distinguishing between "erasable" data and "non-erasable" data is VTH, that is, the threshold is greater than VTH for "erasable" data, and less than VTH for "non-erasable" data. Assume that the threshold of the programming state is VT2. Then the process of rewriting data is actually the process of moving the threshold from VT1 to VT2, or vice versa, the process of erasing data is the process of moving the threshold from VT2 to VT1. It should be noted here that VT1 and VT2 both represent a range. As long as they are distributed around VTH, data can be distinguished. The smaller the distribution of VT1 and VT2, the better the consistency of the data and the better the performance of repeated erasing and writing. During the NOR FLASH programming process, a high voltage VG is usually added to the gate end of the floating gate transistor and a high voltage VD is added to the drain end for a duration of T. After T, the threshold of the programmed storage cell is moved from the initial VT1 to VT3. This VT3 is usually between VT1 and VT2, that is, the erasure or programming of the data is completed. In particular, in this embodiment, combined with the fact that the storage cells for parallel operation are usually in units of large-capacity pages, and the inconsistency of each storage cell in terms of storage rate, when reading the initial threshold state of the storage cell (VT1 in this embodiment), the operating voltage VG, VD or the operating time T is changed to reduce the difference in storage efficiency between different storage cells from the beginning, and further avoid the defect of greater difference when repeated multiple times.

[0063] Based on the memory of the present invention, another embodiment of the present invention is combined with another specific memory device to further describe the novel memory and the operation method thereof provided by the present invention, and the process is as follows:

[0064] In this embodiment, the threshold VTH is represented by a three-bit binary number. When reading for the first time, the current value of the memory cell is read to obtain the current threshold state of the memory cell, which is represented by three-bit data, from "000", "001", "010" to "111", a total of eight states. Among them, "000" to "100" all represent the need for programming, but they represent the distance between the current threshold and VTH in turn, "000" is the farthest, and "100" is the closest. According to the difference shown by the threshold state, differentiated programming conditions are adopted. For example, there are two memory cells I and II. The initial state of I is "100", so this cell is relatively close to VTH, and relatively weak programming conditions, VG1 and T1, can be used to avoid using strong programming conditions and moving the threshold too high; the initial state of II is "000", so this cell is relatively far from VTH, and relatively strong programming conditions, a combination of VG2 and T1, can be used. Such a strong combination can quickly raise the threshold of II. After the first programming is completed, read verification is performed. If the read result of I is "110", it is closer to the programming state "111". Only relatively weak programming conditions are needed for weak programming to avoid over-programming, so the combination of VG1 and T1 is still used. If the read result of II is "100", it is still far from the programming state "111", and it is only after the first use of stronger programming conditions that it is programmed to this threshold range, proving that this storage unit is relatively slow. Continue to increase the programming intensity and use the combination of VG3 and T2. In this way, after two programmings, both I and II can be programmed to the "111" state. In this way, both cells are programmed twice. If the traditional method is used, I needs to be programmed twice, and II may be programmed more than three times or even more than once. It not only improves the programming efficiency, but also improves the programming consistency and saves a lot of power consumption. The specific programming method flow of this embodiment is as follows. Figure 4A-4B shown.

[0065] In addition, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and those skilled in the art can simply change or replace them, for example:

[0066] (1) The modified programming conditions may also include the drain voltage VD;

[0067] (2) The method in this paper can be applied to both writing “0” and writing “1” in new dual-terminal memories such as RRAM;

[0068] (3) NOR FLASH in this article can also be replaced by NAND FLASH, RRAM, MRAM, and PRAM;

[0069] (4) The programming operation in the embodiment can be replaced by an erasing operation, and the specific operation method is consistent with the process disclosed in the present invention.

[0070] As described above, it is obvious that the memory disclosed in the present invention can effectively improve the programming efficiency and reliability of the memory.

[0071] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A memory, characterized in that: include: Storage cells with different performances, each of which is provided with a fixed threshold value VTH, and the VTH is represented by at least three binary numbers; A reading module, for reading the current value of the storage unit to obtain a current threshold state of the storage unit; A first judgment module, judging whether the storage unit needs to be operated according to the threshold state, comprising: when the threshold state is greater than or equal to VTH, the judgment result of the first judgment module is "no", and entering the execution module; A second judgment module, enabled when the judgment result of the first judgment module is "yes", for judging the distance between the threshold state and VTH; The execution module controls the storage unit to perform corresponding operations according to the judgment results of the first judgment module and the second judgment module, including: when the execution module receives an instruction from the second judgment module, the execution module adopts operating conditions of different strengths to control the storage unit to continue related operations according to the distance between the threshold state obtained by the second judgment module and VTH, and when the distance between the threshold state and VTH gradually increases, the strength of the adopted operating conditions gradually weakens.

2. The memory according to claim 1, characterized in that: The threshold state of the storage unit includes: "all 0"-"all 1" represented by at least three binary bits.

3. The memory according to claim 1, characterized in that: The threshold state of the memory cell is the same as the binary number of VTH.

4. The memory according to any one of claims 1 to 3, characterized in that: The first judgment module also includes: When the threshold state is less than VTH, the judgment result of the first judgment module is "yes", and the second judgment module is entered.

5. The memory according to claim 4, characterized in that: The second judgment module includes: When the threshold state is "all 0", the threshold state is farthest from VTH; When the threshold state is smaller than the maximum value of the VTH value, the distance between the threshold state and VTH is the shortest.

6. The memory according to claim 5, characterized in that: The execution module also includes: When the execution module receives the instruction from the first determination module, the execution module controls the storage unit to terminate the related operation.

7. The memory according to claim 6, characterized in that: The operating conditions include: a gate voltage VG, and / or a drain voltage VD, and / or an operating time T.

8. The memory according to claim 7, characterized in that: The intensity control of the operating conditions includes: Enhanced gate voltage VG, and / or enhanced drain voltage VD, and / or increased operation time T to obtain enhanced operation conditions; Weakening the gate terminal voltage VG, and / or weakening the drain terminal voltage VD, and / or reducing the operation time T obtains weakened operation conditions.

9. The memory according to claim 8, characterized in that: The memory is a non-volatile flash memory, a data storage flash memory, a resistive random access memory, a magnetic memory and / or a phase change memory; And / or, the operation of the memory includes a programming operation and / or an erasing operation.

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