Testing a comparator within a memory security logic circuit with a fault enable generation circuit

Abstract

Embodiments of the present disclosure relate to testing a comparator within a memory security logic circuit with a fault enable generation circuit. A decoder decodes a memory address and selectively drives a select line of the memory, such as a word line or a mux line. A decoding circuit encodes data on the select line to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal indicating whether the decoder is operating properly. To test the proper operation of the comparison circuit, a subset of the MBIST scan routine blocks the encoded address from the comparison circuit and applies a forced signal in its place. The test signal and the forced signal from the scan routine are then compared by the comparison circuit, where the test result signal generated by the comparison circuit indicates whether the comparison circuit itself is operating properly.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 789,573, filed on Jan. 8, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention generally relates to memory security logic for testing integrated circuit memories and, more particularly, to comparator circuits for testing memory security logic. Background Art

[0004] Figure 1 A simplified block diagram of an integrated circuit memory 10 is shown. The memory includes a memory core 12 having an array of memory cells (C) 14 arranged in rows and columns, where the rows are associated with word lines 16 and the columns are associated with bit lines 18. The memory cells 14 can be, for example, static random access memory (SRAM) cells. The word lines 16 are selectively driven by a row decoder 20 that receives a memory address on an address bus 22 and decodes the received address bits (or a subset thereof) of the memory address to select one of the word lines 16 for actuation (e.g., driven to a logic high). The memory 10 also includes a column decoder 24 coupled to the address bus 22. The column decoder 24 also receives the memory address on the address bus 22 and decodes the received address bits (or a subset thereof) of the memory address to generate signals on column multiplexer (mux) lines 19 that select a plurality of bit lines 18 coupled to an input / output (I / O) circuit 28.

[0005] In a write mode, write data is applied to input data lines at the I / O circuit 28, and a memory address is applied to the address bus 22, where the bits of the memory address specify the location within the memory core 12 where the write data is to be stored. The row decoder 20 and the column decoder 24 decode the received address bits of the memory address and select the word line 16 and mux lines 19 corresponding to the memory address (which control the operation of the column multiplexer 21 to select the bit lines 18). A write operation is then performed to store the write data in the memory cells 14 at the selected word line 16 and bit lines 18.

[0006] In the read mode, a memory address is applied to the address bus 22, where bits of the memory address specify the location within the memory core 12 from which to retrieve read data. The row decoder 20 and the column decoder 24 decode the received address bits of the memory address and select the word line 16 and the mux line 19 for that memory address, which controls the operation of the column multiplexer 21 to select the bit line 18. A read operation to retrieve the read data stored in the memory cell 14 at the selected word line 16 and bit line 18 is then performed, and the read data is output by the I / O circuit 28 to the output data line.

[0007] The memory 10 further includes a security logic circuit 30 that monitors operations performed by the memory 10 (such as, for example, the write operation or the read operation discussed above) and generates an output error flag (SELOK) in response to the detection of a soft or hard fault by the security logic, which may result in erroneously written data or erroneously read data. For example, the security logic circuit 30 monitors the accuracy of the selection made by a decoder circuit such as the row decoder or the column decoder when accessing the memory array 12, and if the correct selection is made (i.e., no fault is detected), the output error flag (SELOK) may be logic high, and if an incorrect selection is made (i.e., a fault is detected), the output error flag (SELOK) may be logic low. More specifically, consider an illustrative example in which the security logic circuit 30 monitors the accuracy of the selection of the word line 16 by the row decoder 20. In this case, if the correct word line 16 is selected (i.e., no fault is detected), the output error flag (SELOK) may be logic high, and if an incorrect word line is selected (i.e., a fault is detected), the output error flag (SELOK) may be logic low. The security logic circuit 30 may alternatively and in fact additionally monitor the accuracy of the selection of the multiplexer (mux) line 19 for the selected column decoded by the column decoder. In this case, if the correct mux line 19 is selected (i.e., no fault is detected), the output error flag (SELOK) may be logic high, and if an incorrect mux line 19 is selected (i.e., a fault is detected), the output error flag (SELOK) may be logic low. The word line and the mux line are collectively referred to herein as the "selection lines" 17 of the memory 10.

[0008] Now refer to Figure 2, which shows a block diagram of the safety logic circuit 30. The safety logic circuit 30 includes a decoder circuit 32 having an input coupled to a selection line 17 (which can be the word line 16 or the mux line 19 or both as indicated above). The decoder circuit 32 operates to decode the data on the selection line 17 to generate an encoded address for output on the encoded address bus 34. A comparison circuit 38 operates to compare the address bits of the encoded address on the encoded address bus 34 with the address bits of the memory address on the address bus 22. The comparison circuit 38 sets the logical state of an error flag (SELOK) in response to the comparison. If the addresses do not exactly match, the error flag (SELOK) can be driven to a first logical state (e.g., logical low), which indicates that there is an error in the decoder (row decoder 20 or column decoder 24) in decoding the memory address and making a selection of the corresponding selection line 17.

[0009] As an example, the memory can include M selection lines (corresponding to the word line 16 and / or the mux line 19), and the encoded address bus 34 can have N bits, where N also equals the number of bits in the memory address on the address bus 22. Thus, the encoder circuit 32 is an MxN encoder. During the correct operation of a decoder (such as the row decoder 20 or the column decoder 24), only one of the selection lines 17 at a time will be asserted (e.g., logical high) in response to the decoded memory address on the address bus 22. All other selection lines 17 will be de-asserted (e.g., logical low). The encoder circuit 32 operates on the data for all the selection lines 17 to generate an encoded address on the encoded address bus 34 that matches the memory address if the decoder (20 or 24) is operating correctly.

[0010] In Figure 3A a simplified circuit example of the decoder circuit 32 is shown. In this example, the encoder is a 4x2 NOR matrix encoder implemented using n-channel MOSFET devices 36(1)-36(8). For the memory address <10>, the decoders 20, 24 will decode these memory address bits and assert only the third selection line 17 (SL(2)) at logical high. All other selection lines 17 will be de-asserted at logical low. The decoder circuit 32 will decode the selection line 17 data <0100> to generate the encoded address <10>, because only the MOSFET devices 36(2) and 36(6) will be conducting at logical high by SL(2) in the decoder, and all other MOSFET devices 36(1), 36(3)-36(5) and 36(7)-36(8) will be off. It will be noted that Figure 3AAn example circuit implementation for encoder 32 will generate both the encoded address on encoded address bus 34 and the complement of the encoded address (referred to as encoded address N). Although the use of only the encoded address is a possibility, the operation of security logic circuit 30 is enhanced if both the encoded address and the complement of the encoded address are processed in the manner disclosed herein. Figure 3B is a table showing the full encoding operation for an example of Figure 3A (where add = encoded address and addN = encoded address N).

[0011] Those skilled in the art can expand the Figure 3A example 4x2 simplified circuit to form an MxN decoder circuit 32.

[0012] Referring again to Figure 2 , comparison circuit 38 includes a plurality (N) of bit comparator circuits 40 that operate to perform a bit-by-bit comparison of the N bits in the encoded address (from encoded address bus 34), the N bits of the complement of the encoded address, and the N bits in the memory address (from address bus 22). The output 60 of each bit comparator circuit 40 is asserted (logic high) only when both the bit of the true encoded address and the logical inverse of the bit of the complementary encoded address match the corresponding bit of the memory address. Logic circuit 44 logically combines the outputs from bit comparator circuits 40 to generate an error flag (SELOK) that is asserted (e.g., logic high) when the bits of the true encoded address and the inverted bits of the complementary encoded address match the corresponding bits of the memory address, thus indicating normal operation of the decoder (20 or 24) in selecting one of select lines 17 (i.e., word line 16 or mux line 19).

[0013] More specifically, in the case where encoder circuit 32 is implemented in a manner that generates both the encoded address and the complement of the encoded address (encoded address N) as shown in Figure 3A , the bit comparator circuits 40 of comparison circuit 38 perform a bit-by-bit comparison of the N bits in the encoded address (from encoded address bus 34), the corresponding N bits of the complement of the encoded address (also from encoded address bus 34), and the corresponding N bits in the memory address (from address bus 22).

[0014] Figure 4A circuit diagram showing an example circuit for each bit comparator circuit 40 is presented. The bit comparator circuit 40 includes a logic NAND gate 50 having inputs that receive an encoded address (on the true part of the encoded address bus 34t), a memory address, and the logical inverse of the complement of the encoded address (on the complement part of the encoded address bus 34c) for a corresponding single bit, which is inverted by a logic inverter 52. The bit comparator circuit 40 also includes a logic NOR gate 54 having inputs that receive the encoded address, the memory address, and the logical inverse of the complement of the encoded address for a corresponding single bit. The output of the NOR gate 54 is inverted by a logic inverter 56. The output of the NAND gate 50 and the output of the inverter 56 are applied to the inputs of a logic NAND gate 58. When there is a match in the logical states among the encoded address, the complement of the encoded address inverted by the inverter 52, and the corresponding bit of the memory address, the output 60 of the bit comparator circuit 40 generated by the NAND gate 58 is asserted (logic high).

[0015] Now refer to Figure 5 , which shows a circuit diagram of a logic circuit 44 that logically combines the outputs from the N bit comparator circuits 40 to generate an error flag (SELOK). The logic circuit includes an N-input logic NAND gate 66 coupled to receive the outputs 60 from the N bit comparator circuits 40. The output of the NAND gate 66 is inverted by a logic inverter 58 to generate the error flag (SELOK). When all of the outputs 60 from the N bit comparator circuits 40 are logic high, the error flag (SELOK) is asserted as logic high (i.e., this will only occur when the encoded address matches the memory address). The logical operation is essentially a logical AND of the outputs 60. In the case of a mismatch indicating a fault in the decoder 20 or 24, at least one of the outputs 60 from the N bit comparator circuits 40 will be logic low indicating a detected bit mismatch, and the error flag (SELOK) is de-asserted as logic low to indicate the presence of a fault.

[0016] Memory Built-In Self-Test (MBIST) processing typically scans all addresses by applying appropriate test vectors and checking the error flag (SELOK) in each cycle. However, the MBIST check will not detect faults on the comparator circuit 40 signals (i.e., the signals associated with the outputs of the logic circuits within the N bit comparator circuits 40 and within the logic circuit 44) that cause an incorrect assertion of the error flag (SELOK) as logic high. This is referred to as a stuck-at-1 (stuck-at logic high) condition.

[0017] There is a need in the art for an improved test scheme that can test and detect faults on the comparator circuit 40 signals by only ordinary MBIST test scan operations. Summary of the Invention

[0018] In an embodiment, a circuit includes: a decoder coupled to a memory address bus and configured to receive a memory address and decode the memory address to selectively drive a plurality of select lines of a memory; an encoding circuit configured to encode data on the plurality of select lines to generate an encoded address on an encoded address bus; a comparison circuit coupled to the encoded address bus and the memory address bus and configured to compare the encoded address with the memory address and generate a test result signal indicating whether the decoder is operating properly in response to the comparison; a blocking circuit configured to block a channel of the encoded address to a portion of the encoded address bus coupled to the comparison circuit in response to a test control signal; and a test control circuit configured to generate the test control signal and apply a forcing signal to the portion of the encoded address bus, wherein the memory address bus is configured to receive a test signal provided by a memory built-in self-test (MBIST) scan routine, and the forcing signal and the test signal are configured to test the comparison circuit such that the test result signal generated by the comparison circuit in response to the comparison indicates whether the comparison circuit itself is operating properly.

[0019] In an embodiment, a method for testing a security logic circuit of a memory is provided. The security logic circuit includes a comparison circuit that operates to compare bits of an encoded address obtained by encoding data on a plurality of select lines of the memory with bits of a memory address for selecting a portion of the memory, the data being generated in response to decoding of the memory address. The method includes: performing a memory built-in self-test (MBIST) scan routine to test the memory; and in response to a subset of the MBIST scan routine, testing the comparison circuit of the security logic circuit by: applying a forcing signal to the comparison circuit for use in place of the encoded address; applying a test signal to the comparison circuit, wherein the test signal is provided by the MBIST scan routine; comparing the forcing signal with the test signal by the comparison circuit, wherein the forcing signal and the test signal are configured to test whether a bit comparator within the comparison circuit is operating properly; and generating a test result signal indicating whether the bit comparator of the comparison circuit is operating properly in response to the comparison by the comparison circuit.

[0020] In an embodiment, a circuit includes: a memory circuit; a memory built-in self-test (MBIST) circuit configured to test the memory circuit using an MBIST scan routine; and a test circuit. The memory circuit includes: a decoder coupled to a memory address bus and configured to receive a memory address and decode the memory address to selectively drive a plurality of select lines of the memory circuit; an encoding circuit configured to encode data on the plurality of select lines to generate an encoded address on an encoded address bus; and a comparison circuit coupled to the encoded address bus and the memory address bus and configured to compare the encoded address with the memory address and generate a test result signal indicating whether the decoder is operating properly in response to the comparison. The memory built-in self-test (MBIST) circuit receives the test result signal. The test circuit includes: a control circuit that generates a test control signal and a forcing signal in response to a subset operation of the MBIST scan routine; and a blocking circuit configured to block a channel of the encoded address to a portion of the encoded address bus coupled to the comparison circuit in response to the test control signal; wherein the forcing signal is applied to the portion of the encoded address bus, and a test signal from a subset of the MBIST scan routine is applied to the memory address bus, the forcing signal and the test signal being configured to test the comparison circuit, and the comparison circuit operates to compare the forcing signal with the test signal and generate a test result signal indicating whether the comparison circuit is operating properly. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] For a better understanding of the embodiments, reference is made to the drawings by way of example only, in which:

[0022] Figure 1 is a simplified block diagram of an integrated circuit memory;

[0023] Figure 2 is a block diagram of a security logic circuit;

[0024] Figure 3A is a simplified circuit example of an encoder circuit;

[0025] Figure 3B is a table illustrating an encoding operation;

[0026] Figure 4 is a circuit diagram of a bit comparator circuit;

[0027] Figure 5 is a circuit diagram for a logic circuit;

[0028] Figure 6 is a block diagram of a security logic circuit;

[0029] Figure 7 Illustrates the operation of a test;

[0030] Figure 8 is a table of the illustrated test operations; and

[0031] Figure 9 is a circuit diagram for an alternative embodiment of a logic circuit. DETAILED DESCRIPTION

[0032] Reference is now made to Figure 6 , which shows a block diagram of a safety logic circuit 130 with enhanced test functionality. The safety logic circuit 130 may be used in place of Figure 1 circuit 30. Like reference numerals refer to the same or similar components and their description will not be repeated (see, the above discussion).

[0033] The safety logic circuit 130 generally differs from the safety logic circuit 30 in that it includes a fault enable generation functional test operation for detecting faults on the compare circuit 38 signals (i.e., signals associated with the outputs of the logic circuits within the bit comparator circuit 40 kernel logic circuit 40) that result in an incorrect assertion of the error flag (SELOK) logic high. This is referred to as the stuck-at fault detection process.

[0034] The tri-state blocking circuit 132 is positioned on the encoded address bus 34 between the encoder circuit 32 and the compare circuit 38. The operation of the tri-state blocking circuit 132 is controlled by a control signal 134, which is generated by the fault enable generation test control circuit 136. When the control signal (CS) 134 is asserted low (e.g., logic low), the tri-state blocking circuit 132 is disabled and the bits of the encoded address (output from the encoder circuit 32 on the encoded address bus 34) are passed through the tri-state blocking circuit 132 to the compare circuit 38. Conversely, when the control signal 134 is asserted (e.g., logic high), the tri-state blocking circuit 132 is enabled, causing the bus lines of a portion 34a of the encoded address bus 34 to be disconnected from the encoded address bus 34. In this configuration, the bits of the encoded address (output from the encoder circuit 32 on the encoded address bus 34) are blocked by the tri-state blocking circuit 132 from passing through to the input of the compare circuit 38.

[0035] The control circuit 136 also generates a multi-bit forcing signal 140 for application to the disconnected portion 34a of the encoded address bus 34. The multi-bit forcing signal 140 forces all bits of the disconnected portion 34a of the encoded address bus 34 to a known logic state. For example, this can include forcing all bits to a logic high state or forcing all bits to a logic low state. In the context of the embodiments discussed herein in which the encoded address bus 34 carries both the encoded address and the complement of the encoded address (encoded address N), the multi-bit forcing signal 140 will include N bits corresponding to the encoded address in which all bits are set to logic low and are applied to the encoded address bus 34t; and N bits corresponding to the complement of the encoded address in which all bits are set to logic high and are applied to the complementary encoded address bus 34c. See, Figure 7 After assertion of the control signal 34 that enables the tri-state blocking circuit 132, application of the multi-bit forcing signal 140 to the disconnected portion 34a of the encoded address bus 34 is made.

[0036] Memory built-in self-test (MBIST) for the integrated circuit memory 10 performs common and well-known operations by scanning all memory addresses for read and write and can also operate to check the assertion of an error flag (SELOK) in each MBIST test cycle.

[0037] During normal scan operations performed by the MBIST, scan vectors are generated by the MBIST and a subset of the scan vectors that includes memory addresses and write enables along with the BIST test (TBIST) signal are received and processed by the test control circuit 136 to enable a fault enable generation functional test operation on the comparison circuit 38. Accordingly, a subset of the normal MBIST scan routine is utilized to activate a test mode for testing whether the comparator 40 of the secure logic circuit 130 is operating properly. Certain MBIST modes are advantageously used to check the comparator 40, and thus the MIST coverage is improved compared to prior art test configurations.

[0038] As an example, testing is enabled in response to satisfaction of the following Boolean expression related to a subset of the scan vectors:

[0039] TBIST*(not(WEN)*ASEL+WEN*not(ASEL)

[0040] Where: ASEL = A0 + A1 + A2 + A3 + … + An. When enabled to perform a fault enable generation functional test operation, test control circuit 136 generates control signal 134 for enabling tri-state blocking circuit 132 and generates multi-bit forcing signal 140. The multi-bit test signal 142, which is part of the MBIST scan vector, can then be applied to address bus 22. The multi-bit test signal 142 sets one bit (corresponding to a particular one of the N bit comparator circuits 40 to be tested) to a test logic level (e.g., asserted to logic high) and sets the remaining bits (corresponding to the remaining ones of the N bit comparator circuits 40 not to be tested) to the opposite logic level (e.g., de-asserted to logic low).

[0041] In the absence of a fault on the compare circuit 38 signals (i.e., the signals associated with the logic circuits within the N bit comparator circuits 40 and within the logic circuit 44), the error flag (SELOK) will have a first logic state (e.g., logic low). Conversely, if there is a fault on the compare circuit 38 signals, the error flag (SELOK) will have a second logic state (e.g., logic high, indicating a stuck-at-logic-high fault). The application of the multi-bit test signal 142 to the address bus 22 is made after the assertion of the control signal 34 that enables the tri-state blocking circuit 132, as with the multi-bit forcing signal 140.

[0042] As previously noted, compare circuit 38 includes a plurality of bit comparator circuits 40, and testing of each individual comparator circuit within the bit comparator circuits 40 must be performed to ensure the proper operation of compare circuit 38. This is accomplished by first asserting control signal 134 to enable tri-state blocking circuit 132 and then applying a sequence of multi-bit test signals 142 for application to address bus 22. Each multi-bit test signal 142 in the sequence will have a different single bit set to the test logic level. For example, with an N-bit address bus 22 and N bit comparator circuits 40, the following sequence of multi-bit test signals 142 can be generated and applied to address bus 22:

[0043] Test signal <1> = <000…001>,

[0044] Test signal <2> = <000…010>,

[0045] Test signal <3> = <000…100>,

[0046] and so on,

[0047] Test signal <n-1>= <010…000>, and finally

[0048] Test signal <n>= <100…000>.

[0049] Consider in more detail an embodiment for testing the comparison circuit 38 as Figure 4 and Figure 7 illustrated. The bit comparator circuits in the N-bit comparator circuit 40 that receive the logic low from the test signal 142 on the address bus 22 should generate an output 60 that is logic high, and the selected bit comparator circuits in the N-bit comparator circuit 40 that receive the logic high from the test signal 142 should generate an output 60 that is logic low. Since at least one of the outputs 60 is logic low, the logic circuit 44 will generate an error flag (SELOK) with a first logic state (logic low), which indicates that the selected bit comparator circuits in the N-bit comparator circuit 40 are operating properly (i.e., they are not suffering from a stuck-at-1 fault). In conjunction with the foregoing, consider the opposite case where the selected bit comparator circuits in the N-bit comparator circuit 40 are not operating properly (i.e., they are suffering from a stuck-at-1 fault). In this case, all outputs 60 will be logic high, and the logic circuit 44 will generate an error flag (SELOK) with a second logic state (logic high). This logic high output for the error flag (SELOK) is detectable, for example, as an indication of a fault in the comparison circuit 38 by the MBIST in response to the execution of the test mode.

[0050] The sequence of test signals can also include test signals where all bits of the address are set to a logic level opposite to the test logic level (e.g., de-asserted to logic low), and the write enable (WEN) signal is set to the test logic level. In this case, there is a selection made by the comparator circuit corresponding to the comparison with the WEN. The desired logic state of the error flag (SELOK) in response to this test signal remains logic low. If a logic low signal is generated, this indicates the proper operation of the comparator for generating the write enable (WEN) signal that specifies whether the designated memory is operating in the write mode or the read mode.

[0051] Figure 8 A table is shown that illustrates the results of the test operations for the sequence of test signals in an example where N = 6. References to A0 - A5 represent the bits of the address bus 22 to which the test signals are applied, and the corresponding logic state values for each of the bits A0 - A5 for each test signal in the sequence are shown. References to comparator coverage indicate that the comparator circuits being tested for each test signal are the bit comparator circuits that receive the identified bits on the address bus 22. Thus, the first test signal <000001> is configured to test the first bit comparator circuit A0, and an error flag (SELOK) in the logic low state indicates that the first bit comparator circuit A0 is operating properly.

[0052] The test operations described above involve, for example, the detection of incorrect operation due to a stuck-at fault in each bit comparator circuit 40. For example, consider separately Figure 4 and Figure 5 the bit comparator circuit 40 and the logic circuit 44. If the bit comparator circuit 40 and / or the logic circuit 44 has a stuck-at logic high fault, it cannot operate to produce an output 60 in the logic low state, regardless of what the individual bit inputs are for the memory address from the address bus 22, and both the encoded address and the complement of the encoded address (encoded address N) from the encoded address bus 34. However, the bits of the multi-bit forced signal 140 and the multi-bit test signal 142 are specifically selected such that a normally operating bit comparator circuit 40 and logic circuit 44 will generate a logic low output 60 (and thus produce a logic low error flag (SELOK)). If the error flag (SELOK) does not go logic low during the test operation of each of the selected N-bit comparator circuits in the N-bit comparator circuit 40, then it can be determined that a particular one of the N-bit comparator circuits in the N-bit comparator circuit 40 selected by the test signal is faulty or the logic circuit 44 is faulty.

[0053] The tests disclosed herein are used to operate as an adjunct to the memory built-in self-test (MBIST) for the integrated circuit memory 10. For this reason, no external test pins need to be used to support the test operation. The MBIST receives the error flag (SELOK) as an input. In combination with the conventional tests performed by the MBIST on the row decoder 20, the error flag (SELOK) generated by the comparison circuit 38 will be logic high in the absence of a row decoding fault (conversely, logic low in the case of a row decoder fault). However, for testing the bit comparator circuit 40 and the logic circuit 44, the error flag (SELOK) will be logic low when the selected bit comparator circuit 40 does not have a stuck-at 1 fault (conversely, logic high in the case of a stuck-at fault). Given this opposite logic state indication of faults for the two different test operations, some modification of the MBIST is needed so that the MBIST will recognize the logic high state of the error flag (SELOK) as a fault due to the execution of the fault test on the comparison circuit 38.

[0054] Figure 9 An alternative embodiment of the logic circuit 44 is shown which will cause the error flag (SELOK) to instead have a logic low state indicating a detected fault when testing for faults in the comparison circuit 38 (bit comparator circuit 40 and logic circuit 44). Figure 9 An embodiment utilizes two input logic XNOR gates 68' instead of the inverter circuit 68. One input of the XNOR gate 68' receives the output of the NAND gate 66, and the other input of the XNOR gate 68' receives the test mode signal 144. In one embodiment, the test mode signal 144 may be retrieved from one or more of the test control signal 134 and / or the test enable signal (TEN).

[0055] When the test mode signal 144 is asserted low to indicate that the MBIST is operating to perform a test on the decoder 20 or 24, the logic XNOR gate 68' operates to invert the logic state at the output of the NAND gate 66 to generate the error flag (SELOK). In this case, where the signal at the output of the NAND gate 66 is low in the absence of a detected fault, the error flag (SELOK) will be high in the absence of a detected fault.

[0056] Conversely, when the test mode signal 144 is asserted high to indicate that the MBIST is operating to perform a test on the comparison circuit 38, the logic XNOR gate 68' operates to pass the logic state at the output of the NAND gate 66 to generate the error flag (SELOK). In this case, where the signal at the output of the NAND gate 66 is high in the absence of a detected fault, the error flag (SELOK) will also be high in the absence of a detected fault.

[0057] Thus, the MBIST can handle the same logic state in both test modes with respect to the detection of a fault (i.e., a low error flag (SELOK) indicates a detected fault in either test mode). With this circuit configuration, there is no need to change the operation of the MBIST to recognize a low logic state of the error flag (SELOK) in the comparison circuit 38 test mode as a fault. In both test states, a low logic state for the error flag (SELOK) will be an indication of fault detection.

[0058] It is also possible that a fault may exist in the control circuit 136 that generates the control signal 134 as well as the multi-bit force signal 140. To illustrate this possible fault scenario, the other input of the XNOR gate 68' is alternatively configured to receive the test control signal 134 as generated by a duplicate of the control circuit 136.

[0059] Although the present invention has been described in detail in the drawings and the foregoing description, such description and illustration are to be considered illustrative or exemplary and not restrictive; the present invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.< / n>

Claims

1. A circuit, comprising: a decoder, coupled to a memory address bus and configured to receive a memory address and decode the memory address to selectively drive a plurality of select lines of a memory; an encoding circuit, configured to encode data on the plurality of select lines to generate an encoded address on an encoded address bus; a comparison circuit, coupled to the encoded address bus and the memory address bus and configured to compare the encoded address with the memory address and generate a test result signal in response to the comparison, the test result signal indicating whether the decoder is operating properly; a blocking circuit, configured to block a channel of the encoded address to a portion of the encoded address bus coupled to the comparison circuit in response to a test control signal; and a test control circuit, configured to generate the test control signal and apply a forcing signal to the portion of the encoded address bus, wherein the memory address bus is configured to receive a test signal provided by a memory built-in self-test (MBIST) scan routine, the forcing signal and the test signal being configured to test the comparison circuit such that the test result signal generated by the comparison circuit in response to the comparison indicates whether the comparison circuit itself is operating properly.

2. The circuit according to claim 1, wherein the test control circuit is selectively enabled to generate the test control signal and the forcing signal in response to a subset of the memory built-in self-test (MBIST) scan routine.

3. The circuit according to claim 1, wherein the comparison circuit includes a plurality of bit comparator circuits, the plurality of bit comparator circuits being configured to compare bits of the memory address bus with corresponding bits of the encoded address bus, and wherein the test signal from the MBIST scan routine selectively picks one of the plurality of bit comparator circuits to be tested for proper operation.

4. The circuit according to claim 1, wherein the comparison circuit includes a plurality of bit comparator circuits, the plurality of bit comparator circuits being configured to compare bits of the memory address bus with corresponding bits of the encoded address bus, and wherein the MBIST scan routine provides a sequence of test signals, each test signal in the sequence being configured to pick a different one of the plurality of bit comparator circuits to be tested for proper operation.

5. The circuit according to claim 1, wherein the select lines include one or more of word lines for the memory or column multiplexer lines for the memory.

6. The circuit according to claim 1, wherein a logical state of the test result signal generated by the comparison circuit indicating proper operation of the decoder and a logical state of the test result signal generated by the comparison circuit indicating proper operation of the comparison circuit itself are different logical states.

7. The circuit according to claim 1, wherein a logical state of the test result signal generated by the comparison circuit and indicating whether the decoder is operating normally and a logical state of the test result signal generated by the comparison circuit and indicating whether the comparison circuit itself is operating normally are the same logical state.

8. The circuit according to claim 1, wherein the blocking circuit is a tri-state blocking circuit configured to disconnect the portion of the encoded address bus in response to the test control signal.

9. The circuit according to claim 1, wherein the encoded address bus includes a true bus portion and a complement bus portion, the true bus portion carrying the encoded address, and the complement bus portion carrying a complement of the encoded address.

10. The circuit according to claim 9, wherein the forcing signal forces all bits of the true bus portion to a first logical state and forces all bits of the complement bus portion to a second logical state different from the first logical state.

11. The circuit according to claim 1, wherein the forcing signal forces all bits of the encoded address bus to the same logical state.

12. A method for testing a security logic circuit of a memory, wherein the security logic circuit includes a comparison circuit that operates to compare bits of an encoded address obtained by encoding data on a plurality of select lines of the memory with bits of a memory address for selecting a portion of the memory, the data being generated in response to decoding of the memory address, the method comprises: performing a memory built-in self-test (MBIST) scan routine to test the memory; and in response to a subset of the MBIST scan routine, testing the comparison circuit of the security logic circuit by: applying a forcing signal to the comparison circuit to replace the encoded address; applying a test signal to the comparison circuit, wherein the test signal is provided by the MBIST scan routine; comparing, by the comparison circuit, the forcing signal with the test signal, wherein the forcing signal and the test signal are configured to test normal operation of a bit comparator within the comparison circuit; and generating a test result signal in response to the comparison by the comparison circuit, the test result signal indicating whether the bit comparator of the comparison circuit is operating normally.

13. The method according to claim 12, wherein applying the forcing signal includes blocking a path of the encoded address through the encoded address bus to the comparison circuit.

14. The method according to claim 12, further comprising evaluating the test result signal by the MBIST.

15. The method according to claim 12, wherein the comparison circuit includes a plurality of bit comparators, and wherein the test signal selectively picks one bit comparator among the plurality of bit comparators to be tested for normal operation.

16. The method according to claim 12, wherein the comparison circuit includes a plurality of bit comparators, and wherein applying the test signal includes generating a sequence of test signals, each test signal in the sequence being configured to select a different one of the plurality of bit comparators to be tested for proper operation.

17. A circuit, comprising: A memory circuit, comprising: A decoder, coupled to a memory address bus and configured to receive a memory address and decode the memory address to selectively drive a plurality of select lines of the memory circuit; An encoding circuit, configured to encode data on the plurality of select lines to generate an encoded address on an encoded address bus; and A comparison circuit, coupled to the encoded address bus and the memory address bus and configured to compare the encoded address with the memory address and generate a test result signal in response to the comparison, the test result signal indicating whether the decoder is operating properly; A memory built-in self-test (MBIST) circuit, configured to test the memory circuit using an MBIST scan routine and receive the test result signal; and A test circuit, comprising: A control circuit, responsive to a subset of operations of the MBIST scan routine, to generate a test control signal and a forcing signal; and A blocking circuit, configured to block the passage of the encoded address to a portion of the encoded address bus coupled to the comparison circuit in response to the test control signal; wherein the forcing signal is applied to the portion of the encoded address bus, and a test signal from the subset of the MBIST scan routine is applied to the memory address bus, the forcing signal and the test signal being configured to test the comparison circuit, the comparison circuit operating to compare the forcing signal with the test signal and generate the test result signal indicating whether the comparison circuit is operating properly.

18. The circuit according to claim 17, wherein the comparison circuit includes a plurality of bit comparator circuits configured to compare bits of the memory address bus with corresponding bits of the encoded address bus, and wherein the test signal from the MBIST scan routine selectively selects one of the plurality of bit comparator circuits to be tested for proper operation.

19. The circuit according to claim 17, wherein the comparison circuit includes a plurality of bit comparator circuits configured to compare bits of the memory address bus with corresponding bits of the encoded address bus, and wherein the MBIST scan routine provides a sequence of test signals, each test signal in the sequence being configured to select a different one of the plurality of bit comparator circuits to be tested for proper operation.

20. The circuit according to claim 17, wherein the select lines include one or more of word lines for the memory or column multiplexer lines for the memory.

21. The circuit according to claim 17, wherein the blocking circuit is a three-state blocking circuit configured to disconnect the portion of the encoded address bus in response to the test control signal.

Images