Step etching of silicon oxide and silicon nitride stacks

Abstract

A method for forming a stair-step structure in a stack on a substrate is provided. The method includes at least one stair-step cycle. Each stair-step cycle includes trimming the mask and etching the stack. Etching the stack is provided in multiple cycles, wherein each cycle includes etching a SiO2 layer and etching a SiN layer. Etching the SiO2 layer includes flowing a SiO2 etching gas into a plasma processing chamber, wherein the SiO2 etching gas includes at least one of SF6 and NF3, a hydrofluorocarbon, and an inert bombardment gas; generating a plasma from the SiO2 etching gas; providing a bias; and stopping etching the SiO2 layer. Etching the SiN layer includes flowing a SiN etching gas into the plasma processing chamber, wherein the SiN etching gas includes a hydrofluorocarbon and oxygen; generating a plasma from the SiN etching gas; providing a bias; and stopping etching the SiN layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 62 / 593,082, filed November 30, 2017, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure relates to the formation of semiconductor devices, and more particularly, to the formation of stepped semiconductor devices. Background Art

[0004] During semiconductor wafer processing, stepped features are sometimes required. For example, in 3D flash memory devices, multiple cells are stacked together in a chain format to save space and increase packaging density. The stepped structure allows electrical contact to each gate layer. Such a stepped structure can be formed from multiple alternating layers of silicon oxide (SiO2) and silicon nitride (SiN), where such a stack is called an ONON stack. In addition to stepped semiconductor devices, ONON stacks can also be used to form other semiconductor devices. Summary of the Invention

[0005] To achieve the foregoing and in accordance with the purposes of the present disclosure, a method for forming a stepped structure in a stack on a substrate in a plasma processing chamber is provided, wherein the stack includes multiple bilayers of silicon oxide and silicon nitride under a mask. The method includes at least one step cycle. Each step cycle includes trimming the mask and etching the stack. Etching the stack is performed in multiple cycles, wherein each cycle includes etching a SiO2 layer and etching a SiN layer. Etching the SiO2 layer includes flowing a SiO2 etching gas into the plasma processing chamber, wherein the SiO2 etching gas includes at least one of sulfur hexafluoride (SF6) and nitrogen trifluoride (NF3), a hydrofluorocarbon, and an inert bombardment gas; generating a plasma from the SiO2 etching gas; providing a bias; and stopping etching the SiO2 layer. Etching the SiN layer includes flowing a SiN etching gas into the plasma processing chamber, wherein the SiN etching gas includes a hydrofluorocarbon and oxygen; generating a plasma from the SiN etching gas; providing a bias; and stopping etching the SiN layer.

[0006] These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings and in which like references indicate similar elements and in which:

[0008] Figure 1 is a high-level flow diagram of a process that may be used in embodiments of the present disclosure.

[0009] Figures 2A-2G is a schematic cross-sectional view of a stack etched according to an embodiment of the present disclosure.

[0010] Figure 3 A more detailed flow chart of the SiO2 etching process.

[0011] Figure 4 A more detailed flow chart of the SiN etching process is shown in FIG.

[0012] Figure 5 is a schematic diagram of a plasma processing chamber that may be used to practice the present disclosure.

[0013] Figure 6 A computer system is shown that is suitable for implementing a controller used in embodiments of the present disclosure. Specific implementation plan

[0014] The present invention will now be described in detail with reference to several preferred embodiments shown in the accompanying drawings. In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without some or all of these specific details. In other cases, well-known process steps and / or structures have not been described in detail in order to avoid unnecessarily obscuring the present invention.

[0015] The traditional method of etching a double-layer stack of silicon oxide (SiO2) and silicon nitride (SiN) is to use the SiO2 layer as a mask to etch the SiN layer in the first process, and then use the SiN as a mask to etch the SiO2 layer in the second process. Because the SiN layer is used as a mask to etch the SiO2 layer and vice versa, the selectivity must be very high. To provide the desired selectivity, previous methods produced enough polymer to cause tapering of the etched stack sidewalls.

[0016] Three-dimensional NAND (3D NAND) step etching is a critical process. The industry is moving toward stacks of 96 SiO2 and SiN bilayers and beyond. This process requires rapid production to reduce costs. However, there are always trade-offs between various parameters, such as profile angle, line edge roughness (LER), etch selectivity, and throughput. Maintaining vertical profile angles, good LER, and free rounding / faceting across multiple bilayers while reducing processing time becomes a significant challenge.

[0017] For ease of understanding, Figure 11 is a high-level flow chart of a process that can be used in an embodiment of the present disclosure. This embodiment is used to form a staircase structure in a stack. An organic mask is formed on the stack of alternating SiO2 and SiN (ONON) layers (step 104).

[0018] Figure 2A 2 is a cross-sectional view of a stack 200 including a multi-layer memory stack 204 formed on a wafer 208. In this embodiment, each of the plurality of memory stacks is formed of a double layer of SiN layer 212 forming an ONON stack and SiO2 layer 216 on top thereof. A mask 220 is formed over the memory stack 204 (step 104). The mask 220 may be a photoresist mask formed using a spin coating process and photolithographic patterning. In an alternative embodiment, the mask 220 may be an organic layer that is spun onto an organic layer or otherwise applied without photolithographic patterning.

[0019] Mask 220 is trimmed (step 108). If mask 220 is an organic mask, mask 220 may be trimmed using an organic trimming process. Figure 2B is a cross-sectional view of the stack 200 after the mask 220 has been trimmed.

[0020] After trimming the mask 220 (step 108 ), multiple cycles of etching the SiO 2 layer (step 112 ) and etching the SiN layer (step 116 ) are provided. Figure 3 3 is a more detailed flow chart of etching the SiO2 layer (step 112). The SiO2 etching gas flows into the processing chamber (step 304). The SiO2 etching gas includes at least one of sulfur hexafluoride (SF6) and nitrogen trifluoride (NF3), a hydrofluorocarbon, and an inert bombardment gas. In this example, the SiO2 etching gas is mainly composed of 10 to 100 standard cubic centimeters per minute (sccm) SF6, 50-250sccm fluoroform (CHF3), 100-500sccm helium (He), and 10-200sccm NF3. CHF3 is a hydrofluorocarbon. He is an inert bombardment gas. The SiO2 etching gas is formed into a plasma (step 308). Inductively coupled radio frequency (RF) power is provided at 13.56 megahertz (MHz) with a power of at least 2000 watts. A low bias voltage of less than 150 volts (V) is provided (step 312) to cause ion bombardment of helium ions, thereby activating the surface of the stack for ion-assisted etching, wherein the in-situ plasma etches the activated surface of the stack. A chamber pressure of 10 to 20 millitorr (mTorr) is provided. The etching process is stopped after 5 seconds. The etching process can be stopped by stopping the flow of SiO2 etching gas (step 316). In addition, the RF power can be turned off. Figure 2C2 is a cross-sectional view of the stack 200 after the top SiO2 layer 216 in the stack 200 has been etched (step 112). The benefit of a separate SiO2 recipe is that the SiO2 recipe has a lean oxide etch chemistry. The lean oxide etch chemistry provides a vertical ONON etch profile.

[0021] After the top SiO 2 layer 216 is etched (step 112 ), the top SiN layer 212 is etched (step 116 ). Figure 4 4 is a more detailed flow chart for etching the SiN layer (step 116). SiN etching gas flows into the processing chamber (step 404). The SiN etching gas includes a hydrofluorocarbon and oxygen (O2). In this example, the SiN etching gas is mainly composed of 50 to 150 sccm of carbon tetrafluoride (CF4), 50 to 200 sccm of fluoromethane (CH3F), and 50 to 150 sccm of O2. CH3F is a hydrofluorocarbon. The SiN etching gas is formed into a plasma (step 408). Inductively coupled RF power is provided at 13.56 MHz with a power of at least 2000 watts. A bias voltage of 150 to 400 volts is provided (step 412). A chamber pressure of 30 to 100 mTorr is provided. The etching process is stopped after 5 seconds. The etching process can be stopped by stopping the flow of SiN etching gas (step 416). In addition, the RF power can be stopped. Figure 2D 1 is a cross-sectional view of the stack 200 after the top SiN layer 212 in the stack 200 has been etched (step 116). Since the etch is selective, the SiO2 layer 216 acts as an etch stop layer. The top SiO2 layer 216 can be used as an etch mask.

[0022] The etching of the SiO 2 layer 216 (step 112 ) and the etching of the SiN layer 212 (step 116 ) are repeated (step 120 ) twice. Figure 2E is a cross-sectional view of the stack 200 after the etching of the SiO2 layer 216 (step 112) and the etching of the SiN layer 212 (step 116) are repeated twice (step 120). A first step 224 having a height of three bi-layers has been etched.

[0023] The staircase is not completed (step 124), and the process returns to the step of trimming the mask (step 108). An example recipe for trimming an organic mask provides a pressure between 30 and 400 mTorr. A trim gas is flowed into the process chamber, wherein the trim gas is 1000 sccm O2, 40 sccm N2, and 50 sccm C4F6 or NF3. The trim gas forms a plasma. After the trimming is complete, the trim gas flow is stopped. Figure 2F is a cross-sectional view of the stack 200 after the mask 220 has been trimmed.

[0024] The steps of etching the SiO2 layer 216 (step 112) and etching the SiN layer 212 (step 116) are repeated three times, completing the step etching in this embodiment (step 124). Figure 2G is a cross-sectional view of stack 200 after etching second step 228. In this example, three layers of SiO2 and SiN are etched to form second step 228 while deepening first step 224. The deepening of first step 224 etches the first step without a mask and provides vertical sidewalls and corners without faceting.

[0025] The complete staircase provides an improved structure relative to staircases created using other processes in a faster manner than other processes. The above embodiment has less taper than processes that use more polymer to increase selectivity. Because the process uses a low bias to etch at least one layer of each bilayer, the rounding of facets and corners is reduced. Normally, a lower bias will result in lower throughput. However, the chemistry of the SiO2 etching gas and the SiN etching gas can provide high throughput at low bias. In addition, a higher bias can be used to etch only one layer of the bilayer. In addition, this embodiment reduces the roughness of the line edges. Since each step in this embodiment is three bilayers, the stack has at least six SiO2 and SiN bilayers in this embodiment.

[0026] In other embodiments, steps can be formed in one or more directions (X or Y). In other embodiments, other features can be etched into multiple silicon oxide and silicon nitride bilayers. Various embodiments reduce corner faceting and sidewall etching on non-stepped structures while increasing the etch rate of the bilayer.

[0027] In other embodiments, the first layer is a silicon nitride layer. In various embodiments, subsequent steps may be provided, such as removing any remaining mask 220. Various embodiments may be used to etch high aspect ratio features, such as contacts.

[0028] In various embodiments, the SiO etching gas comprises at least one of SF6 or NF3, a hydrofluorocarbon, and an inert bombardment gas. In various embodiments, the SiO etching gas is oxygen-free. During etching the SiO2 layer (step 112), the oxygen present can cause the organic mask 220 to be laterally etched during the SiO2 vertical etching (step 112). The lateral etching of the organic mask reduces profile control. In various embodiments, the hydrofluorocarbon can be at least one of CH2F2, CH3F, or CHF3.

[0029] In various embodiments, the magnitude of the bias provided during etching the SiN layer (step 116) is greater than the magnitude of the bias provided during etching the SiO2 layer (step 112). For example, in some embodiments, etching the SiN layer (step 116) has a bias magnitude between 150 volts and 400 volts, inclusive, and etching the SiO2 layer (step 112) has a bias magnitude less than 150 volts. In other embodiments, etching the SiN layer (step 116) has a bias magnitude between 150 volts and 700 volts, and etching the SiO2 layer (step 112) has a bias magnitude between 20 volts and 100 volts, inclusive.

[0030] In various embodiments, the chamber pressure during etching the SiN layer (step 116) is greater than the chamber pressure during etching the SiO2 layer (step 112). For example, in some embodiments, etching the SiN layer (step 116) has a chamber pressure greater than 30 mTorr, such as a chamber pressure between 30 mTorr and 100 mTorr, and etching the SiO2 layer (step 112) has a chamber pressure less than 20 mTorr.

[0031] Various embodiments provide for a fast etching process and increased throughput. For example, etching of the SiO2 layer (step 112) can be performed in no more than 10 seconds. In various embodiments, etching of the SiN layer (step 116) can be performed in no more than 10 seconds. In various embodiments, etching of the SiN layer (step 116) can be performed in no more than 5 seconds. In various embodiments, etching of the SiN and SiO2 bilayer can be performed in no more than 15 seconds.

[0032] In various embodiments, etching the SiN layer (step 116) selectively etches the SiN layer 212 relative to the SiO2 layer 216 with a selectivity in the range of 2:1 to 4:1. Etching the SiN layer (step 116) also selectively etches the SiN layer 212 relative to the mask 220. In various embodiments, etching the SiO2 layer (step 112) selectively etches the SiO2 layer 216 relative to the mask 220. Etching the SiO2 layer (step 112) does not selectively etch the SiO2 layer 216 relative to the SiN layer 212. Endpoint control is used to stop the etching of the SiO2 layer 216.

[0033] In one embodiment, the stack includes at least six bilayers of silicon oxide and silicon nitride. In another embodiment, the stack includes more than 60 bilayers of silicon oxide and silicon nitride. In the above embodiment, each step is three bilayers. In other embodiments, each step can be three to ten bilayers. In such an embodiment, the etching of the SiO2 layer (step 112) and the etching of the SiN layer (step 116) are cyclically repeated three to ten times for each step. If the stack has more than 60 bilayers and there are three bilayers in each step, the step etching process can be repeated at least 20 times. In such an embodiment, depending on the thickness of mask 220 and the selectivity of the etching process, mask 220 can only be used to form approximately seven steps. In this case, a new mask 220 can be formed every seven steps, so that at least three masks 220 are applied during the etching of at least twenty steps.

[0034] In one embodiment, during the flow of the SiN etching gas, at least some of the hydrofluorocarbons flow from the sides of the plasma processing chamber in a direction having a component parallel to the top surface of the top of the stack. As a result, the hydrofluorocarbons flowing from the sides of the plasma processing chamber initially flow over the sides of substrate 208 toward the center of substrate 208, which, in this example, is disk-shaped. The ratio of the flow of the hydrofluorocarbons from the top of the plasma processing chamber to the flow of the hydrofluorocarbons from the sides of the plasma processing chamber can be used as an adjustment knob. The adjustment knob allows adjustment to improve process uniformity. In this embodiment, the hydrofluorocarbons do not flow from the sides of the plasma processing chamber during the flow of the SiO2 etching gas.

[0035] Figure 5An example of a plasma processing system 500 that can be used to process a substrate 208 according to one embodiment of the present invention is schematically illustrated. The plasma processing system 500 includes a plasma reactor 502 having a plasma processing chamber 504 surrounded by a chamber wall 562. A plasma power source 506, tuned by a matching network 508, provides power to a transformer-coupled plasma (TCP) coil 510 located near a power window 512 to generate a plasma 514 in the plasma processing chamber 504 by providing inductively coupled power. The TCP coil (upper power source) 510 can be configured to produce a uniform diffusion profile within the plasma processing chamber 504. For example, the TCP coil 510 can be configured to produce a toroidal power distribution in the plasma 514. The power window 512 is positioned to separate the TCP coil 510 from the plasma processing chamber 504 while enabling energy to be transferred from the TCP coil 510 to the plasma processing chamber 504. A wafer bias voltage power source 516, tuned by a matching network 518, provides power to an electrode 520 to set a bias voltage on the substrate 208. The electrode 520 provides a chuck for the substrate 208, wherein the electrode 520 acts as an electrostatic chuck. The substrate temperature controller 566 is controllably connected to the Peltier heater / cooler 568. The controller 524 sets the set points for the plasma power supply 506, the substrate temperature controller 566, and the wafer bias voltage supply 516.

[0036] The plasma power source 506 and the wafer bias voltage power source 516 can be configured to operate at a specific radio frequency, such as 13.56 MHz, 27 MHz, 2 MHz, 400 kilohertz (kHz), or a combination thereof. The plasma power source 506 and the wafer bias voltage power source 516 can be appropriately sized to provide a range of powers to achieve desired processing performance. For example, in one embodiment of the present invention, the plasma power source 506 can provide a power in the range of 50 to 5000 watts, and the wafer bias voltage power source 516 can provide a bias voltage in the range of 20 to 1500 V. In addition, the TCP coil 510 and / or the electrode 520 can include two or more sub-coils or sub-electrodes, which can be powered by a single power source or by multiple power sources.

[0037] like Figure 5As shown, the plasma processing system 500 also includes a gas source 530. The gas source 530 provides gas or remote plasma to a center feed 536 and a side feed 538. The center feed 536 and the side feed 538 are in the form of nozzles. The center feed 536 is located approximately above the center of the substrate 208. The side feeds 538 can be one or more nozzles positioned closer to the sides of the substrate 208 than to the center of the substrate 208. The center feed 536 provides gas with a greater vertical component. The vertical component is perpendicular to the surface of the substrate 208, as shown by arrow V. The side feeds 538 have a greater horizontal component than the center feed. The horizontal component is parallel to the surface of the substrate 208, as shown by arrow H. As shown, the gas from the side feeds 538 flows from the sides of the substrate 208 to the center of the substrate 208. Process gases and byproducts are removed from the plasma processing chamber 504 via a pressure control valve 542 and a pump 544, which also serve to maintain a specified pressure within the plasma processing chamber 504. A gas source 530 is controlled by a controller 524. Embodiments of the present invention may be implemented using a Kiyo, available from Lam Research Corp. of Fremont, California.

[0038] Figure 6 6 is a block diagram showing a computer system 600, which is suitable for realizing the controller 524 used in the embodiments of the present disclosure. The computer system can have multiple physical forms, ranging from integrated circuits, printed circuit boards and small handheld devices to giant supercomputers. The computer system 600 includes one or more processors 602, and can further include an electronic display device 604 (for displaying graphics, text and other data), a main memory 606 (for example, random access memory (RAM)), a storage device 608 (for example, a hard disk drive), a removable storage device 610 (for example, an optical disk drive), a user interface device 612 (for example, a keyboard, a touch screen, a small keyboard, a mouse or other positioning devices, etc.) and a communication interface 614 (for example, a wireless network interface). The communication interface 614 enables software and data to be transmitted between the computer system 600 and an external device by a link. The system can also include a communication infrastructure 616 (for example, a communication bus, a cross-over bar (cross-over bar) or a network), and the aforementioned equipment / module is connected to the communication infrastructure 616.

[0039] The information transmitted via the communication interface 614 can be in the form of a signal that can be received by the communication interface 614 through a communication link, such as an electronic, electromagnetic, optical, or other signal, which carries the signal and can be a communication link implemented using wire or cable, optical fiber, telephone line, cellular telephone link, radio frequency link, and / or other communication channels. Using such a communication interface, it is contemplated that one or more processors 602 can receive information from a network or can output information to a network in the course of implementing the above-described method steps. In addition, the method embodiments can be executed solely on the processor or can be executed in conjunction with a remote processor over a network such as the Internet, which shares a portion of the processing.

[0040] The term "non-transitory computer-readable medium" is generally used to refer to media such as main memory, secondary memory, removable storage, and storage devices (e.g., hard disks, flash memory, hard drive memory, CD-ROMs, and other forms of permanent memory), and should not be interpreted as encompassing transitory subject matter such as carrier waves or signals. Examples of computer code include machine code, such as that produced by a compiler, and files including higher-level code that is executed by a computer using an interpreter. A computer-readable medium may also be computer code transmitted by a computer data signal embodied in a carrier wave and represented as a sequence of instructions that can be executed by a processor.

[0041] The controller 524 is used to provide an adjustment ratio of the flow rate of the hydrofluorocarbon through the center feed 536 and the flow rate of the hydrofluorocarbon through the side feed 538. This adjustment allows the ratio of the flow rate of the hydrofluorocarbon perpendicular to the surface of the substrate 208 to the flow rate of the hydrofluorocarbon parallel to the surface of the substrate 208 to be controlled.

[0042] Although the present invention has been described in terms of several preferred embodiments, there are variations, permutations, and various alternative equivalents that fall within the scope of the present invention. It should also be noted that there are many alternative ways to implement the methods and apparatus of the present invention. Therefore, the following claims are intended to be interpreted as including all such variations, permutations, and various alternative equivalents that fall within the true spirit and scope of the present invention.

Claims

1. A method for forming a stepped structure in a stack on a substrate in a plasma processing chamber, wherein: The stack includes a plurality of bilayers of silicon oxide and silicon nitride under a mask, the method including at least one step cycle, wherein each step cycle includes: trimming the mask; and etching the stack in a plurality of cycles, wherein each cycle comprises: Etching the SiO2 layer, comprising: flowing a SiO2 etching gas into the plasma processing chamber, wherein the SiO2 etching gas comprises at least one of SF6 and NF3, a hydrofluorocarbon, and an inert bombardment gas; generating plasma from the SiO2 etching gas; providing bias; and Stopping the SiO2 layer etching; and Etching a SiN layer, wherein the SiN layer is selectively etched relative to the SiO2 layer and the mask, comprising: flowing a SiN etching gas into the plasma processing chamber, wherein the SiN etching gas comprises a hydrofluorocarbon and oxygen; generating plasma from the SiN etching gas; providing bias; and The SiN layer etching is stopped.

2. The method according to claim 1, wherein The SiO2 etching gas is oxygen-free.

3. The method according to claim 1, wherein The method comprises at least twenty step cycles.

4. The method according to claim 1, wherein The inert bombardment gas is He.

5. The method according to claim 1, wherein The hydrofluorocarbon in the SiN etching gas is at least one of CH2F2, CH3F and CHF3.

6. The method according to claim 1, wherein The magnitude of the bias during the etching of the SiN layer is greater than or equal to the magnitude of the bias during the etching of the SiO 2 layer.

7. The method according to claim 1, wherein The bias during the etching of the SiN layer has a magnitude between 150 volts and 400 volts, inclusive, and the bias during the etching of the SiO2 layer has a magnitude less than 150 volts.

8. The method of claim 1, further comprising providing a pressure greater than 30 mTorr during the etching of the SiN layer, and providing a pressure less than 20 mTorr during the etching of the SiO2 layer.

9. The method according to claim 1, wherein The etching of the SiN layer is less than 10 seconds for each cycle, and the etching of the SiO 2 layer is less than 10 seconds for each cycle.

10. The method according to claim 1, wherein The etching the stack includes three to ten cycles.

11. The method according to claim 1, wherein The stack includes more than 60 double layers.

12. The method according to claim 1, wherein The flowing of the SiN etching gas into the plasma processing chamber flows the hydrofluorocarbon through a center feed and a side feed, wherein the center feed includes one or more nozzles and the side feed includes one or more nozzles closer to the side of the substrate than to the center of the substrate.

13. The method according to claim 12, wherein: The one or more nozzles of the side feed cause the hydrofluorocarbon to flow in a direction from the side of the substrate toward the center of the substrate.

14. The method according to claim 1, wherein The etching of the SiN layer has an etch selectivity of SiN to SiO2 in a range of 2:1 to 4:

1.

15. The method according to claim 14, wherein The SiO 2 etch does not selectively etch the SiO 2 layer relative to the SiN layer.

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