Image Sensor

Abstract

An image sensor includes: a semiconductor layer including a first portion and a second portion, the semiconductor layer having a first surface and a second surface facing each other; a device isolation layer in the semiconductor layer and defining a plurality of pixels; a first grid pattern on a first surface on the first portion of the semiconductor layer; and a light shielding pattern on the first surface on the second portion of the semiconductor layer. A top surface of the first grid pattern is located at a first height, a top surface of the light shielding pattern is located at a second height, the first height is lower than the second height, and the first height and the second height are defined relative to the first surface of the semiconductor layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0003842 filed on January 11, 2019 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concept relates to an image sensor, and more particularly, to an image sensor having improved image quality. Background Art

[0004] An image sensor is a semiconductor device that converts an optical image into an electrical signal. Image sensors can be divided into charge coupled device (CCD) type and complementary metal oxide semiconductor (CMOS) type. CIS (CMOS image sensor) is understood to correspond to a CMOS type image sensor. CIS generally includes a plurality of pixels arranged in two dimensions. Each pixel includes a photodiode (PD). The photodiode is used to convert incident light into an electrical signal. Summary of the invention

[0005] Embodiments of the inventive concept provide an image sensor with improved image quality.

[0006] An embodiment of the inventive concept provides an image sensor having: a semiconductor layer including a first portion and a second portion, the semiconductor layer having a first surface and a second surface facing each other; a device isolation layer in the semiconductor layer and defining a plurality of pixels; a first grid pattern on a first surface on the first portion of the semiconductor layer; and a light shielding pattern on the first surface on the second portion of the semiconductor layer. A top surface of the first grid pattern is located at a first height, a top surface of the light shielding pattern is located at a second height, the first height is lower than the second height, and the first height and the second height are defined relative to the first surface of the semiconductor layer.

[0007] Embodiments of the inventive concept also provide an image sensor having: a semiconductor layer including a first portion and a second portion surrounding the first portion; a device isolation layer in the semiconductor layer and defining a plurality of pixels; a grid pattern on the first portion of the semiconductor layer, the grid pattern extending along the device isolation layer and including a first pattern; and a light shielding pattern on the second portion of the semiconductor layer. The thickness of the first pattern is less than the thickness of the light shielding pattern. The first pattern covers a side surface of the light shielding pattern.

[0008] Embodiments of the inventive concept also provide an image sensor having: a semiconductor layer including a first portion and a second portion; a device isolation layer in the semiconductor layer and defining a plurality of pixels; a grid pattern on the first portion of the semiconductor layer; and a light shielding structure on the second portion of the semiconductor layer. The thickness of the grid pattern is less than the thickness of the light shielding structure.

[0009] Embodiments of the inventive concept also provide an image sensor having: a semiconductor layer including a first portion and a second portion, the semiconductor layer having a first surface and a second surface facing each other; a device isolation layer in the semiconductor layer and defining a plurality of pixels; a grid pattern on a first surface on a first portion of the semiconductor layer, the grid pattern including a first pattern and a low refractive index pattern on the first pattern; a light shielding pattern on a first surface on a second portion of the semiconductor layer; and a color filter on a first pixel among a plurality of pixels in the first portion of the semiconductor layer. The thickness of the first pattern is less than the thickness of the light shielding pattern, and the refractive index of the low refractive index pattern is less than the refractive index of the color filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features of the inventive concept will be described hereinafter with reference to the accompanying drawings.

[0011] Figure 1 A schematic block diagram of an image sensor according to an embodiment of the inventive concept is shown.

[0012] Figure 2 A simplified circuit diagram of a sensor array of an image sensor according to an embodiment of the inventive concept is shown.

[0013] Figure 3 A circuit diagram of a pixel of an image sensor according to an embodiment of the inventive concept is shown.

[0014] Figure 4 A plan view of an image sensor according to an embodiment of the inventive concept is shown.

[0015] Figure 5 Shown along Figure 4 sectional views taken along lines II′ and II-II′ illustrate an image sensor according to an embodiment of the inventive concept.

[0016] Figure 6 Shown along Figure 4 sectional views taken along lines II′ and II-II′ illustrate an image sensor according to an embodiment of the inventive concept.

[0017] Figure 7 Shown along Figure 4 sectional views taken along lines II′ and II-II′ illustrate an image sensor according to an embodiment of the inventive concept.

[0018] Figure 8 Shown along Figure 4 sectional views taken along lines II′ and II-II′ illustrate an image sensor according to an embodiment of the inventive concept.

[0019] Fig. 9 A cross-sectional view of an image sensor according to an embodiment of the inventive concept is illustrated.

[0020] Fig.10 A plan view of an image sensor according to an embodiment of the inventive concept is shown.

[0021] Fig.11A , Fig. 11B , Fig. 11C and Fig.11D Shown along Figure 4 sectional views taken along lines II′ and II-II′ illustrate a method of manufacturing an image sensor according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0022] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings.

[0023] It should be understood that the drawings are intended to illustrate the general features of the methods, structures and / or materials used in certain example embodiments and to supplement the written description provided below. However, these drawings are not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment, and should not be interpreted as limiting or restricting the range of values ​​or properties contained in the example embodiments. For example, for clarity, the relative thickness and position of molecules, layers, regions and / or structural elements may be reduced or exaggerated. The use of similar or identical reference numerals in the various drawings is intended to indicate the presence of similar or identical elements or features. In addition, it should be understood that when a first layer or element is described below as being "disposed on" a second layer or element, or "on" a second layer or element, the first layer or element may be directly on the second layer or element, or there may be an intermediate layer or element between the first layer or element and the second layer or element.

[0024] As is customary in the field of the present invention, embodiments can be described and illustrated based on the block that performs one or more functions described. These blocks (herein may be referred to as units or modules, etc.) are physically implemented by analog and / or digital circuits, such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc., and may be optionally driven by firmware and / or software. For example, the circuit may be implemented in one or more semiconductor chips, or implemented on substrate supports such as printed circuit boards, etc. The circuit constituting the block may be implemented by dedicated hardware, or implemented by a processor (e.g., one or more programmed microprocessors and associated circuits), or implemented by a combination of dedicated hardware that performs some functions of the block and a processor that performs other functions of the block. Without departing from the scope of the present invention, each block of the embodiment may be physically divided into two or more interactive and discrete blocks. Similarly, without departing from the scope of the present invention, the block of the embodiment may be physically combined into more complex blocks.

[0025] Figure 1 A schematic block diagram of an image sensor according to an embodiment of the inventive concept is shown. Figure 2 A simplified circuit diagram of a sensor array of an image sensor according to an embodiment of the inventive concept is shown.

[0026] refer to Figure 1 , an image sensor according to some example embodiments of the inventive concept includes an active pixel sensor (APS) array 10, a row decoder 20, a row driver 30, a column decoder 40, a timing generator 50, a correlated double sampler (CDS) 60, an analog-to-digital converter (ADC) 70, and an input / output (I / O) buffer 80.

[0027] like Figure 2 As shown in , the APS array 10 includes a first portion 2 on which light is incident and a second portion 4 on which light is not incident. The first portion 2 and the second portion 4 include pixels PX1 and PX2 arranged in two dimensions, respectively. The first portion 2 has a first pixel PX1 disposed thereon, and the first pixel PX1 converts the incident light into an electrical signal. The second portion 4 has a second pixel PX2 disposed thereon, and the second pixel PX2 can output an electrical signal generated by a pixel on which light is not incident. The first pixel PX1 in the first portion 2 and the second pixel PX2 in the second portion 4 can be driven by a plurality of driving signals, such as a row selection signal Row SEL, a reset signal Rx, and a charge transfer signal Tx provided from a row driver 30. The electrical signal generated from the APS array 10 is provided to the correlated double sampler 60.

[0028] The row driver 30 provides a number of driving signals for driving a number of pixels to the APS array 10 in response to the decoding result obtained from the row decoder 20. In the case where the pixels are arranged in a matrix shape, a driving signal may be provided for each row.

[0029] The timing generator 50 provides timing signals and control signals to the row decoder 20 and the column decoder 40 .

[0030] The correlated double sampler 60 receives the electrical signal generated from the APS array 10, and holds and samples the received electrical signal. The correlated double sampler 60 may perform a double sampling operation to sample a specific noise level and signal level of the electrical signal, and output a difference level corresponding to the difference between the noise level and the signal level.

[0031] The analog-to-digital converter 70 converts an analog signal corresponding to the difference level received from the correlated double sampler 60 into a digital signal and outputs the converted digital signal.

[0032] The input / output buffer 80 latches the digital signals and then sequentially outputs the latched digital signals to an image signal processor (not shown) in response to a decoding result obtained from the column decoder 40 .

[0033] Figure 3 A circuit diagram of a pixel of an image sensor according to an embodiment of the inventive concept is shown.

[0034] refer to Figure 3 , the first pixel PX1 and the second pixel PX2 include a photoelectric conversion device PD that converts incident light into an electrical signal, and also include a reading device that reads the electrical signal generated from the photoelectric conversion device PD. Figure 3 The reading device shown in the figure includes a transmission gate TG, a reset device RG, a drive device DG and a selection device SG. The drive signals (e.g., a charge transfer signal Tx, a reset signal Rx and a row selection signal Row SEL) of the transmission gate TG, the reset device RG and the selection device SG are commonly connected to the pixels included in the same row. Hereinafter, a single photoelectric conversion device PD will be described.

[0035] The photoelectric conversion device PD generates and accumulates photocharges corresponding to the amount of external incident light. For example, the photoelectric conversion device PD may include one of the following items: a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), and a combination thereof. The photoelectric conversion device PD is connected to a transmission gate TG. The transmission gate TG transfers the accumulated charge to the floating diffusion region FD.

[0036] The floating diffusion region FD receives accumulated charges generated in the photoelectric conversion device PD. The floating diffusion region FD may have parasitic capacitance and thus may accumulatively store charges. The floating diffusion region FD may be electrically connected to the driving device DG and may control the driving device DG.

[0037] The transfer gate TG transfers charges from the photoelectric conversion device PD to the floating diffusion region FD. The transfer gate TG may be composed of one device and may be controlled in response to a charge transfer signal Tx.

[0038] The reset device RG periodically resets the floating diffusion region FD and can be controlled in response to a reset signal Rx. The reset device RG includes a source connected to the floating diffusion region FD and a drain connected to a power supply voltage VDD. When the reset signal Rx turns on the reset device RG, the power supply voltage VDD connected to the drain of the reset device RG is provided to the floating diffusion region FD.

[0039] The driving device DG combined with a constant current source (not shown) functions as a source follower amplifier, amplifying a change in the potential of the floating diffusion region FD receiving the photocharges accumulated in the photoelectric conversion device PD. The driving device DG outputs the amplified potential to the output line Vout.

[0040] The selection device SG is used to select each row of pixels to be read out. The selection device SG can be driven by the row selection signal RowSEL, and when turned on, transmits the power supply voltage VDD connected to the drain of the selection device SG to the drain of the driving device DG.

[0041] Figure 4 A plan view of an image sensor according to an embodiment of the inventive concept is shown. Figure 5 Shown along Figure 4 sectional views taken along lines II′ and II-II′ illustrate an image sensor according to an embodiment of the inventive concept.

[0042] refer to Figure 4 and Figure 5 , the semiconductor layer 100 includes a first portion 2, a second portion 4 and a third portion 6. The second portion 4 may be located around the first portion 2 of the semiconductor layer 100, and the third portion 6 may be located around the second portion 4 of the semiconductor layer 100. For example, the first portion 2 is a light receiving region, the second portion 4 is a light shielding region, and the third portion 6 is an input / output region. The semiconductor layer 100 may be, for example, a silicon semiconductor layer, a germanium semiconductor layer, a silicon germanium semiconductor layer, a II-VI compound semiconductor layer, a III-V compound semiconductor layer, or a silicon on insulator (SOI) semiconductor layer. The semiconductor layer 100 has a first surface 1a and a second surface 1b. The first surface 1a and the second surface 1b may face each other.

[0043] The first device isolation layer DTI1 is disposed in the first portion 2 and the second portion 4 of the semiconductor layer 100. The first device isolation layer DTI1 may penetrate the semiconductor layer 100. For example, the first device isolation layer DTI1 may have a first surface coplanar with the first surface 1a of the semiconductor layer 100, and may also have a second surface opposite to the first surface of the first device isolation layer DTI1 and coplanar with the second surface 1b of the semiconductor layer 100. The first device isolation layer DTI1 may contact the lowermost interlayer dielectric layer 201a of the interlayer dielectric layers 201 and 201a included in the wiring structure 200 to be described below. The first device isolation layer DTI1 defines a first pixel PX1 and a second pixel PX2 of the semiconductor layer 100. The first pixel PX1 is disposed in the first portion 2 of the semiconductor layer 100, and the second pixel PX2 is disposed in the second portion 4 of the semiconductor layer 100. The first device isolation layer DTI1 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon nitride layer such as AlO 2 or HfO 2 The present invention may be composed of one or more dielectric layers, semiconductor materials such as polysilicon, and metal materials such as tungsten, copper or aluminum.

[0044] The protective isolation layer SL is disposed in the third portion 6 of the semiconductor layer 100. The protective isolation layer SL may penetrate the semiconductor layer 100. For example, the protective isolation layer SL may have a first surface coplanar with the first surface 1a of the semiconductor layer 100, and may also have a second surface opposite to the first surface of the protective isolation layer SL and coplanar with the second surface 1b of the semiconductor layer 100. The protective isolation layer SL may be in contact with the wiring dielectric layer 209 to be described below. The protective isolation layer SL defines a through-hole region TVR in the third portion 6 of the semiconductor layer 100. The protective isolation layer SL may have a polygonal or annular shape. Alternatively, the protective isolation layer SL may have a polygonal or circular grid structure. The protective isolation layer SL may include one or more of a silicon nitride layer, a tantalum oxide layer, and a hafnium oxide layer.

[0045] The photoelectric conversion devices PD are disposed in the first pixel PX1 and the second pixel PX2 of the semiconductor layer 100. The photoelectric conversion devices PD may be arranged spaced apart in a first direction X and a second direction Y intersecting the first direction X. The photoelectric conversion devices PD in the first portion 2 of the semiconductor layer 100 may individually receive light incident on the second surface 1b of the semiconductor layer 100. The photoelectric conversion devices PD may include, for example, n-type impurities.

[0046] The wiring structure 200 is disposed on the first surface 1a of the semiconductor layer 100. The wiring structure 200 includes interlayer dielectric layers 201 and 201a, a first connection line 203, a second connection line 205, a through hole 207, a transmission gate TG, and a wiring dielectric layer 209. The interlayer dielectric layers 201 and 201a are sequentially stacked on the first surface 1a of the semiconductor layer 100. The interlayer dielectric layers 201 and 201a may include, for example, a silicon oxide layer or a silicon nitride layer. The first connection line 203 and the second connection line 205 may be disposed in the interlayer dielectric layers 201 and 201a, respectively. The first connection line 203 is disposed on the first portion 2 and the second portion 4 of the semiconductor layer 100. The second connection line 205 is disposed on the third portion 6 of the semiconductor layer 100. One of the second connection lines 205 that is closer to the semiconductor layer 100 than any other second connection line 205 is disposed on the wiring dielectric layer 209. For example, the first connection line 203 and the second connection line 205 may include a metal material such as copper or tungsten. The through hole 207 is provided on the third portion 6 of the semiconductor layer 100. The through hole 207 may be provided in the interlayer dielectric layers 201 and 201a. The through hole 207 may connect the second connection lines 205 to each other. Although not shown, through holes such as the through hole 207 may also be provided on the first portion 2 and the second portion 4 of the semiconductor layer 100. The through hole 207 may include a metal material such as copper or tungsten.

[0047] The transmission gate TG is disposed on the first surface 1a of the semiconductor layer 100. The transmission gate TG is disposed on the first portion 2 and the second portion 4 of the semiconductor layer 100. The transmission gate TG may be arranged to correspond to the photoelectric conversion device PD of the first pixel PX1 and the second pixel PX2. The transmission gate TG is covered by the lowermost interlayer dielectric layer 201a closest to the first surface 1a of the semiconductor layer 100. The wiring dielectric layer 209 is between the lowermost interlayer dielectric layer 201a and the first surface 1a on the third portion 6 of the semiconductor layer 100. The wiring dielectric layer 209 covers the first surface 1a on the third portion 6 of the semiconductor layer 100. The wiring dielectric layer 209 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a thermal oxide layer. In other embodiments, the wiring dielectric layer 209 is not provided. In such other embodiments, the interlayer dielectric layer 201 may be disposed between the first surface 1a of the semiconductor layer 100 and the second connection line 205 adjacent to the first surface 1a of the semiconductor layer 100.

[0048] The anti-reflection layer 300 is disposed on the second surface 1b of the semiconductor layer 100. The anti-reflection layer 300 is disposed on the first portion 2, the second portion 4, and the third portion 6 of the semiconductor layer 100. The anti-reflection layer 300 on the third portion 6 of the semiconductor layer 100 electrically insulates the semiconductor layer 100 from a pad 520 to be described below. The anti-reflection layer 300 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a high-k dielectric layer such as a hafnium oxide layer and an aluminum oxide layer.

[0049] The grid pattern 400 is disposed on the anti-reflection layer 300. For example, the grid pattern 400 may be disposed on the second surface 1b on the first portion 2 of the semiconductor layer 100. The grid pattern 400 may overlap with the first device isolation layer DTI1 and extend along the first device isolation layer DTI1. The grid pattern 400 includes a first segment P1 and a second segment P2. The first segment P1 extends in the first direction X and is spaced apart from each other in the second direction Y. The second segment P2 extends in the second direction Y and is spaced apart from each other in the first direction X. The first segment P1 and the second segment P2 are connected to a light shielding pattern 410 to be described below. The grid pattern 400 may have a polygonal grid structure.

[0050] The grid pattern 400 exposes the photoelectric conversion device PD in the first pixel PX1 provided in the semiconductor layer 100. The grid pattern 400 may be composed of a plurality of layers. The grid pattern 400 may include a first grid pattern 401 (hereinafter may be referred to as the first pattern 401) and a second grid pattern 403 (hereinafter may be referred to as the second pattern 403) sequentially stacked on the anti-reflection layer 300. The first pattern 401 may include a conductive material. For example, the first pattern 401 may include one or more of a metal and a conductive metal nitride. The first pattern 401 may include, for example, one or more of titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum (Al), and copper (Cu). The first pattern 401 may have a thickness of about 1000 mm. to about The second pattern 403 is disposed on the first pattern 401. The second pattern 403 may include an organic material. The second pattern 403 may include a material having a refractive index less than a refractive index of a color filter 530 to be described below. The second pattern 403 may include a low-refractive material having a refractive index equal to or less than about 1.4. The second pattern 403 may have a thickness greater than the first thickness T1 of the first pattern 401.

[0051] The light shielding pattern 410 is disposed on the anti-reflection layer 300. For example, the light shielding pattern 410 may be placed on the second surface 1b on the second portion 4 of the semiconductor layer 100. The light shielding pattern 410 may completely cover the second portion 4 of the semiconductor layer 100. For example, the light shielding pattern 410 may cover the photoelectric conversion device PD disposed in the second pixel PX2 of the semiconductor layer 100. The grid pattern 400 may cover the side surface 411 of the light shielding pattern 410. In some embodiments, the first pattern 401 of the grid pattern 400 may cover the side surface 411 of the light shielding pattern 410 and contact the light shielding pattern 410. The grid pattern 400 may cover the side surface 411 of the light shielding pattern 410 and the adjacent portion of the top surface 410a. For example, the grid pattern 400 may extend from the first portion 2 of the semiconductor layer 100 to the second portion 4. In other embodiments, the grid pattern 400 may cover a portion of the side surface 411 of the light shielding pattern 410 and expose the top surface 410 a of the light shielding pattern 410 .

[0052] The light shielding pattern 410 may be composed of a single layer. The light shielding pattern 410 may have a thickness of about to about The second thickness T2 of the light shielding pattern 410 may be greater than the first thickness T1 of the first pattern 401 (T2>T1). The top surface 410a of the light shielding pattern 410 may be located at a first height that is higher than the second height of the top surface 401a of the first pattern 401. The first height and the second height are respective distances from the second surface 1b of the semiconductor layer 100, or in other words, the first height and the second height are defined or obtained relative to the second surface 1b of the semiconductor layer 100. For example, the distance between the top surface of the first pattern 401 and the second surface 1b of the semiconductor layer 100 is smaller than the distance between the top surface 410a of the light shielding pattern 410 and the second surface 1b of the semiconductor layer 100. For example, the light shielding pattern 410 may include a metal material, such as tungsten (W).

[0053] The through hole 510 is arranged in the third part 6 of the semiconductor layer 100. For example, each through hole 510 can be arranged in the through hole region TVR of the semiconductor layer 100. As another example, a plurality of through holes 510 can be arranged in the through hole region TVR of the semiconductor layer 100. The through hole 510 can penetrate the semiconductor layer 100, the anti-reflection layer 300 and the wiring dielectric layer 209 and be connected to the second connection line 205 of the wiring structure 200. A pad 520 is arranged on the third part 6 of the semiconductor layer 100. For example, the pad 520 can be arranged on the anti-reflection layer 300, and the anti-reflection layer 300 is placed on the second surface 1b on the third part 6 of the semiconductor layer 100. The pads 520 can be electrically insulated from each other. The pads 520 can be arranged on the through hole 510 and connected to the through hole 510. Each through hole 510 and a corresponding pad of the pad 520 overlapping therewith can be integrally combined into a single body.

[0054] In some embodiments, at least one of the pads 520 may be connected to the light shielding pattern 410. For example, Figure 4 As shown in, in some embodiments, at least one of the pads 520 may extend along the first direction X at the connection pad 521 to be physically and / or electrically connected to the light shielding pattern 410. Therefore, at least one of the pads 520 may be physically and / or electrically connected to the grid pattern 400 through the light shielding pattern 410. The grid pattern 400 connected to at least one of the pads 520 may be connected to the second connection line 205 through the through hole 510. In other embodiments, the pads 520 may be physically and / or electrically spaced from the light shielding pattern 410 and the grid pattern 400. In such other embodiments, the pads 520 are not physically and / or electrically connected to the light shielding pattern 410. The light shielding pattern 410 connected to the grid pattern 400 may be electrically connected to the second connection line 205 of the wiring structure 200 and / or the first connection line 203 of the wiring structure 200 disposed on the second part 4 of the semiconductor layer 100 through a through hole (not shown) disposed in the second part 4 of the semiconductor layer 100.

[0055] The grid pattern 400 may be used as a path for externally introduced electrostatic charge to be discharged from the active pixel sensor array 10. For example, the electrostatic charge may be discharged to the second connection line 205 through the grid pattern 400, the light shielding pattern 410, the at least one pad 520, and the through hole 510 connected to the at least one pad 520. As another example, the electrostatic charge may be discharged to the first connection line 203 and / or the second connection line 205 through the grid pattern 400, the light shielding pattern 410, and the through hole (not shown). In this case, a ground voltage or a negative voltage may be applied to the first connection line 203 and / or the second connection line 205.

[0056] According to some example embodiments of the inventive concept, the grid pattern 400 may have a stacking structure different from that of the light shielding pattern 410. The first pattern 401 of the grid pattern 400 may include a metal material thinner than the light shielding pattern 410, and thus may minimize light absorption while serving as a path for static charges to be discharged. The second pattern 403 of the grid pattern 400 may include a low-refractive material, and thus may refract light incident from an edge adjacent to the color filter 530 and allow the associated pixel to receive the refracted light. Therefore, an image sensor with reduced crosstalk and improved luminous efficiency may be provided.

[0057] The color filter 530 is disposed on the first portion 2 of the semiconductor layer 100. For example, the color filter 530 may be disposed on the second surface 1b of the semiconductor layer 100 and arranged to correspond to the photoelectric conversion device PD in the first pixel PX1. The color filter 530 may cover the grid pattern 400 and the anti-reflection layer 300. The color filter 530 may include a high refractive material having a refractive index equal to or greater than about 1.5.

[0058] The color filter layer 540 is disposed on the second portion 4 of the semiconductor layer 100. For example, the color filter layer 540 may be disposed on the second surface 1b of the semiconductor layer 100 and may cover the photoelectric conversion device PD in the second pixel PX2. The color filter layer 540 may cover the anti-reflection layer 300. The pad 520 is exposed by the color filter 530 and the color filter layer 540. The microlens MR is disposed on the color filter 530. The microlens MR may be disposed to correspond to the photoelectric conversion device PD in the first pixel PX1. The color filter layer 540 and the pad 520 are exposed by the microlens MR.

[0059] Figure 6 Shown along Figure 4 The cross-sectional view taken along the lines II′ and II-II′ of FIG. 1 shows an image sensor according to an embodiment of the inventive concept. Figure 6 Zhongyu Figure 5 The description provided below will focus on Figure 6 About Figure 5 The characteristics described are different from those of the others.

[0060] refer to Figure 6, the shielding structure 410A is disposed on the second portion 4 of the semiconductor layer 100. For example, the shielding structure 410A is disposed on the second surface 1b on the second portion 4 of the semiconductor layer 100. The shielding structure 410A covers the photoelectric conversion device PD disposed in the second pixel PX2. The shielding structure 410A includes a light shielding pattern 410, a first pattern 401, and a second pattern 403 sequentially stacked on the anti-reflection layer 300. The first pattern 401 disposed on the first portion 2 may extend onto the second portion 4 of the semiconductor layer 100. The first pattern 401 covers the side surface 411 and the top surface 410a of the light shielding pattern 410. The first pattern 401 may contact and be connected to the light shielding pattern 410. On the second portion 4 of the semiconductor layer 100, the second pattern 403 disposed on the first pattern 401 may extend along the first pattern 401 on the second portion 4 of the semiconductor layer 100. The second pattern 403 covers the side surface and the top surface of the first pattern 401 disposed on the second portion 4 of the semiconductor layer 100. For example, the grid pattern 400 may have a third thickness T3 that is less than the fourth thickness T4 of the shielding structure 410A (T3<T4). The grid pattern 400 may have a top surface at a height lower than the top surface of the shielding structure 410A, which is a distance from the second surface 1b of the semiconductor layer 100. The pads 520 are exposed by the shielding structure 410A, the color filter layer 540, and the microlens MR. Each pad 520 may have a fifth thickness T5 that is less than the third thickness T3 of the grid pattern 400 and less than the fourth thickness T4 of the shielding structure 410A (T5<T3, T5<T4). The fifth thickness T5 of the pad 520 may be substantially the same as the second thickness T2 of the light shielding pattern 410.

[0061] Figure 7 Shown along Figure 4 The cross-sectional view taken along the lines II′ and II-II′ of FIG. 1 shows an image sensor according to an embodiment of the inventive concept. Figure 7 Zhongyu Figure 5 The description provided below will focus on Figure 7 About Figure 5 The characteristics described are different from those of the others.

[0062] refer to Figure 7 The first device isolation layer DTI1 extends from the second surface 1b toward the first surface 1a in the semiconductor layer 100. The first device isolation layer DTI1 is spaced apart from the lowermost interlayer dielectric layer 201a of the wiring structure 200. For example, the first surface of the first device isolation layer DTI1 (i.e., Figure 7 The lower surface shown in FIG. 1 is not coplanar with the first surface 1a of the semiconductor layer 100, and the second surface of the first device isolation layer DTI1 (ie, the lower surface shown in FIG. 1) is not coplanar with the first surface 1a of the semiconductor layer 100. Figure 7The upper surface shown in FIG. 1 is coplanar with the second surface 1 b of the semiconductor layer 100. The first surface of the first device isolation layer DTI1 is located at a height between the first surface 1 a and the second surface 1 b of the semiconductor layer 100.

[0063] Figure 8 Shown along Figure 4 The cross-sectional view taken along the lines II′ and II-II′ of FIG. 1 shows an image sensor according to an embodiment of the inventive concept. Figure 8 Zhongyu Figure 5 The description provided below will focus on Figure 8 About Figure 5 The characteristics described are different from those of the others.

[0064] refer to Figure 8 , the first photoelectric conversion device PD1 and the second photoelectric conversion device PD2 are disposed in each of the first pixel PX1 and the second pixel PX2. For example, a pair of the first photoelectric conversion device PD1 and the second photoelectric conversion device PD2 are disposed in each of the first pixel PX1 and the second pixel PX2. The second device isolation layer DTI2 may be disposed in each of the first pixel PX1 and the second pixel PX2. The second device isolation layer DTI2 may be disposed between a pair of the first photoelectric conversion device PD1 and the second photoelectric conversion device PD2 in each of the first pixel PX1 and the second pixel PX2, so that the pair of the first photoelectric conversion device PD1 and the second photoelectric conversion device PD2 are physically separated from each other. In some embodiments, although not shown, the second device isolation layer DTI2 is connected to the first device isolation layer DTI1. In other embodiments, the second device isolation layer DTI2 is not connected to the first device isolation layer DTI1. The second device isolation layer DTI2 extends from the second surface 1b of the semiconductor layer 100 toward the first surface 1a. The second device isolation layer DTI2 contacts the second surface 1b of the semiconductor layer 100 and is spaced apart from the first surface 1a of the semiconductor layer 100. For example, the second device isolation layer DTI2 has a first surface located at a height between the first surface 1a and the second surface 1b of the semiconductor layer 100 (ie, as shown in FIG. 1 ). Figure 8 The second device isolation layer DTI2 has a second surface coplanar with the second surface 1b of the semiconductor layer 100 (ie, as shown in FIG. 1 ). Figure 8 The second device isolation layer DTI2 may include, for example, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer such as AlO 2 or HfO 2 One or more of the dielectric layers.

[0065] Fig. 9 A cross-sectional view of an image sensor according to an embodiment of the inventive concept is illustrated.

[0066] refer to Fig. 9 , the semiconductor layer 100 is provided with a pair of first floating diffusion regions FD1 and second floating diffusion regions FD2 therein. For example, the pair of first floating diffusion regions FD1 and second floating diffusion regions FD2 are provided at first pixels and second pixels of the semiconductor layer 100 (see Figure 5 The first floating diffusion region FD1 and the second floating diffusion region FD2 may be disposed adjacent to the first surface 1a of the semiconductor layer 100. The second floating diffusion region FD2 is disposed in the semiconductor layer 100 on one side of the transmission gate TG. Figure 5 The transmission gate TG, Fig. 9 The transmission gate TG has a portion buried in the semiconductor layer 100. The through-electrode structure TES is provided in the semiconductor layer 100. Although not shown, the through-electrode structure TES may penetrate the first device isolation layer (see Figure 5 The through-electrode structure TES may be configured to correspond to one of the first pixel PX1 and the second pixel PX2. Each through-electrode structure TES includes a through-electrode 701 and a through-dielectric pattern 703. The through-dielectric pattern 703 may surround the sidewall of the through-electrode 701. The through-dielectric pattern 703 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride. The through-electrode 701 may include, for example, n-type doped polysilicon or p-type doped polysilicon.

[0067] The buried dielectric pattern 705 is disposed between each through-electrode structure TES and the first surface 1a of the semiconductor layer 100. The buried dielectric pattern 705 has a surface coplanar with the first surface 1a of the semiconductor layer 100 (ie, Fig. 9 The buried dielectric pattern 705 may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0068] The wiring structure 200 is disposed on the first surface 1a of the semiconductor layer 100. The wiring structure 200 includes a plurality of interlayer dielectric layers 201, a connection line 210, a first connection through hole 211, and a second connection through hole 213. The first connection through hole 211 is connected to the first floating diffusion region FD1, penetrating at least one interlayer dielectric layer 201. The second connection through hole 213 is connected to the through electrode 701 of the through electrode structure TES, penetrating the buried dielectric pattern 705 and at least one interlayer dielectric layer 201. The connection line 210 may be disposed on at least one interlayer dielectric layer 201, and connects the first connection through hole 211 and the second connection through hole 213 to each other. The connection line 210, the first connection through hole 211, and the second connection through hole 213 may include, for example, one or more of a metal (e.g., tungsten, copper, or aluminum) and a metal nitride (e.g., tantalum nitride, titanium nitride, or tungsten nitride).

[0069] The grid pattern 400 is disposed on the second surface 1b of the semiconductor layer 100. The grid pattern 400 may be disposed on the first device isolation layer (see Figure 5 The grid pattern 400 may be connected to the light shielding pattern (see Figure 5 410). A dielectric layer 709 is disposed on the color filter 530. The dielectric layer 709 may cover a top surface of the color filter 530. The dielectric layer 709 may include, for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0070] The contact plug structure 710 is disposed on the through electrode structure TES. The contact plug structure 710 penetrates the anti-reflection layer 300, the grid pattern 400, the color filter 530 and the dielectric layer 709. The contact plug structure 710 is connected to the through electrode structure TES. Each contact plug structure 710 includes a contact plug 713 and a spacer 711. The contact plug 713 penetrates the anti-reflection layer 300, the grid pattern 400, the color filter 530 and the dielectric layer 709. The spacer 711 may surround the sidewall of the contact plug 713. For example, the contact plug 713 may include a metal material, such as tungsten. For example, the spacer 711 may include a dielectric material, such as a silicon oxide layer or a silicon nitride layer.

[0071] The bottom electrode 720 may be disposed on the dielectric layer 709. The bottom electrode 720 may be disposed to correspond to the photoelectric conversion device PD. The bottom electrodes 720 are spaced apart from each other. The contact plug structure 710 may be disposed to correspond to the bottom electrode 720 and electrically connected to the bottom electrode 720. The bottom electrode 720 may include a transparent conductive material. For example, the bottom electrode 720 may include one or more of ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), and an organic transparent conductive material.

[0072] The photoelectric conversion layer PDL is disposed on the bottom electrode 720. For example, the photoelectric conversion layer PDL may include an organic photoelectric conversion layer. The organic photoelectric conversion layer may include a p-type organic semiconductor material and an n-type organic semiconductor material, and the p-type and n-type semiconductor materials may form a pn junction. For example, the organic photoelectric conversion layer PDL may include quantum dots or chalcogenides.

[0073] The top electrode 730 is disposed on the photoelectric conversion layer PDL. The top electrode 730 may include a transparent conductive material. For example, the top electrode 730 may include one or more of ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), and an organic transparent conductive material.

[0074] The capping layer 740 is disposed on the top electrode 730. The capping layer 740 may include a dielectric material. For example, the capping layer 740 may include one or more of aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0075] The microlens MR is disposed on the cover layer 740 .

[0076] Fig.10 A plan view of an image sensor according to an embodiment of the inventive concept is shown.

[0077] refer to Fig.10 , the grid pattern 400 includes an outer segment UP, a first segment P1 and a second segment P2. The outer segment UP includes a pair of third segments P3 and a pair of fourth segments P4. The pair of third segments P3 extends in the second direction Y and is spaced apart from each other in the first direction X. The pair of fourth segments P4 extends in the first direction X and is spaced apart from each other in the second direction Y. The ends of the pair of third segments P3 are connected to the ends of the pair of fourth segments P4. Therefore, the outer segment UP can have a rectangular ring shape. The first segment P1 and the second segment P2 are arranged inside the outer segment UP. The first segment P1 extends in the first direction X and is spaced apart from each other in the second direction Y. The second segment P2 extends in the second direction Y and is spaced apart from each other in the first direction X. The first segment P1 and the second segment P2 can be connected to the outer segment UP. The shading pattern 410 surrounds the outer side wall of the outer segment UP of the grid pattern 400.

[0078] FIG. 11A to FIG. 11D Shown along Figure 4 sectional views taken along lines II′ and II-II′ illustrate a method of manufacturing an image sensor according to an embodiment of the inventive concept.

[0079] refer to Fig.11A, a semiconductor layer 100 is provided. The semiconductor layer 100 has a first surface 1a and a second surface 1b facing each other. The semiconductor layer 100 includes a first portion 2, a second portion 4, and a third portion 6. A photoelectric conversion device PD is formed in the first portion 2 and the second portion 4 of the semiconductor layer 100. The photoelectric conversion device PD may be formed by performing an ion implantation process in which impurities are implanted into the semiconductor layer 100 through the first surface 1a. For example, the photoelectric conversion device PD may be formed by implanting n-type impurities.

[0080] A wiring structure 200 is formed on a first surface 1a of a semiconductor layer 100. The wiring structure 200 includes a transmission gate TG, interlayer dielectric layers 201 and 201a, a first connection line 203, a second connection line 205, a through hole 207, and a wiring dielectric layer 209. The transmission gate TG is formed on the first surface 1a on the first portion 2 and the second portion 4 of the semiconductor layer 100. The wiring dielectric layer 209 is formed on the first surface 1a on the third portion 6 of the semiconductor layer 100. The interlayer dielectric layers 201 and 201a are sequentially formed on the first surface 1a of the semiconductor layer 100. The lowermost interlayer dielectric layer 201a of the interlayer dielectric layers 201 and 201a covers the transmission gate TG and the wiring dielectric layer 209. The first connection line 203 and the second connection line 205 are disposed in the interlayer dielectric layers 201 and 201a. The first connection line 203 is disposed on the first portion 2 and the second portion 4 of the semiconductor layer 100. The second connection line 205 is disposed on the third portion 6 of the semiconductor layer 100. The first connection line 203 and the second connection line 205 are covered by the interlayer dielectric layers 201 and 201a. A through hole 207 is formed in the interlayer dielectric layers 201 and 201a. The through hole 207 is disposed on the third portion 6 of the semiconductor layer 100. The through hole 207 can connect the second connection lines 205 to each other.

[0081] A first device isolation layer DTI1 is formed in the first portion 2 and the second portion 4 of the semiconductor layer 100. The first device isolation layer DTI1 may be formed by etching the semiconductor layer 100 to form a first trench TH1 and filling the first trench TH1 with a dielectric material and / or a conductive material. For example, as shown in the figure, the first trench TH1 may be formed by etching the second surface 1b of the semiconductor layer 100. As another example, the first trench TH1 may be formed by etching the first surface 1a of the semiconductor layer 100 before forming the wiring structure 200. The first device isolation layer DTI1 may define a first pixel PX1 and a second pixel PX2 in the first portion 2 and the second portion 4 of the semiconductor layer 100. The first pixel PX1 is disposed in the first portion 2 of the semiconductor layer 100, and the second pixel PX2 may be disposed in the second portion 4 of the semiconductor layer 100. The photoelectric conversion device PD is disposed in the first pixel PX1 and the second pixel PX2.

[0082] 11B, a protection isolation layer SL is formed in the third portion 6 of the semiconductor layer 100. The protection isolation layer SL may be formed by forming a second trench TH2 in the third portion 6 of the semiconductor layer 100 and filling the second trench TH2 with a dielectric material. In some embodiments, the second trench TH2 may be formed to penetrate the third portion 6 of the semiconductor layer 100. The protection isolation layer SL may define a through hole region TVR in the third portion 6 of the semiconductor layer 100.

[0083] An anti-reflection layer 300 is formed on the second surface 1b of the semiconductor layer 100. The anti-reflection layer 300 covers the second surface 1b of the semiconductor layer 100, the second surface of the first device isolation layer DTI1 (ie, Fig. 11B The upper surface shown in FIG. 1 ) and the second surface of the protective isolation layer SL (ie, as shown in FIG. 1 ) Fig. 11B The second trench TH2 is formed in the third portion 6 of the semiconductor layer 100. The second trench TH2 is formed in the third portion 6 of the semiconductor layer 100. For example, the hole VH is formed in the through hole region TVR of the semiconductor layer 100. The hole VH can expose one or more of the second connection lines 205, penetrate the anti-reflection layer 300, the semiconductor layer 100 and the wiring dielectric layer 209.

[0084] A light shielding layer 601 is formed on the second surface 1b of the semiconductor layer 100. The light shielding layer 601 is formed on the first portion 2, the second portion 4, and the third portion 6 of the semiconductor layer 100. The light shielding layer 601 fills the hole VH and covers the top surface of the anti-reflection layer 300. The light shielding layer 601 may be formed to have a thickness of about to about The light shielding layer 601 may include a metal material, such as tungsten (W). A first mask pattern 603 is formed on the light shielding layer 601. The first mask pattern 603 is formed on the second portion 4 and the third portion 6 of the semiconductor layer 100. For example, the first mask pattern 603 exposes the light shielding layer 601 formed on the first portion 2 of the semiconductor layer 100, and also exposes a portion of the light shielding layer 601 formed on the third portion 6 of the semiconductor layer 100. The first mask pattern 603 may include, for example, a photoresist material.

[0085] refer to Fig. 11C, an etching process is performed in which the first mask pattern 603 is used as an etching mask to etch the light shielding layer 601. Therefore, a light shielding pattern 410 is formed on the second portion 4 of the semiconductor layer 100, and a pad 520 and a through hole 510 are formed on / in the third portion 6 of the semiconductor layer 100. The light shielding pattern 410 exposes the top surface of the anti-reflection layer 300 formed on the first portion 2 of the semiconductor layer 100. The light shielding pattern 410 covers the top surface of the anti-reflection layer 300 formed on the second portion 4 of the semiconductor layer 100. The through hole 510 is formed in the hole VH, and the pad 520 is formed on the through hole 510. For example, the pads 520 may be formed to be spaced apart from each other, and at least one of the pads 520 may be connected to the light shielding pattern 410. As another example, the pads 520 may be formed to be spaced apart from each other, and the pad 520 may not be connected to the light shielding pattern 410. The etching process may be a dry etching process. After the etching process, the remaining first mask pattern 603 is removed. The first mask pattern 603 may be removed by performing an ashing process or a stripping process.

[0086] A thin film layer 605 is formed on the second surface 1b of the semiconductor layer 100. The thin film layer 605 covers the top surface of the anti-reflection layer 300 formed on the first portion 2 of the semiconductor layer 100, the top surface and side surfaces of the light shielding pattern 410 formed on the second portion 4 of the semiconductor layer 100, and the top surface and side surfaces of the pad 520 formed on the third portion 6 of the semiconductor layer 100. The thin film layer 605 may be formed to have a thickness less than that of the light shielding pattern 410. The thin film layer 605 may be formed to have, for example, about 100 Å. to about The thin film layer 605 may include, for example, one or more of titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum (Al), and copper (Cu). A low-refractive layer 607 is formed on the thin film layer 605. The low-refractive layer 607 covers the top surface and the side surface of the thin film layer 605. The low-refractive layer 607 may include a low-refractive material having a refractive index equal to or less than about 1.4.

[0087] A second mask pattern 609 is formed on the low-refractive layer 607. The second mask pattern 609 is formed on the first portion 2 and the second portion 4 of the semiconductor layer 100. The second mask pattern 609 is formed to overlap with the first device isolation layer DTI1 formed in the first portion 2 of the semiconductor layer 100. The second mask pattern 609 is formed along the first device isolation layer DTI1 formed in the first portion 2 of the semiconductor layer 100. For example, the second mask pattern 609 may expose a portion of the low-refractive layer 607 formed on the first portion 2 of the semiconductor layer 100, a portion of the low-refractive layer 607 formed on the second portion 4 of the semiconductor layer 100, and the entire low-refractive layer 607 formed on the third portion 6 of the semiconductor layer 100. As another example, the second mask pattern 609 may expose a portion of the low-refractive layer 607 formed on the first portion 2 of the semiconductor layer 100, and the entire low-refractive layer 607 formed on the third portion 6 of the semiconductor layer 100. In this case, the second mask pattern 609 may cover the entire top surface of the low-refractive layer 607 formed on the second portion 4 of the semiconductor layer 100. The second mask pattern 609 may include, for example, a photoresist material.

[0088] refer to Fig.11D , an etching process is performed, wherein the second mask pattern 609 is used as an etching mask to etch the low refractive layer 607 and the thin film layer 605. Thus, a grid pattern 400 is formed on the first portion 2 of the semiconductor layer 100. The grid pattern 400 is formed to overlap with the first device isolation layer DTI1 formed in the first portion 2 of the semiconductor layer 100. The grid pattern 400 exposes the photoelectric conversion device PD formed in the first pixel PX1. The grid pattern 400 may cover a portion of the top surface and the side surface of the light shielding pattern 410, and the side surface and the top surface of the light shielding pattern 410 are adjacent to the first portion 2 of the semiconductor layer 100. The grid pattern 400 includes a first pattern 401 and a second pattern 403. The first pattern 401 is formed by the patterned thin film layer 605, and the second pattern 403 is formed by the patterned low refractive layer 607. The first pattern 401 may cover a portion of the top surface and the side surface of the light shielding pattern 410. The top surface of the pad 520 is exposed by the grid pattern 400. The etching process may be a dry etching process. After the etching process, the remaining second mask pattern 609 may be removed. The second mask pattern 609 is removed by performing an ashing process or a stripping process.

[0089] Return to reference Figure 5, a color filter 530 is formed on the second surface 1b of the semiconductor layer 100. The color filter 530 may be formed to correspond to the photoelectric conversion device PD formed in the first pixel PX1. A color filter layer 540 is formed on the second surface 1b of the semiconductor layer 100. The color filter layer 540 may be formed on the second portion 4 of the semiconductor layer 100, covering the light shielding pattern 410. The color filter 530 and the color filter layer 540 expose the pad 520 formed on the third portion 6 of the semiconductor layer 100. A microlens MR is formed on the color filter 530.

[0090] According to an example embodiment of the present invention, the grid pattern may be formed to have a stacking structure different from that of the light shielding pattern. The grid pattern may include a first pattern that includes a metal material and is thinner than the light shielding pattern, and thus the first pattern may minimize light absorption while serving as a path for electrostatic charges to be discharged. The grid pattern may include a second pattern formed of a low-refractive material, and thus the second pattern may refract light incident from an edge of a color filter adjacent to the color filter and allow the associated pixel to receive the refracted light. Thus, an image sensor with reduced crosstalk and improved luminous efficiency may be provided.

[0091] Although the inventive concept has been described in conjunction with some example embodiments shown in the accompanying drawings, it should be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and features of the inventive concept. It is obvious to those skilled in the art that various replacements, modifications and changes may be made to the disclosed embodiments without departing from the scope and spirit of the inventive concept.

Claims

1. An image sensor, comprising: a semiconductor layer including a first portion and a second portion, the semiconductor layer having a first surface and a second surface facing each other; a device isolation layer in the semiconductor layer and defining a plurality of pixels; a first grid pattern on the first surface of the semiconductor layer, on the first portion; and The light shielding pattern on the first surface of the semiconductor layer, on the second portion, wherein a top surface of the first grid pattern is located at a first height, a top surface of the light shielding pattern is located at a second height, the first height is lower than the second height, and the first height and the second height are defined relative to a first surface of the semiconductor layer, wherein the thickness of the first grid pattern is smaller than the thickness of the light shielding pattern, The first grid pattern extends on the second portion to cover a side surface of the light shielding pattern.

2. The image sensor according to claim 1, further comprising: a second grid pattern on the first grid pattern, The first grid pattern includes one or more of a metal and a metal nitride, and the second grid pattern includes a low-refractive material. 3 . The image sensor of claim 1 , wherein the first grid pattern extends on the second portion to expose a top surface of the light shielding pattern. 4 . The image sensor according to claim 1 , wherein the first grid pattern extends on the second portion to cover a top surface of the light shielding pattern.

5. The image sensor according to claim 1, further comprising: a second grid pattern on the first grid pattern, The side surface of the first grid pattern is aligned with the side surface of the second grid pattern. 6 . The image sensor of claim 1 , wherein the first grid pattern is disposed on the device isolation layer disposed in the first portion of the semiconductor layer.

7. The image sensor of claim 1 , wherein the pixel comprises: a plurality of first pixels in a first portion of the semiconductor layer; as well as a plurality of second pixels in a second portion of the semiconductor layer, The image sensor further includes a plurality of first photoelectric conversion devices in the first pixels and a plurality of second photoelectric conversion devices in the second pixels, The first grid pattern is configured to expose the first photoelectric conversion device, and the light shielding pattern covers the second photoelectric conversion device.

8. The image sensor of claim 1 , wherein the pixel comprises: a plurality of first pixels in a first portion of the semiconductor layer; as well as a plurality of second pixels in a second portion of the semiconductor layer, The image sensor further comprises: each pair of first photoelectric conversion devices in the first pixel and each pair of second photoelectric conversion devices in the second pixel, and The microlens is located on the first surface of the semiconductor layer and covers each pair of first photoelectric conversion devices.

9. The image sensor according to claim 1, wherein the semiconductor layer further comprises a third portion, The image sensor further comprises: A pad is provided on the third portion on the first surface of the semiconductor layer, and the first grid pattern is connected to the pad through the light shielding pattern. 10 . The image sensor according to claim 1 , wherein the device isolation layer penetrates the semiconductor layer and contacts the first surface and the second surface of the semiconductor layer. 11 . The image sensor according to claim 1 , wherein the device isolation layer is in contact with a first surface of the semiconductor layer and is spaced apart from a second surface of the semiconductor layer. 12 . The image sensor according to claim 1 , wherein a material of the first grid pattern is different from a material of the light shielding pattern.

13. The image sensor of claim 1 , wherein the pixels include a first pixel in a first portion of the semiconductor layer and a second pixel in a second portion of the semiconductor layer, The image sensor further comprises: a plurality of color filters on the first pixel; a color filter layer on the second portion; as well as A plurality of micro lenses on the color filter, The microlens exposes the color filter layer.

14. An image sensor, comprising: a semiconductor layer including a first portion and a second portion surrounding the first portion; a device isolation layer in the semiconductor layer and defining a plurality of pixels; a grid pattern on the semiconductor layer, the grid pattern extending along the device isolation layer on the first portion and comprising a first pattern; and The light shielding pattern on the semiconductor layer, on the second portion, wherein the thickness of the first pattern is smaller than the thickness of the light shielding pattern, and The first pattern covers the side surface of the light shielding pattern. The image sensor according to claim 14 , wherein the light shielding pattern comprises a single layer. 16 . The image sensor of claim 14 , wherein the grid pattern further comprises a low-refractive pattern on the first pattern. The image sensor according to claim 14 , wherein the first pattern comprises a metal material.

18. An image sensor, comprising: A semiconductor layer including a first portion and a second portion; a device isolation layer in the semiconductor layer and defining a plurality of pixels; a grid pattern on the semiconductor layer, on the first portion; as well as The light shielding structure on the semiconductor layer is on the second portion, wherein the thickness of the grid pattern is smaller than the thickness of the light shielding structure, The grid pattern extends on the second portion to cover a side surface of the light shielding structure.

19. The image sensor according to claim 18, wherein: The grid pattern includes a first pattern and a second pattern sequentially stacked on the semiconductor layer on the first portion, and The light shielding structure includes a light shielding pattern, a conductive pattern, and an organic pattern stacked on the semiconductor layer on the second portion, The first pattern is connected to the conductive pattern, and the second pattern is connected to the organic pattern.

Images