Magnetic shielding structure for MRAM array

Abstract

An embodiment of a packaged semiconductor device is provided, the packaged semiconductor device comprising: a semiconductor die having an active side and an opposing backside, the semiconductor die including a magnetoresistive random access memory (MRAM) cell array formed within an MRAM region on the active side of the semiconductor die; and a top cap comprising a soft magnetic material positioned on the backside of the semiconductor die, wherein the top cap includes a recess formed in a first major surface of the top cap, the first major surface facing the backside of the semiconductor die, and the recess is positioned above the MRAM cell array.

Description

Technical Field

[0001] The present disclosure relates generally to magnetoresistive random access memory (MRAM) systems and, more particularly, to magnetic shielding for MRAM. Background Art

[0002] MRAM is a memory technology that uses magnetic polarization to store data, compared to random access memory (RAM) technology, which uses charge to store data. A key benefit of MRAM is that it retains stored data even when system power is not applied, making it a suitable non-volatile memory for implementation in a variety of devices. Although MRAM technology is relatively new, it has significant application opportunities. Summary of the Invention

[0003] In one embodiment of the present disclosure, a packaged semiconductor device is provided, comprising: a semiconductor die having an active side and an opposing back side, the semiconductor die including a magnetoresistive random access memory (MRAM) cell array formed within an MRAM region on the active side of the semiconductor die; and a top cap comprising a soft magnetic material positioned on the back side of the semiconductor die, wherein the top cap includes a recess formed in a first major surface of the top cap, the first major surface facing the back side of the semiconductor die, and the recess being positioned over the MRAM cell array.

[0004] According to one aspect of the above embodiment, the sidewall of the recess is separated from the periphery of the MRAM cell array by a spacing distance.

[0005] Another aspect of the above embodiment provides that the semiconductor die further includes active circuitry, the active circuitry being formed in a circuitry region on the active side, the active circuitry being laterally adjacent to the MRAM cell array, and the first portion of the semiconductor die having a first thickness in the circuitry region.

[0006] Another aspect of the above embodiment provides that the second portion of the semiconductor die has a second thickness in the MRAM region, the second thickness being greater than the first thickness, the second portion forming a stack, the stack being positioned vertically adjacent to the MRAM cell array, and the recess being sized to fit over and surround the stack.

[0007] Still another aspect of the above embodiment provides that the recess is formed to a depth corresponding to a difference between a back side of the semiconductor die in the circuit region and a back side of the semiconductor die in the MRAM region.

[0008] Another still further aspect of the above embodiment provides that the first major surface of the top cover is in direct contact with the back side of the semiconductor die in the circuit area.

[0009] Still another aspect of the above embodiment provides that the packaged semiconductor device further comprises: a molded body directly contacting and attached to lateral edges of the top cover and the back side of the semiconductor die in the circuit area.

[0010] Another still further aspect of the above embodiment provides that the first major surface of the top cover is attached to the back side of the semiconductor die in the circuit area with an adhesive.

[0011] Another still further aspect of the above embodiment provides that the inner surface of the recess is attached to the sidewalls and back side of the stack with an adhesive.

[0012] Another further aspect of the above embodiment provides that the second portion of the semiconductor die has the first thickness in the MRAM region, and the inner surface of the recess is attached to the backside of the semiconductor die in the MRAM region with an adhesive.

[0013] Another aspect of the above embodiment is that the packaged semiconductor device further includes: a redistribution layer (RDL) structure, the RDL structure being formed on the active side of the semiconductor die, the RDL structure including a plurality of metal structures, the plurality of metal structures electrically contacting a plurality of die pads on the active side of the semiconductor die, the plurality of metal structures providing a plurality of external contact pads on an outermost surface of the RDL structure; and a plurality of solder balls being attached to the plurality of external contact pads.

[0014] Another aspect of the above embodiment provides that the packaged semiconductor device further includes: a bottom cover, the bottom cover including the soft magnetic material, the bottom cover having a second main surface positioned on the outermost surface of the RDL structure, wherein the bottom cover includes a plurality of openings aligned with the plurality of solder balls.

[0015] Still another aspect of the above embodiment provides that a combined height is measured between the second major surface of the bottom cover and the first major surface of the top cover, and a lateral spacing distance between a sidewall of the recess and a perimeter of the MRAM cell array has a value greater than the combined height.

[0016] Yet another additional aspect of the above embodiment provides that a lateral edge of the bottom cover overlaps at least a portion of a lateral width of a sidewall portion of the top cover.

[0017] Another still further aspect of the above embodiment provides that the semiconductor die is one of a plurality of semiconductor dies in a panel, the top cover is one of a plurality of top covers positioned on the back side of the plurality of semiconductor dies, the RDL structure is one of a plurality of RDL structures formed on the active side of the plurality of semiconductor dies, the plurality of solder balls are part of a larger plurality of solder balls attached to the plurality of external contact pads on the outermost surface of each of the plurality of RDL structures, and the bottom cover is one of a plurality of bottom covers positioned on the outermost surface of the plurality of RDL structures.

[0018] Another aspect of the above embodiment provides that the packaged semiconductor device further includes: a bottom cover, the bottom cover including a soft magnetic material positioned on the active side of the semiconductor die, wherein the bottom cover includes a plurality of openings, the plurality of openings are aligned with a plurality of die pads on the active side of the semiconductor die; and a plurality of solder balls, the plurality of solder balls being attached to the plurality of die pads.

[0019] Another additional aspect of the above embodiment provides that the packaged semiconductor device further includes: a printed circuit board (PCB), the PCB having a plurality of bonding pads on the front side of the PCB; and a bottom cover, the bottom cover including the soft magnetic material attached to the front side of the PCB, wherein the bottom cover includes a plurality of openings aligned with the plurality of bonding pads, wherein each bonding pad is exposed within each opening, and the plurality of solder balls are attached to the plurality of bonding pads through the plurality of openings in the bottom cover.

[0020] Another aspect of the above embodiment provides that the packaged semiconductor device further includes: a second top cover, the second top cover including the soft magnetic material, a second recess formed in the first main surface of the second top cover, wherein the semiconductor die further includes a second MRAM array, and the second recess is positioned on the second MRAM cell array.

[0021] Another aspect of the above embodiment provides that the semiconductor die further includes a second MRAM cell array, and the top cover further includes a second recess formed in the first major surface of the top cover, the second recess being positioned over the second MRAM cell array.

[0022] Another aspect of the above embodiment provides that the relative magnetic permeability of the soft magnetic material is greater than 50. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0024] Figure 1A and 1B is a block diagram depicting an example packaged semiconductor device including a magnetic shielding structure for an MRAM array according to some embodiments of the present disclosure.

[0025] Figure 2 and 3 is a block diagram depicting aspects of an example magnetic shield structure for an MRAM array, according to some embodiments of the present disclosure.

[0026] Figure 4A 、 4B 4C are block diagrams depicting example portions of magnetic shielding structures for an MRAM array according to some embodiments of the present disclosure.

[0027] Figure 5A 、 5B , 5C, 5D, 5E, 5F, 5G, 5H, 5I, and 5J are block diagrams depicting example methods for fabricating a packaged semiconductor device including a magnetic shielding structure for an MRAM array according to some embodiments of the present disclosure.

[0028] Figure 6A and 6B is a block diagram depicting an example device view of representative process steps of a wafer-level process for fabricating a packaged semiconductor device including a magnetic shield structure for an MRAM array according to some embodiments of the present disclosure.

[0029] Figure 7A 、 7B 7C, 7D, 7E, 7F, 7G, and 7H are block diagrams depicting another example method for fabricating a packaged semiconductor device including a magnetic shielding structure for an MRAM array according to some embodiments of the present disclosure.

[0030] Figure 8A 、 8B 8C are block diagrams depicting example alternative process steps for fabricating a packaged semiconductor device including a magnetic shield structure for an MRAM array, according to some embodiments of the present disclosure.

[0031] Figure 9A and 9B is a block diagram depicting an example device view of representative process steps of a wafer-level process for fabricating a packaged semiconductor device including a magnetic shielding structure for an MRAM subarray according to some embodiments of the present disclosure.

[0032] Figure 10A and 10Bis a block diagram depicting an example device view of further embodiments of a packaged semiconductor device according to some embodiments of the present disclosure.

[0033] The present invention is illustrated by way of example and not limitation in the accompanying drawings, in which like reference numerals designate like elements unless otherwise indicated. Elements in the drawings are illustrated for simplicity and clarity and have not necessarily been drawn to scale. DETAILED DESCRIPTION

[0034] The following sets forth a detailed description of various embodiments that is intended to illustrate the present invention and is not to be construed as limiting.

[0035] Overview

[0036] Typically, magnetoresistive random access memory (MRAM) includes a large number of magnetic bit cells formed on a semiconductor substrate, where each cell represents a data bit. Information is written to the bit cell by changing the magnetization direction of the magnetic element within the bit cell, and the bit cell is read by measuring the resistance of the bit cell (e.g., low resistance typically represents a "0" bit and high resistance typically represents a "1" bit). The bit cells are programmed using programming lines, which are typically called bit lines and digit (or word) lines.

[0037] One drawback of memory arrays implemented using MRAM cells is their lack of immunity to magnetic fields in the surrounding environment, which can disrupt or corrupt the data values ​​stored by the multiple magnetic bit cells by flipping the magnetization direction. Managing the potential for latent read failures is a major obstacle to enabling MRAM for mainstream applications.

[0038] The present disclosure provides a magnetic shielding structure made of a soft magnetic material with high relative magnetic permeability. The soft magnetic material redirects magnetic flux around an MRAM cell array, thereby reducing the magnetic field strength at the MRAM array and suppressing any magnetic field interference that would otherwise occur. In some embodiments, the magnetic shielding structure includes a top cover that fits over a portion of a semiconductor die that includes an MRAM array. In some embodiments, the backside of the semiconductor die is thinned in an area around the MRAM array, so that a thicker portion of the semiconductor die is above the MRAM array. In such embodiments, the top cover has a recess into which the thicker portion of the semiconductor die fits. In other embodiments, the entire backside of the semiconductor die is thinned, with the top cover having a recess positioned above the MRAM array. In both types of embodiments, the recess provides a magnetic reluctance greater than that of the shielding structure, and when subjected to a magnetic induction perpendicular to the substrate, the shielding structure redirects magnetic flux around the MRAM cell array. The magnetic shield structure also includes a bottom cover spanning the active side of the semiconductor die with openings for external connections of the packaged semiconductor device.

[0039] Example Embodiments

[0040] Figure 1A shows a cross-sectional view, and Figure 1B A planar bottom-up view of an example packaged semiconductor device 100 including a magnetic shielding structure for an MRAM array is shown. In the illustrated embodiment, the device 100 includes a semiconductor die 102, which in turn includes an MRAM array 104 formed in an active side 130 of the die 102. As discussed further below, the device 100 also includes a magnetic shielding structure formed by a top cover 108 and a bottom cover 118, wherein recesses are aligned above the MRAM array 104. In the illustrated embodiment, the device 100 also includes a redistribution layer (RDL) structure 110 formed above the active side 130 of the die 102, and a plurality of external connections 116 attached to pads 114 formed on an outermost surface of the RDL structure 110, wherein a plurality of openings 140 in the bottom cover 118 are aligned with the pads 114 and attach the external connections 116. These components are discussed further below.

[0041] Figure 1AThe die 102 in FIG. 1 is shown with the active side facing downward. The active side 130 of the die 102 includes the MRAM array 104 (as indicated by block 104, which spans the area on the active side 130 where the MRAM array is formed) and active circuitry 106 implemented laterally outside the MRAM array 104 (e.g., on the left and right sides of block 104). The MRAM array 104 includes a plurality of MRAM bit cells arranged in one or more sub-arrays. Various embodiments of magnetic shielding structures for the one or more sub-arrays are discussed further below. The active circuitry 106 includes electronic components such as a processor, memory, logic, analog circuitry, passive devices, etc. Support circuitry for the MRAM array 104 (such as a memory controller and access circuitry for reading from and writing to the MRAM bit cells) may also be implemented in the active circuitry 106 near the MRAM array 104.

[0042] Die 102 is implemented on a semiconductor substrate. MRAM array 104 and active circuitry 106 are formed using multiple process steps on a first side of the semiconductor substrate, which becomes active side 130. The remainder of the semiconductor substrate behind active side 130 is referred to as bulk silicon. While this remainder is often referred to as bulk silicon, it (and the semiconductor substrate) can be any semiconductor material or combination of materials, such as gallium arsenide, silicon germanium, silicon on insulator (SOI), silicon, single crystal silicon, and the like, as well as combinations thereof.

[0043] The die 102 includes a bulk silicon stack 120 that is positioned above the MRAM array 104 and extends laterally beyond the outer perimeter of the MRAM array 104 by some distance, where the MRAM array and the lateral distance are also referred to as the MRAM array area, as shown in FIG. Figure 2 102 ). Stack 120 has a height (or thickness) 132 measured from active side 130, thereby forming a top surface 126 (also referred to as a first back side 126 of die 102) and sidewalls 136. The remaining area of ​​die 102 is thinner (compared to stack 120), having a height (or thickness) 134 measured from active side 130, where height 134 is less than height 132. The area outside the MRAM array area has a top surface 128 (also referred to as a second back side 128 of die 102). Because the area outside the MRAM array area includes active circuitry 106, the area outside the MRAM array area is electrically referred to as active circuitry area 106, or simply area 106. This "top hat" shape can be achieved by removing a portion of the bulk silicon of die 102 from area 106 outside the MRAM array area (wherein the MRAM array area includes the MRAM array 104 and some lateral distance surrounding the MRAM array 104), as described below in conjunction with Figure 5D and 5E Further discussion.

[0044] The active side 130 also includes a plurality of die pads, which are shown for simplicity. Figure 1A The plurality of die pads are not shown in FIG, but the plurality of die pads are Figure 5A 102 and subsequent figures as die pads 502. The die pads can be arranged in different locations on the active side 130, such as in one or more rows around the perimeter of the die 102, or in other arrangements, such as near the center of the die 102. Each die pad can be electrically coupled to the active circuitry 106 implemented in the active side 130 of the die 102. In the embodiment shown, the lateral edges of the die 102 also form part of the lateral edges of the device 100, wherein the lateral edges of the die 102 and the device 100 are perpendicular to the active side 126 and the back side 130 of the die 102.

[0045] A plurality of build-up layers are formed over the active side 130 of the die 102 to form a redistribution layer (RDL) structure 110. The build-up layers may include a plurality of conductive layers, including layers forming conductive structures and dielectric layers (including layer 112) that insulate the conductive structures. External connection pads 114 are also formed on the outermost dielectric surface of the RDL structure 110, wherein the conductive structure of the RDL structure 110 includes traces (e.g., routing paths that implement redistribution) from pads (502) on the die 102 to the external connection pads 114 at different locations relative to the active side 130 of the die 102. Each of the external connection pads 114 also has an attached external connection 116, such as a solder bump, a copper pillar, a nickel pillar, or other suitable connection. The RDL structure 110 has a substantially uniform height at least on the outermost dielectric surface of the RDL structure 110, wherein the external connection pads 114 may extend beyond the outermost dielectric surface of the RDL structure 110. It should be noted that the use of metal posts, such as nickel posts, may require additional considerations due to the enhanced magnetic permeability of some metals, as discussed further below.

[0046] The dielectric layer of the RDL structure 110 is formed of a dielectric material, examples of which may include, but are not limited to, silicon oxide, silicon nitride, silicon dioxide, silicon oxynitride, polyimide, and other suitable materials including oxides, nitrides, and the like. The conductive layer of the RDL structure 110 may be formed of a conductive material, examples of which may include, but are not limited to, nickel, gold, copper, aluminum, or other suitable conductive metals or alloys consisting of one or more suitable conductive metals. The external connection pads 114 may be coated with a conductive material, examples of which may include, but are not limited to, nickel, gold, copper, aluminum, tin, silver, titanium, or other suitable conductive metals or alloys consisting of one or more suitable conductive metals, to improve the "bondability" properties of the pads 114. In some embodiments, the external connection pads 114 may include under-bump metallization (UBM) to improve wettability and adhesion of external connections (such as solder bumps 116). The UBM is formed of a thin film stack of one or more conductive metals, examples of which may include, but are not limited to, nickel, gold, copper, aluminum, titanium, tungsten, chromium, palladium, or other suitable conductive metals or alloys consisting of one or more suitable conductive metals.

[0047] The magnetic shield structure includes a top cover 108 over the back side of the die 102 and a bottom cover 118 over the active side 130, which in the embodiment shown includes the back sides 126 and 128 of the die 102. The top cover 108 and the bottom cover 118 are formed of a soft magnetic material, which is a material that is configured to be magnetized in a magnetic field and not be magnetized when the magnetic field is removed (in contrast to a hard magnetic material that remains magnetized even when the magnetic field is removed). Soft magnetic materials are generally characterized by their high relative permeability (μR). Magnetic permeability is generally a measure of a material's ability to support a magnetic field formed within itself, and relative permeability (μR) is the ratio of the magnetic permeability of a given material to the magnetic permeability of a vacuum (μ0). Example relative permeability values ​​(μR) for soft magnetic materials are 50 (e.g., nickel-zinc ferrite) to 500 (e.g., manganese-zinc ferrite), or 5,000 (e.g., iron), or 20,000 (e.g., mu-metal), or even greater (e.g., 200,000 for 99.95% pure iron). Examples of soft magnetic materials include, but are not limited to, iron, iron and mild steel, iron-silicon alloys, iron-aluminum-silicon alloys, nickel-iron alloys (e.g., mu-metal), iron-cobalt alloys, ferrites, amorphous alloys, and ceramics formed from iron oxide with one or more divalent oxides such as NiO, MgO, or ZnO.

[0048] The top cover 108 has a first major surface 124 and an opposing second major surface 122, wherein a lateral edge 142 is perpendicular to the first major surface 124 and the second major surface 122. In the embodiment shown, the lateral edge 142 of the top cover 108 extends to and is parallel to the lateral edge of the die 102, thereby forming the device edge. In some embodiments, the lateral edge 142 may not reach the lateral edge of the die 102 (e.g., Figure 5F ), while in other embodiments, lateral edges 142 may exceed the lateral edges of die 102 (e.g., when top cover 108 has a larger lateral perimeter than die 102). In some embodiments, top cover 108 is formed as a separate piece (whose lateral perimeter may be less than, equal to, or greater than the lateral perimeter of die 102) that includes a recess formed in first major surface 124, which is the surface facing die 102. The recess is formed to a depth 138 that is equal to the difference between back side 126 and back side 128 of die 102, which is also the distance that stack 120 extends beyond the (thinner) back side 128. The recess is shaped to fit over and around stack 120, with the dimensions of the recess (e.g., the width, length, and depth of the recess) corresponding to the dimensions of stack 120 (e.g., the width, length, and height of stack 120). The cap 108 may be attached to one or more back sides of the die 102, such as by using a combination of Figure 5F The adhesive in question may be combined with Figure 5G The molding compound discussed is fixed in place. In other embodiments, the top cap 108 can be formed directly onto the back side of the tube core 102 by depositing a soft magnetic material and then planarizing it. Figure 2 and Figure 5F The embodiments of the top cover 108 and the recess (labeled as recess 220 ) are further discussed.

[0049] The bottom cover 118 is a plate-like structure having a first major surface on the outermost surface of the RDL structure 110. In some embodiments, the bottom cover 118 is formed as a separate piece that is attached to the outermost surface of the RDL structure 110, such as by using an adhesive. Figure 1BThe opposing second major surface of the bottom cover 118 is shown in a planar bottom-up view of . The bottom cover 118 includes a plurality of openings 140 that extend through the board (e.g., from the first major surface to the second major surface) and are aligned with the external connection pads 114. Each opening 140 has a width that is large enough to accommodate an external connection 116 (such as the diameter of a solder bump or metal pillar), which can allow the bottom cover 118 to be attached after the external connection 116 is attached to the pad 114. In other embodiments, the bottom cover 118 can be formed directly onto the RDL structure 110 by depositing a soft magnetic material and then planarizing and etching the openings 140, which are aligned with the external connection pads 114. In such embodiments, attachment of the external connection 116 occurs after the openings 140 are formed. In other embodiments, the bottom cover 118 can be attached directly to the bottom surface of the die 102, such as in embodiments without an RDL structure 110, where the external connection 116 is directly attached to the pad 502, such as in embodiments without an RDL structure 110. Figure 10A and 10B shown.

[0050] The lateral edges 144 of the bottom cover 118 are perpendicular to the first and second major surfaces of the bottom cover 118. In the embodiment shown, the lateral edges 144 of the bottom cover 118 extend to and are parallel to the lateral edges of the top cover 108 and the die 102, thereby providing a continuous package edge. In the embodiment shown, the thickness of the bottom cover 118 is less than the thickness or height (e.g., the height of the solder bumps or metal pillars) of the external connections 116, thereby ensuring that the bottom cover 118 does not interfere with the attachment of the device 100 to a carrier substrate such as a printed circuit board (PCB).

[0051] In the embodiment shown, the bottom cover 118 has a plurality of openings 140 aligned with the external connections 116 and the pads 114 located around the perimeter of the die 102 (e.g., in two rows). Preferably, the external connections 116 and the pads 114 are located outside the MRAM array area. It should be noted that this embodiment is preferred because it has a solid, unbroken, continuous plate portion of the bottom cover 118 below the MRAM array 104 (e.g., there are no openings 140 below the MRAM array 104). Figure 1B In some embodiments, the bottom cover 118 can be formed simply as the center portion of the broken outline without the need for the opening 140 around the peripheral edge, where such embodiments of the bottom cover 118 still extend over a portion of the top cover, as shown in FIG. Figure 10A and 10BHowever, in other embodiments, the external connections 116 and pads 114 may be located near the center of the die 102 below the MRAM array 104, in which case the bottom cover 118 also has an opening 140 aligned below the MRAM array 104. Such an embodiment still provides shielding of the MRAM array 104, even though it may not be as effective as the continuous plate portion embodiment.

[0052] It should also be noted that the use of metal posts may require additional considerations due to the enhanced magnetic permeability of some metals, such as nickel, compared to other metals or alloys used for external connections. Since the high magnetic permeability of some metals may attract magnetic field lines from the environment, the placement of a given metal post depends on the geometry of the given metal post relative to the surrounding magnetic materials (such as the bottom cover 118) and other metal posts. Although metal posts are generally referred to herein, it should be understood that the use of such metal posts may require additional configuration restrictions with respect to magnetic shielding structures not discussed herein.

[0053] Figure 2 A cross-section and simplified view of the device 100 including a magnetic shielding structure for modeling magnetic behavior is shown. The top cover 108 is modeled as two parts of uniform thickness: a "flat" top portion 202 with a uniform height h3 (the height h3 is the height of the top cover 108 above the stack 120) and a "ring-shaped" sidewall portion 204 with a uniform height h5 (the height h5 is the height of the top cover 108 up to the plane defined by the top surface 126 of the stack 120) and an inner sidewall 210 formed by a recess 220. The bottom cover 118 is modeled as a plate portion 206 with a uniform height h4 without the plurality of openings 140. It should be noted that by using an effective thickness h4 that is less than the physical thickness of the bottom cover, the approximate effect of the openings 140 in the model can be taken into account. The sidewall portion 204 is separated from the plate portion 206 by a height h1 in the region 106 (the height h1 includes the height of the thinned portion of the die 102 and the height of the RDL structure 110), and the sidewall flat top portion 202 is separated from the plate portion 206 by a height h2 in the MRAM array region (the height h2 includes the height of the stack 120 and the height of the RDL structure 110). Therefore, the top cap 108 and the bottom cap 118 (the top cap 108 and the bottom cap 118 have high magnetic permeability) are separated by gaps h1 and h2 of material having low magnetic permeability.

[0054] The size of the recess 220 generally corresponds to the size of the MRAM array area. The MRAM array area includes both the area of ​​the MRAM array 104 labeled as perimeter 208 and a lateral distance 212 beyond perimeter 208. The lateral distance 212 (where "lateral" indicates a distance measured in a lateral direction parallel to a plane of the active side 130 of the die 102) is included to ensure that the recess 220 surrounds all MRAM bit cells within the MRAM array 104, thereby accounting for any misalignment within some predetermined tolerance margin. Thus, the inner sidewall 210 formed by the recess 220 falls a certain lateral distance 212 outside the perimeter 208. The lateral distance 212 also prevents magnetic fringe fields emerging from the lower corner of the top cap 108 at the outer edge of the gap h1 from reaching the MRAM bit cells. The lateral distance 212 should preferably be at least the same size as h1.

[0055] Figure 4A A perspective view of the flat top portion 202 of the top cover 108 is shown, Figure 4B A perspective view of the side wall portion 204 of the top cover 108 is shown, and Figure 4C A perspective view of the plate portion 206 of the bottom cover 118 is shown. The flat top portion 202 and the plate portion 206 are modeled as solid blocks of soft magnetic material, and the sidewall portion 204 is modeled as a solid block of soft magnetic material with a recess 220 extending through the entire portion 204 (e.g., the recess 220 forms a hole or space through the sidewall portion 204). To calculate the magnetic saturation threshold, the inner sidewall 210 of the recess 220 is pushed outward upward into the flat top portion 202 and downward into the plate portion 206, which will be discussed below in conjunction with Figure 3 Further discussion.

[0056] exist Figure 4A In FIG. 1 , the flat top portion 202 has a planar top surface (e.g., in a horizontal xy plane relative to the drawing) having a length lo in a first lateral direction (e.g., left-right relative to the drawing) and a width wo in a second lateral direction (e.g., in the direction into and out of the page). The length lo and the width wo form an overall area Ao, which can be expressed as Ao = lo x wo. The area Ao of the flat top portion 202 is divided into two parts: A1 and A2. A2 is the cross-sectional area of ​​the recess 220, which spans the MRAM array area, including both the MRAM array 104 and the lateral distance 212 (demarcated by the extrapolation of the inner sidewalls 210 of the recess 220). A1 is the remaining area outside of area A2. Figure 2Portions of A1 and A2 are also shown in the cross-sectional view as bold horizontal lines marked A1 and A2, respectively. Area A2 has a length 12 in the first lateral direction and a width w2 in the second lateral direction, even though in other embodiments, recesses 210 of other shapes (e.g., square, circular, elliptical) may be formed. Thus, area A2 may be represented as A2=12×w2, and area A1 may be represented as A1=Ao-A2. Additionally, the thickness or height of the flat top portion 202 is h3, where the critical vertical cross-sectional area A3 may be defined upon extrapolation of the inner sidewall 210. Area A3 includes all four vertical areas corresponding to the extrapolation of the inner sidewall 210 within the flat top portion 202, and may be represented as A3=2(12+w2)h3. Example portions of area A3 are also represented as shown with Figure 2 The bold vertical dashed lines are parallel to the side walls 210 in FIG.

[0057] exist Figure 4B , the sidewall portion 204 has a planar top surface with an area A1, wherein the outer perimeter of A1 has a length of lo and a width of wo, and the inner perimeter of A1 has a length of w2 and a width of w2. Figure 2 As shown, the thickness or height h5 of sidewall portion 204 is equal to h2 minus h1, where h2 is the combined height of die 102 in the MRAM array area plus the height of RDL structure 110, and h1 is the combined height of die 102 in the active circuitry area plus the height of RDL structure 110.

[0058] exist Figure 4C , the plate portion 206 has a planar top surface having an area equal to A1 plus A2. The plate portion 206 has a thickness or height h4, wherein the critical vertical cross-sectional area A4 can be defined upon extrapolation of the inner sidewall 210. Area A4 includes all four vertical areas corresponding to the extrapolation of the inner sidewall 210 within the plate portion 206 and can be represented as A4=2(12+w2)h4. An example portion of area A4 is also represented as Figure 2 The bold vertical dashed lines are parallel to the side walls 210 in FIG.

[0059] Back to Figure 2 , when encountering magnetic induction B ⊥ (also called magnetic flux density B ⊥ , also referred to as the B perpendicular), the magnetic shield structure is configured to reroute magnetic flux around the MRAM array 104. It should be noted that the simple calculations used here provide an approximation of the magnetic induction distribution in the shield structure. For other embodiments where the shield structure is thinner than its lateral dimensions, these approximations are sufficiently accurate for engineering purposes (e.g., for designing an effective shield structure). However, numerical simulations may be required to resolve the full three-dimensional distribution of magnetic induction in the device.

[0060] exist Figure 2 In the example shown, B ⊥ Enter the top surface of the flat top portion 202 (having an area Ao) and move in a vertical direction (or relative to Figure 2 The downward direction) travels downward, thereby providing magnetic flux Ao·B ⊥ , the magnetic flux Ao·B ⊥ Equal to (A1+A2)·B ⊥ The first magnetic flux φ1 is defined as the magnetic flux B1 perpendicularly passing through the cross-sectional area A1 outside the MRAM array area (where The second magnetic flux φ2 is defined as the magnetic flux B2 perpendicularly passing through the cross-sectional area A2 within the MRAM array area (where ), the magnetic induction B2 leaves the mesa portion 202 and continues to travel downward through the MRAM array region.

[0061] The magnetic induction B1 may also include the flux A2·B within the flat top portion 202 within the MRAM array region (or region A2). ⊥ The portion A3·B3 of the cross-sectional area is redirected outside the MRAM array area (or area A1), where B3 is a magnetic induction perpendicular to the cross-sectional area A3 (in the lateral direction). In other words, Flux A1·B ⊥ Portions A4·B4 may also be redirected toward the MRAM array 104 through the plate portion 206 , where B4 is the magnetic induction perpendicular to the cross-sectional area A4 (also in the lateral direction).

[0062] In general, the magnetic induction B2 across the MRAM array 104 should be minimized to avoid any disturbance at the MRAM array 104, which can be achieved by designing the magnetic shielding structure to remain below the magnetic saturation threshold. ⊥ When the magnetization of the magnetic shield structure cannot be further increased, saturation occurs, in which the magnetic flux density levels off. In some embodiments, the critical field strength or maximum field strength of the magnetic field experienced at the MRAM array 104 without causing interference is 0.15 Tesla (T), although in other embodiments, this field strength may be smaller or larger depending on the magnetic interference immunity of the type of MRAM bit cell used in the MRAM array 104. B2 is oriented to be less than the critical field strength.

[0063] The magnetic saturation threshold can be used Figure 3 It is determined by the equivalent magnetic circuit diagram of the magnetic shielding structure. Figure 3The simplified circuit in provides an accurate approximation of the actual system for the absolute magnetic field strength that will not lead to saturation, making it possible to calculate the magnetic saturation threshold. For simplicity, it is assumed that the non-saturated soft magnetic material has infinite permeability. However, since the material of the tube core 102 and the RDL structure 110 in the gap (e.g., silicon, insulating material, copper, aluminum wire, etc.) has a much lower magnetic permeability than the soft magnetic material (the permeability is very close to the permeability of vacuum μ0), the gaps h1 and h2 between the top cover part and the bottom cover part are modeled as corresponding magnetic resistances R1 and R2. The magnetic resistances R1 and R2 can be determined based on the gaps h1 and h2, the areas A1 and A2 forming the gaps h1 and h2, and the approximate permeability of the material in the gap (the approximate permeability can be expressed as the approximate relative permeability of the gap material multiplied by the permeability of the vacuum):

[0064]

[0065]

[0066] The total magnetic flux passing through the magnetic shield structure (provided as Figure 3 = The input of the circuit in FIG1 is equal to the flux φ1 through the sidewall portion 204 plus the flux φ2 through the MRAM array 104, which can be rewritten as B through the combined area A1+A2. ⊥ .

[0067] based on Figure 3 In the circuit, field B2 can be relative to B ⊥ Sure:

[0068]

[0069] It is effective under the following conditions:

[0070]

[0071]

[0072]

[0073] In some embodiments, the magnetic saturation threshold of the soft magnetic material used to implement the magnetic shielding structure may be 0.7 T, although in other embodiments, the magnetic saturation threshold may be smaller or larger depending on the soft magnetic material used.

[0074] Since the recess 220 is filled with bulk silicon, the magnetic permeability of the bulk silicon is much smaller than that of the soft magnetic material, the magnetic resistance through the recess 220 is much greater than the magnetic resistance through the soft magnetic material of the top cover 108. Therefore, the recess 220 is configured to transmit the magnetic induction B through the top cover 108 (or the path of minimum magnetic resistance). ⊥The recess 220 redirects the magnetic flux around the MRAM array 104. The recess 220 can redirect the magnetic flux even without the stack 120. As discussed further below, the recess 220 can be aligned above the MRAM array 104 where the die 102 has a single thickness (e.g., a thinned die with a single backside), with the recess 220 filled with air. Because the magnetic permeability of air is much lower than the magnetic permeability of the soft magnetic material, the magnetic reluctance through the recess 220 is much higher than the reluctance through the soft magnetic material of the top cap 108 and redirects the magnetic flux around the MRAM array 104. The bottom cap 118 is also configured to redirect the magnetic flux around the MRAM array 104 to a lesser extent by providing another path of minimum reluctance. The bottom cap 118 overlaps the solid portion of the sidewall portion 204 by a certain amount to minimize any fringing magnetic fields or leakage at the gaps h1 and h2 because the top cap 108 and the bottom cap 118 do not completely surround or enclose the die 102. For example, in some embodiments, the gap h1 may preferably be 50 microns or less.

[0075] In general, as the perimeter or footprint 208 of the MRAM array 104 increases (e.g., an 8 Mb array has a larger footprint than a 2 Mb array), the area A2 of the recess 220 increases appropriately, thereby maintaining the lateral distance 212 between the inner sidewalls 210 of the recess 220 and the outer perimeter 208 of the MRAM array 104. The recess 220 maintains the lateral distance 212 between the inner sidewalls 210 of the recess 220 and the outer perimeter 208 of the MRAM array 104 regardless of whether the stack 120 is present. The width of the sidewall portion 204 surrounding the MRAM array area (e.g., relative to the width of the sidewall portion 204) is proportional to the width of the sidewall portion 204. Figure 4B The left and right parts of (lo-12) / 2 and relative to Figure 4B The front and rear (wo-w2) / 2) should be large enough to provide sufficient area A1 from the magnetic induction B ⊥ The magnetic flux of can be directed around the MRAM array 104 through the region A1 while minimizing the field B2 passing through the recess 220 and through the MRAM array 104. Other values ​​can also be adjusted to ensure that B ⊥ is fully redirected around the MRAM array 104 and B2 remains below the critical field strength. For example, the height h5 of the recess 220 can also increase as the occupied area 208 increases, and the occupied area 208 should generally be as large as possible while remaining within the saturation limit. The height h3 of the top cap 108 above the recess 220 can be reduced as the height h5 of the recess 220 increases to maintain the same overall package thickness, or the height h3 can be increased to provide sufficient area A3, the magnetic induction B ⊥The magnetic flux can be directed around the MRAM array 104 through the area A3. The height h4 of the bottom cover 118 can also be increased or decreased while maintaining sufficient area A4, magnetic induction B ⊥ The magnetic flux can be directed through the region A4 around the MRAM array 104. Thus, the magnetic shielding structure can be tuned to the specific requirements of various end products including dies having MRAM arrays.

[0076] It should also be noted that the size of the top cap 108 and the bottom cap 118 can be limited to the area on the die 102 that includes the MRAM array 104 and need not cover the entire active side and back side of the die 102 (e.g., Figure 1A ). It is preferred to keep the lateral dimensions of the top and bottom covers 108, 118 as small as possible while adjusting the dimensions of the top and bottom covers 108, 118 to ensure that the magnetic shielding structure remains within the saturation limit. A magnetic shielding structure with a larger lateral dimension can collect a larger magnetic flux, which means a greater likelihood of saturation. A magnetic shielding structure with a smaller lateral dimension protects the smaller footprint of the MRAM array 104 (compared to the footprint of the entire die 102) while limiting the magnetic flux. If the MRAM array 104 has a very large footprint 208 (e.g., a 16Mb array), such an array may benefit from being divided into multiple smaller sub-arrays, where a magnetic shielding structure may be formed for each sub-array, or a single magnetic shielding structure with a recess may be formed for each sub-array. Figure 9A and 9B An example of such an embodiment is shown in .

[0077] Figure 5A 、 5B , 5C, 5D, 5E, 5F, 5G, 5H, 5I and 5J are block diagrams depicting example methods for fabricating a packaged semiconductor device including a magnetic shielding structure for an MRAM array. In the illustrated embodiment, a stack 120 is formed over the MRAM array 104, and the top cover 108 has a recess 220 that mates to the stack 120, as discussed further below. While the figures show a single die 102 fabricated into a device, the die 102 can represent multiple dies on a wafer, where the process steps described below can be applied to all dies on the wafer. In combination Figure 6A and 6B This wafer-level fabrication approach is also discussed.

[0078] Figure 5AThe active side 130 of the die 102 is shown in a planar, bottom-up view, including a plurality of die pads 502 located around the perimeter of the die 102. Also shown is the perimeter of the MRAM array 104. While the figures show the MRAM array 104 located near the center of the die 102, in different embodiments, the MRAM array 104 may be located elsewhere on the active side 130 of the die 102.

[0079] Figure 5B A cross-sectional view of die 102 is shown before any back grinding or thinning steps are performed. Die 102 has an original thickness, with an original backside 504 opposite active side 130 and lateral edges 506 perpendicular to active side 130. Active side 130 of die 102 is attached to a suitable temporary carrier, such as glass carrier 508. Thus, die 102 is oriented with the active side facing downward.

[0080] Figure 5C A back grinding step 510 is shown applied to the back side 504 of the die 102, which removes a portion of the bulk silicon from the back side 504 of the die 102, thereby exposing a new back side 126. In some embodiments, the new back side 126 is formed so that the remaining portion of the bulk silicon above the MRAM array 104 has the desired height of the stack 120. In some embodiments, back grinding, such as back grinding 510, can be performed using chemical mechanical polishing (CMP) or other planarization methods.

[0081] Figure 5D A photoresist mask 512 is shown formed over the backside 126 of the die 102 and used to form the stack 120. Figure 5E . A photoresist mask 512 may be deposited over the backside 126 as a layer of photoresist material, which is then patterned so that the photoresist mask 512 is over and generally aligned with the MRAM array 104. Because there may be some margin of error due to alignment tolerances when forming the photoresist mask 512, the photoresist mask 512 is formed to cover an area that is some lateral distance 212 greater than the footprint 208 of the MRAM array 104 in order to ensure that the sidewalls 136 of the resulting stack 120 (and the inner sidewalls 210 of the top cap 108) remain outside the footprint 208. For example, the lateral distance 212 may be on the order of a few microns or tens of microns, where for an 8 mm 2 For die 102, MRAM array 104 may have a footprint 208 of approximately 1.5 mm x 1.5 mm. Example photoresist materials include, but are not limited to, polymer resins containing photoactive (or photosensitive) compounds.

[0082] Figure 5EAn etch step 516 is shown applied to the exposed portion of the backside 126 of the die 102, removing another portion of the bulk silicon around the photoresist mask 512 from the backside 126 of the die 102, thereby exposing the new backside 128. Thus, the stack 120 is formed with sidewalls 136 that are located outside the footprint 208 of the MRAM array 104. The thickness of the die 102 around the stack 120 can be as thin as 10 to 20 microns or as large as 50 microns, while the stack 120 can be as thick as 200 to 300 microns or greater, such as 350 microns, depending on the die thickness requirements. In some embodiments, the etching can be performed using a wet etchant or a dry etchant that selectively removes bulk silicon from around the photoresist mask 512.

[0083] Figure 5F The top cap 108 is shown positioned on the backside of the die 102. In the embodiment shown, the backside of the die 102 includes backsides 126 and 128. In some embodiments, the top cap 108 is a separate piece that includes a recess 220 that substantially fits into the stack 120, where the depth of the recess corresponds to the height of the stack 120 measured from the backside 126 of the die 120. The recess 220 of the top cap 108 is configured to fit over and around the stack 120. Because there may be some margin of error due to alignment tolerances when placing the top cap 108 on the die 102, the recess 220 is formed to have a sufficiently large cross-sectional area A2 to surround the stack 120, such as by introducing additional lateral distance between the inner sidewalls 210 and the footprint 208 of the MRAM array 104 to ensure that the inner sidewalls 210 surround the sidewalls 136 of the resulting stack 120.

[0084] The bottom surface 124 of the top cap 108 (relative to the drawing) is in contact with or flush with the back side 128. Optionally, an adhesive 518 can be used to secure the top cap 108 to the back side of the die 102, as shown by the bold dashed line. The adhesive 518 can optionally be placed on any combination of the back side 128, the back side 126, and the sidewalls 136. Examples of adhesives such as adhesive 518 include, but are not limited to, solder alloys, polyimides, silicones, or epoxy-based materials containing suspended fillers such as carbon nanotubes or beryllium oxide, aluminum nitride, boron nitride, or diamond powder. The adhesive 518 can also have thermally conductive properties to transfer heat from the die 102 to the top cap 108.

[0085] The top cover 108 also has lateral edges 142. In the embodiment shown, the lateral edges 142 do not reach the lateral edges 506 of the die 102, thereby exposing a portion of the back side 128. In other embodiments, the lateral edges 142 of the top cover 108 may reach the lateral edges 506 of the die 102, wherein adhesive 518 may be used in such embodiments to secure the top cover 108 to the back side of the die 102.

[0086] exist Figure 5F In another embodiment, the top cap 108 can be positioned on the back side of the die 102 by being formed directly on the die 102. In such an embodiment, the top cap 108 can be formed by depositing (e.g., sputtering, electroplating, casting, screen printing, etc.) a soft magnetic material over the back sides 126 and 128 of the die 102. In some embodiments, a thin bonding layer may be required before depositing the soft magnetic material, wherein such a thin bonding layer may be sputtered. After depositing the soft magnetic material, a planarization step (e.g., grinding, polishing, etc.) is performed to produce a planar top surface 122 of the top cap 108, wherein the resulting device has a final package thickness. In such an embodiment, similar to Figure 1A and 1B As shown in FIG, the lateral edge 142 of the top cover 108 will extend to the lateral edge 506 of the tube core 102. This embodiment will also jump forward to Figure 5I The process steps shown in FIG. 1 are as follows, because when depositing the cap 108, Figure 5G and 5H When implemented in a wafer-level process, the lateral edges 142 and 506 will be formed during the final singulation step by sawing or otherwise separating the device from the larger wafer, as described below in conjunction with Figure 6B Further discussion.

[0087] In an embodiment of a cast soft magnetic material, the casting material can be a mixture of soft magnetic particles dispersed in a polymer (e.g., epoxy resin). The casting material should have a high particle filling factor. This viscous mixture may be deposited by, for example, screen printing. For a high filling factor, a mixture of different particle sizes can be used so that smaller particles can fill the space between adjacent larger particles. Optionally, the polymer can be at least partially a volatile compound that evaporates during curing at an elevated temperature. This may further increase the filling factor. In order to prevent the accumulation of excessive mechanical stress caused by shrinkage during curing and evaporation, it may be necessary to apply vertical pressure (e.g., in a downward direction relative to the accompanying drawings) during curing so that the casting material can reflow around the tube core 102. Applying vertical pressure can also achieve flattening of the top surface of the deposited material, where grinding or polishing may not be required.

[0088] Figure 5GThe encapsulation step of overmolding the top cover 108 with a molding compound 520 is shown. In the embodiment shown, the molding compound 520 is attached to the lateral edges 142 of the top cover 108 and the exposed portion of the back side 128, thereby firmly attaching the top cover 108 to the tube core 102 with or without the use of an optional adhesive 518. In some embodiments, the thickness or lateral width 526 of the sidewall portion of the top cover 108 is thin enough to allow a sufficient amount of molding compound to contact the exposed portion of the back side 128 while remaining thick enough to meet the magnetic saturation requirements discussed above. Examples of molding compounds (such as molding compound 520) include, but are not limited to, biphenyl or polyaromatic epoxy resins, as well as other types of encapsulation materials in other embodiments. The encapsulation step can be performed by an encapsulation method, such as transfer molding, film assisted molding, glob top, dam and fill, bottom fill, lamination, or other types of other encapsulation methods.

[0089] Figure 5H A back grinding step 522 is shown applied to the top surface of the mold compound 520 , exposing a new backside 524 of the mold compound 520 and the top surface 122 of the top cover 108 . Figure 5H The device is shown with the final package thickness.In some embodiments, the exposed top surface 122 of the top cover 108 can be laser marked to indicate information about the device.

[0090] Figure 5I The back side of the resulting device (including Figure 5H The back side 524 and 122 shown in FIG are attached to a tape 528 or other suitable temporary carrier, and the glass carrier 508 is removed. Figure 5I In some embodiments, an RDL structure 110 is formed over the active side 130 of the die 102, with a set of pads 114 exposed at an outer surface 530 of the RDL structure 110. For example, as discussed further below, multiple RDL structures 110 can be formed over multiple dies 102 as a wafer-level or panel-level approach. Each RDL structure 110 can have a substantially uniform height or thickness of 20 microns to 40 microns measured from the active side 130 of the die 102 to the outer (dielectric) surface of the RDL structure 110. In some embodiments, external connections 116 (such as solder balls or metal pillars) are attached to the pads 114. In other embodiments, the RDL structure 110 is not formed, and instead the external connections 116 are formed directly on the pads 502, such as Figure 10B. In some embodiments, tape 528 is formed from a polymer film (e.g., PVC (polyvinyl chloride), polyolefin, polyethylene, or similar material) with die adhesive disposed on a surface of the polymer film. In some embodiments, tape 528 is a dicing tape 528 that is removable in response to UV (ultraviolet) light exposure or a temperature excursion (e.g., the die adhesive weakens in response to UV exposure or a temperature excursion) or by the use of a release layer. Tape 528 releases the device or releases the plurality of dies produced by singulating the wafer.

[0091] Figure 5J The bottom cover 118 is shown attached to the outer surface 530 of the RDL structure 110, thereby producing a packaged semiconductor device 532. In the embodiment shown, the bottom cover 118 is attached after the external connections 116 are attached to the pads 114. The bottom cover 118 includes a plurality of openings 140 aligned with the external connections 116 and the pads 114, wherein the openings 140 have a diameter large enough to fit over the diameter of the external connections 116. In other embodiments, the bottom cover 118 can be attached before the external connections 116 are attached to the pads 114. The bottom cover 118 can be attached by an adhesive (e.g., bonding agent). Figure 5F The bottom cover 118 is attached using the adhesive 518 discussed above. In other embodiments, the bottom cover 118 can be omitted from the device 532 and instead attached to a printed circuit board (PCB) to which the device 532 is attached, such as Figures 8A-8C shown.

[0092] exist Figure 5J In another embodiment, after the RDL structure 110 and the pads 114 are completed, but before the external connections 116 are attached to the pads 114, a bottom cap 118 (eg, Figure 5I The process step will omit the attachment of connection 116). In this embodiment, the soft magnetic material can be deposited (e.g., sputtered, electroplated, cast (the casting can also be combined with the above) Figure 5F The bottom cover 118 is formed over the outermost surface of the RDL structure 110 by a process such as fabrication considerations provided herein (e.g., screen printing, etc.). In some embodiments, a thin adhesive layer may be required before depositing the soft magnetic material, wherein such a thin adhesive layer may be sputtered. After depositing the soft magnetic material, a planarization step (e.g., grinding, polishing, etc.) may be performed, if necessary, to form a planar outer surface of the bottom cover 118. A plurality of openings 140 are then formed, such as by etching through the bottom cover 118 (and optionally through the adhesive layer) to expose the pads 114. The external connections 116 are then attached to the pads 114 through the openings 140. In such an embodiment, similar to Figure 1A and 1B, the lateral edges 144 of the bottom cover 118 will extend to the lateral edges 506 of the die 102. When implemented in a wafer-level approach, the lateral edges 144 and 506 will be formed during the final singulation step by sawing or otherwise separating the devices from the larger wafer, as described below in conjunction with Figure 6B Further discussed. In some embodiments, external connection 116 can be a metal pillar, wherein opening 140 can be used in part to define the diameter of the pillar. For example, an insulating material can be deposited to coat bottom cap 118 including the inner sidewall surfaces of opening 140 while also exposing underlying pad 114, thereby allowing a metal pillar to grow within each opening 140.

[0093] In still other embodiments, when the RDL structure 110 is not present, the bottom cap 118 may be attached directly to the bottom surface of the die 102, such as Figure 10B It should be noted that Figure 5J The bottom cover 118 is shown extending laterally past the lateral edge 142 of the top cover 108 and completely overlapping the lateral width 526 of the sidewall portion of the top cover 108, while Figure 10B The bottom cap 118 is shown laterally overlapping a smaller portion of the lateral width 526 of the sidewall portion of the top cap 108. Similar to forming the bottom cap 118 on the RDL structure 110 as described above, the bottom cap 118 can be attached to the die 102 by an adhesive or by depositing a soft magnetic material over the bottom surface of the die 102, wherein in some embodiments, the external connections 116 can be attached before or after attaching the bottom cap 118, or in other embodiments, the external connections 116 can be attached after depositing the bottom cap 118.

[0094] As described above, the aforementioned steps described in conjunction with a single die 102 can be applied to multiple dies 102 on a wafer for wafer-level or panel-level method embodiments. For example, the corresponding active sides of a wafer including multiple dies or a reconstituted wafer or panel including multiple dies surrounded by a mold compound can be attached to Figure 5B The glass carrier 508 in the back surface can also be applied to the back surface grinding step 510. Figure 5C A photoresist material may be deposited over the back side of the entire wafer and then patterned to allow the photoresist mask 512 to be in the Figure 5D An etch step 516 may be applied to the exposed areas of the wafer to form an MRAM array 104 on each die 102 of the wafer. Figure 5E A stack 120 is created above each MRAM array 104 on each die 102 in the wafer. Figure 6A It is shown in Figures 5B-5EA corresponding planar bottom-up view of an example wafer 600 and each of the dies 605 resulting from the process steps described in FIG.

[0095] The separate top cover 108 can then be placed (with or without adhesive) on the Figure 5F Each of the stacks 120, wherein Figure 5G In another wafer-level embodiment, an array or panel of caps 108 can be placed over the back side of the wafer and aligned with the stack 120, which can be singulated into individual caps 108 simultaneously with die singulation. A back grinding step 522 can be applied to the entire wafer to expose the Figure 5H All top covers 108 in the Figure 5I In another wafer-level embodiment, a layer of soft magnetic material is deposited over all back sides of the die 102 (with or without a thin adhesive layer) and planarized to form multiple top caps 108 on all dies 102. Finally, a separate bottom cap 118 can be attached to the Figure 5J each RDL structure 110 on each tube core 102 of the wafer in. In another wafer-level embodiment, an array or panel of bottom covers 118 can be attached to the RDL structures 110 on the wafer. In another wafer-level embodiment, a layer of soft magnetic material can be deposited over all of the RDL structures 110 (with or without a thin adhesive layer), planarized, and etched with openings 140 to form multiple bottom covers 118 on all of the tube cores 102, wherein after the bottom covers 118 are manufactured, external connections 116 are attached to the pads 114. In yet another wafer-level embodiment, the attachment of the bottom covers 118 can be omitted, wherein the bottom covers 118 can be attached to a printed circuit board (PCB), and the resulting packaged semiconductor device attached to the PCB and aligned with the bottom covers 118, as described below in conjunction with Figures 8A-8C Further described. Figure 6B It is shown in Figures 5F-5J 6 and each device 615. Optionally, a bottom cover 118 can be attached to the resulting device 615, or the bottom cover 118 can be omitted from the device 615 and instead attached to the PCB, as indicated by the bottom cover 118 shown in dashed outline. A singulation step 620 then separates the device wafer 610 into a plurality of packaged semiconductor devices 615, thereby forming vertical lateral edges of the devices.

[0096] Figure 7A 、 7B, 7C, 7D, 7E, 7F, 7G, and 7H are block diagrams depicting another example method for fabricating a packaged semiconductor device including a magnetic shielding structure for an MRAM array. In the embodiment shown, no stack is formed over the MRAM array 104, where the die 102 has a single backside and thickness. As discussed further below, the top cover 108 still has a recess 220 that fits over the MRAM array 104. Although the figures show a single die 102 fabricated into a device, the die 102 can represent multiple dies on a wafer, where the process steps described below can be combined with those described above. Figure 6A and 6B A similar approach as discussed above applies to all dies on the wafer. Figure 9A and 9B Additional embodiments of wafer-level fabrication methods for dies including multiple MRAM sub-arrays are discussed.

[0097] Figure 7A A cross-sectional view of die 102 is shown before any back grinding or thinning steps are performed. Die 102 has an original thickness, with an original backside 504 opposite active side 130 and lateral edges 506 perpendicular to active side 130. Active side 130 is attached to a suitable temporary carrier, such as glass carrier 508. Thus, die 102 is oriented with the active side facing downward. MRAM array 104 is also shown as being located off-center on active side 130.

[0098] Figure 7B A back grinding step 710 is shown applied to the back side 504 of the die 102 , which removes a portion of the bulk silicon from the back side 504 of the die 102 , exposing a new back side 712 across the entire die 102 . Figure 7B The thickness of the die 102 in FIG. 1 is the final uniform thickness of the die 102 , which may be 10 microns to 20 microns in some embodiments.

[0099] Figure 7CThe top cap 108 is shown positioned on the backside of the die 102. In the embodiment shown, the backside of the die 102 includes backside 712. The top cap 108 includes a recess 220 configured to be positioned above the MRAM array 104. The recess 220 has inner sidewalls 210 in the top cap 108. Because there may be some margin of error due to alignment tolerances when placing the top cap 108 on the die 102, the recess 220 is formed to have a cross-sectional area A2 (defined by the inner sidewalls 210) that is greater than the footprint 208 of the MRAM array 104 by some lateral distance 212 to ensure that the recess 220 is sufficiently positioned above the MRAM array 104, with the sidewalls 210 remaining outside the footprint 208. The lateral distance 212 may be on the order of a few microns or tens of microns.

[0100] Figure 7D 102 is shown attached to the back side 712 of the die 102 by an adhesive 714. In the embodiment shown, the adhesive 714 is attached to the surface within the recess 220 and to the back side of the die 712, thereby securely attaching the top cap 108 to the die 102. Prior to placing the top cap 108 on the die 102, the adhesive 714 can be placed in the recess 220 with the bottom surface 124 of the top cap 108 in contact with or flush with the back side 712. In other embodiments, additional adhesive can optionally be placed on the back side 712 to further secure the top cap 108. The adhesive 714 can be similar to the adhesive 514 and can also have thermally conductive properties.

[0101] The top cover 108 also has lateral edges 142. In the embodiment shown, the lateral edges 142 do not reach the lateral edges 506 of the die 102, thereby exposing a portion of the back side 712. In other embodiments, the lateral edges 142 of the top cover 108 can reach the lateral edges 506 of the die 102, wherein the adhesive 714 can be used to secure the top cover 108 to the die 102.

[0102] Figure 7E The encapsulation step of overmolding the top cover 108 with a mold compound 520 is shown. In the embodiment shown, the mold compound 520 is attached to the lateral edges 142 and the exposed portions of the back side 712 of the top cover 108.

[0103] Figure 7F A back grinding step 722 is shown applied to the top surface of the mold compound 520 , exposing a new backside 524 of the mold compound 520 and the top surface 122 of the top cover 108 . Figure 7F The device is shown with the final package thickness.

[0104] Figure 7GThe back side of the resulting device (including back sides 524 and 122) is shown attached to tape 528 or other suitable temporary carrier, and the glass carrier 508 is removed. Figure 7G , the device is flipped with the active side facing up. In some embodiments, an RDL structure 110 is formed over the active side 130 of the die 102, wherein a set of pads 114 are exposed at an outer surface 530 of the RDL structure 110. For example, as discussed further below, multiple RDL structures 110 can be formed over multiple dies 102 as a wafer-level or panel-level approach. Each RDL structure 110 can have a substantially uniform height or thickness of 20 microns to 40 microns measured from the active side 130 of the die 102 to the outer (dielectric) surface of the RDL structure 110. In some embodiments, external connections 116 (such as solder balls or metal pillars) are attached to the pads 114.

[0105] Figure 7H Attachment of a bottom cover 118 to the outer surface 530 of the RDL structure 110 is shown, resulting in a packaged semiconductor device 730. In the embodiment shown, the bottom cover 118 is attached after the external connections 116 are attached to the pads 114. The bottom cover 118 includes a plurality of openings 140 aligned with the external connections 116 and the pads 114, wherein the openings 140 have a diameter large enough to fit over the diameter of the external connections 116. In other embodiments, the bottom cover 118 can be attached before the external connections 116 are attached to the pads 114. The bottom cover 118 can be attached by an adhesive, such as the adhesive 714 discussed above. In other embodiments, the bottom cover 118 can be omitted from the device 730 and instead attached to a PCB to which the device 730 is attached, such as Figures 8A-8C shown.

[0106] exist Figure 7H In another embodiment, after the RDL structure 110 and the pad 114 are completed, but before the external connection 116 is attached to the pad 114, the external connection 116 can be connected to the pad 114 in a manner similar to the above combination. Figure 5J A bottom cap 118 is formed on the RDL structure 110 in a manner similar to that discussed above, wherein the bottom cap 118 may be attached by an adhesive or deposited on the RDL structure 110. In still other embodiments, when the RDL structure 110 is not present, the bottom cap 118 may be directly attached to the bottom surface of the die 102, such as Figure 10A It should be noted that Figure 7H The bottom cover 118 is shown extending laterally past the lateral edge 142 of the top cover 108 and completely overlapping the lateral width 526 of the sidewall portion of the top cover 108, while Figure 10AThe bottom cap 118 is shown laterally overlapping a smaller portion of the lateral width 526 of the sidewall portion of the top cap 108. Similar to forming the bottom cap 118 on the RDL structure 110 as described above, the bottom cap 118 can be attached to the die 102 by an adhesive or by depositing a soft magnetic material over the bottom surface of the die 102, wherein in some embodiments, the external connection 116 can be attached before or after attaching the bottom cap 118, or in other embodiments, the external connection 116 can be attached after depositing the bottom cap 118. Additionally, in any of the above embodiments, the external connection 116 can be a metal pillar, wherein the opening 140 can be used in part to define the diameter of the pillar grown within the opening 140.

[0107] Figure 8A 、 8B 8C are block diagrams depicting example alternative process steps for fabricating a packaged semiconductor device including a magnetic shield structure for an MRAM array. Figure 8A Shown as Figure 7G The device shown, but as Figure 5I The apparatus shown can also be used in alternative process steps.

[0108] Figure 8B The bottom cover 118 of the magnetic shield structure is shown attached to a printed circuit board (PCB) 802 by an adhesive 806, which can be similar to the other adhesives described above. The bottom cover 118 includes a plurality of openings 140 aligned with landing pads 804 on the PCB 802, wherein the openings 140 have a diameter large enough to allow the device to be placed on the PCB. Figure 8A The diameter of the external connection 116 on the device in FIG. 1 passes through the opening 140 and contacts the landing pad 804. A printed circuit board (PCB) includes conductive features on a non-conductive substrate. The PCB can be a flexible PCB using polyimide or a rigid PCB using FR4 or BT resin. The packaged semiconductor device can be attached and electrically connected to the PCB via a plurality of external connections, such as solder balls or metal pillars.

[0109] Figure 8C The device is shown attached to the PCB and aligned with the bottom cover 118. In some embodiments, the external connections 116 are bonded to the landing pads 804 (e.g., reflowed), which provides sufficient attachment of the device to the PCB. In other embodiments, another layer of adhesive 806 is used to attach the outer surface 530 of the RDL structure 110 to the bottom cover 118.

[0110] As described above, the MRAM array 104 may benefit from being divided into multiple smaller sub-arrays, wherein sub-arrays may be formed for Figure 9AMagnetic shielding structures for each sub-array are shown. Alternatively, a single magnetic shielding structure may be formed with Figure 9B The recesses of each sub-array are shown. Figure 9A and Figure 9B Such an embodiment is also shown as part of a wafer-level approach, although a separate die approach may be implemented in other embodiments.

[0111] Figure 9A An example wafer 905 including multiple die 900 is shown, along with a corresponding planar bottom-up view of each die 900. Each die 900 includes an MRAM array comprising at least a first sub-array 104 and a second sub-array 904, and may include additional sub-arrays in other embodiments. The first sub-array 104 and the second sub-array 904 can be located at different locations, or at least have sufficient distance between the sub-arrays to allow the lateral width of the sidewall portion of a separate top cover 108 (and top cover 908) to be positioned above each sub-array. The space between the sub-arrays can be used to house memory peripheral circuitry such as address decoders, sense amplifiers, error correction circuitry, etc. Top covers 108 and 908 include recesses 220 and 920, respectively, positioned above sub-arrays 104 and 904, respectively. In other words, each sub-array has its own recess, with the sub-arrays preferably not sharing recesses. In some embodiments, a stack 120 may be formed over each subarray, with recesses 220 and 920 fitting over and around the stack 120 in a manner similar to that described above. In other embodiments, a stack need not be formed, with each top cover 108 and 908 positioned in a manner similar to that described above (e.g., in connection with 7D) such that recesses 220 and 920 are aligned over subarrays 104 and 904. Bottom cover 118 may optionally be attached (as indicated by the dashed outline) as a separate cover or as a panel for the cover, or may be omitted as similarly described above. A singulation step 620 then separates device wafer 905 into a plurality of packaged semiconductor devices.

[0112] Figure 9B An example wafer 910 is shown including a plurality of dies, such as those in combination with Figure 9A1 and 9. However, rather than having a separate top cap 108 (and 908) above each MRAM subarray 104 and 904, a single top cap 108 may have multiple recesses aligned with each subarray. For example, top cap 108 includes recess 220 aligned with subarray 104 and recess 920 aligned with subarray 904. In some embodiments, a stack 120 may be formed above each subarray, with recesses 220 and 920 fitting over and around stack 120 in a manner similar to that described above. In other embodiments, a stack need not be formed, with each top cap 108 and 908 positioned in a manner similar to that described above (e.g., in connection with 7D) such that recesses 220 and 920 are aligned over subarrays 104 and 904. Bottom cap 118 may optionally be attached (as indicated by the dashed outline) as a separate cap or as a panel of the cap, or may be omitted as similarly described above. Then, a singulation step 620 separates the device wafer 905 into a plurality of packaged semiconductor devices.

[0113] Semiconductor dies (e.g., semiconductor die 102) may be formed from (e.g., singulated from) a semiconductor wafer, which may be any semiconductor material or combination of materials such as gallium arsenide, silicon germanium, silicon on insulator (SOI), silicon, single crystal silicon, and combinations thereof. The active circuitry of the semiconductor die (e.g., semiconductor die 102) is formed on the silicon wafer using a series of numerous process steps applied to the semiconductor wafer, including, but not limited to: depositing semiconductor materials, including dielectric materials and metals, such as growth, oxidation, sputtering, and conformal deposition; etching the semiconductor materials, such as using wet or dry etchants; planarizing the semiconductor materials, such as performing chemical mechanical polishing or planarization; performing photolithography to achieve patterning, including depositing and removing photolithographic masks or other photoresist materials; ion implantation; annealing, and the like. Examples of active circuitry include, but are not limited to: integrated circuit components such as processors, memory, logic, analog circuitry, sensors, MEMS (micro-electromechanical systems) devices; stand-alone discrete devices such as resistors, inductors, capacitors, diodes, power transistors; etc. In some embodiments, the active circuitry may be a combination of the integrated circuit components listed above or may be another type of microelectronic device.

[0114] By now, it should be understood that a magnetic shielding structure has been provided, wherein the magnetic shielding structure is made of a soft magnetic material, the magnetic shielding structure reduces magnetic interference with an MRAM array, and the MRAM array may include one or more sub-arrays. The magnetic shielding structure includes a top cover, and the top cover further includes a recess aligned with each sub-array, wherein the recess is filled with air or silicon or both and provides a magnetic resistance greater than the magnetic resistance of the shielding structure, and the shielding structure redirects magnetic flux around the MRAM cell array.

[0115] Because the apparatus embodying the present invention is largely composed of electronic components and circuits known to those skilled in the art, as described above, the circuit details will not be explained more than is deemed necessary to facilitate understanding and appreciation of the basic concepts of the invention and to avoid obscuring or diverting attention from the teachings of the invention.

[0116] As used herein, the terms "approximately" and "about" mean a value that is close to or within an acceptable range of an indicated value, quantity, or quality, which also includes the exact indicated value itself. It should be noted that, as used herein, the term "laterally" means "in a lateral direction" (e.g., a horizontal direction parallel to the plane of the substrate), and the term "space" refers to a void or volume devoid of material.

[0117] Also as used herein, the terms “substantial” or “substantially” mean sufficient to achieve the stated purpose or value in a practical manner, taking into account any minor defects or deviations, if any, that are insignificant from the stated purpose or value arising from normal and expected process anomalies that may occur during wafer fabrication.

[0118] Although the present invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the present invention as set forth in the claims below. For example, additional or fewer recesses may be implemented in FIG. 1 . Accordingly, this specification and drawings are to be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems described herein with respect to specific embodiments are not intended to be construed as key, required, or essential features or elements of any or all the claims.

[0119] Furthermore, the terms "front," "back," "top," "bottom," "above," "below," etc., if any, in the description and claims are used for descriptive purposes and are not necessarily intended to describe permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in other orientations than those illustrated or otherwise described herein.

[0120] In addition, as used herein, the terms "a" or "an" are defined as one or more than one. Moreover, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed as implying that another claim element introduced by the indefinite article "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an." The same is true for the use of definite articles.

[0121] Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Claims

1. A packaged semiconductor device, characterized in that: include: a semiconductor die having an active side and an opposing backside, the semiconductor die including an array of magnetoresistive random access memory (MRAM) cells formed within an MRAM region on the active side of the semiconductor die; as well as a top cap comprising a soft magnetic material positioned on the back side of the semiconductor die, wherein The top cover includes a recess formed in a first major surface of the top cover, The first main surface faces the back side of the semiconductor die, and The recess is positioned on the MRAM cell array; The semiconductor die further includes active circuitry formed in a circuit region on the active side, the active circuitry being laterally adjacent to the MRAM cell array, The first portion of the semiconductor die has a first thickness in the circuit region; A second portion of the semiconductor die has a second thickness in the MRAM region, the second thickness being greater than the first thickness, the second portion forming a stack positioned vertically adjacent to the MRAM cell array, and The recess is sized to fit over and around the stack.

2. The packaged semiconductor device according to claim 1, wherein: A sidewall of the recess is separated from a periphery of the MRAM cell array by a spacing distance.

3. The packaged semiconductor device according to claim 1, wherein: A second portion of the semiconductor die has the first thickness in the MRAM region, and An inner surface of the recess is attached to the backside of the semiconductor die in the MRAM region with an adhesive.

4. The packaged semiconductor device according to claim 1, wherein: Also includes: a redistribution layer (RDL) structure formed on the active side of the semiconductor die, the RDL structure comprising a plurality of metal structures electrically contacting a plurality of die pads on the active side of the semiconductor die, the plurality of metal structures providing a plurality of external contact pads on an outermost surface of the RDL structure; as well as A plurality of solder balls are attached to the plurality of external contact pads.

5. The packaged semiconductor device according to claim 4, wherein: Also includes: a bottom cover comprising the soft magnetic material, the bottom cover having a second major surface positioned on the outermost surface of the RDL structure, wherein The bottom cover includes a plurality of openings aligned with the plurality of solder balls.

6. The packaged semiconductor device according to claim 5, wherein: There is a combined height between the second major surface of the bottom cover and the first major surface of the top cover, and A lateral spacing distance between a sidewall of the recess and a perimeter of the MRAM cell array has a value greater than the combined height.

7. The packaged semiconductor device according to claim 1, wherein: Also includes: a bottom cover comprising a soft magnetic material positioned on the active side of the semiconductor die, wherein the bottom cover comprising a plurality of openings aligned with a plurality of die pads on the active side of the semiconductor die; as well as A plurality of solder balls are attached to the plurality of die pads.

8. The packaged semiconductor device according to claim 1, wherein: Also includes: a second top cover, the second top cover comprising the soft magnetic material, a second recess formed in the first main surface of the second top cover, wherein The semiconductor die additionally includes a second MRAM array, and The second recess is positioned on the second MRAM cell array.

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