Security processor and operation method thereof, method for encrypting or decrypting data

Abstract

A security processor and an operation method thereof, and a method for encrypting or decrypting data are provided. The security processor includes: a random number generator, which is configured to generate a first random number; and a modulus calculator, which is configured to generate a first random operand based on first input data and the first random number, and generate output data by performing a modulus operation on the first random operand, wherein a result value of performing the modulus operation on the first input data is the same as a result value of performing the modulus operation on the first random operand.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0005855 filed on January 16, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a security processor, and more particularly, to a security processor capable of effectively protecting a computer system from a side channel attack (SCA (side channel attack)) and an operating method of the security processor. Background Art

[0004] The security processor may perform security algorithms such as cryptographic operations by using information that requires security (e.g., keys). The leakage of confidential information based on the security processor implementing the cryptographic operation may be referred to as a side channel, and the attack method using the side channel may be referred to as SCA. The security processor may adopt countermeasures against SCA to avoid compromising the cryptographic operation.

[0005] A template attack is an example of an SCA. In a template attack, an attacker can create a "template" using a device that is similar to the target of the attack. The attacker has access to a virtually unlimited number of inputs and attack operations on their copy of the target device. Thus, the attacker can create a model of how the side channel information relates to confidential information on the target device by recording the side channel information for a large number of inputs processed on the copy of the device. For example, the attacker can create a model of how the amount of power on the target device corresponds to the input when performing a cryptographic operation.

[0006] Defense techniques against SCA, including shielding or hiding side channel information, may affect the performance of the security processor. For example, implementing defense techniques may increase the circuit area or average power consumption of the security processor. In addition, these defense techniques may not provide adequate protection against certain SCAs such as template attacks and power analysis attacks. Summary of the invention

[0007] The inventive concept provides a security processor and an operating method thereof, the security processor being capable of effectively preventing a side channel attack (SCA) while minimizing increased power consumption or performance overhead.

[0008] According to one aspect of the present invention, a security processor is provided, comprising: a random number generator, which is configured to generate a first random number; and a modulus calculator, which is configured to generate a first random operand based on first input data and the first random number, and generate output data by performing a modulus operation on the first random operand, wherein, for any value of the first input data (i.e., for any value of the first input data to be processed by the security processor), a result value of the modulus operation on the first input data is the same as a result value of the modulus operation on the first random operand.

[0009] According to another aspect of the present invention, a security processor is provided, comprising: a random number generator configured to generate a first random number; a modulus calculator configured to generate a first random operand by multiplying a modulus by the first random number and adding the multiplication result to first input data, and then performing a modulo operation of dividing the first random operand by the modulus to generate output data.

[0010] According to one aspect of the present invention, there is provided an operating method of a security processor, the operating method comprising: generating a first random number; generating a first random operand based on a modulus, the first random number and first input data; and generating output data based on the first random operand, wherein, for any value of the first input data, a remainder when the first random operand is divided by the modulus is the same as a remainder when the first input data is divided by the modulus.

[0011] A method for encrypting or decrypting data is described. The method includes: generating a random number; multiplying the random number by a modulus; generating a random operand by adding the result of the multiplication to input data; generating output data by performing a modulo operation on the random operand using the modulus; and performing a cryptographic operation (e.g., encrypting data or decrypting data) based on the output data. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram illustrating an electronic system according to an example embodiment;

[0014] Figure 2 is a block diagram illustrating a security processor according to an example embodiment;

[0015] Figure 3 is a block diagram illustrating a random operand generator according to an example embodiment;

[0016] Figure 4 is a block diagram illustrating a security processor according to an example embodiment;

[0017] Figure 5 and Figure 6 is a diagram illustrating the operation of an arithmetic processor according to an example embodiment;

[0018] Figure 7 is a diagram illustrating a re-encoder according to an example embodiment;

[0019] Figure 8 shows a recoding table according to an example embodiment;

[0020] Fig. 9 shows a control signal table according to an example embodiment;

[0021] Fig.10 is a circuit diagram illustrating a local multiplier according to an example embodiment;

[0022] Fig.11 is a block diagram illustrating a security processor according to an example embodiment;

[0023] Fig.12 is a block diagram illustrating a security processor according to an example embodiment;

[0024] Fig.13 is a diagram illustrating the operation of a security processor according to an example embodiment;

[0025] Fig.14 is a block diagram illustrating a security processor according to an example embodiment; and

[0026] Fig.15 is a block diagram illustrating an application processor according to example embodiments. DETAILED DESCRIPTION

[0027] Figure 1 is a block diagram illustrating an electronic system 1 according to an example embodiment.

[0028] refer to Figure 1 , the electronic system 1 may include a security processor 10, a memory 20, and a central processing unit (CPU) 30. The electronic system 1 may correspond to various types of systems including, for example, a laptop computer, a mobile phone, a smart phone, a tablet personal computer (PC), and a personal digital assistant (PDA).

[0029] The CPU 30 may output various control signals for controlling the security processor 10 and the memory 20. In another embodiment, an application processor (AP) may perform the function of the CPU 30.

[0030] The memory 20 may store data under the control of the CPU 30 or the security processor 10. In an embodiment of the inventive concept, the memory 20 may record input data ID received from an external source, provide the input data ID to the security processor 10 under the control of the CPU 30, receive output data OD from the security processor 10, and record the received output data OD, wherein the output data OD is a result of performing a security operation on the input data ID.

[0031] The electronic system 1 may also include a security processor 10 (which may be separate from the CPU 30) that is capable of implementing fast arithmetic processing related to security operations. The security processor 10 may perform operations using confidential information. The security processor 10 may also be referred to as a secure calculator. In one embodiment, the security processor 10 may perform encryption or decryption operations using a personal key, a private key, or both in a public key infrastructure (PKI).

[0032] The security processor 10 may perform various operations related to encryption or decryption operations. For example, the security processor 10 may perform all operations related to encryption or decryption of data. Alternatively, the security processor 10 may only perform some of the multiple operations related to all encryption or decryption operations.

[0033] According to an embodiment of the inventive concept, data processed by the encryption or decryption operation of the security processor 10 may be referred to as input data ID, and data generated as a result of the encryption or decryption operation may be referred to as output data OD. In one embodiment, the input data ID may represent a private key or a public key in a PKI, and the output data OD may represent data encrypted or decrypted based at least in part on the private key, the public key, or both.

[0034] The encryption or decryption operation in the security processor 10 may include one or more multiplication operations. For example, when the security processor 10 executes a public key algorithm, the security processor 10 may perform arithmetic operations (addition, subtraction, multiplication, remainder operations, and modulus operations, etc.) on relatively large numbers. In some cases, the operation may be identified as secure when the size of the operand is greater than a certain threshold (e.g., at least 1024 bits in the case of the Rivest Shamir Adleman (RSA) algorithm).

[0035] For operations using large operands, the security processor 10 can implement digital-serial multiplication. As an example, Algorithm 1 for performing general serial multiplication is described as follows:

[0036]

[0037]

[0038] Algorithm 1

[0039] As another example, Algorithm 2 for performing digital serial multiplication is described as follows:

[0040]

[0041]

[0042] Algorithm 2

[0043] Referring to Algorithm 1 and Algorithm 2 above, digital serial multiplication is a special case of general serial multiplication, which can multiply several bits b of the multiplier B at a time. i Perform calculations.

[0044] When performing a multiplication operation as described above, the power consumed by the security processor 10 is affected by the operation value. Therefore, when similar operations are frequently performed, SCA such as a template attack can be used to identify the input data value (e.g., A or B). Additionally or alternatively, confidential information such as a key of the security processor 10 can also be analyzed.

[0045] Hiding techniques and shielding techniques can be employed as countermeasures against this type of SCA. Hiding techniques can refer to methods of reducing the variation in power consumption when processing different inputs by reducing side channel signals (or by increasing noise). However, hiding techniques may result in a significant increase in circuit area, average power consumption, or both (e.g., an increase of more than two times). In addition, if actual operations are performed only when the clock signal is in a specific state (e.g., a low state), overall performance may be reduced.

[0046] The masking technique may refer to randomizing the input by performing a masking operation before the encryption operation. Then, an unmasking operation may be performed after the encryption operation to cancel the masking operation (obtaining a mathematically equivalent operation). However, when the input data value (i.e., A or B) in the multiplication operation corresponds to "0", the masking effect is lost, and thus the information of the security processor 10 may still be at risk of information leakage.

[0047] Therefore, according to an embodiment of the present disclosure, the security processor 10 can provide a random characteristic to the input data ID by changing the input data ID targeted by the SCA based on a random number. This can enable the security processor 10 to minimize the risk of leaking information during the SCA targeting the input data ID. That is, the power consumption during the operation on the actual input data ID can be randomly changed, so the vulnerability to template attacks can be eliminated or reduced.

[0048] To this end, the security processor 10 may include a random number generator 100 and a modulus calculator 200. The random number generator 100 may generate random numbers. For example, the random number generator 100 may generate random numbers based on an entropy signal generated by a user's motion, thermal noise of a resistor, short noise of a pn junction of a semiconductor, short noise generated by photons, radiation waves, etc. In another example, the random number generator 100 may generate random numbers based on an entropy signal that randomly changes in a metastable state.

[0049] The modulo calculator 200 may generate a random operand based on the input data ID received from the memory 20 and the random number received from the random number generator 100, and may output output data OD by performing a modulo operation on the random operand. The modulo operation may be an operation of outputting a remainder obtained by dividing the dividend by the divisor, and may also be referred to as a modulo operation.

[0050] Therefore, the electronic system 1 can perform cryptographic operations in the following manner: generate a random number using the random number generator 100; multiply the random number by a modulus, generate a random operand by adding the result of the multiplication to the input data ID, generate output data OD by performing a remainder operation on the random operand using the modulus at the modulus calculator 200; and perform the cryptographic operation based on the output data OD.

[0051] According to the technical idea of ​​the present invention, the modulus calculator 200 can perform a modulo operation on a random operand generated based on a random number and an input data ID, and the random operand can be different from the input data ID itself. Since the characteristics of the random operand vary according to the random number, the security processor 10 can have a strong immunity to SCA. For example, the use of a random operand can obscure the relationship between the input data ID and information leaked from the security processor 10 (e.g., power usage information).

[0052] Figure 2 is a block diagram showing a security processor according to an example embodiment. Figure 1 Description given.

[0053] refer to Figure 2 , the security processor 10 may include a random number generator 100 and a modulus calculator 200 , and the modulus calculator 200 may include a random operand generator 210 and an output data generator 220 .

[0054] The random number generator 210 can receive the random number RN from the random number generator 100, from the memory ( Figure 120) receives the first input data ID1. The random operand generator 210 can generate a random operand RO based on the random number RN and the first input data ID1. In one embodiment, the random operand generator 210 can generate the random operand RO by inputting the random number RN and the first input data ID1 into a specific formula. In the example, the random operand generator 210 can generate the random operand RO in the following manner: multiplying the modulus M with the random number RN, and then generating the random operand RO by adding the multiplication result to the first input data ID1 (where RO=ID1+RN*M). The modulus M can be the divisor of the modulus operation performed by the output data generator 220 to generate the output data OD.

[0055] The output data generator 220 may receive a random operand RO from the random operand generator 210, from the memory ( Figure 1 20) receives the second input data ID2. The output data generator 220 may perform an arithmetic operation (eg, addition, subtraction, multiplication, and division) on the random operand RO and the second input data ID2, and may generate the output data OD by performing a modulo operation using the modulus M as a divisor.

[0056] According to the properties of the remainder operation (mod), any numbers such as A, B, r and modulus M and any arithmetic operation △ (for example, any one of addition, subtraction, multiplication and division) can satisfy the following Formulas 1 and 2.

[0057] [Formula 1]

[0058] A mod M = (A + rM) mod M

[0059] [Formula 2]

[0060] (A△B)mod M={(A+rM)△B}mod M

[0061] ={A△(B+rM)}mod M

[0062] According to the above formula 1 and formula 2, the first input data ID1, the second input data ID2 and the random operand RO can satisfy formula 3 and formula 4.

[0063] [Formula 3]

[0064] ID1 mod M = (ID1 + RN * M) mod M

[0065] =RO mod M

[0066] [Formula 4]

[0067] (ID1△ID2)mod M={(ID1+RN*M)△ID2}mod M

[0068] =(RO△ID2)mod M

[0069] The security processor 10 according to the technical idea of ​​the present invention can perform a modulo operation on the random operand RO based on the random number RN instead of the first input data ID1. According to the nature of the modulo operation, the result of the modulo operation performed on the random operand RO can be the same as the result of the modulo operation performed on the first input data ID1, and the security processor 10 can effectively reduce the risk of SCA by performing the modulo operation on the random operand RO with the random characteristic added.

[0070] That is, because the modulo operation is performed on the randomized input RO△ID2 instead of the input itself (i.e., ID1△ID2), the security processor 10 can reduce the possibility of side channel information leakage. However, the operation itself and the output of the modulo operation remain unchanged. Therefore, the security processor 10 can generate the expected output and reduce the risk of SCA without substantially increasing the power consumption or chip area.

[0071] Figure 3 is a block diagram illustrating a random operand generator according to example embodiments.

[0072] refer to Figure 3 , the random operand generator 210 may include a multiplier 211 and an adder 212. The multiplier 211 may receive a random number RN and a modulus M, and may perform multiplication on the random number RN and the modulus M. In an example, the multiplier 211 may receive a random number RN and a modulus M from a security processor (e.g., Figure 1 A register within the security processor 10) receives the module M.

[0073] In an embodiment, the multiplier 211 may divide the random number RN into a plurality of unit random numbers, and may generate a plurality of unit moduli UM by multiplying each of the plurality of unit random numbers by the modulus M. The multiplier 211 may output the generated plurality of unit moduli UM to the adder 212 .

[0074] According to an embodiment, the multiplier 211 may divide the random number RN into a plurality of unit random numbers having a small unit size (e.g., 2 bits), may perform a plurality of partial multiplication operations for multiplying each of the plurality of unit random numbers and the modulus M, and thus may efficiently perform multiplication operations on a random number having a large number of bits and the modulus M. The adder 212 may add the plurality of unit moduli UM to the first input data ID1 by the number of digits to generate a random operand RO.

[0075] Figure 4 is a block diagram illustrating a security processor according to an example embodiment.

[0076] refer to Figure 4 The security processor 10 may include a random number register 213 , a multiplier 211 , an adder 212 , a random operand register 216 , and an internal memory 300 , and the multiplier 211 may include a recoder 214 and a local multiplier 215 .

[0077] The random number register 213 can be obtained from the random number generator ( Figure 1 100) receives the random number RN and outputs the random number RN having a specific number of bits (e.g., t bits) to the multiplier 211.

[0078] The recoder 214 may receive the random number RN and perform a recoding operation on the received random number RN. In an example, the recoding operation may correspond to a Booth recoding operation, which is applicable to logic elements used to implement a digital serial algorithm of the random number RN and the modulo M.

[0079] A plurality of local multiplication operations may be performed, each local multiplication operation being part of a multiplication of a random number RN by a modulus M, and a recoding operation corresponding to each local multiplication operation may be performed. The recoding operation may include replacing the value of the random number with a different value that is mathematically equal to the original value to efficiently implement the multiplication. When the recoding operation is performed, the number of local multiplication operations may be reduced. A typical recoding operation may include a Booth recoding operation.

[0080] In one embodiment, the recoder 214 may include a recoding table storing conversion information for converting each of the plurality of unit random numbers RN into a plurality of recoded values, and may generate a plurality of recoded values ​​from each of the plurality of unit random numbers based on the recoding table. Figure 7 Describe the recoding table in detail.

[0081] In an embodiment, the recoder 214 may include a control signal table storing corresponding information about the correspondence between the plurality of control signals SEL and each of the plurality of recoded values, and may output the plurality of control signals SEL for each of the plurality of recoded values ​​to the local multiplier 215 based on the control signal table. Figure 8 Describe the control signal table in detail.

[0082] The local multiplier 215 may receive the m-bit modulus M and a plurality of control signals SEL and generate a plurality of unit moduli UM based on the plurality of control signals SEL. The plurality of unit moduli UM may correspond to values ​​obtained by multiplying a plurality of unit random numbers by the modulus M, respectively.

[0083] The internal memory 300 can store data from outside the security processor 10 (e.g., Figure 1 The internal memory 300 may receive the original data OrgD received by the memory 20 in the memory 20, and may output the segmented data SD (data after the original data OrgD is segmented in units of m bits) to the adder 212. To this end, the internal memory 300 may be implemented as at least one storage device, and may include, for example, at least one of a volatile memory and a non-volatile memory.

[0084] Non-volatile memory may include flash memory, random access memory (RAM), phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM) and ferroelectric RAM (FRAM), etc., and volatile memory may include dynamic RAM (DRAM), static RAM (SRAM), synchronous DRAM (SDRAM), latches, triggers and registers, etc.

[0085] The adder 212 may receive a plurality of unit moduli UM and the segmentation data SD, and may also receive a round-up value Cr from the random operand register 21. The round-up value Cr may represent data corresponding to a portion of m bits exceeding the number of bits of the segmentation data SD in the calculation for the previous segmentation data SD. The adder 212 may generate a random operand RO of (m+a) bits by adding a plurality of unit moduli UM, the segmentation data SD, and the round-up value Cr by the number of digits. The adder 212 may store the generated random operand RO in the random operand register 216.

[0086] The random operand register 216 may store the random operand RO, and when the operation on all the original data OrgD is completed, the stored random operand RO may be output. Figure 4In the embodiment, the random operand register 216, the random number register 213 and the internal memory 300 are shown as being separated from each other. However, the present embodiment is not limited thereto. Two or more of the random operand register 216, the random number register 213 and the internal memory 300 may be implemented as a single storage element. In addition, in Figure 4 , an example is shown in which the adder 212 receives the segmentation data SD from the internal memory 300. However, this is only an example, and the adder 212 may receive the segmentation data SD from a memory external to the security processor 10 (e.g., Figure 1 20) receives segmentation data SD.

[0087] Figure 5 and Figure 6 are diagrams respectively illustrating operations of an arithmetic processor according to example embodiments.

[0088] refer to Figure 4 and Figure 5 , the multiplier 221 may receive a random number RN (e.g., a 4-bit random number RN) and divide the random number RN into a first unit random number URN1 and a second unit random number URN2, each of which is in units of two bits. The multiplier 221 may generate a 10-bit first unit modulus UM1 by multiplying the first unit random number URN1 by an 8-bit modulus M. The multiplier 221 may generate a 10-bit second unit modulus UM2 by multiplying the second unit random number URN2 by a modulus M (e.g., a modulus having 8 bits).

[0089] According to an embodiment of the inventive concept, the multiplier 221 may calculate a plurality of re-encoding values ​​for the random number RN based on the re-encoding table, and may multiply the modulus M by the first unit random number and the second unit random number by using a plurality of control signals corresponding to each of the plurality of re-encoding values ​​based on the control signal table. Figures 7 to 10 This is described in detail.

[0090] Figure 5 An embodiment in which both the first unit modulus UM1 and the second unit modulus UM2 have 10 bits is shown, but the inventive concept is not limited thereto. The number of bits of the first unit modulus UM1 and the number of bits of the second unit modulus UM2 can be greater than or less than 10 bits, depending on the result of multiplying the first unit random number URN1 and the second unit random number URN2 by the modulus M.

[0091] refer to Figure 4 and Figure 6, the adder 212 may receive the first unit modulus UM1 and the second unit modulus UM2 from the multiplier 221, receive the segmentation data SD from the internal memory 300, and receive the first round-up value Cr1 from the random operand register 216. The adder 212 may add the first unit module UM1, the second unit module UM2, the segmentation data SD, and the first round-up value Cr1 by digit. In one example, the second unit modulus UM2 is a value obtained by multiplying the second unit random number URN2 by the modulus M, and the position of the digit of the second unit random number URN2 is two digits higher than the position of the digit of the first unit random number URN1. Therefore, in order to obtain the required total number of digits, the addition may be performed by offsetting the second unit random number URN2 by two digits.

[0092] As a result of the addition, the adder 212 can generate 12-bit data. The first bit o0 to the eighth bit o7 (i.e., 8 bits corresponding to the segmented data SD) of the generated data can be stored as a calculated random operand RO in the random operand register 216. In the addition operation of the next segmented data SD, the ninth bit o8 to the twelfth bit o11 can be used as the second round-up value Cr2.

[0093] Figure 7 is a diagram illustrating a re-encoder according to example embodiments.

[0094] refer to Figure 4 and Figure 7 The recoder may include a recoding table for storing conversion information between the recoder input and the recoded value. The conversion information may include a plurality of recoded values ​​corresponding to the patterns of the plurality of recoder inputs, respectively. The recoder input Reco_In may include bits b of the unit random number. i and reference bit bref. The recoder input Reco_In can be based on the bit (b i and bref) have a form corresponding to one of the various modes. For example, the recoder input Reco_In may correspond to any one of the first mode Pat(1) to the eighth mode Pat(8). In one example, the unit random number includes 2 bits, and the reference bit bref is 1 bit.

[0095] According to the conversion information stored in the recoding table, the recoder input Reco_In can be mapped or converted to a recoded value corresponding thereto. In the example, the first recoded value Val(1) corresponding to the recoder input Reco_In having the first pattern Pat(1) is stored in the conversion information. In this example, when the bit b of the unit random number iWhen the reference bit bref has the first pattern Pat(1), the recoder may output a first re-encoded value Val(1).

[0096] Additionally or alternatively, a recoded value may be generated based on the above conversion operation, and the recoded value may be output in the form of a control signal sel[0:k]. In one example, when the random number is two bits, the control signal sel[0:k] may include four bits.

[0097] According to an embodiment of the inventive concept, when the Booth recoding method described above is applied, the recoded output may take a value from the set {-2, -1, 0, 1, 2}. Therefore, the recoded value corresponding to the recoder input having any one mode may be the same as the recoded value corresponding to the recoder input having another mode. That is, multiple recoder input modes may be mapped to the same recoded value.

[0098] In addition, based on the control signal sel[0:k], the local multiplier 215 can generate a result of multiplying the random number RN by any value in {-2, -1, 0, 1, 2} (e.g., a local multiplication coefficient) in a local multiplication operation. Therefore, in one local multiplication operation, the local multiplier 215 can receive the modulus M and the control signal sel[0:k] as inputs and generate any value in {-2M, -M, 0, M, 2M} through a local multiplication operation process.

[0099] Figure 8 A re-encoding table according to an example embodiment is shown.

[0100] refer to Figure 8 , when the random number RN is an 8-bit value "01101001", the random number RN can be converted as shown in Formula 5 so that the coefficients have values ​​in {-2, -1, 0, 1, 2}.

[0101] [Formula 5]

[0102] RN=01101001 (2)

[0103] =0.2 7 +1 2 6 +1 2 5 +0.2 4 +1 2 3 +0.2 2 +0.2 1 +1.20

[0104] =2·2 6 -1·2 4 -twenty two 2 +1·20 (1)

[0105] =1·2 6 +2 2 4 +2 2 2 +1·20 (2)

[0106] That is, the random number RN can be converted to (1)2·2 6 -1·2 4 -twenty two 2 +1·20 and (2)1·2 6 +2 2 4 +2 2 2 +1·20. The above two converted values ​​may have the same value 105 as the original random number RN.

[0107] According to the above conversion example, two bits of the unit random number URN can be converted to any one of the values ​​{-2, -1, 0, 1, 2}. Therefore, the 8-bit random number RN can be divided into four unit random numbers, each of which has two bits. For example, the two least significant bits can be divided into the first unit random number, the next two low bits can be divided into the second unit random number, the next two low bits can be divided into the third unit random number, and the two most significant bits can be divided into the fourth unit random number.

[0108] In addition, when it is assumed that the recoding operation is first performed from the low bit of the random number RN, the high bit of the unit random number performing the current recoding operation can be used as a reference bit in the next recoding operation. For example, when the recoding operation is performed on the second unit random number, the high bit of the two bits of the first unit random number can correspond to the reference bit Ref bit.

[0109] In the case of performing a re-encoding operation on the first unit random number including the two least significant bits, the bit corresponding to "0" may be defined as a reference bit Ref bit. Therefore, assuming that the two bits on which the current re-encoding operation is performed are b 2i+1 and b 2i , then the reference bit Ref bit in the current re-encoding operation can correspond to b 2i-1 , and the reference bit (Next Ref bit) in the next re-encoding operation can correspond to b 2i+1 .

[0110] The random number RN is "01101001 (2) In the example of ", the first unit random number can be "01" (from the first and second bits), and the reference bit can be "0". Figure 8As shown in the recoding table, the recoder input including the bits of the first unit random number and the reference bit Ref can correspond to "010", and the recoding value Recoding Value corresponding to the recoder input can be "1".

[0111] The second unit random number including the next two low bits may be "10" (from the third and fourth bits), and the reference bit Ref bit may be the high bit "0" from the previous first unit random number. Therefore, the recoder input including the bits of the second unit random number and the reference bit Ref bit may correspond to "100", and the recoded value corresponding to the recoder input may be "-2".

[0112] The third unit random number including the next two low bits may also be "10" (from the fifth and sixth bits), and the reference bit Ref bit may be the high bit "1" from the previous second unit random number. Therefore, the recoder input including the bits of the third unit random number and the reference bit Ref bit may correspond to "101", and the recoded value corresponding to the recoder input may be "-1".

[0113] The fourth unit random number including the next two low bits may be "01" (from the seventh and eighth bits), and the reference bit Ref bit may be the high bit "1" from the previous third unit random number. Therefore, the recoder input including the bits of the fourth unit random number and the reference bit Ref bit may correspond to "011", and the recoded value corresponding to the recoder input may be "2".

[0114] In other words, the re-encoder can receive "01101001 (2) " as the random number RN and generates "2", "-1", "-2" and "1" as re-encoded values.

[0115] In some examples, the recoding table is pre-generated and stored in the security processor, but the embodiment is not limited thereto. In one example, the recoding value corresponding to the recoder input shown in the recoding table can be obtained by calculating a specific formula, and a configuration for calculating the specific formula can be provided in the security processor to generate the recoding value through an operation process.

[0116] Fig. 9 A control signal table according to an example embodiment is shown.

[0117] refer to Figure 8 and Fig. 9 ,when Fig. 9When the re-encoded value shown in the control signal table corresponds to "-2", the first control signal sel0 to the fourth control signal sel3 may have a value of "1010", and when the re-encoded value corresponds to "-1", the first control signal sel0 to the fourth control signal sel3 corresponding thereto may have a value of "1001". In addition, when the re-encoded value corresponds to "0", the first control signal sel0 to the fourth control signal se13 may have a value of "0000". When the re-encoded value corresponds to "1", the first control signal sel0 to the fourth control signal sel3 may have a value of "0101". When the re-encoded value corresponds to "2", the first control signal sel0 to the fourth control signal sel3 may have a value of "0110". The above-mentioned first control signal sel0 to the fourth control signal sel3 can be used as a signal for selecting a coefficient to be multiplied by the module in the local multiplication operation described below.

[0118] According to an embodiment of the inventive concept, the re-encoder may provide the local multiplier with the reference Figure 8 The first control signal sel0 to the fourth control signal sel3 corresponding to the recoded values ​​described (e.g., "2", "-1", "-2" and "1"). In the example, the recoder can output "0101" as the first control signal sel0 to the fourth control signal sel3 to the local multiplier based on "1" (i.e., the recoded value corresponding to the first unit random number). The recoder can output "1010" as the first control signal sel0 to the fourth control signal sel3 to the local multiplier based on "-2" (i.e., the recoded value corresponding to the second unit random number).

[0119] Fig.10 is a circuit diagram illustrating a partial multiplier according to an example embodiment.

[0120] refer to Fig.10 , the modulus M (M[0] to M[n-1]) of the bit and the first control signal sel0 to the fourth control signal sel3 according to the re-encoding result of the random number can be provided to the local multiplier 225. Fig.10 , logic elements constituting one local multiplier 225 are shown, but more than two local multiplications may be performed together. Therefore, the security processor 10 may include more than two local multipliers 225. The local multiplier 225 may generate a (n+1)-bit unit modulus UMi[n:0] and a 1-bit symbol data UMi_neg as a result of multiplying an n-bit modulus M (M[0] to M[n-1]) by a 2-bit unit random number.

[0121] The local multiplication result value of the (n+1)-bit unit modulus UMi[n:0] and the 1-bit symbol data UMi_neg may be any one of {-2M, -M, 0, M, 2M} for the modulus M. The 1-bit symbol data UMi_neg may correspond to the first control signal sel0.

[0122] Multiple logic elements may be used to implement the local multiplier 225. Fig.10 , an example in which the local multiplier 225 includes a plurality of inverters 410, a plurality of AND gates, and a plurality of OR gates is shown. For example, in addition to the n-bit modulus M (M[0] to M[n-1]), a zero value may be further input to the right of the least significant bit (i.e., M[0]) of the n-bit modulus M (M[0] to M[n-1]). In addition, a zero value may be further input to the left of the most significant bit (i.e., M[n-1]) of the n-bit modulus M (M[0] to M[n-1]).

[0123] The local multiplier 225 may include a plurality of (e.g., n+2) inverters 225_1 corresponding to the n-bit modulus M (M[0] to M[n-1]) and the two zero values ​​described above. In addition, the first stage of the local multiplier 225 may also include a first AND gate block 225_2 and a first OR gate block 225_3. The first AND gate block 225_2 may include a plurality of AND gates (AND1_11, AND1_12 to AND1_(n+2)1, AND1(n+2)2). As an example, two AND gates may be arranged corresponding to each bit of the n-bit modulus M (M[0] to M[n-1]) and each of the two zero values. Taking the least significant bit M[0] of the n-bit modulus M (M[0] to M[n-1]) as an example, the first AND gate AND1_21 can receive the second selection signal sel1 and the least significant bit M[0] as input, and the second AND gate AND1_22 can receive the first selection signal sel0 and the inverted value of the least significant bit M[0] as input.

[0124] In addition, the first OR gate block 225_3 may include first to (n+2)th OR gates OR1_(n+2). Taking the least significant bit M[0] of the n-bit modulus M (M[0] to M[n-1]) as an example, the output of the first AND gate AND1_21 and the output of the second AND gate AND1_22 may be provided as the input of the second OR gate OR1_2.

[0125] The second stage of the local multiplier 225 may also include a second AND gate block 225_4 and a second OR gate block 225_5. As an example, the second AND gate block 225_4 may include a plurality of AND gates (AND2_11, AND2_12 to AND2_n1, AND2_n2). Taking the two least significant bits M[0] and M[1] of the n-bit modulus M (M[0] to M[n-1]) as an example, the first AND gate AND2_21 may receive the fourth selection signal sel3 and the output of the third OR gate OR1_3 of the first OR gate block 225_3, and the second AND gate AND2_22 may receive the third selection signal sel2 and the output of the second OR gate OR1_2 of the first OR gate block 225_3.

[0126] The second OR gate block 225_5 may include a first OR gate OR2_1 to an nth OR gate OR2_n. Taking the least significant bit M[0] of the n-bit modulus M (M[0] to M[n-1]) as an example, the output of the first AND gate AND2_21 and the output of the second AND gate AND2_22 may be provided as the input of the second OR gate OR2_2. The detailed connection relationship of other logic elements included in the local multiplier 225 may be implemented as shown in the accompanying drawings, and its detailed description is omitted.

[0127] exist Fig.10 In the logic element shown, the above re-encoding result can be reflected in the local multiplication operation through the first control signal sel0 to the fourth control signal sel3. For example, the first control signal sel0 and the second control signal sel1 can determine the positive / negative sign, and the third control signal sel2 and the fourth control signal sel3 can determine whether the coefficient of the local multiplication corresponds to "1" or "2".

[0128] When the local multiplication result is negative, the sign data UMi_neg can be used to generate a two's complement code. For example, -2M can be calculated as In this equation, (M<<1) corresponds to multiplication by 2, and the bitwise NOT can be used. and "+1" to generate two's complement code.

[0129] The local multiplier according to an embodiment of the inventive concept may generate a unit modulus (UMi[n:[0]) and a sign data UMi_neg corresponding to a value obtained by multiplying a unit random number by the modulus M based on the first control signal sel0 to the fourth control signal sel3, and may output the generated unit modulus (UMi[n:0]) and UMi_neg to an adder (e.g., Figure 3 adder 212).

[0130] Fig.11FIG. 1 is a diagram showing a security processor 10a according to an example embodiment. The security processor 10a may be similar to the reference Figure 2 The security processor 10 described above may include multiple random operand generators. Figure 2 Description given.

[0131] refer to Fig.11 The security processor 10a may include a random number generator 100a and a modulus calculator 200a. The modulus calculator 200a may include a first random operand generator 210a, a second random operand generator 230a, and an output data generator 220a.

[0132] The first random operand generator 210a may receive a first random number RN1 from the random number generator 100a, from a memory (eg, Figure 1 20) receives the first input data ID1. The first random operand generator 210a can generate the first random operand RO1 based on the first random number RN1 and the first input data ID1. In an example, the first random operand generator 210a can generate the first random operand RO1 by multiplying the first random number RN1 by modulus M and then adding it to the first input data ID1 (where RO1=ID1+RN1*M).

[0133] The second random operand generator 230a may receive a second random number RN2 from the random number generator 100a, from a memory (eg, Figure 1 20) receives the second input data ID2. The second random operand generator 230a can generate the second random operand RO2 based on the second random number RN2 and the second input data ID2. In an example, the second random operand generator 230a can generate the second random operand RO2 by multiplying the second random number RN2 by modulus M and then adding it to the second input data ID2 (where RO2=ID2+RN2*M).

[0134] The output data generator 220a can generate the output data OD by receiving the first random operand RO1 and the second random operand RO2, performing arithmetic operations (e.g., addition, subtraction, multiplication, and division) on the first random operand RO1 and the second random operand RO2, and performing a modulo operation on the result of the arithmetic operation, in which the modulus M is used as a divisor.

[0135] According to the properties of the remainder operation (mod), any numbers such as A, B, r, and modulus M and any arithmetic operation Δ (for example, any one of addition, subtraction, multiplication, and division) can satisfy the following Formula 6.

[0136] [Formula 6]

[0137] (A△B)mod M={(A+rM)△(B+rM)}mod M

[0138] Formula 7 for the first input data ID1, the second input data ID2, the first random operand RO1, and the second random operand RO2 is established based on Formula 6 above.

[0139] [Formula 7]

[0140] (ID1△ID2)mod M={(ID1+RN1*M)△(ID2+RN2*M)}mod M

[0141] =(RO1△RO2)mod M

[0142] That is, the security processor 10a according to the embodiment of the present invention can perform a modulo operation on the first random operand RO1 calculated based on the first input data ID1 and the first random number RN1, and perform a modulo operation on the second random operand RO2 calculated based on the second input data ID2 and the second random number RN2. Similar to the case of the first input data ID1, the security processor 10a can perform a modulo operation on the second input data ID2 by using the second random operand RO2 generated using the second random number RN2. Therefore, the security of the security processor 10a can be improved (for example, by reducing the vulnerability of the security processor 10a to SCA based on power analysis).

[0143] Fig.12 1 is a block diagram showing a security processor 10b according to an example embodiment. The security processor 10b may be similar to the reference Figure 2 The security processor 10 described above can generate multiple random numbers and multiple random operands for each operation. Figure 2 Description given.

[0144] refer to Fig.12 , the security processor 10b may include a random number generator 100b and a modulus calculator 200b. The modulus calculator 200b may include a random operand generator 210b and an output data generator 220b. The random number generator 100b may output a first random number RN1 to the random operand generator 210b. The random operand generator 210b may use the first random number RN1 to generate a first random operand ROa, and the output data generator 220b may use the first random operand ROa in an operation on at least some of the second input data ID2.

[0145] The random number generator 100b may output a second random number RN2 different from the first random number RN1 to the random operand generator 210b when operating on the second input data ID2. For example, the random number generator 100b may update the output data signal from the first random number RN1 to the second random number RN2 when operating on the second input data ID2. The random operand generator 210b may use the second random number RN2 to generate a second random operand ROb, and the output data generator 220b may use the second random operand ROb in the operation of at least some of the second output data ID2.

[0146] According to an embodiment of the inventive concept, by updating the random numbers output from the random number generator 100 b during the operation on the input data, the randomness of the first and second random operands ROa and ROb may be further improved, and the input data ID1 may be effectively protected from SCA.

[0147] Fig.13 is a diagram illustrating the operation of the security processor 10 b according to an example embodiment.

[0148] refer to Fig.12 and Fig.13 , the second input data ID2 may include the first sub-input data SID1 and the second sub-input data SID2. The random number generator 100b may generate a first random number RN1, and the random operand generator 210b may calculate a first random operand ROa using the first random number RN1. The output data generator 220b may use the first random operand ROa generated based on the first random number RN1 in the operation on the first sub-input data SID1 in the second input data ID2. For example, the output data generator 220b may generate the first sub-output data SOD1 by multiplying the first sub-input data SID1 by the first random operand ROa.

[0149] Next, the random number generator 100b may generate a second random number RN2, and the random operand generator 210b may calculate a second random operand ROb using the second random number RN2. The output data generator 220b may use the second random operand ROb generated based on the second random number RN2 in the operation of the second sub-input data SID2 in the second input data ID2. In an example, the output data generator 220b may generate the second sub-output data SOD2 by multiplying the second sub-input data SID2 by the second random operand Rob.

[0150] The output data generator 220b may generate a remainder value obtained by adding the generated first sub-output data SOD1 and second sub-output data SOD2 by the digit number and by dividing the added result by the modulus M as the output data OD. In one example, the output data generator 220b may add the first sub-output data SOD1 and a result obtained by matching the least significant bit of the second sub-output data SOD2 and the least significant bit of the second sub-input data SID2.

[0151] Fig.14 1 is a diagram showing a security processor 10c according to an example embodiment. The security processor 10c may be similar to the reference 1 except that the security processor 10c may include a random number register within a random operand generator. Figure 2 The security processor 10 described above is omitted. Figure 2 Description given.

[0152] refer to Fig.14 The security processor 10c may include a random number generator 100c and a modulus calculator 200c. The modulus calculator 200c may include a random operand generator 210c and an output data generator 220c. The random operand generator 210c may include a random number register 223c for storing random numbers.

[0153] The random operand generator 210c may output a random number request signal RSig_RN to the random number generator 100c. The random number generator 100c may store the updated random number RN_upt updated in response to the random number request signal RSig_RN in the random number register 223c.

[0154] In one embodiment, when a specific event occurs, the random operand generator 210c may output a random number request signal RSig_RN to the random number generator 100c. In one embodiment, the specific event may be completion of recoding of input data. In another embodiment, the specific event may be completion of recoding of a specific number of bits.

[0155] In another embodiment, the random operand generator 210 c may output the random number request signal RSig_RN to the random number generator 100 c when the time point of a specific event has passed.

[0156] Fig.15 is a block diagram illustrating an application processor 1000 according to an example embodiment.

[0157] refer to Fig.15, the application processor 1000 may be implemented as a system on a chip (SoC). The application processor 1000 may include a central processing unit (CPU) 1010, a security processor 1020, a modem 1030, a display controller 1040, a read-only memory (ROM) 1050, a storage controller 1060, and a RAM 1070. In addition to the components shown, the application processor 1000 may also include other components such as a power management unit, a graphics processing unit (GPU), and a clock unit.

[0158] The CPU 1010 may process or execute programs or data stored in the ROM 1050 and / or the RAM 1070. The ROM 1050 may store programs and / or data. In addition, the RAM 1070 may temporarily store programs, data, and instructions. The storage controller 1060 may perform an interface connection with an external storage device, and may read or write data by controlling the external storage device according to a data access request. In addition, the display controller 1040 may control the display operation of the screen by driving the display device.

[0159] According to an embodiment of the inventive concept, the security processor 1020 may perform security operations as described herein. In one embodiment, the security processor 1020 may include a modulus calculator 1021 and may perform a modulus operation using a random number. Fig.15 Although not shown in FIG. 1 , the security processor 1020 may also include a random number generator and the like.

[0160] When the modem 1030 is provided in the application processor 1000, the application processor 1000 may be referred to as a modem application processor (ModAP). Information requiring security calculation may be transmitted / received to / from an external system through the modem 1030. At this time, the security processor 1020 may perform the security calculation according to the above-described embodiment.

[0161] As described above, embodiments have been disclosed in the drawings and the specification. Although specific terms have been cited herein to describe the embodiments, it should be understood that these terms are only used to describe the technical ideas of the inventive concept, and do not limit the scope of the inventive concept as defined in the claims. Therefore, it will be understood by those of ordinary skill in the art that various modifications and equivalent embodiments are possible without departing from the scope of the inventive concept. Therefore, the true scope of protection of the inventive concept should be determined by the technical ideas of the appended claims.

Claims

1. A security processor, comprising: a random number generator configured to generate a first random number and a second random number; as well as A modulus calculator, the modulus calculator comprising: a first random operand generator configured to generate a first random operand by multiplying a modulus by the first random number and adding the multiplication result to first input data; a second random operand generator configured to generate a second random operand by multiplying the modulus by the second random number and adding the multiplication result to second input data; and an output data generator configured to generate output data by performing a modulo operation after performing an arithmetic operation on the first random operand and the second random operand, wherein the modulus is the divisor of the remainder operation, and For any value of the first input data, a result value of performing the modulo operation on the first input data is the same as a result value of performing the modulo operation on the first random operand.

2. The security processor according to claim 1, wherein: The first random operand generator comprises: a multiplier configured to multiply the modulus by the first random number; An adder configured to generate the first random operand by adding the first input data and a multiplication result of the multiplier.

3. The security processor according to claim 2, wherein: The multiplier comprises: a re-encoder configured to generate a plurality of control signals respectively corresponding to a plurality of unit random numbers constituting the first random number; a unit modulus generator configured to generate a plurality of unit moduli corresponding to values ​​obtained by multiplying the modulus by the plurality of unit random numbers based on the plurality of control signals, The adder is configured to generate the first random operand by adding the plurality of unit moduli to the first input data in digit order.

4. The security processor according to claim 3, wherein: The recoder is configured to convert each of the plurality of unit random numbers into a plurality of re-encoded values, and to generate the plurality of control signals based on the plurality of re-encoded values.

5. The security processor according to claim 4, wherein: The re-encoder comprises: a recoding table storing conversion information for converting the plurality of unit random numbers into the plurality of recoded values ​​based on Booth recoding; and a control signal table storing corresponding information about the plurality of control signals respectively corresponding to the plurality of re-encoded values, wherein the recoder is configured to convert the plurality of unit random numbers into the plurality of recoded values ​​based on the recoding table, and output the plurality of control signals for each of the plurality of recoded values ​​to the unit modulo generator based on the control signal table, and The unit mode generator is configured to generate the plurality of unit modes based on the plurality of control signals.

6. The security processor according to claim 3, further comprising a memory storing raw data including the first input data, in, The modulus calculator is configured to sequentially load a plurality of pieces of segmented data obtained by segmenting the original data in units of m bits, Here, m is a natural number.

7. The security processor according to claim 6, wherein: The adder is configured to perform a second operation on a second piece of the plurality of pieces of split data before performing a first operation on a first piece of the plurality of pieces of split data. The first random operand generator further comprises a first register, the first register being used to store a rounded-up value exceeding m bits in the second operation, and The adder is configured to generate the first random operand by adding the round-up value loaded from the first register, the plurality of unit moduli, and the first split data by digits.

8. A security processor comprising: a random number generator configured to generate a first random number; as well as A modulus calculator, the modulus calculator comprising: a random operand generator, the random operand generator being configured to generate a first random operand by multiplying a modulus with the first random number and adding the multiplication result to first input data; and an output data generator, the output data generator being configured to receive second input data, The random number generator is further configured to generate a second random number different from the first random number during operation on the second input data. The random operand generator is further configured to generate a second random operand by multiplying the modulus by the second random number and adding the multiplication result to the first input data during an operation on the second input data. The second input data includes first sub-input data and second sub-input data, and The output data generator is further configured to generate first sub-output data by performing an arithmetic operation on the first random operand and the first sub-input data, generate second sub-output data by performing the arithmetic operation on the second random operand and the second sub-input data, and generate output data by performing a modulo operation after adding the first sub-output data and the second sub-output data, The modulus is the divisor of the remainder operation.

9. The security processor according to claim 8, wherein: The random operand generator further includes a register storing at least one random number received from the random number generator, and wherein the random operand generator is configured to output a random number request signal to the random number generator after outputting the first random operand to the output data generator, and The random number generator is configured to output the second random number to the register in response to the random number request signal.

10. The security processor according to claim 8, wherein: The modulo calculator is configured to: generating a plurality of control signals corresponding to the first random number based on Booth recoding the first random number, and A plurality of unit moduli corresponding to result values ​​of multiplying the first random number by the moduli are generated based on the plurality of control signals.

11. The security processor according to claim 10, wherein: The modulus calculator is configured to generate the first random operand by adding the plurality of unit moduli to the first input data by a number of digits.

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