Method of manufacturing a molded semiconductor package with optical detection features

Abstract

A molded semiconductor package includes a molding compound having a first major surface, a second major surface opposite the first major surface, and an edge extending between the first and second major surfaces. A semiconductor chip is embedded in the molding compound. A plurality of metal pads are also embedded in the molding compound and electrically connected to the semiconductor chip. The metal pads have a bottom surface that is uncovered by the molding compound at the second major surface of the molding compound. The metal pads disposed at a periphery of the molded package have a side surface that is uncovered by the molding compound at the edge of the molding compound. The surfaces of the metal pads that are uncovered by the molding compound are plated. The side surface of each metal pad disposed at a periphery of the molded package is recessed inward from the edge of the molding compound. A corresponding method of manufacture is also described.

Description

[0001] This application is a divisional application of the invention patent application filed on March 1, 2017, with application number 201710116951.9 and entitled "Method for manufacturing a molded semiconductor package having optical detection features". Technical Field

[0002] This application relates to molded semiconductor packages, and more particularly to molded semiconductor packages having optical detection features. Background Technology

[0003] Many types of molded semiconductor packages have so-called LTI (leadtip inspection) features at the edges of the molded package to allow optical inspection of the joints or connections between the metal pads of the molded package, which has a substrate such as a circuit board to which the molded package is attached. The LTI feature is a portion of the metal pads at the periphery of the molded package that extends to the edge of the molded package and is not covered by molding compound, thus allowing optical inspection from the side.

[0004] A single molded package is typically formed from a molded substrate comprising multiple semiconductor chips and metal pads electrically connected to the chips. The semiconductor chips and the metal pads are embedded in a molding compound. The metal pads are exposed at the bottom surface of the molding compound. The metal pads of adjacent packages are connected. These connections are severed by a mechanical sawing process. The exposed portion of each cut metal pad forms an LTI (Limited Injection Technology) feature on the side of the single molded package, which is not covered by the molding compound due to the package individualization process.

[0005] However, LTI features are typically achieved using a two-step sawing process. Furthermore, due to the two-step sawing process, metal burrs are often present on the LTI features. The metal material of the pads can also become contaminated during sawing. In both cases, the likelihood of successful optical inspection is reduced due to the degraded LTI features. Alternatively, LTI features can be achieved using a selective etching process with non-electrolytic plating. However, selective etching is limited by leadframe suppliers and requires a suitable anisotropic copper etchant.

[0006] Therefore, a simpler and more cost-effective technology is needed to manufacture molded semiconductor packages with optical detection features. Summary of the Invention

[0007] According to one embodiment of a method for manufacturing a molded semiconductor package, the method includes: providing a molded semiconductor substrate comprising a molding compound, wherein a semiconductor chip and metal pads are embedded in the molding compound, each metal pad being electrically connected to a corresponding one of the semiconductor chips and not covered by the molding compound at a first main surface; and individualizing the molded semiconductor substrate into individual molded packages, each of the individual molded packages comprising one or more semiconductor chips and corresponding metal pads, each metal pad being... The package has a bottom surface not covered by the molding compound at the first main surface, and metal pads disposed around the periphery of each molded package also have sides not covered by the molding compound at the edges along which the molded package is individualized; the molded package is immersed in a chemical bath that roughens the bottom surface of each metal pad and removes burrs from the sides of the metal pads disposed around the periphery of each molded package; and after immersing the molded package in the chemical bath, the sides of the metal pads not covered by the molding compound are plated.

[0008] According to one embodiment of a molded semiconductor package, the molded semiconductor package includes: a molding compound having a first main surface, a second main surface opposite to the first main surface, and an edge extending between the first main surface and the second main surface; a semiconductor chip embedded in the molding compound; and a plurality of metal pads embedded in the molding compound and electrically connected to the semiconductor chip. The metal pads have a bottom surface at the second main surface of the molding compound that is not covered by the molding compound. The metal pads disposed around the periphery of the molded package have side surfaces at the edge of the molding compound that are not covered by the molding compound. The side surfaces of the metal pads not covered by the molding compound are plated. The side surfaces of each metal pad disposed around the periphery of the molded package are recessed inward from the edge of the molding compound.

[0009] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0010] The elements in the accompanying drawings are not necessarily drawn to scale relative to each other. Similar reference numerals denote corresponding similar parts. Features of the various illustrated embodiments may be combined unless they are mutually exclusive. Various embodiments are illustrated in the accompanying drawings and are described in detail below.

[0011] Figure 1A flowchart illustrating one embodiment of a method for manufacturing a molded semiconductor package with optical detection features.

[0012] Figure 2 and Figure 3 Show Figure 1 The corresponding top-down views show the semiconductor substrates molded during different stages of the manufacturing process.

[0013] Figure 4 Show Figure 1 A more detailed flowchart of the roughening / deburring and plating processes in the method shown is provided.

[0014] Figure 5 It shows the implementation Figure 4 An embodiment of a multi-stage tool with separate compartments or immersion tanks for roughening / deburring and plating processes, as shown.

[0015] Figure 6 Showing according to Figures 1 to 5 The bottom perspective view of a molded semiconductor package manufactured using the described method.

[0016] Figure 7 Showing soldered to the circuit board Figure 6 A side perspective view of a molded semiconductor package.

[0017] Figure 8 Showing according to Figures 1 to 5 A cross-sectional view of a molded semiconductor package having a flip-chip configuration, manufactured by the described method.

[0018] Figure 9 Showing according to Figures 1 to 5 A cross-sectional view of a molded semiconductor package manufactured by the described method and having a wire bonding configuration. Detailed Implementation

[0019] According to the embodiments described herein, leadless molded semiconductor packages such as QFN (quad-flat no-leads), DFN (dual-flat no-leads), and TSNP (Thin Small Non-Leaded Package) are manufactured from molded substrates and have optical detection features, also referred to herein as Lead End Detection (LTI) features, at the edges of individual molded packages. Leadless semiconductor packaging technology, also commonly referred to as MLP (micro leadframe) and SON (small-outline no leads), is a surface mount technology for connecting integrated circuits (ICs) to the surface of printed circuit boards (PCBs) without through-hole connections. The leadless semiconductor packages described herein are manufactured by individualizing a molded semiconductor substrate into individual molded packages using a single-step sawing process, followed by plating the LTI features. In this way, after individualization, the exposed surface of the metal pads of the individual package can be roughened, and the LTI features are plated.

[0020] Figure 1 An embodiment of a method 100 for manufacturing a molded semiconductor package from a molded semiconductor substrate 200 is shown. The method 100 refers to... Figure 2 and Figure 3 To describe, the Figure 2 and Figure 3 Multiple molded semiconductor substrates 200 are shown during different stages of the manufacturing process.

[0021] Method 100 includes providing molded semiconductor substrates 200 (block 102), each of said molded semiconductor substrates 200 including a molding compound 202, a semiconductor chip (out of sight), and metal pads 204 embedded in said molding compound 202. Each metal pad 204 is electrically connected to a corresponding one in the semiconductor chip and is not covered by the molding compound 202 at the bottom surface of said bottom surface of said bottom surface of said bottom surface of the molding compound 202. Figure 2 and Figure 3The surfaces visible in the exploded view. Any standard process for manufacturing the molded semiconductor substrate 200 can be used. For example, the metal pads 204 can be implemented using leads from a lead frame strip. In a wire bonding configuration, the semiconductor chip can be attached to the chip pads of the lead frame strip. In a flip-chip configuration, the terminals of the semiconductor chip can be connected, for example, to the metal pads 204 beneath the chip via metal pillars. In either chip configuration, both the chip and the metal pads 204 are embedded in the molding compound 202. During the manufacturing of the molded substrate 200, the bottom surface of the metal pads 204 contacts the substrate and is therefore not covered by the molding compound 202 at the bottom main surface of the molding compound 202.

[0022] One or more molded semiconductor substrates 200 can be temporarily attached to a carrier 206, such as a substrate, or a UV-curable tape 208 (box 104). In the case of the UV-curable tape 208, the UV-curable tape 208 has heat and chemical resistance, allowing it to withstand chemical baths. The UV-curable tape 208 may include a base film, an adhesive on the base film, and a pad on the adhesive. In one embodiment, the base film comprises a polyolefin, the adhesive comprises acrylic acid, and the pad comprises polyethylene terephthalate.

[0023] The individual molded semiconductor package 210 formed from each molded semiconductor substrate 200 is... Figure 2 The dashed box in the figure shows that they have not yet been individualized in the manufacturing process, that is, they have not yet been separated into individual packages, for example, by sawing. Figure 2 and Figure 3 The decomposition diagram in the figure shows the process before individualization. Figure 2 ) and after unitization ( Figure 3 One of the individual molded packages 210.

[0024] The molded semiconductor substrate 200 is then individualized into individual molded packages 210 along saw marks 212 (box 106). As used herein, the term "individualization" generally refers to the act or process of separating a combined unit into an individual molded package 210. In one embodiment, a single-step sawing process is used to individualize the molded semiconductor substrate 200, in which the saw blade cuts the molding compound 202 only once along each saw mark 212. This avoids a two-step sawing process in which the molding compound is partially cut, further processing such as chemical etching is performed, and then the molding compound is cut a second time along the same saw mark to complete the individualization of the molded package. Avoiding this two-step sawing process reduces the overall cost of the individual molded package. The molded semiconductor substrate 200 is made of… Figure 3The dashed box in the figure shows that, because they have been individualized at this point in the process, they are separated into individual molded packages 210.

[0025] Each individual molded semiconductor package 210 includes one or more semiconductor chips (not shown) and corresponding metal pads 204 electrically connected to the respective chips. Figure 2 and Figure 3 As shown in the exploded view, each metal pad 204 has a bottom surface that is not covered by the molding compound 202 at the bottom surface of the molding compound 202. The metal pads 204 disposed around the periphery of each molded package 210 also have sides 214 that are not covered by the molding compound 202 at the edges 216 (along which the molded packages 210 are individualized). The uncovered sides 214 of the metal pads 204 disposed around the periphery of each molded package 210 form LTI features, which are achieved by cutting the connected metal pads 204 along the saw cut 212 as part of a single-step sawing process.

[0026] like Figure 3 As shown, after individualization, the carrier 206 still retains a single molded semiconductor package 210. The carrier 206, with the single molded semiconductor package 210 temporarily attached, is then immersed in a chemical bath (box 108). The chemical bath roughens the bottom surface of each metal pad 204 and the side surfaces 214 of the metal pads 204 disposed around the periphery of each molded package 210. By roughening the surfaces of the metal pads 204 not covered by the molding compound 202, the surface area available for plating is increased, ensuring that plating is more likely to attach / bond to the exposed surfaces of the metal pads 204. The side surfaces 214 of the metal pads 204 disposed around the periphery of each molded package 210 may have burrs, i.e., rough edges or ridges left by the action of a saw blade. The chemical bath removes the burrs from the side surfaces 214 of the metal pads 204 disposed around the periphery of each molded package 210. The surface of the metal pad 204 not covered by the molding compound 202 is plated after immersion in a chemical bath (box 110). The molded semiconductor package 210 can undergo post-plating processes such as automated inspection, testing, carrier removal, bonding, etc. (box 112).

[0027] Figure 4 More details are shown in the section including Figure 1 An embodiment of the roughening / deburring and plating processes 108, 110 in method 100. Reference Figure 5 describe Figure 4 , Figure 5 Generally, it is shown that it has the function of implementing Figure 4The multi-stage tool 400 of the roughening / deburring and plating processes 108, 110 shown is a separate compartment or immersion tank 402-414.

[0028] After individualization and before immersion in a chemical bath, the molded semiconductor package 210 is cleaned with a cleaning solution (box 400). This may include immersing the carrier 206 to which the molded semiconductor package 210 is attached in a chemical bath. Figure 5 In the first compartment / immersion tank 402 of the multi-stage tool 400 shown, the first compartment / immersion tank 402 is filled with a cleaning solution such as an acidic solution with a concentration of, for example, 10% HCl.

[0029] Next, the carrier 206 to which the molded semiconductor package 210 is attached is transferred to Figure 5 The second compartment / immersion tank 404 of the multi-stage tool 400 shown has nozzles for rinsing the molded package 210 once or more to remove cleaning solution and residues from the cleaning process (box 402).

[0030] Then the carrier 206 with the molded semiconductor package 210 attached is transferred to Figure 5 The multi-stage tool 400 shown includes a third compartment / immersion tank 406 (box 404). The third compartment / immersion tank 406 is filled with a chemical bath that roughens the bottom surface of each metal pad 204 and removes burrs from the sides 214 of the metal pads 204 disposed around the periphery of each molded package 210. When the molded package 210 is immersed in the chemical bath, approximately 3 to 15 micrometers of metal are etched away from the surfaces of the metal pads 204 not covered by the molding compound 202. In one embodiment, the chemical bath comprises sodium persulfate, which is the sodium salt of persulfate, also known as perdisulfate. More generally, the chemical bath may be selected from the group consisting of: hydrogen peroxide solution; ferric chloride solution; salt solution; copper sulfate; and ferric sulfate.

[0031] Then the carrier 206 with the molded semiconductor package 210 attached is transferred back Figure 5 The second compartment / immersion tank 404 of the multi-stage tool 400 shown is used to perform one or more rinsing cycles to remove chemical bath solutions and residues from the roughening / deburring process (box 406). The surfaces of the metal pads 204 not covered by the molding compound 202 are then plated by electroless plating.

[0032] In one embodiment, the electroless plating process is an electroless nickel immersion gold (ENIG) process, in which a nickel-phosphorus or nickel-boron alloy layer is deposited on the surface of the metal pad 204 not covered by the molding compound 202, and then covered with a gold layer. The ENIG process may include transferring the carrier 206 to which the molded semiconductor package 210 is attached. Figure 5 The fourth compartment / immersion tank 408 (box 408) of the multi-stage tool 400 is shown. A catalyst for electroless plating is introduced into the fourth compartment / immersion tank 408. For example, in the case where the metal pad 204 comprises copper, the catalyst may comprise palladium. Thus, the surface of the metal pad 204 not covered by the molding compound 202 can have a palladium-catalyzed copper surface prior to the plating process. An additional electroless palladium plating layer can be plated for magnetically sensitive products.

[0033] Once again, the carrier 206 with the molded semiconductor package 210 attached is transferred back. Figure 5 The second compartment / immersion tank 404 of the multi-stage tool 400 shown is used to perform one or more rinsing cycles to remove deactivated palladium and residues from the palladium surface activation process (box 410).

[0034] Then the carrier 206 with the molded semiconductor package 210 attached is transferred to Figure 5 The fifth compartment / immersion tank 410 of the multi-stage tool 400 is shown. As part of the electroless nickel plating process performed in the fifth compartment / immersion tank 410, a nickel-phosphorus or nickel-boron alloy layer is deposited on the surface of the metal pad 204 that is not covered by the molding compound 202.

[0035] Transfer the carrier 206 to which the molded semiconductor package 210 is attached. Figure 5 The second compartment / immersion tank 404 of the multi-stage tool 400 shown is used to perform one or more rinsing cycles to remove residues from the non-electrolytic nickel plating deposition process (box 414).

[0036] Then the carrier 206 with the molded semiconductor package 210 attached is transferred to Figure 5The sixth compartment / immersion pool 412 (box 416) of the multi-stage tool 400 is shown. The molded package 210 is immersed in a gold solution in the sixth compartment / immersion pool 412 to form a gold layer on the nickel-plated side of the metal pad 204. This gold layer protects the underlying nickel from oxidation. In the case of an electroless nickel / palladium immersion gold (ENEPIG) plating process, a barrier against nickel corrosion is provided between the electroless nickel plating layer and the gold layer. Additionally, an optional electroless palladium plating layer can be added for magnetically sensitive products.

[0037] Transfer the carrier 206 to which the molded semiconductor package 210 is attached. Figure 5 The second compartment / immersion tank 404 of the multi-stage tool 400 shown is used to perform one or more rinsing cycles to remove residues from the gold immersion process (box 418).

[0038] Then the carrier 206 with the molded semiconductor package 210 attached is transferred to Figure 5 The seventh compartment / immersion tank 414 (box 420) of the multi-stage tool 400 is shown. In the seventh compartment / immersion tank 414, the nickel-gold plated surface of the metal pad 204 is covered by a protective layer. In one embodiment, the protective layer is a high-temperature antioxidant coating. The protective layer may include an organic compound such as an organophosphorus, an organosilane, or a mixture of organophosphorus and organosilane.

[0039] Transfer the carrier 206 to which the molded semiconductor package 210 is attached. Figure 5 The second compartment / immersion tank 404 of the multi-stage tool 400 shown is used to perform one or more rinsing cycles to remove residues from the protective coating process (box 422). The carrier 206 and the molded semiconductor package 210 are then dried, for example, in an oven (box 424).

[0040] Figure 6 Showing the above in combination Figures 1 to 5 Bottom perspective view of the molded semiconductor package 210 manufactured by the described method. Figure 7A side perspective view of a molded semiconductor package 210 soldered to a circuit board 500 is shown. For the metal pads 204 disposed around the periphery of the molded package 210, a continuous plating surface extends from the bottom surface of the metal pads 204 (i.e., the surface adjacent to the circuit board 500) to the side surface 214 not covered by the molding compound 202 at the edge 216 of the (cut) molding compound 202. Thus, there is no stepped profile in the plating, nor in the LTI features on all four sides of the molded package 210. Furthermore, the plating surface of the metal pads 204 may be covered by a protective layer such as an antioxidant coating, which may include the organic compounds described above. The antioxidant coating can act as an adhesion promoter, thus enabling fluxless soldering of the molded package 210 to the circuit board 500. This allows for direct metal pad-to-solder bonding. Figure 7 After being attached to the circuit board 500, the LTI features plated on the side 214 of the metal pads 204 surrounding the molded package 210 are visible.

[0041] Figure 8 Showing the above in combination Figures 1 to 5 A cross-sectional view of a molded semiconductor package 210 manufactured by the described method and having a flip-chip configuration. According to this embodiment, the molded semiconductor package 210 includes a molding compound 202 having a first main surface 201, a second main surface 203 opposite to the first main surface 201, and an edge 216 extending between the first and second main surfaces 201, 203. One or more semiconductor chips 600 are embedded in the molding compound 202, and a plurality of metal pads 204, also embedded in the molding compound 202, are electrically connected to each semiconductor chip 600.

[0042] In a flip-chip configuration, the bottom side of a semiconductor chip 600 embedded in a molding compound 202 has terminals for providing electrical connections to the semiconductor chip 600. A passivation layer 602, such as silicon nitride, may be applied to the bottom side of the semiconductor chip 600. Metal pads 204 may be leads of a lead frame. Connections may be provided between the terminals of the semiconductor chip 600 and the leads of the lead frame (i.e., metal pads 204) via copper pillars 604, which are attached to the respective leads via solder joints 606.

[0043] The metal pad 204 has a bottom surface 215 that is not covered by the molding compound 202 at the second main surface 203 of the molding compound 202. The metal pad 204 disposed around the periphery of the molded package 210 also has a side surface 214 that is not covered by the molding compound 202 at the edge 216 of the molding compound 202, i.e., at the cut surface of the molding compound 202. In conjunction with the foregoing... Figures 1 to 5Following the described package individualization process, the surfaces 214 and 215 of the metal pads 204 not covered by the molding compound 202 are roughened and then plated with, for example, a nickel-phosphorus or nickel-boron alloy layer 608 and a gold layer 610. The roughening / deburring process after individualization etches away approximately 3 to 15 micrometers of metal from the surfaces 214 and 215 of the metal pads 204 not covered by the molding compound 202. Thus, the side surface 214 of each metal pad 204 surrounding the molded package 210 is recessed inward from the edge 216 of the molding compound 202 by an amount of r. The bottom surface 215 of all metal pads 204 is also recessed inward from the bottom surface 203 of the molding compound 202 by the same amount.

[0044] In some embodiments, the metal pad 204 comprises copper. The surfaces 214, 215 of the metal pad 204 not covered by the molding compound 202 may have a palladium-catalyzed copper surface plated with a nickel-phosphorus or nickel-boron alloy layer 608 as described above. The plated surfaces 214, 215 of the metal pad 204 may be covered with a protective layer 612, such as a high-temperature antioxidant coating, which may include organic compounds such as organophosphorus, organosilane, or mixtures of organophosphorus and organosilane, as also described above. In each case, the plated sides 214 of the metal pad 204 disposed around the periphery of the molded package 210 provide LTI features.

[0045] Figure 9 Showing the above in combination Figures 1 to 5 A cross-sectional view of a molded semiconductor package 210 manufactured by the described method and having a wire bonding configuration. According to this embodiment, the molded semiconductor package 210 includes a molding compound 202 having a first main surface 201, a second main surface 203 opposite to the first main surface 201, and an edge 216 extending between the first and second main surfaces 201, 203. One or more semiconductor chips 700 are embedded in the molding compound 202, and a plurality of metal bonding pads 204, also embedded in the molding compound 202, are electrically connected to each semiconductor chip 700.

[0046] In the wire bonding configuration, the bottom side of the semiconductor chip 700 embedded in the molding compound 202 is attached to the chip pad 702 of the lead frame, for example, via a bonding joint 704. The bottom side of the semiconductor chip 700 may form a terminal of the chip 700 in the case of a vertical device, or no terminal in the case of a lateral device. In either case, one or more additional terminals 706 are present on the top side of the semiconductor chip 700 opposite to the chip pad 702. The top-side terminals 706 are connected to the leads of the lead frame via bonding wires 708. The leads of the lead frame form the metal pads 204 of the molded package 210. In one embodiment, as... Figure 9As shown, each metal pad 204 disposed around the periphery of the molded package 210 has a side 214 with the same height h as the lead frame.

[0047] The metal pad 204 has a bottom surface 215 that is not covered by the molding compound 202 at the second main surface 203 of the molding compound 202. The metal pad 204 disposed around the periphery of the molded package 210 also has a side surface 214 that is not covered by the molding compound 202 at the edge 216 of the molding compound 202, i.e., at the cut surface of the molding compound 202. In conjunction with the foregoing... Figures 1 to 5 Following the individualization process of the package described, the surfaces 214 and 215 of the metal pads 204 not covered by the molding compound 202 are roughened and plated with, for example, a nickel-phosphorus or nickel-boron alloy layer 608 and a gold layer 610. The roughening / deburring process after individualization etches away approximately 3 to 15 micrometers of metal from the surfaces 214 and 215 of the metal pads 204 not covered by the molding compound 202. Thus, the side surface 214 of each metal pad 204 located around the periphery of the molded package 210 is recessed inward from the edge 216 of the molding compound 202 by an amount of r. The bottom surface 215 of all metal pads 204 is also recessed inward from the bottom surface 203 of the molding compound 202 by the same amount.

[0048] In some embodiments, the metal pad 204 comprises copper. The uncoated surfaces 214, 215 of the metal pad 204, not covered by the molding compound 202, may have a palladium-catalyzed copper surface plated with a nickel-phosphorus or nickel-boron alloy layer 608 as described above. The plated surfaces 214, 215 of the metal pad 204 may be covered with a protective layer 612, such as a high-temperature antioxidant coating, which may include organic compounds such as organophosphorus, organosilane, or mixtures of organophosphorus and organosilane, also described above. In each case, the plated side surface 214 of the metal pad 204 provides LTI features.

[0049] For ease of description, spatial relative terms such as "below," "below," "down," "above," and "upper" are used to explain the position of one element relative to a second element. These terms are also intended to cover various orientations of the device that differ from those depicted in the figures. Additionally, terms such as "first" and "second" are used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout the text, similar terms refer to similar elements.

[0050] As used herein, the terms “having,” “containing,” “including,” “comprising,” etc., are open-ended terms indicating the existence of the stated element or feature without excluding additional elements or features. Unless expressly stated herein, the words “a,” “an,” and “described” are intended to include both the plural and the singular.

[0051] In light of the variations and applications described above, it should be understood that this invention is not limited to the above description or the accompanying drawings. Rather, the invention is limited only by the appended claims and their legally equivalents.

Claims

1. A method for manufacturing a molded semiconductor package, the method comprising: a) Provides a molded semiconductor substrate comprising a molding compound, a semiconductor chip and metal pads embedded in the molding compound, each metal pad being electrically connected to a corresponding one of the semiconductor chips and not covered by the molding compound at a first main surface of the molding compound; b) Individually molding the semiconductor substrate into individual molded packages, each of the individual molded packages including one or more semiconductor chips and corresponding metal pads, each metal pad having a bottom surface not covered by the molding compound at the first main surface, and the metal pads disposed around the periphery of each molded package also having a side surface not covered by the molding compound at the edge along which the individual molded package is formed. Execute after step b): c) Immersing the molded package in a chemical bath, wherein, while the molded package is immersed in the chemical bath, the chemical bath roughens the bottom surface of each metal pad and removes burrs from the sides of the metal pads located around the periphery of each molded package by etching away approximately 3 to 15 micrometers of metal from the side of the metal pads not covered by the molding compound. as well as d) After immersing the molded package in the chemical bath, the surfaces of the metal pads not covered by the molding compound are plated.

2. The method according to claim 1, wherein, The chemical bath is selected from the group consisting of: hydrogen peroxide solution; ferric chloride solution; salt solution; copper sulfate; and ferric sulfate.

3. The method according to claim 1, wherein, The chemical bath includes sodium persulfate.

4. The method according to claim 1, wherein, The surfaces of the metal pads not covered by the molding compound are coated by electroless plating.

5. The method according to claim 4, wherein, The electroless plating includes an electroless nickel immersion gold (ENIG) process, in which a nickel-phosphorus or nickel-boron alloy layer is deposited on the surface of the metal pad that is not covered by the molding compound, and then covered with a gold layer.

6. The method according to claim 5, further comprising: A catalyst for non-electrolytic plating is introduced prior to depositing the nickel-phosphorus or nickel-boron alloy layer.

7. The method according to claim 6, wherein, The metal pad comprises copper, the catalyst comprises palladium, and the surface of the metal pad not covered by the molding compound has a palladium-catalyzed copper surface before the nickel-phosphorus or nickel-boron alloy layer is deposited.

8. The method according to claim 1, further comprising: The molded package is cleaned in an acidic solution before being immersed in the chemical bath; as well as After cleaning the molded package in the acidic solution, the molded package is rinsed before immersing it in the chemical bath.

9. The method according to claim 1, further comprising: The plated surface of the metal solder pad is covered with a protective layer.

10. The method according to claim 1, wherein, The molded semiconductor substrate is temporarily fixed to a UV-curable tape, which is heat- and chemical-resistant, at least during immersion and plating, so that the UV-curable tape can withstand the chemical bath.

11. The method according to claim 1, wherein, The molded semiconductor substrate is individualized into the individual molded package using a single-step sawing process.

12. The method according to claim 10, wherein, The UV-curable tape remains intact after the molded semiconductor substrate is individualized.

13. A molded semiconductor package manufactured by the method according to any one of claims 1-12, comprising: A molding compound having a first main surface, a second main surface opposite to the first main surface, and an edge extending between the first main surface and the second main surface; Semiconductor chips embedded in the molding compound; as well as Multiple metal pads embedded in the molding compound and electrically connected to the semiconductor chip; The metal pads disposed around the periphery of the molded semiconductor package have sides not covered by the molding compound at the edges of the molding compound. This side is recessed inward from the edge of the molded compound.

14. The molded semiconductor package according to claim 13, wherein, The recess is 3 to 15 micrometers.

15. The molded semiconductor package according to claim 13 or 14, wherein, The side surface of the metal pad is further coated with another metal coating that is different from the metal pad material.

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