Integrated Circuit Version Control Unit, Control Circuit, and Modification Method

Abstract

The present invention discloses an integrated circuit version control unit, a control circuit and a modification method. The version control unit includes a metal and via series branch, a metal parallel branch and a via parallel branch; the metal and via series branch, the metal parallel branch and the via parallel branch are connected in parallel; the metal and via series branch includes a plurality of metal layers and a plurality of vias connected in series in sequence, and each metal layer and via are connected at intervals; a cut-off position is reserved for each metal layer and via; the metal parallel branch includes a plurality of parallel metal branches, and each metal branch is provided with a notch; the via parallel branch includes a plurality of parallel via branches; each via branch of each layer includes two connected metal layers, and the two connected metal layers have an overlapping area; a position for placing a via is reserved in the overlapping area. The integrated circuit version control unit, the control circuit and the modification method proposed by the present invention can improve the convenience of modifying the integrated circuit version control information and improve the work efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and relates to a method for engineering modification of integrated circuits, in particular to an integrated circuit version control unit, a control circuit, and a modification method. Background Art

[0002] At present, the integrated circuit design life cycle mainly includes design, manufacturing, and packaging and testing. The demarcation point between design and manufacturing is distinguished by the design company providing layout data to the integrated circuit foundry. Usually, after the foundry obtains and confirms the design company's data, it starts to make a mask pattern according to the layout data and manufacture the integrated circuit.

[0003] In the integrated circuit design process, an Engineering Change Order (ECO) refers to manually modifying the netlist generated by the design tool synthesis, and then re-performing backend placement and routing, timing verification, physical verification, and generating the final manufacturing data provided to the foundry. Implementing an engineering modification can correct small-scale chip design errors at a relatively low cost and in a relatively short iteration cycle. Engineering modifications can generally be implemented in two stages:

[0004] (1) Chip design stage. Implementing an engineering modification at this stage can save the design iterations of complete design synthesis, placement and routing, parasitic extraction, and timing verification (ranging from several days to several months depending on the design scale). The degree of freedom for engineering modification at this stage is relatively large, and all layout resources can be modified.

[0005] (2) After chip manufacturing is completed. Implementing an engineering modification at this stage can save the mask manufacturing cost. The mask has extremely high precision and is costly. A complete set of chip manufacturing data usually requires dozens of mask layers (up to a hundred layers for the latest 7nm process). If the purpose of modifying the design can be achieved by only modifying several layers of the layout (usually metal and vias, collectively referred to as routing resources), the cost can be greatly reduced. Engineering modifications completed only by modifying the metal layer mask need to reserve spare devices at the beginning of the design, so that the spare devices can be incorporated into the main circuit by modifying the metal layer during engineering modification.

[0006] R & D personnel usually hope to obtain the version information of different engineering change chips in a certain way for material management and software configuration optimization. These version information can be marked in the following several ways, but all inevitably have some problems.

[0007] (1) Encapsulation version. During the encapsulation phase, corresponding text information can be printed on the chip surface for chips modified in different version projects. However, effective version control cannot be implemented for unencapsulated bare chips; in addition, for products with certain special requirements, the circuit board will be potted during assembly for waterproofing, dustproofing, anti-aging, etc., and the chip version cannot be judged through encapsulation after potting; furthermore, there may be slight differences in the configuration of chips modified in different projects, and the information marked on the encapsulation cannot be read by the software, so differential configuration cannot be performed for chips modified in different project versions.

[0008] (2) Burn version information into eFuse or EPROM / Flash. During the chip testing phase, the corresponding project modification version information can be burned into specific locations in the internal eFuse or EPROM / Flash of the chip during the automated testing process, and the corresponding project modification version information can be judged by reading the content of the specific location later. However, both the eFuse and Flash values can only be burned during automated testing, and the version of unburned chips cannot be judged. And an additional separate IP module is required for eFuse, while special processes are required for EPROM / Flash or the required chip die and Flash die need to be co-packaged in the same package during encapsulation, with poor universality.

[0009] (3) When making engineering modifications, in addition to the original engineering modifications, the netlist information of the reserved version flag bits in the circuit is modified, and then the EDA tool is relied on for placement and routing to generate the required design files. As mentioned before, the placement and routing of the tool for engineering modifications rely on the pre-reserved spare devices. The spare devices are usually scattered throughout the chip and may be far from the location where modification is required, and more routing resources need to be modified. In addition, the routing resources for modifying the version flag and the routing resources for modifying the original engineering modification are not necessarily exactly the same. It is very likely that additional routing resources will be consumed to modify the version flag, increasing the cost of engineering modifications.

[0010] The Chinese patent "A method for reducing the number of modified layers during integrated circuit engineering modification (CN106709154A)" provides a solution that only requires modifying a single-layer via to complete the modification. As Figure 1 shown, this solution introduces a hard module unit during the integrated circuit design. Several default value modification units are arranged in the hard module unit. Any bit of the output of each default value modification unit can be independently set to '0' or '1'. Therefore, for the default value of any register or the parameters of the analog module, this hard module unit can be called. The wiring of the default value modification units is all on the same metal layer. When performing ECO, only one via layer or one metal layer needs to be modified, which can greatly reduce the cost of re-making the mask and can reduce the time for the foundry to modify the mask, improving the efficiency of engineering modifications.

[0011] Figure 2 The schematic diagram of the method provided by the invention during engineering modification is shown. The metal wires connected to the pull-down unit and the metal wires connected to the pull-up unit are located on metal layer 2. The output high-level wiring H[n], output low-level wiring L[n], input wiring I[n] and output wiring O[n] of the default value modification unit are all located on metal layer 3. This example illustrates the modification of O[4] and O[1]. Taking the modification of O[4] as an example: the via connecting L[4] and the metal wire connected to the pull-down unit is disconnected at A1, and a via is added at A2 to connect I[4] and the metal wire connected to the pull-up unit. The modification of O[1] is similar to that of O[4]. This embodiment illustrates that no matter how many groups of default value modification units need to be modified, it can be achieved by modifying the same via layer, thereby greatly reducing the cost caused by the revision.

[0012] However, when the invention modifies the output value, the preset metal layer must be modified, such as the via between metal layer 2 and metal layer 3 in the above implementation. If the routing resources required to be changed for the predetermined engineering modification do not include the via between metal layer 2 and metal layer 3, then in order to change its output, the via between metal layer 2 and metal layer 3 needs to be additionally modified, resulting in an increase in the engineering modification cost.

[0013] In view of this, there is an urgent need to design a new integrated circuit version information adjustment method to overcome at least part of the above-mentioned defects of the existing integrated circuit version information adjustment method. Summary of the invention

[0014] The present invention provides an integrated circuit version control unit, a control circuit and a modification method, which can improve the convenience of modifying integrated circuit version control information and improve work efficiency.

[0015] To solve the above technical problem, according to one aspect of the present invention, the following technical solution is adopted:

[0016] An integrated circuit version control unit, the version control unit comprising: a metal and via series branch, a metal parallel branch and a via parallel branch;

[0017] The metal and via series branches, the metal parallel branches and the via parallel branches are connected in parallel, and the outputs of the branches are connected to each other to form the output of the version control unit;

[0018] The first end of the metal and via series branch is connected to the pull-down unit, and the first end of the metal parallel branch and the input of the via parallel branch are connected to the pull-up unit;

[0019] The metal and via series branches include a number of metal layers and a number of vias connected in series in sequence. Each metal layer and via are connected at intervals, and finally connected to the output through a metal layer; the metal layers in the metal and via series branches are directly connected to the metal layers in the metal parallel branches; positions for cutting are reserved for each layer of metal layer and via;

[0020] The metal parallel branches include a number of parallel metal branches. Each metal branch is respectively connected to the pull-up unit, and each metal branch is respectively provided with a notch;

[0021] The via parallel branches include a number of parallel via branches. Each via branch is respectively connected to the pull-up unit; each layer of via branch includes two connected metal layers, and the two connected metal layers have an overlapping area; positions for placing vias are reserved in the overlapping area, and the metal overlapping part meets the physical design rules required after placing the vias.

[0022] As an embodiment of the present invention, the metal parallel branches include n metal branches. Each metal branch includes one layer of metal layer, which are respectively denoted as: the first metal layer, the second metal layer,..., the (n - 1)th metal layer, the nth metal layer; where n≥2;

[0023] The via parallel branches include n - 1 via branches. The ith via branch includes the ith metal layer and the (i + 1)th metal layer; where i is an integer and 1≤i≤n - 1; the ith via is provided between the ith metal layer and the (i + 1)th metal layer.

[0024] As an embodiment of the present invention, n = 4.

[0025] According to another aspect of the present invention, the following technical solution is adopted:

[0026] An integrated circuit version control circuit, the integrated circuit version control circuit includes at least one of the above integrated circuit version control units and an encoder; each integrated circuit version control unit is respectively connected to the encoder.

[0027] According to still another aspect of the present invention, the following technical solution is adopted:

[0028] A method for modifying integrated circuit version control information using the above integrated circuit version control unit, the method includes:

[0029] Setting vias at the set via positions according to the control version information, and cutting at the set reserved cutting positions of the metal and via series branches.

[0030] As an embodiment of the present invention, the method includes: receiving data input by each version control unit through an encoder, and outputting version information after encoding.

[0031] The beneficial effects of the present invention are as follows: The integrated circuit version control unit, control circuit and modification method proposed by the present invention can improve the convenience of modifying integrated circuit version control information and improve work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 FIG. 6 is a schematic diagram of a hard module unit in an embodiment of the prior art.

[0033] Figure 2 FIG. 10 is a schematic diagram of implementing metal only ECO with a hard module unit in an embodiment of the prior art.

[0034] Figure 3 FIG. 14 is a schematic diagram of the composition of the version control unit in an embodiment of the present invention.

[0035] Figure 4 FIG. 18 is a schematic diagram of modifying the version control unit in an embodiment of the present invention.

[0036] Figure 5 FIG. 22 is a schematic diagram of engineering modification version control coding in an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0037] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] In order to further understand the present invention, the preferred implementation schemes of the present invention will be described below in conjunction with embodiments. However, it should be understood that these descriptions are only for further explaining the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0039] The description of this part only focuses on several typical embodiments, and the present invention is not limited to the scope described in the embodiments. The mutual replacement of the same or similar prior art means and some technical features in the embodiments is also within the scope of the description and protection of the present invention.

[0040] The present invention discloses an integrated circuit version control unit. Figure 3 FIG. 38 is a schematic diagram of the composition of the version control unit in an embodiment of the present invention; please refer to Figure 3 , in an embodiment of the present invention, the version control unit includes: a metal and via series branch 1, a metal parallel branch 3 and a via parallel branch 5. The metal and via series branch 1, the metal parallel branch 3 and the via parallel branch 5 are connected in parallel, and the outputs of each branch are connected to each other to form the output of the version control unit. The first end of the metal and via series branch 1 is connected to a pull-down unit 7, and the first end of the metal parallel branch 3 and the input of the via parallel branch 5 are connected to a pull-up unit 9.

[0041] The metal and via series branch 1 includes a number of metals and a number of vias connected in series in sequence. Each metal and via are connected at intervals and finally output through metal connection; the metals in the metal and via series branch 1 are directly connected to the metals in the metal parallel branch; a position for cutting is reserved for each layer of metal and via. The metal parallel branch 3 includes a number of parallel metal branches 30, each metal branch 30 is respectively connected to the pulling-up unit 9, and each metal branch 30 is respectively provided with a notch. The via parallel branch 5 includes a number of parallel via branches 50, each via branch 50 is respectively connected to the pulling-up unit 9; each layer of via branch 50 includes two connected metal layers, and there is an overlapping area between the two connected metal layers; a position for placing a via is reserved in the overlapping area, and the metal overlapping part meets the physical design rules required after placing the via.

[0042] In an embodiment of the present invention, the metal parallel branch includes n metal branches, each metal branch includes one layer of metal, which are respectively denoted as: the first metal, the second metal,..., the (n - 1)th metal, the nth metal; where n ≥ 2. The via parallel branch includes (n - 1) via branches, and the ith via branch includes the ith metal and the (i + 1)th metal; where i is an integer and 1 ≤ i ≤ n - 1; the ith via is provided between the ith metal and the (i + 1)th metal. In one embodiment, n = 4, and of course n can also be 5, 6, 7, 8, 9, 12, 15, etc.

[0043] The present invention can achieve version change only by modifying any layer of metal or via. In addition, this version control information modification scheme can fully utilize the routing resources required for the original engineering modification, including metals and vias, without additional cost. This scheme includes the implementation of the engineering modification version control unit ( Figure 3 ) and the version control scheme implemented using this unit ( Figure 5 ).

[0044] Figure 3 A plan view showing the implementation of the engineering modification version control unit is shown for a four-layer metal and three-layer via interconnection process. Figure 3 Divided into three major parts from bottom to top: the metal and via series branch 1, the metal parallel branch 3, and the via parallel branch 5. These three major branches form a parallel structure, and the outputs of each branch are connected to each other to form the output of the engineering modification version control unit.

[0045] The metal and via series branch includes the first metal layer M1, the first via V1 (used to connect the first metal layer M1 and the second metal layer M2), the second metal layer M2, the second via V2 (used to connect the second metal layer M2 and the third metal layer M3)... connected in sequence until the fourth metal layer M4 and connected to the output, which are connected in series with the pulling-down unit 7 in sequence. A position for cutting is reserved for each layer of metal and via, such as Figure 3As shown, they are the first reserved cutting position S_M1, the second reserved cutting position S_V1, the third reserved cutting position S_M2, the fourth reserved cutting position S_V2, the fifth reserved cutting position S_M3, the sixth reserved cutting position S_V3, and the seventh reserved cutting position S_M4 in sequence.

[0046] The metal parallel branches include four parallel branches connected to the pull-up unit 9, namely the first parallel branch (with the first metal layer M1), the second parallel branch (with the second metal layer M2), the third parallel branch (with the third metal layer M3), and the fourth parallel branch (with the fourth metal layer M4). The inputs of the four branches are respectively connected to the pull-up unit 9, and the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 are respectively provided with a first notch P_M1, a second notch P_M2, a third notch P_M3, and a fourth notch P_M4 (as Figure 3 shown). The four metal layers can be connected to the output through the fourth metal layer M4.

[0047] The via parallel branches include three parallel branches connected to the pull-up unit 9, namely the fifth parallel branch, the sixth parallel branch, and the seventh parallel branch. The fifth parallel branch includes the first metal layer M1 and the second metal layer M2, and the first metal layer M1 and the second metal layer M2 are provided with a first overlapping area P_V1; the sixth parallel branch includes the second metal layer M2 and the third metal layer M3, and the second metal layer M2 and the third metal layer M3 are provided with a second overlapping area P_V2; the third parallel branch includes the third metal layer M3 and the fourth metal layer M4, and the third metal layer M3 and the fourth metal layer M4 are provided with a third overlapping area P_V3. The first overlapping area P_V1, the second overlapping area P_V2, and the third overlapping area P_V3 respectively reserve positions for placing the first via V1, the second via V2, and the third via V3, and the metal overlapping part meets the physical design rules required after placing the vias.

[0048] As Figure 4 shown, before the engineering modification, the version control unit is in the initial state, that is, the output is connected to the pull-down unit through the series branch, and the metal parallel branches and the via parallel branches are in a disconnected state from the pull-up unit. Therefore, the output of the version control unit is '0'. If an engineering modification occurs and it is assumed that only the via V1 is modified in the original engineering modification, then the S_V1 in the series branch can be removed, and the V1 can be added to the position of P_V1 in the via parallel branch. This can disconnect the output that was originally connected to the pull-down unit through the series branch and connect the branch where P_V1 is located in the via parallel branch that was originally disconnected from the pull-up unit to the output. Therefore, the output is '1'.

[0049] Similarly, the output originally being '0' can be changed to '1' by disconnecting any of the points S_M1, S_V1, S_M2, S_V2, S_M3, S_V3, S_M4 in the series branch and connecting the corresponding points P_M1, P_V1, P_M2, P_V2, P_M3, P_V3, P_M4 in the parallel branch.

[0050] The core of the engineering change version control unit in the present invention lies in a topological structure composed of a series branch disconnected by any layer of metal or via and a parallel branch connectable by any layer of metal or via. Any shape and position change satisfying this topological relationship should be regarded as the content of the present invention. This includes but is not limited to adjusting the metal cascading order in the series branch, stacking multiple metal layers in the parallel branch, merging via parallel branches and metal parallel branches, etc.

[0051] The present invention discloses a method for modifying integrated circuit version control information using the above integrated circuit version control unit. The method includes: setting vias at set via positions according to control version information and cutting at set reserved cutting positions of the metal and via series branches. In one embodiment, the method includes: receiving data input by each version control unit through an encoder, and outputting version information after encoding.

[0052] The present invention also discloses an integrated circuit version control circuit. The integrated circuit version control circuit includes at least one of the above integrated circuit version control units and an encoder; each integrated circuit version control unit is respectively connected to the encoder.

[0053] It should be noted that Figure 3 The output of the shown engineering change version control unit can only achieve one modification from the initial '0' to '1'. Once modified to '1', it cannot be modified back to '0' again. To mark multiple engineering changes, multiple version control units and peripheral auxiliary circuits need to cooperate to achieve this. Figure 5 Taking a 4-bit version output as an example, the implementation of a complete engineering change block control circuit composed of 16 version control units and an encoder circuit from thermometer code to binary code is shown. The encoder circuit is composed of adders, which add the outputs of the 16 engineering change version control units and output the corresponding binary code. In the initial state, the outputs of all 16 version control units are '0', so the encoder input is 16'b0000_0000_0000_0000, and thus the encoder output is 4'b000; when the output of version control unit [0] is changed to '1' for the first engineering change, the encoder output is 4'b001; when the output of version control unit [1] is changed to '1' for the second engineering change, the encoder input is 16'b0000_0000_0000_0011, and the encoder output is 4'b010. And so on. In one embodiment of the present invention, usingFigure 5 The circuit shown can mark a total of 16 different versions (the initial version and 15 engineering modification versions).

[0054] In summary, the integrated circuit version control unit, control circuit, and modification method proposed by the present invention can improve the convenience of modifying integrated circuit version control information and improve work efficiency.

[0055] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0056] The description and application of the present invention here are illustrative and do not intend to limit the scope of the present invention to the above embodiments. The effects or advantages involved in the embodiments may not be reflected in the embodiments due to various factors. The description of the effects or advantages is not used to limit the embodiments. The deformations and changes of the embodiments disclosed here are possible, and the substitutions and equivalent components of the embodiments are well known to those of ordinary skill in the art. Those skilled in the art should clearly understand that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the present invention. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. An integrated circuit version control unit, characterized in that, the version control unit includes: a metal and via series branch, a metal parallel branch, and a via parallel branch; the metal and via series branch, the metal parallel branch, and the via parallel branch are connected in parallel, and the outputs of each branch are connected to each other to form the output of the version control unit; the first end of the metal and via series branch is connected to a pull-down unit, and the first end of the metal parallel branch and the input of the via parallel branch are connected to a pull-up unit; the metal and via series branch includes a plurality of metal layers and a plurality of vias connected in series in sequence, each metal layer and via are connected at intervals, and finally connected to the output through a metal layer; the metal layer in the metal and via series branch is directly connected to the metal layer in the metal parallel branch; a cut-off position is reserved for each metal layer and via; the metal parallel branch includes a plurality of parallel metal branches, each metal branch is respectively connected to the pull-up unit, and each metal branch is respectively provided with a notch; the via parallel branch includes a plurality of parallel via branches, each via branch is respectively connected to the pull-up unit; each layer of via branch includes two connected metal layers, and the two connected metal layers have an overlapping area; a position for placing a via is reserved in the overlapping area, and the metal overlapping part meets the physical design rules required after placing the via.

2. The integrated circuit version control unit according to claim 1, characterized in that: the metal parallel branch includes n metal branches, each metal branch includes a metal layer, which are respectively denoted as: the first metal layer, the second metal layer,..., the (n - 1)th metal layer, the nth metal layer; where n ≥ 2; the via parallel branch includes n - 1 via branches, and the ith via branch includes the ith metal layer and the (i + 1)th metal layer; where i is an integer, 1 ≤ i ≤ n - 1; the ith via is provided between the ith metal layer and the (i + 1)th metal layer.

3. The integrated circuit version control unit according to claim 2, characterized in that: n＝4。 4. An integrated circuit version control circuit, characterized in that: the integrated circuit version control circuit includes at least one integrated circuit version control unit according to any one of claims 1 to 3 and an encoder; each integrated circuit version control unit is respectively connected to the encoder.

5. A method for modifying integrated circuit version control information using any one of the integrated circuit version control units according to claims 1 to 3, characterized in that, the method includes: setting a via at a set via position according to the control version information, and cutting at the set reserved cut-off position of the metal and via series branch.

6. The method for modifying integrated circuit version control information according to claim 5, characterized in that: the method includes: receiving data input by each version control unit through an encoder, and outputting version information after encoding.

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