A low thermal resistance packaging structure for power semiconductor devices and a manufacturing method thereof

Abstract

The present invention relates to a low-thermal-resistance packaging structure for power semiconductor devices and a method for manufacturing the same. The packaging structure comprises an electrode interconnection sheet, a power chip, and a lead frame sequentially arranged within a press-fit plastic package. A press-fit buffer layer is provided in the electrode press-fit region between the electrode interconnection sheet and the power chip. The electrode interconnection sheet and the lead frame are connected via a pin soldering layer. A plurality of plastic package anchor holes are provided around the chip die-bonding region of the lead frame. Compared to the prior art, the present invention achieves reliable electrothermal stress press-fitting between the chip, the electrode interconnection sheet, and the lead frame. A temperature-compensated, through-type rigid connection is formed between the press-fit plastic package and the lead frame, creating a double-sided heat dissipation channel for the chip. This allows the device to achieve superior electrothermal characteristics and a wide safe operating range under extreme operating conditions.

Description

Technical Field

[0001] The present invention relates to a leadless press-fit packaging technology for semiconductor chips, and in particular to a low thermal resistance packaging structure for power semiconductor devices and a manufacturing method thereof. Background Art

[0002] Leadless press-fit packaging for semiconductor chips is a highly reliable packaging method for semiconductor power chips, primarily used for high-power devices such as power ICs, MOSFETs, and IGBTs. Compared to soldered packaging, press-fit packaging offers the advantages of a compact structure, dual-sided heat dissipation, and the elimination of the failure modes associated with bond wires and solder layers found in traditional soldered IGBT technology. While this method is primarily used in the packaging of MOSFETs and IGBT high-power modules (IPMs), its application in discrete semiconductor chip devices has not been reported.

[0003] There are two main types of crimping technology:

[0004] 1. Spring compression type, represented by ABB and patented;

[0005] 2. Boss press-fit type, represented by TOSHIBA, WESTCODE, DYNEX and CRRC Times Electric Co., Ltd.

[0006] The technical structures of the two types of crimping technologies mentioned above are both composed of additional mechanical pressure elements, and their shortcomings are:

[0007] A. The introduction of external pressure and springs may lead to potential failures due to uneven pressure or spring fatigue, which restricts the improvement of its time reliability.

[0008] B. Due to the limitation of the additional mechanical pressure element mechanism, the crimping technology cannot be applied in the packaging of power ICs and discrete devices that have strict requirements on structural dimensions.

[0009] C. The package of high-power modules (IPM) is non-airtight. The module is filled with insulating materials such as silicone gel or epoxy resin to isolate the chip from the external environment (water, air, dust). However, the filling material usually also isolates the heat transfer, and the isolation effect degrades during long-term operation.

[0010] At present, due to the upgrade of semiconductor chip materials from the first generation to the third generation wide bandgap materials, coupled with the increasing power density of semiconductor power chip devices and the increasing requirements for the use environment, the existing device structure and devices manufactured with thermosetting plastic packaging materials and injection molding (transfer molding) packaging technology are unable to give full play to the excellent characteristics of the third generation wide bandgap material chips with an operating junction temperature above 175°C due to the limitations of the inherent characteristics of materials, structures and processes. They are also unable to meet the reliability requirements of high-power devices, thereby limiting the expansion of the cost-effectiveness advantages of third-generation semiconductor devices and the industrialization process of high-end power devices.

[0011] In view of the above reasons, only comprehensive innovation in packaging structure, materials and process technology can meet the requirements for promoting the development of the modern semiconductor industry. Summary of the Invention

[0012] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and to provide a low thermal resistance packaging structure for power semiconductor devices and a manufacturing method thereof.

[0013] The purpose of the present invention can be achieved by the following technical solutions:

[0014] A low thermal resistance packaging structure for a power semiconductor device comprises an electrode interconnection sheet, a power chip and a lead frame arranged in sequence in a crimped plastic package. A crimping buffer layer is provided in the electrode crimping area between the electrode interconnection sheet and the power chip. The electrode interconnection sheet and the lead frame are connected via a pin welding layer. A plurality of plastic package anchor holes are provided around the chip die-bonding area of ​​the lead frame.

[0015] Preferably, a chip bonding area between the power chip and the lead frame is provided with a pressure welding bonding layer.

[0016] Preferably, the electrode interconnection sheet is provided with a high-temperature resistant electrical insulation coating on a side facing the lead frame between the electrode crimping areas.

[0017] Preferably, the electrode interconnection sheet is an electrode interconnection heat sink having the dual functions of electrical conduction and heat diffusion.

[0018] Preferably, a temperature-compensated through-type rigid connection is formed between the crimped plastic package body and the lead frame.

[0019] Preferably, the compression-bonded plastic package body is made of thermoplastic polymer material.

[0020] Preferably, the compression-bonding buffer layer is specifically a compression-bonding strain buffer alloy layer.

[0021] A method for manufacturing a low thermal resistance packaging structure for a power semiconductor device, comprising:

[0022] S1. A pressing buffer layer and a pressing welding layer are respectively fabricated in the electrode pressing area of ​​the electrode interconnect sheet, a pressing welding layer is fabricated in the chip bonding area of ​​the lead frame, and a plurality of plastic package anchor holes are processed around the chip bonding area;

[0023] S2. Place the electrode interconnect sheet, power chip, and lead frame into a positioning fixture according to the specified position requirements, and place them into a vacuum press welding machine to complete die bonding, electrode eutectic welding, and press-bonding buffer layer coplanar bonding to produce the device core component;

[0024] S3. The device inner core component is placed into the injection mold according to the specified position requirements, and thermoplastic polymer material is injected to make the crimped plastic package body and the device inner core component form a rigid whole through the plastic package body anchoring hole, and the device is completed after cooling.

[0025] Preferably, the injection mold is a high-temperature and high-pressure injection mold without remelting, and the thermoplastic polymer material is injected in a high-temperature and high-pressure manner in S2.

[0026] Preferably, the S1 further includes:

[0027] A high-temperature resistant electrical insulation coating is formed on a side of the electrode interconnection sheet facing the lead frame between the electrode crimping areas.

[0028] Compared with the prior art, the present invention has the following advantages:

[0029] 1. The source of the pressing force that forms the pressure contact connection between the chip's input and output electrodes and the interconnection system is changed from an externally attached mechanical pressure element to the strain force formed by the thermal strain difference of the relevant structural materials inside the device. This achieves reliable electrothermal stress pressing between the chip and the electrode interconnection sheet and lead frame, and forms a temperature-compensated through-type rigid connection between the press-fit plastic package and the lead frame, forming a double-sided heat dissipation channel for the chip, so that the device can obtain better electrothermal characteristics and a wide safe working area under extreme working conditions.

[0030] 2. The strain compensation and recovery characteristics formed by the thermal strain difference of the polymer multi-material structure used in the press-fit plastic package are far superior to those of unit mechanical elastic elements, which can greatly reduce the hidden dangers of device failure caused by uneven pressure or spring fatigue.

[0031] 3. The present invention adopts a lead-free pressing surface and a pressing strain buffer alloy layer, and a high-temperature resistant low-dielectric insulating coating, which greatly reduces the packaging parasitic effect and improves the working reliability of the device.

[0032] 4. The electrode interconnection sheet adopts a monolithic structure for electrode interconnection and heat dissipation, forming an efficient heat conduction channel with the high-strength, high-thermal-conductivity, and high-insulation press-fit plastic package.

[0033] 5. The crimping buffer layer can compensate for the temperature influence of the crimping pressure difference, block the diffusion of Cu ions in the electrode crimping area of ​​the electrode interconnection sheet to the ohmic contact area of ​​the chip electrode, and reduce the possibility of chip breakdown.

[0034] 6. Since this packaging structure eliminates additional mechanical components and does not use conventional thermosetting polymer materials and injection molding (transfer molding) processes, it eliminates structural limitations and will enable press-fit packaging technology to be applied in power IC and discrete device packaging that have stringent requirements on structural dimensions. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a front view of the packaging structure of the present invention;

[0036] Figure 2 for Figure 1 Cross-sectional view in the AA direction;

[0037] Figure 3 for Figure 1 Cross-sectional view in the BB direction.

[0038] Markings in the figure: 1. Lead frame, 2. Power chip, 3. Electrode interconnection sheet, 4. Pressed plastic package, 5. High-temperature resistant electrical insulation coating, 6. Pressed buffer layer, 7. Pressed solder bond layer, 8. Pin welding layer, 9. Plastic package anchor hole. DETAILED DESCRIPTION

[0039] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0040] Example

[0041] like Figure 1 As shown, the present application proposes a low thermal resistance packaging structure for power semiconductor devices, including an electrode interconnection sheet 3, a power chip 2 and a lead frame 1 arranged in sequence in a crimped plastic package 4. A crimping buffer layer 6 is provided in the electrode crimping area between the electrode interconnection sheet 3 and the power chip 2, which is specifically a crimping strain buffer alloy layer in this embodiment, which can compensate for the temperature influence of the crimping pressure difference, block the diffusion of Cu ions in the electrode crimping area of ​​the electrode interconnection sheet 3 to the chip electrode ohmic contact area, and reduce the possibility of chip breakdown. Several plastic package anchor holes 9 are provided around the chip solidification area of ​​the lead frame 1, so that the crimped plastic package 4 becomes a rigid whole with the core components of the device through the plastic package anchor holes 9. The electrode interconnection sheet 3 and the lead frame 1 are connected by a pin welding layer 8 to realize the electrical connection of the input and output of the power chip 2.

[0042] The crimped plastic package 4 is made of a thermoplastic polymer. The difference in thermal expansion coefficient (CTE) between the recrystallized material and the heterogeneous insert material under high temperature and high pressure creates a stress differential greater than 10 MPa, ensuring reliable crimping of the chip electrodes and chip interconnects.

[0043] The electrode interconnection sheet 3 is an electrode interconnection heat sink with dual functions of electrical conduction and heat diffusion, which reduces the possibility of heat accumulation during chip operation.

[0044] The electrode interconnection sheet 3 is provided with a low-dielectric, high-temperature-resistant electrical insulation coating 5 on the side facing the lead frame 1 between the electrode crimping areas, aiming to eliminate the possibility of inter-electrode short circuit caused by deformation of the electrode interconnection sheet 3 during high-pressure injection molding, while reducing the parasitic effects of the package.

[0045] A chip bonding area between the power chip 2 and the lead frame 1 is provided with a pressure welding bonding layer 7 , specifically a vacuum pressure welding alloy solder layer, to achieve low thermal resistance bonding of the power chip 2 .

[0046] Providing at least one power chip 2 with back metallization, the method for manufacturing the low thermal resistance packaging structure of the power semiconductor device includes:

[0047] S1. A pressing buffer layer 6 and a pressing soldering layer 7 are respectively formed in the electrode pressing area of ​​the electrode interconnection sheet 3. A high-temperature resistant electrical insulation coating 5 is formed between the electrode pressing areas of the electrode interconnection sheet 3 and on the side facing the lead frame 1. A pressing soldering layer 7 is formed in the chip bonding area of ​​the lead frame 1, and a plurality of plastic package anchor holes 9 are processed around the chip bonding area.

[0048] S2. Place the electrode interconnect sheet 3, power chip 2, and lead frame 1 into a positioning fixture according to the specified position requirements, and place them into a vacuum press welding machine to complete die bonding, electrode eutectic welding, and coplanar bonding of the press-bonded buffer layer 6 to produce the device core component;

[0049] S3. The core components of the device are installed into a high-temperature and high-pressure injection mold without remelting according to the specified position requirements, and thermoplastic polymer materials are injected at high temperature and high pressure to make the crimped plastic package body 4 and the core components of the device become a rigid whole through the plastic package body anchoring hole 9. After cooling, the internal stress difference realizes the crimping of the electrode interconnection sheet 3 and the chip electrode, completing the plastic packaging of the device.

[0050] The power IC devices and high-power discrete devices packaged using the technical solution of this application have been tested by a third-party national component reliability testing agency and have met the following standards: AEC-Q100; AEC-Q101; Level I (automotive grade, military grade).

[0051] This application is applicable to the manufacture of a packaging structure for discrete devices that encapsulate multiple power semiconductor chips on the same carrier. This application scientifically utilizes the thermal strain differential parameters of relevant structural materials to construct a more compact structural system with engineering capabilities, significantly reducing the thermal resistance of the power semiconductor device package, allowing multiple power chips 2 to maximize their performance under specified technical conditions, enabling the device to obtain better electrothermal characteristics and a wider safe operating area (SOA) under extreme operating conditions, and significantly improving its reliability indicators.

Claims

1. A low thermal resistance packaging structure for a power semiconductor device, characterized in that: The invention comprises an electrode interconnection sheet (3), a power chip (2) and a lead frame (1) which are sequentially arranged in a crimped plastic package (4); a crimping buffer layer (6) is provided in the electrode crimping area between the electrode interconnection sheet (3) and the power chip (2); the electrode interconnection sheet (3) and the lead frame (1) are connected via a pin welding layer (8); and a plurality of plastic package anchor holes (9) are provided around the chip solidification area of ​​the lead frame (1); The source of the pressure contact force that forms the pressure contact connection between the chip input and output electrodes and the interconnection system is changed from an external mechanical pressure element to the strain force formed by the thermal strain difference of the relevant structural materials inside the device. The press-fit plastic package (4) forms a rigid whole with the core component of the device through the plastic package anchoring hole (9). The press-fit plastic package (4) adopts a thermoplastic polymer material. The stress difference formed by the difference in thermal expansion coefficient between the recrystallized material of the press-fit plastic package (4) and the thermal expansion coefficient of the related heterogeneous embedded component material under high temperature and high pressure conditions will generate a pressure greater than 10MPa, thereby realizing reliable press-fitting of the chip electrode and the chip interconnection sheet.

2. The low thermal resistance packaging structure for a power semiconductor device according to claim 1, characterized in that: A chip crystal bonding area between the power chip (2) and the lead frame (1) is provided with a pressure welding crystal bonding layer (7).

3. The low thermal resistance packaging structure for a power semiconductor device according to claim 1, characterized in that: The electrode interconnection sheet (3) is provided with a high-temperature resistant electrical insulation coating (5) on one side facing the lead frame (1) between the electrode crimping areas.

4. The low thermal resistance packaging structure for power semiconductor devices according to claim 1, characterized in that: The electrode interconnection sheet (3) is an electrode interconnection heat sink with the dual functions of electrical conduction and thermal diffusion.

5. The low thermal resistance packaging structure for power semiconductor devices according to claim 1, characterized in that: A temperature-compensated through-type rigid connection is formed between the crimped plastic package body (4) and the lead frame (1).

6. The low thermal resistance packaging structure for power semiconductor devices according to claim 1, characterized in that: The crimped plastic sealing body (4) is made of thermoplastic polymer material.

7. The low thermal resistance packaging structure for power semiconductor devices according to claim 1, characterized in that: The compression bonding buffer layer (6) is specifically a compression bonding strain buffer alloy layer.

8. A method for manufacturing a low thermal resistance packaging structure for a power semiconductor device according to any one of claims 1 to 7, characterized in that: include: S1, respectively producing a pressing buffer layer (6) and a pressing welding solid crystal layer (7) in the electrode pressing area of ​​the electrode interconnection sheet (3), producing a pressing welding solid crystal layer (7) in the chip solid crystal area of ​​the lead frame (1), and processing a plurality of plastic package anchor holes (9) around the chip solid crystal area; S2, placing the electrode interconnection sheet (3), the power chip (2) and the lead frame (1) into a positioning fixture according to the specified position requirements, and placing them into a vacuum pressing welding machine to complete the solid crystal welding, electrode eutectic welding and pressing the buffer layer (6) coplanar bonding to produce the device core component; S3, the inner core component of the device is placed into the injection mold according to the specified position requirements, and the thermoplastic polymer material is injected to make the crimped plastic package body (4) and the inner core component of the device become a rigid whole through the plastic package body anchoring hole (9), and the plastic package of the device is completed after cooling.

9. The method for manufacturing a low thermal resistance packaging structure for a power semiconductor device according to claim 8, characterized in that: The injection mold is a high-temperature and high-pressure injection mold without remelting, and the thermoplastic polymer material is injected in a high-temperature and high-pressure manner in S3.

10. The method for manufacturing a low thermal resistance packaging structure for a power semiconductor device according to claim 8, characterized in that: Said S1 further comprises: A high-temperature resistant electrical insulation coating (5) is produced on one side of the electrode interconnection sheet (3) facing the lead frame (1) between the electrode crimping areas.

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