Semiconductor package

Abstract

A semiconductor package is disclosed, including: a semiconductor chip; a first chip pad on a bottom surface of the semiconductor chip and adjacent to a first side surface of the semiconductor chip in a first direction, the first side surface separated from the first chip pad in a plan view in the first direction; and a first lead frame coupled to the first chip pad. The first lead frame includes: a first portion on a bottom surface of the first chip pad and extending from the first chip pad in a second direction opposite the first direction and away from the first side surface of the semiconductor chip; and a second portion connected to a first end of the first portion and extending in the first direction when viewed in the plan view to extend beyond the first side surface of the semiconductor chip after passing a side of the first chip pad.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0111079, filed on September 1, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor package, and more specifically to a semiconductor package having a lead frame. Background Technology

[0004] In the semiconductor industry, integrated circuit packaging technologies have been developed to meet the demands for small form factor devices and high package reliability. For example, packaging technologies capable of achieving chip-scale packaging are being actively developed to meet the needs of small form factor devices, and packaging technologies that can improve efficiency in the packaging process and enhance the mechanical and electrical reliability of the packaged products have attracted considerable attention in the area of ​​high package reliability.

[0005] Chip-on-film (COF) technology is a novel packaging type that has been developed for display driver ICs and compact communication devices, reflecting a trend towards thinner and lighter designs. When utilizing COF technology to implement high-resolution display devices, the driving frequencies of televisions and monitors increase, thereby increasing the driving load on the driver ICs and generating heat from the integrated circuit. As a solution to these problems, a heat-radiating plate can be formed on the bottom surface of the dielectric layer to dissipate heat generated from the semiconductor device formed on the top surface of the dielectric substrate. However, other or alternative methods may be desired. Summary of the Invention

[0006] Some exemplary embodiments of the present invention provide semiconductor packages with improved structural stability.

[0007] Some exemplary embodiments of the present invention provide semiconductor packages with enhanced electrical properties.

[0008] The purpose of this invention is not limited to the above-mentioned purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0009] According to some exemplary embodiments of the present invention, a semiconductor package may include: a semiconductor chip; a first chip pad on the bottom surface of the semiconductor chip and adjacent to a first side surface of the semiconductor chip in a first direction, the first side surface being separated from the first chip pad in a first direction in a plan view; and a first lead frame coupled to the first chip pad. The first lead frame may include: a first portion on the bottom surface of the first chip pad, the first portion extending from the first chip pad in a second direction opposite to the first direction and away from the first side surface of the semiconductor chip; and a second portion, when viewed in a plan view, the second portion being connected to a first end of the first portion and extending along the first direction to extend beyond the first side surface of the semiconductor chip after passing through one side of the first chip pad.

[0010] According to some exemplary embodiments of the present invention, which may be the same as or different from the previously mentioned exemplary embodiments, a semiconductor package may include: a thermally radiating member; a substrate on the thermally radiating member; a lead frame on the substrate; a semiconductor chip disposed on the lead frame and having a central region and a peripheral region surrounding the central region on its bottom surface; and chip pads disposed on the peripheral region of the bottom surface of the semiconductor chip, the chip pads coupling the semiconductor chip to the lead frame. The lead frame may include: a first portion extending from the bottom surface of the chip pads to the central region of the bottom surface of the semiconductor chip; a second portion extending from the central region toward the outside of the semiconductor chip; and a connecting portion on the central region, through which the first portion and the second portion are connected to each other.

[0011] According to some exemplary embodiments of the present invention, which may be the same as or different from the previously mentioned exemplary embodiments, a semiconductor package may include: a thermally radiating member; a substrate on the thermally radiating member; a lead frame on the substrate, the lead frame having a hook shape connecting a first end of the first portion to a first end of the second portion, the first portion and the second portion extending in a first direction; and a semiconductor chip including chip pads coupled to the first portion. The connection portion connecting the first portion and the second portion to each other may be farther from a first side surface of the semiconductor chip than the chip pads. The first side surface may be adjacent to the chip pads. Attached Figure Description

[0012] Figure 1This is a cross-sectional view illustrating some example embodiments of a semiconductor package according to the present invention.

[0013] Figure 2 It is shown Figure 1 A magnified view of part A.

[0014] Figure 3 This is a plan view illustrating some example embodiments of a semiconductor package according to the present invention.

[0015] Figure 4 It is shown Figure 3 A magnified view of part B.

[0016] Figure 5 and Figure 6 This is a plan view illustrating some example embodiments of a semiconductor package according to the present invention.

[0017] Figure 7 This is a cross-sectional view illustrating some example embodiments of a semiconductor package according to the present invention.

[0018] Figure 8 This is a plan view illustrating some example embodiments of a semiconductor package according to the present invention.

[0019] Figure 9 This is a cross-sectional view illustrating some example embodiments of a semiconductor package according to the present invention.

[0020] Figure 10 This is a plan view illustrating some example embodiments of a semiconductor package according to the present invention.

[0021] Figure 11 This is a cross-sectional view illustrating some example embodiments of a semiconductor package according to the present invention.

[0022] Figure 12 This is a plan view illustrating some example embodiments of a semiconductor package according to the present invention.

[0023] Figure 13 It is shown Figure 12 A magnified view of part C. Detailed Implementation

[0024] A semiconductor package based on the present invention will now be described below with reference to the accompanying drawings.

[0025] Figure 1 This is a cross-sectional view illustrating some example embodiments of a semiconductor package according to the present invention. Figure 2 It is shown Figure 1 A magnified view of part A. Figure 3 These illustrate some example embodiments of semiconductor packaging based on the concept of the present invention. Figure 1 The cross-sectional view corresponding to the bottom view. Figure 3 In the text, for ease of description, some components are shown as overlapping each other. Figure 4 It is shown Figure 3 A magnified view of part B.

[0026] refer to Figures 1 to 3 The semiconductor package 10 may include: a substrate 100; a heat-radiating member 200 disposed on one surface of the substrate 100; a lead frame 400 disposed on another surface of the substrate 100; and a semiconductor chip 300 mounted on the substrate 100. For example, the semiconductor package 10 may be a chip-on-film (COF) type semiconductor device.

[0027] The substrate 100 may be a flexible film-type substrate. The substrate 100 may include a dielectric material. For example, the substrate 100 may include polyimide (PI).

[0028] A heat-radiating member 200 may be disposed on the bottom surface of the substrate 100. The heat-radiating member 200 may completely cover the bottom surface of the substrate 100. Alternatively, unlike what is shown, the heat-radiating member 200 may be disposed on the bottom surface of the substrate 100 only below the area where the semiconductor chip 300 is mounted. The heat-radiating member 200 may contact the bottom surface of the substrate 100. It will be understood that when references are made to an element being “connected” or “coupled” to another element or “on” another element, the element may be directly connected or coupled to the other element or directly on the other element, or there may be an intermediate element. In contrast, when references are made to an element being “directly connected” or “directly coupled” to another element or “in contact” with another element, there is no intermediate element at the point of contact. The heat-radiating member 200 may have a thickness of about 1 mm to about 10 mm. The heat-radiating member 200 may be configured to dissipate heat generated from the semiconductor chip 300 outwards and then transfer it downwards through the lead frame 400. The heat-radiating component 200 may include a metallic conductor or non-conductor (e.g., a non-conductive material) having high thermal conductivity. For example, the heat-radiating component 200 may include aluminum (Al). The heat-radiating component 200 may be a sheet or a thermally conductive pattern, and may be a heat-radiating sheet or a heat-radiating pattern.

[0029] Although not shown, an adhesive layer may be used to attach the heat-radiating member 200 to the substrate 100. The adhesive layer may include an adhesive member such as an acrylic adhesive. Furthermore, the adhesive layer may include conductive particles. For example, conductive particles may include metal particles or metal spheres. The conductive particles allow the adhesive layer to easily transfer heat from the substrate 100 to the heat-radiating member 200.

[0030] The lead frame 400 may be disposed on the substrate 100. The shape of the lead frame 400 will be discussed in detail after the shape of the semiconductor chip 300, which will be described below, is explained.

[0031] Semiconductor chip 300 may be mounted on substrate 100. Semiconductor chip 300 may be or may include memory devices, integrated circuits, transistors (e.g., junction transistors and field-effect transistors), diodes (e.g., rectifier diodes, light-emitting diodes, and photodiodes), or any other active device. Alternatively, semiconductor chip 300 may be or may include capacitors, resistors, coils, or any other passive device. When viewed in a plane, semiconductor chip 300 may have a central region CR and a peripheral region PR surrounding the central region CR. Semiconductor chip 300 may be flip-chip mounted on substrate 100. For example, the front surface of semiconductor chip 300 may face substrate 100. In the following description, the term "front surface" may be defined as referring to the active surface on which the circuit layer of semiconductor chip 300 is formed, and the term "rear surface" may be defined as referring to the opposite surface or the passive surface opposite the front surface. For example, the first semiconductor chip 300 may include chip pads 310 disposed on its top surface. Chip pads 310 may be disposed on the peripheral region PR of semiconductor chip 300. The surface of the chip pad 310 may face the substrate 100. Each chip pad 310 may have a first side surface 310a and a second side surface 310b. For example, when the semiconductor chip 300 is defined as having a third side surface 300a adjacent to the chip pad 310, the first side surface 310a of the chip pad 310 may face a direction toward the third side surface 300a, and the second side surface 310b of the chip pad 310 may be opposite the third side surface 300a. In this case, the second side surface 310b of the chip pad 310 may face the central region CR, and the first side surface 310a of the chip pad 310 may face the peripheral region PR or the outside of the semiconductor chip 300. The distance from the third side surface 300a of the semiconductor chip 300 to the second side surface 310b of the chip pad 310 may be approximately 0.1% to approximately 10% of the width of the semiconductor chip 300.

[0032] It should be noted that ordinal numbers such as “first,” “second,” and “third” can simply be used as labels for certain elements, steps, etc., to distinguish them from one another. Terms not described using “first,” “second,” etc., in the specification may still be referred to as “first” or “second” in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., “first” in a particular claim) may be described elsewhere with a different ordinal number (e.g., “second” in the specification or another claim). Additionally, terms such as “about” or “approximately” can reflect quantities, dimensions, orientations, or layouts that vary only slightly and / or in a manner that does not significantly alter the operation, function, or structure of a particular element. For example, a range from “about 0.1 to about 1” could include ranges such as a deviation of 0%–5% from 0.1 and a deviation of 0% to 5% from 1, especially if such deviations maintain the same effect as the listed ranges.

[0033] The semiconductor chip 300 can be coupled to a lead frame 400 disposed on the top surface of the substrate 100. For example, the chip pad 310 of the semiconductor chip 300 can contact the lead frame 400.

[0034] Leadframes 400 may be disposed on substrate 100 and connected to chip pads 310 of semiconductor chip 300. On substrate 100, leadframes 400 may be used to transmit electrical signals from semiconductor chip 300 toward an external output device. Leadframes 400 may be spaced apart from each other. Leadframes 400 may have distal ends extending to the exterior of semiconductor chip 300. Leadframes 400 may comprise a metal such as copper (Cu).

[0035] The following will refer to Figure 3 and Figure 4 Discuss the shape of the lead frame 400.

[0036] Each leadframe 400 may have a bracket shape extending from the chip pad 310 toward the central region CR of the semiconductor chip 300 and subsequently extending from the central region CR of the semiconductor chip 300 toward the peripheral region PR. For example, each leadframe 400 may include: a first portion 410 connected to (e.g., directly connected to and in contact with) the chip pad 310, a second portion 420 extending from the first portion 410 toward the outside of the semiconductor chip 300, and a connecting portion 430 connecting the first portion 410 to the second portion 420. The first portion 410 and the second portion 420 may be legs of the leadframe 400 having a curved shape. In the description herein, the first portion 410, the second portion 420, and the third portion 430 are arbitrarily defined for ease of illustration, and the leadframe 400 may be formed from the same material as a single, individual component (e.g., a single monolithic structure). The shape of a single leadframe 400 disposed below a chip pad 310 will be discussed below. Each leadframe 400 may have the same shape and the same dimensions as the other leadframes. The lead frame 400 can have a curved shape, such as a hook shape or a J-shape (or an inverted J-shape), which can be as follows: Figure 3 and Figure 4 The angular shapes depicted (e.g., including 90-degree angles).

[0037] The first portion 410 may have a straight line shape extending from the bottom surface 310c of the chip pad 310 in a first direction D1. In this description, the first direction D1 may be defined as an inward direction from the chip pad 310 to the semiconductor chip 300 (e.g., toward the center of the semiconductor chip 300 and away from adjacent edges of the semiconductor chip 300). For example, the first direction D1 may be oriented from the peripheral region PR toward the central region CR. The second direction D2 may be defined as an outward direction from the chip pad 310 to the semiconductor chip 300. For example, the second direction D2 may be oriented from the central region CR toward the peripheral region PR. The first portion 410 may extend from the chip pad 310 in the first direction D1. For example, in a plan view, the first portion 410 may protrude from the second side surface 310b of the chip pad 310. The first portion 410 may have a first end (e.g., an end connected to the third portion 430) disposed at a specific distance from the chip pad 310 in the first direction D1. The first portion 410 may have a second end (e.g., a terminal end) disposed at a specific distance from the chip pad 310 in the second direction D2. For example, in a plan view, the first portion 410 may have a portion protruding from a first side surface 310a of the chip pad 310 and a portion protruding from a second side surface 310b of the chip pad 310. Unlike what is shown, the second end (e.g., a terminal end) of the first portion 410 may be disposed below the bottom surface of the chip pad 310 to overlap with the chip pad 310 in a plan view. The second end of the first portion 410 may serve as a pad to which the chip pad 310 of the semiconductor chip 300 is coupled.

[0038] The second portion 420 may have a straight line shape extending from the central region CR in the second direction D2. The second portion 420 may have a third end (e.g., an end connected to the third portion 430) disposed on the central region CR (e.g., closer to the center of the substrate 100). When viewed in plan view, the second portion 420 may protrude beyond the third side surface 300a of the semiconductor chip 300 after passing through the peripheral region PR from the central region CR. The third end of the second portion 420 may be located on the central region CR. In plan view, the second portion 420 may have a fourth end (e.g., a terminal end) located on the outside of the semiconductor chip 300. The fourth end of the third portion 420 may correspond to a terminal connected to an external output device. The second portion 420 may be spaced apart from the first portion 410 in the third direction D3. The third direction D3 may be defined as a direction parallel to the top surface of the substrate 100 and intersecting the first direction D1 and the second direction D2. The third direction D3 may be perpendicular to the first direction D1 and the second direction D2. For example, the first portion 410 and the second portion 420 may have a linear shape in which they are arranged in a third direction D3 and extend longitudinally in a first direction D1 and a second direction D2. An article, layer, or portion of an article or layer described as extending “longitudinally” in a particular direction has a length in that particular direction and a width perpendicular to that direction, wherein the length is greater than the width. The spacing g between the first portion 410 and the second portion 420 may range from about 10 μm to about 100 μm. The second portion 420 may be spaced apart from the chip pad 310 in the third direction D3.

[0039] The second portion 420 may be disposed adjacent to one side of the first portion 410 (e.g., the longitudinal side). The first portion 410 and the second portion 420 may be disposed at the same vertical height from the top surface of the substrate 100.

[0040] The first portion 410 and the second portion 420 can be connected to each other. For example, the first end of the first portion 410 and the third end of the second portion 420 can be connected to each other on the central region CR via a connecting portion 430. In embodiments where the leadframe 400 is a single component, the connection can be borderless. The connecting portion 430 can be disposed on the central region CR. The connecting portion 430 can have a linear shape extending in a third direction D3 from the first end of the first portion 410 toward the third end of the second portion 420. Therefore, the leadframe 400 can have a support shape including: a first portion 410 extending from the chip pad 310 toward the central region CR of the semiconductor chip 300; a connecting portion 430 connecting the first portion 410 to the second portion 420; and a second portion 420 extending from the central region CR toward the peripheral region PR. One end of the support can be elongated relative to the other end.

[0041] Alternatively, the lead frame 400 may have (for example, with an elongated end) a curved U-shape, or a curved J-shape (or inverted J-shape) or hook shape. Figure 5 This is a plan view illustrating some example embodiments of a semiconductor package according to the concept of the present invention. For example... Figure 5 As shown, the connecting portion 430 may have a curved shape, including the following curved shape: it bends in a circular manner from the first end of the first portion 410 toward the third end of the second portion 420. While examples of different curved shapes and other shapes are given in this disclosure, the shape of the connecting portion 430 and the shape of the lead frame 400 are not limited thereto, and the first portion 410 and the second portion 420 may be connected to each other in various ways. The following will focus on... Figure 3 Examples of implementations.

[0042] refer to Figure 1 and Figure 2 In a semiconductor package 10 with a lead frame 400 disposed on a substrate 100 and a heat-radiating member 200, and a semiconductor chip 300 coupled to the lead frame 400, each of the substrate 100, the heat-radiating member 200, and the semiconductor chip 300 may experience thermal expansion due to heat provided during the manufacture of the semiconductor package 10 or generated from the semiconductor chip 300 during operation of the semiconductor package 10. There may be a difference between the coefficient of thermal expansion (CTE) of the substrate 100 and the heat-radiating member 200 and the coefficient of thermal expansion (CTE) of the semiconductor chip 300, and stress may be applied to the lead frame 400, through which the semiconductor chip 300 and the substrate 100 are connected to each other. In this case, the stress caused by the difference in CTE between the semiconductor chip 300 and the substrate 100 may be smaller at the central portion of the semiconductor package 10 (e.g., the central region CR of the semiconductor chip 300 or the central portion of the substrate 100) and larger at the outer portions of the semiconductor package 10 (e.g., the peripheral region PR of the semiconductor chip 300 or the outer portion of the substrate 100). Reference Figure 2 The contact area between the lead frame 400 and the chip pad 310 may have a first point EP1 closest to the second side surface 310b and facing the center region CR, and a second point EP2 closest to the first side surface 310a and facing the outside of the semiconductor chip 300, and the stress applied to the lead frame 400 may be smaller at the first point EP1 than at the second point EP2.

[0043] At the second point EP2 where stronger thermal stress is applied, the lead frame 400 may suffer cracks or may peel off from the chip pad 310 due to the stress continuously applied near the second point EP2.

[0044] According to some exemplary embodiments of the present invention, the leadframe 400 may include a portion disposed near the first point EP1 that experiences less stress and is further away from the interconnects extending from the substrate 100 of the leadframe 400, and may also include another portion of the interconnects constituting the leadframe 400 that experiences more stress and extends from below the bottom surface 310c of the chip pad 310 toward the first side surface 310a. However, in the locations where more stress occurs, there is no direct, close connection between the interconnects outside the connection of the leadframe 400 and the chip pad 310; therefore, the interconnects of the leadframe 400 can withstand less stress than in prior art systems, and the semiconductor package 10 can be more resistant to thermal stress. Thus, the semiconductor package 10 can improve structural stability. Furthermore, because the leadframe 400 is free of cracks, the resistance of the leadframe 400 can be reduced, and the semiconductor package 10 can enhance desired electrical characteristics.

[0045] Go back for reference Figures 1 to 4 An underfill member 500 may be disposed between the substrate 100 and the semiconductor chip 300. The underfill member 500—also described as an underfill portion or underfill layer—may fill the space between the substrate 100 and the semiconductor chip 300. The underfill member 500 may seal the chip pad 310, the first portion 410 of the leadframe 400, and the connection portion 430 of the leadframe 400, and may partially cover the second portion 420 of the leadframe 400. For example, the underfill member 500 may include an underfill material and structure, such as an anisotropic conductive film (ACF) or a non-conductive paste (NCP).

[0046] Although not shown, a surface dielectric layer may also be disposed on the substrate 100. The surface dielectric layer may partially cover the lead frame 400 (or at least a second portion 420 of the lead frame 400) extending outward toward the semiconductor chip 300. For example, a solder resist layer may be used as the surface dielectric layer. The surface dielectric layer may be configured to cover the lead frame 400.

[0047] Figure 3 The lead frames 400 are depicted having the same planar shape (e.g., in a plan view), although some lead frames 400 are rotated and oriented 180 degrees relative to other lead frames 400, but the inventive concept is not limited thereto. Figure 6 This is a plan view illustrating some example embodiments of a semiconductor package according to a concept proposed in this invention. In the following embodiments, references will be omitted. Figures 1 to 4 The technical features discussed herein are repeated in detail, and their differences will be discussed in detail. The same reference numerals may be assigned to the same components as those in some exemplary embodiments of semiconductor packages conceived according to the present invention.

[0048] refer to Figure 6The semiconductor package 20 may include: a substrate 100; a heat-radiating member 200 disposed on one surface of the substrate 100; a lead frame 400 disposed on another surface of the substrate 100; and a semiconductor chip 300 mounted on the substrate 100. For example, the semiconductor package 20 may be a chip-on-film (COF) type semiconductor device.

[0049] The heat-radiating component 200 may be disposed on the bottom surface of the substrate 100. The heat-radiating component 200 may be in contact with the bottom surface of the substrate 100. The heat-radiating component 200 may be configured to dissipate heat generated from the semiconductor chip 300 outwards and then transfer it downwards through the lead frame 400.

[0050] Semiconductor chip 300 can be mounted on substrate 100. Semiconductor chip 300 may include chip pads 310 disposed on its front surface. Chip pads 310 may be disposed on the peripheral region PR of semiconductor chip 300. Semiconductor chip 300 may be coupled to lead frame 400 disposed on the top surface of substrate 100. For example, chip pads 310 of semiconductor chip 300 may contact lead frame 400.

[0051] Leadframes 400 may be disposed on substrate 100 and connected to chip pads 310 of semiconductor chip 300. Leadframes 400 may have a curved shape, such as a support shape (e.g., having an elongated end) or a hook shape, extending from chip pads 310 toward the central region CR of semiconductor chip 300 and subsequently from the central region CR toward the peripheral region PR.

[0052] The lead frame 400 may include a first lead frame 400-1 (e.g., a first type of lead frame, which may be plural) and a second lead frame 400-2 (e.g., a second type of lead frame, which may be plural) adjacent to each other. The first lead frame 400-1 and the second lead frame 400-2 may have planar shapes that are symmetrical to each other when viewed in a planar view. For example, the first lead frame 400-1 and the second lead frame 400-2 may each have a first portion 410-1 and a second portion 410-2, both having a straight line shape extending from the chip pad 310 toward the central region CR of the semiconductor chip 300. The first lead frame 400-1 and the second lead frame 400-2 may each have a second portion 420-1 and a second portion 420-2, both having a straight line shape extending from the central region CR of the semiconductor chip 300 toward the outside of the semiconductor chip 300. When the second portion 420-1 of the first lead frame 400-1 is spaced apart from the first portion 410-1 of the first lead frame 400-1 in a fourth direction parallel to the top surface of the substrate 100, the second portion 420-2 of the second lead frame 400-2 may be spaced apart from the first portion 410-2 of the second lead frame 400-2 in a direction opposite to the fourth direction. The first lead frame 400-1 may have a connecting portion 430-1, which connects the first portion 410-1 and the second portion 420-1 of the first lead frame 400-1 to each other in the central region CR, and the second lead frame 400-2 may have a connecting portion 430-2, which connects the first portion 410-2 and the second portion 420-2 of the second lead frame 400-2 to each other in the central region CR. Although Figure 6 The lead frame depicting the shape of the support portion forms a curved hook shape (e.g., a straight J-shape or an inverted J-shape), but in one embodiment, Figure 6 The depicted lead frame can have a curved type of connection portion, which is consistent with... Figure 5 Similar to those shown.

[0053] Figure 7 This is a cross-sectional view illustrating some example embodiments of a semiconductor package according to the present invention. Figure 8 This is a plan view illustrating some example embodiments of a semiconductor package according to the present invention.

[0054] refer to Figure 7 and Figure 8The semiconductor package 30 may include: a substrate 100; a heat-radiating member 200 disposed on one surface of the substrate 100; a lead frame 400 disposed on another surface of the substrate 100; a semiconductor chip 300 mounted on the substrate 100; and a support 600 supporting the semiconductor chip 300. For example, the semiconductor package 30 may be a chip-on-film (COF) type semiconductor device.

[0055] The heat-radiating component 200 can be disposed on the bottom surface of the substrate 100. The heat-radiating component 200 can contact the bottom surface of the substrate 100.

[0056] Semiconductor chip 300 can be mounted on substrate 100. Semiconductor chip 300 may include chip pads 310 disposed on its front surface. Chip pads 310 may be disposed on the peripheral region PR of semiconductor chip 300. Semiconductor chip 300 may be coupled to lead frame 400 disposed on the top surface of substrate 100.

[0057] Leadframe 400 may be disposed on substrate 100 and may be connected to chip pad 310 of semiconductor chip 300. When viewed in plan view, leadframe 400 may have a curved shape, such as a support shape (e.g., having an elongated end) or a hook shape, extending from chip pad 310 toward the central region CR of semiconductor chip 300 and subsequently from the central region CR toward the peripheral region PR. For example, leadframe 400 may include: a first portion 410 connected to chip pad 310, a second portion 420 extending from the first portion 410 toward the outside of semiconductor chip 300, and a connection portion 430 connecting the first portion 410 to the second portion 420.

[0058] A support 600 may be disposed between the semiconductor chip 300 and the lead frame 400. The support 600 may be disposed on the central region CR. Each of the supports 600 may be inserted between a connection portion 430 of one of the semiconductor chip 300 and the lead frame 400. The support 600 may be formed on or contact the top surface of the connection portion 430 of the lead frame 400 and the rear surface of the semiconductor chip 300. For example, the semiconductor chip 300 may be supported by the support 600 on the connection portion 430. Because the support 600 supports the semiconductor chip 300 upwards, the semiconductor package 30 may have improved structural stability. The support 600 may include, for example, a dielectric material or be formed of, for example, a dielectric material. Figure 8 The illustration depicts a bracket 600 positioned in each lead frame 400, but the inventive concept is not limited thereto. The bracket 600 may be inserted between some of the connection portions 430 in the semiconductor chip 300 and the lead frame 400.

[0059] Figure 9 This is a cross-sectional view illustrating some example embodiments of a semiconductor package according to the present invention. Figure 10 This is a plan view illustrating some example embodiments of a semiconductor package according to the present invention.

[0060] refer to Figure 9 and Figure 10 The semiconductor package 40 may include: a substrate 100; a heat-radiating member 200 disposed on one surface of the substrate 100; a lead frame 400' disposed on another surface of the substrate 100; and a semiconductor chip 300 mounted on the substrate 100. For example, the semiconductor package 40 may be a chip-on-film (COF) type semiconductor device.

[0061] The heat-radiating component 200 can be disposed on the bottom surface of the substrate 100. The heat-radiating component 200 can contact the bottom surface of the substrate 100.

[0062] Semiconductor chip 300 can be mounted on substrate 100. Semiconductor chip 300 may include chip pads 310 disposed on its front surface. Chip pads 310 may be disposed on the peripheral region PR of semiconductor chip 300. Semiconductor chip 300 may be coupled to lead frame 400' disposed on the top surface of substrate 100.

[0063] Leadframes 400' may be disposed on the substrate 100 and connected to the chip pads 310 of the semiconductor chip 300. Each leadframe 400' may include: a first portion 410' connected to the chip pads 310, a second portion 420' extending from the first portion 410' toward the outside of the semiconductor chip 300, and a connecting portion 430' connecting the first portion 410' to the second portion 420'. Each leadframe 400' may have a curved shape, for example, a J-shape (when viewed in cross-section), wherein the leadframe 400' folds itself in a third direction D3 perpendicular to the top surface of the substrate 100.

[0064] The first portion 410' may have a straight line shape extending from the bottom surface 310c of the chip pad 310 in a first direction D1. The first portion 410' may extend in a direction oriented from the chip pad 310 toward the central region CR of the semiconductor chip 300. For example, the first portion 410' may protrude from the second side surface 310b of the chip pad 310. The first portion 410' may have a first end disposed on the central region CR (e.g., where the first portion 410' connects to the third portion 430'). The first portion 410' may have a second end disposed on the peripheral region PR (e.g., a terminal end). For example, in a plan view, the first portion 410' may have a portion protruding from the first side surface 310a of the chip pad 310.

[0065] The second portion 420' may have a linear shape extending in the direction from the central region CR toward the peripheral region PR. The second portion 420' may have a third end disposed on the central region CR (e.g., where the second portion 420' connects to the third portion 430'). When viewed in plan view, the second portion 420' may protrude beyond the third side surface 300a of the semiconductor chip 300 after passing through the peripheral region PR from the central region CR. The third end of the second portion 420' may be disposed on the central region CR. The second portion 420' may have a fourth end disposed on the exterior of the semiconductor chip 300 (e.g., a terminal end). The fourth end of the second portion 420' may correspond to a terminal coupled to an external output device. The second portion 420' may be disposed on the third direction D3 from the first portion 410'. The first portion 410' may be spaced apart from the second portion 420' on the third direction D3, or may contact the second portion 420' without any space between them, to be directly disposed on the second portion 420'. The third direction D3 can be defined as the direction perpendicular to the top surface of the substrate 100.

[0066] The first part 410' and the second part 420' can be connected to each other. For example, the first end of the first part 410' and the third end of the second part 420' can be connected to each other on the central region CR via a connecting part 430'. The connecting part 430' can be disposed on the central region CR. The first end of the first part 410' and the third end of the second part 420' can be connected to each other via a connecting part 430' extending, for example, in a straight line along a third direction D3. Alternatively, as Figure 9 As depicted, the connecting portion 430' may have the following curved shape: curved from a first end of the first portion 410' toward a third end of the second portion 420'. Therefore, each of the lead frames 400' may have a curved shape, such as a U-shape (e.g., having an elongated end), a J-shape, or a hook shape (or a compressed hook shape), comprising: a first portion 410' extending from the chip pad 310 toward the central region CR of the semiconductor chip 300; a connecting portion 430' connecting the first portion 410' to the second portion 420'; and a second portion 420' extending from the central region CR toward the peripheral region PR. The lead frames 400' may have a shape in which each of them is folded upwards on a third side perpendicular to the top surface of the substrate 100. As in the various embodiments described above (e.g., Figures 3-10 As described in [the document], the lead frame has three parts that form a curved shape that bends 180 degrees from end to end, for example, to form a hook shape or a J-shape. However, other hook shapes that bend less than 180 degrees and greater than 90 degrees can also be formed.

[0067] Figure 11 This is a cross-sectional view illustrating some example embodiments of a semiconductor package according to the present invention. Figure 12 This is a plan view illustrating some example embodiments of a semiconductor package according to the present invention. Figure 13 It is shown Figure 12 A magnified view of part C.

[0068] refer to Figures 11 to 13 The semiconductor package 50 may include: a substrate 100; a heat-radiating member 200 disposed on one surface of the substrate 100; a lead frame 400 disposed on another surface of the substrate 100; and a semiconductor chip 300 mounted on the substrate 100. For example, the semiconductor package 50 may be a chip-on-film (COF) type semiconductor device.

[0069] The heat-radiating component 200 can be disposed on the bottom surface of the substrate 100. The heat-radiating component 200 can contact the bottom surface of the substrate 100.

[0070] Semiconductor chip 300 can be mounted on substrate 100. Semiconductor chip 300 may include chip pads 310 disposed on its front surface. Chip pads 310 may be disposed on the peripheral region PR of semiconductor chip 300. Semiconductor chip 300 may be coupled to lead frame 400 disposed on the top surface of substrate 100.

[0071] The lead frame 400 can be disposed on the substrate 100 and connected to the chip pad 310 of the semiconductor chip 300.

[0072] The lead frame 400” may have a curved shape, such as an L-shape, which extends from the chip pad 310 toward the central region CR of the semiconductor chip 300 and then extends from the central region CR toward the peripheral region PR. For example, the lead frame 400” may include: a first portion 410” connected to the chip pad 310, a second portion 420” extending from the central region CR toward the outside of the semiconductor chip 300, and a connection portion 430 connecting the first portion 410” to the second portion 420”.

[0073] In the plan view, the first portion 410” may have a straight line shape extending from the bottom surface 310c of the chip pad 310 in the first direction D1. The first portion 410” may extend from the chip pad 310 in the first direction D1. For example, the first portion 410” may protrude from the second side surface 310b of the chip pad 310. The first portion 410” may have a first end portion disposed on the chip pad 310 in the first direction D1. The first portion 410” may have a second end portion disposed on the chip pad 310 in the second direction D2.

[0074] The second portion 420” may have a linear shape extending from the central region CR toward the third side surface 300a. The second portion 420” may have a third end disposed on the central region CR. When viewed in a plane, the second portion 420” may protrude beyond the third side surface 300a of the semiconductor chip 300 after passing through the peripheral region PR from the central region CR. The third end of the second portion 420” may be disposed on the central region CR. The second end of the second portion 420” may be disposed on the exterior of the semiconductor chip 300.

[0075] The first portion 410” and the second portion 420” can be connected to each other. For example, the first end of the first portion 410” and the third end of the second portion 420” can be connected to each other on the central region CR via a connecting portion 430”. The connecting portion 430” can be disposed on the central region CR. The connecting portion 430” can have a right-angled shape or a curved circular shape. The second portion 420” can have a linear shape extending from the connecting portion 430” toward the outside of the semiconductor chip 300 in a third direction D3. Therefore, the lead frame 400” can all have an L-shape (with sharp corners or rounded corners) including the following: the first portion 410” extends from the chip pad 310 toward the central region CR of the semiconductor chip 300; the connecting portion 430” connects the first portion 410” to the second portion 420”; and the second portion 420” extends from the central region CR toward the peripheral region PR.

[0076] According to some exemplary embodiments of the present invention, a semiconductor package may include a lead frame extending inward from the bottom surface of the chip pads in a direction that generates less stress, thus making the semiconductor package more resistant to thermal stress. Therefore, the semiconductor package can be configured to have higher structural stability.

[0077] Furthermore, because the lead frame is free of cracks, it can reduce resistance, and the semiconductor package can enhance electrical characteristics.

[0078] Although the inventive concept has been described in conjunction with some exemplary embodiments of the present disclosure shown in the accompanying drawings, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and essential characteristics of the inventive concept. Therefore, the embodiments disclosed above should be considered illustrative rather than restrictive.

Claims

1. A semiconductor package, comprising: Substrate; A semiconductor chip, on the substrate, wherein the bottom surface of the semiconductor chip includes a central region and a peripheral region surrounding the central region; A plurality of first chip pads are located in the peripheral region of the bottom surface of the semiconductor chip and are adjacent to a first side surface of the semiconductor chip, the first side surface being separated from the plurality of first chip pads in a first direction; as well as A plurality of first lead frames are disposed between the substrate and the bottom surface of the semiconductor chip, and coupled to the plurality of first chip pads. Each of the plurality of first lead frames is connected to one of the plurality of first chip pads. Each of the plurality of first lead frames includes: In the first part, on the bottom surface of the plurality of first chip pads, the first part extends from the plurality of first chip pads toward the central region along a second direction, the second direction being opposite to the first direction and away from the first side surface of the semiconductor chip; The second portion extends along the first direction from the central region toward the outside of the semiconductor chip, extending beyond the first side surface of the semiconductor chip after passing through one side of the plurality of first chip pads; and A connecting portion, on the central area, connects the first portion and the second portion to each other, and The plurality of first lead frames have the same planar shape.

2. The semiconductor package according to claim 1, wherein, The connection portion between the first portion and the second portion is spaced apart from the first chip pad in the second direction.

3. The semiconductor package according to claim 2, wherein, The connecting portion has a linear shape that extends in a third direction from a first end of the first portion toward a first end of the second portion, the third direction being parallel to the bottom surface of the semiconductor chip and perpendicular to the first and second directions.

4. The semiconductor package according to claim 2, wherein, The connecting portion has a curved U-shape extending from a first end of the first portion to a first end of the second portion.

5. The semiconductor package according to claim 2, further comprising: A support is located between the connecting portion and the bottom surface of the semiconductor chip.

6. The semiconductor package according to claim 1, wherein, The second portion is spaced apart from the first portion in a third direction, the third direction being parallel to the bottom surface of the semiconductor chip and perpendicular to the first and second directions.

7. The semiconductor package according to claim 6, wherein, The second part is spaced 10 μm to 100 μm apart from the first part in the direction of the third party.

8. The semiconductor package according to claim 1, wherein, The second part is disposed on the bottom surface of the first part to overlap in a plan view.

9. The semiconductor package according to claim 8, wherein, The area where the first part and the second part overlap is located below the first chip pad.

10. The semiconductor package according to claim 1, wherein, The distance from the first side surface of the first chip pad to the first side surface of the semiconductor chip in the first direction is 0.1% to 10% of the width of the semiconductor chip, which is measured in the first direction.

11. The semiconductor package according to claim 1, further comprising: The second chip pad is located on the bottom surface of the semiconductor chip and adjacent to the first side surface of the semiconductor chip. The second chip pad is spaced apart from the first chip pad in a third direction, which is parallel to the bottom surface of the semiconductor chip and perpendicular to the first direction and the second direction. as well as The second lead frame is coupled to the second chip pad. The second lead frame includes: The first portion extends from the second chip pad in the second direction on the bottom surface of the second chip pad; and The second part, when viewed in a plan view, is connected to the first end of the first part and extends along the first direction to extend beyond the first side surface of the semiconductor chip after passing through one side of the second chip pad.

12. The semiconductor package of claim 11, wherein, The second portion of the first lead frame is spaced apart from the first portion of the first lead frame in a direction opposite to that of the third party, and The second portion of the second lead frame is spaced apart from the first portion of the second lead frame in the third direction.

13. The semiconductor package according to claim 1, wherein, The substrate supports the first lead frame, and The semiconductor package further includes: A heat-radiating component is located on the bottom surface of the substrate.

14. The semiconductor package of claim 13, further comprising: A bottom filler member surrounds the first chip pad and fills the space between the substrate and the semiconductor chip.

15. A semiconductor package, comprising: Thermal radiation components; Substrate, on the thermal radiating member; Multiple lead frames are on the substrate; A semiconductor chip is disposed on the substrate, the plurality of lead frames are located between the substrate and the bottom surface of the semiconductor chip, and the bottom surface of the semiconductor chip has a central region and a peripheral region surrounding the central region; as well as Multiple chip pads are located on the peripheral region of the bottom surface of the semiconductor chip, and the semiconductor chip is coupled to the multiple lead frames. Each of the plurality of lead frames is connected to one of the plurality of chip pads. Each of the plurality of lead frames includes: The first part extends from the bottom surface of the plurality of chip pads to the central region of the bottom surface of the semiconductor chip; The second part extends from the central region toward the outside of the semiconductor chip; and A connecting portion, on the central area, connects the first portion and the second portion to each other, and The plurality of lead frames have the same planar shape.

16. The semiconductor package of claim 15, wherein, The first portion has a straight line shape extending in a first direction from the chip pad toward the connection portion, the first direction being parallel to the bottom surface of the semiconductor chip, and The second part has a straight line shape extending from the connecting part in a direction opposite to the first direction.

17. The semiconductor package of claim 16, wherein, The first portion and the second portion are spaced apart from each other in a second direction parallel to the bottom surface of the semiconductor chip, the second direction intersecting the first direction.

18. The semiconductor package of claim 16, wherein, The connecting portion has a shape extending in a second direction parallel to the bottom surface of the semiconductor chip, the second direction intersecting the first direction.

19. The semiconductor package according to claim 15, wherein, The distance from the first side surface of the chip pad to the first side surface of the semiconductor chip is 0.1% to 10% of the width of the semiconductor chip, the first side surface of the chip pad faces the central region, the first side surface of the semiconductor chip is adjacent to the chip pad, and the width is measured in the direction from the first side surface of the chip pad toward the first side surface of the semiconductor chip.

20. A semiconductor package, comprising: Thermal radiation components; Substrate, on the thermal radiating member; A semiconductor chip is disposed on the substrate, the bottom surface of the semiconductor chip includes a central region and a peripheral region surrounding the central region, and the semiconductor chip includes a plurality of chip pads disposed in the peripheral region on the bottom surface; as well as A plurality of lead frames are disposed between the substrate and the bottom surface of the semiconductor chip and coupled to the plurality of chip pads. Each of the plurality of lead frames has a hook shape that connects a first end of a first portion to a first end of a second portion, the first portion and the second portion extending in a first direction. Each of the plurality of lead frames is connected to one of the plurality of chip pads. The connection portion of each of the plurality of lead frames that connects the first portion and the second portion to each other is located on the central region and is farther from the first side surface of the semiconductor chip than the plurality of chip pads, the first side surface being adjacent to the plurality of chip pads. The plurality of lead frames have the same planar shape.

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