Circuit and method for fast detection of word line failure conditions in memory circuits

Abstract

The present disclosure generally relates to circuits and methods for rapid detection of wordline fault conditions in memory circuits. A row decoder located on one side of a memory array selectively drives a wordline in response to a row address. Wordline fault detection circuitry located on opposite sides of a first memory array is used to detect a broken wordline fault between opposite sides of the memory array. The wordline fault detection circuitry includes a first clamp circuit that operates to clamp the wordline to ground. An encoder circuit encodes a signal on the wordline to generate an encoded address. A comparator circuit compares the encoded address to a row address, and if the encoded address does not match the row address, the comparator circuit sets an error flag indicating that a broken wordline fault has been detected.

Description

[0001] Priority claim

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 798,541, filed on January 30, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates generally to test circuits, and more particularly, to a test circuit for detecting an open word line condition of a memory circuit. Background Art

[0004] Now refer to Figure 1 , which shows a simplified block diagram of a memory circuit 10. Circuit 10 includes an array 12 of memory cells C arranged in rows and columns. The memory cells in each row are controlled by a word line 14. The memory cells in each column are connected to a bit line 16. Row decoder circuit 18 receives a row address pre-decoded from address 20 and decodes the bits of the row address to select and activate one of the word lines 14. Column decoder circuit 22 receives a column address pre-decoded from address 20 and decodes the bits of the column address to select a plurality of bit lines 16. In write mode, data on data input / output line 24 is written to the memory cell located at the intersection of the word line 14 and the plurality of bit lines 16 selected by address 20. In read mode, data stored in the memory cell located at the intersection of the word line 14 and the plurality of bit lines 16 selected by address 20 is read out to data input / output line 24.

[0005] A successful read or write operation depends on the application of an excitation voltage (typically a logic high voltage, Vdd) by the wordline driver circuitry at the selected wordline 14 to each memory cell C in the selected row. However, it has been recognized that due to a hard fault, such as a physical interruption in the wordline 14 itself, some portion of the selected wordline may be in a floating condition. This hard fault 26 is schematically illustrated by the "X" marking on the faulty wordline 14a. The problem with this type of hard fault is that, due to charge accumulation, the floating portion 32 of the faulty wordline 14a can acquire any voltage from ground to Vdd, and this can hinder the ability to detect the presence of a fault and, further, can result in data being written to and read from incorrect memory cells.

[0006] Conventional wordline fault detection circuitry 30 coupled to wordline 14 is typically configured to detect a stuck-at-ground fault condition and output an error flag in response to detection of the fault. This type of error can be caused by either a hard error or a soft error. Conventional wordline fault detection circuitry 30 will be able to detect a fault in which there is a physical break 26 in wordline 14 but no charge has accumulated on the floating portion 32 of the faulty wordline 14 a, and the voltage on the floating portion 32 is at or near ground. Unfortunately, because testing for faults in that situation relies on detection of the ground voltage, conventional wordline fault detection circuitry 30 will not be able to detect a scenario in which there is a physical break 26 in wordline 14 and sufficient charge has accumulated on the floating portion 32 of the faulty wordline 14 a to raise the voltage on the floating portion 32 to a level significantly above ground.

[0007] There is a need in the art for a fault detection circuit that can ensure proper detection of physical breaks in a word line. Summary of the Invention

[0008] In one embodiment, a circuit includes: a first memory array including a plurality of word lines; a row decoder located on one side of the first memory array and configured to selectively drive the plurality of word lines in response to a row address; and a first word line fault detection circuit located on an opposite side of the first memory array. The first word line fault detection circuit includes: a first clamp circuit configured to clamp the plurality of word lines to ground; a first encoder circuit configured to encode signals on the plurality of word lines to generate a first encoded address; and a first comparator circuit configured to compare the first encoded address with a row address and, if the first encoded address does not match the row address, set a first error flag indicating the presence of an open word line fault between the one side of the first memory array and the opposite side of the first memory array.

[0009] In one embodiment, a method includes: decoding a row address to selectively drive a plurality of word lines of a first memory array on one side of the first memory array; clamping the plurality of word lines to ground at an opposite side of the first memory array; encoding signals on the plurality of word lines to generate a first coded address; comparing the first coded address to a row address; and if the first coded address does not match the row address, setting a first error flag indicating the presence of a broken word line fault between the one side of the first memory array and the opposite side of the first memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0011] Figure 1is a simplified block diagram of the memory circuit;

[0012] Figure 2 is a simplified block diagram of a memory circuit having an open wordline fault detection circuit;

[0013] Figure 3 is a schematic diagram of a memory circuit having a broken word line fault detection circuit;

[0014] Figures 4A-4C Pictured Figure 3 The circuit shown in performs the operation of disconnected word line fault detection;

[0015] Figure 5 is a simplified block diagram of a multi-bank memory circuit with open wordline fault detection circuitry;

[0016] Figure 6 is a schematic diagram of a multi-bank memory circuit with open wordline fault detection circuitry. DETAILED DESCRIPTION

[0017] Now refer to Figure 2 , which shows a simplified block diagram of a memory circuit 100 with a broken wordline fault detection circuit 102. Circuit 100 includes an array 12 of memory cells C arranged in rows and columns. The memory cells in each row are controlled by a wordline 14. The memory cells in each column are connected to a bitline 16. Row decoder circuit 18 receives a row address RAddr and decodes the bits of the row address to select and activate one of the wordlines 14. Column decoder circuit 22 receives a column address CAddr and decodes the bits of the column address to select a plurality of bitlines 16. In write mode, data on data input / output line 24 is written to the memory cell located at the intersection of the wordline 14 selected by row decoder circuit 18 and the plurality of bitlines 16 selected by column decoder circuit 22. In read mode, data stored in the memory cell at the intersection of the wordline 14 selected by row decoder circuit 18 and the plurality of bitlines 16 selected by column decoder circuit 22 is read out to data input / output line 24.

[0018] The open wordline fault detection circuit 102 includes a clamp circuit 104 that responds to assertion of a clamp signal (Clp) by activating the clamp circuit to clamp each of the wordlines 14 to ground. The open wordline fault detection circuit 102 also includes a wordline encoder circuit 106 that is connected to each wordline 14 and operates to encode the signal on the wordline 14 to generate an encoded address EAddr for output. A comparator circuit 108 operates to compare the encoded address EAddr with the row address RAddr and assert an output error flag if the addresses do not match.

[0019] In a particular embodiment, the word line encoder circuit 106 operates to encode the signal on the word line 14 to generate both the encoded address EAddr and the logical inverse of the encoded address EAddrb. The comparator circuit 108 then operates to compare the encoded address EAddr with the row address RAddr and to compare the logical inverse of the encoded address EAddrb with the logical inverse of the row address RAddrb, and assert an output error flag if a match fails in either of the address comparisons.

[0020] The clamp signal (Clp) propagates to further generate a reset signal Rst, which is also applied to the input of the comparator circuit 108. The comparator circuit 108 further operates to check the logic state and logic transitions of the reset signal Rst. In the event that a problem with the reset signal Rst is detected, an error flag may also be asserted by the comparator circuit 108. The reset signal Rst is generated by the clamp signal output by the control circuit 110 and serves as a tracking signal for the word line encoder 106. The activation of the reset signal Rst indicates that sufficient voltage has been formed on the encoding address EAddr bus and the logical inversion of the encoding address EAddrb bus to allow the comparator 108 to detect the state of the EAddr and EAddrb signals. In response to the logic transition of the reset signal Rst at the comparator 108, the comparator acts to latch the EAddr and EAddrb signals and perform address comparison.

[0021] It will be noted that the signal line associated with the generation of the reset signal Rst may itself be subject to a hard fault. For example, the signal line carrying the clamp signal (Clp) from which the reset signal Rst is generated may be interrupted, and in this case, the operation of the clamp circuit 104 will be disrupted. Failure to detect activation of the reset signal Rst at the comparator 108 then indicates the presence of the fault and the detection of the fault. Therefore, the state of the reset signal Rst is sensed by the comparator circuit 108 and in the event of a fault being detected, a flag will be set. The signal line for the reset signal Rst is connected to the farthest clamp circuit in the clamp circuits 104 (e.g., Figure 3 The control gate of the NMOS 200 shown in FIG. 1 is thus effectively ensured that each clamp circuit 104 in the clamp circuit has effectively received the clamp signal Clp.

[0022] The control circuit 110 receives the address 20 of the memory location to be accessed in a read / write manner and performs an address pre-decoding operation to generate a row address RAddr applied to the row decoder 18 and a column address CAddr applied to the column decoder 22. The control circuit 110 asserts the clamp signal (Clp). The clamp circuit 104 then clamps each of the word lines 14 to ground. In response to the clock signal Clk indicating the start of the memory access operation (read / write), the control circuit 110 provides the row address RAddr and the column address CAddr and de-asserts the clamp signal (Clp). The clamp circuit 104 responds by releasing the clamp on each of the word lines 14. The word line encoder circuit 106 then encodes the signals on the word lines 14 to generate the encoded address EAddr (and EAddrb). Comparator circuit 108 then functions to compare the encoded address EAddr with the row address RAddr (and EAddrb with RAddrb) and generates an output error flag whose logic state depends on whether the compared addresses match.

[0023] The operation of controlling the clamping circuit 104 to clamp each of the word lines 14 to ground before the word line encoder circuit 106 operates to encode the signal on the word line 14 and generate the encoded address EAddr is important because the clamping to ground operation effectively discharges each of the word lines 14, and in particular will effectively discharge any charge accumulated on the floating portion 32 of the failed word line 14 a. Thus, any accumulated charge that would adversely affect the operation of encoding the word line signal and generating the encoded address EAddr (and EAddrb) will not be present.

[0024] Consider the following example, in which memory 100 includes a faulty wordline 14a driven by row decoder 18 at a logic high and a non-faulty wordline 14b driven by row decoder 18 at a logic low. Now, assume that clamp circuit 104 is not present (or inoperative), and assume that charge has accumulated on floating portion 32 of faulty wordline 14a. This accumulated charge causes the voltage on floating portion 32 of faulty wordline 14a to rise above ground. Consequently, wordline encoder circuit 106 will see logic high and logic low wordline signals on wordlines 14a and 14b, respectively, corresponding to the logic high and logic low states driven by row decoder 18 in response to decoding row address RAddr. Accordingly, wordline encoder circuit 106 will encode the signal on wordline 14 to generate an encoded address EAddr that matches row address RAddr. In this case, the fault detection circuit will be unable to detect the open wordline condition of faulty wordline 14a.

[0025] Now consider a modification of the aforementioned example, in which clamp circuit 104 is present and operational. Prior to the operation of encoding the signal on wordline 14, clamp signal (Clp) is asserted, and clamp circuit 104 operates to clamp wordlines 14a and 14b to ground. The charge accumulated on floating portion 32 of faulty wordline 14a is discharged, and the voltage on floating portion 32 is driven to ground. Consequently, wordline encoder circuit 106 will see logic low and logic low wordline signals on wordlines 14a and 14b, respectively, which do not correspond to the logic high and logic low states driven by row decoder 18 in response to decoding row address RAddr. Accordingly, wordline encoder circuit 106 will encode the signal on wordline 14 to generate an encoded address EAddr that does not match row address RAddr. In this case, due to the failure to match the address, the comparator will assert an error flag, thereby indicating detection of a broken wordline condition for faulty wordline 14a.

[0026] Now refer to Figure 3 , which shows a schematic diagram of a memory 110 having an open word line fault detection circuit 102. It will be appreciated that for ease of understanding, this schematic diagram presents Figure 2 In this down-scaling simplification, the row address RAddr has only two bits A0 and A1, and therefore there are only four word lines 14a-14d. Details of the memory array 12 have also been omitted.

[0027] The open word line fault detection circuit 102 is located on the opposite side of the memory array 12 from the row decoder 18 and its word line driver circuitry. Thus, the word line 14 extends from the output of the row decoder 18 on the left side of the memory array, through and / or past the memory cells (C, D) of the corresponding row of the memory array. Figure 1 and Figure 2 ) to the open word line fault detection circuit 102 on the right side of the memory array. This location of the open word line fault detection circuit 102 on the opposite side of the memory array from the word line drivers is important so that the open word line fault detection circuit 102 can effectively test for open word line conditions caused by hard faults present within the memory array itself.

[0028] The clamp circuit 104 is formed of a plurality of metal oxide semiconductor field effect transistor (MOSFET) devices 200 whose gate terminals are connected to receive a clamp signal (Clp). One transistor 200 is provided for each word line 14, wherein a first conductive terminal (e.g., a drain terminal) is connected to the word line 14 and a second conductive terminal (e.g., a source terminal) is connected to ground. The transistors 200 in the illustrated example are n-channel devices. In response to assertion of the clamp signal (Clp) (e.g., asserted at a logic high at Vdd), each of the transistors 200 turns on to short-circuit the word line 14 to ground. This has the effect of clamping the word line to ground and, in particular, discharging any charge accumulated on the floating portion of a faulty word line in the word lines 14.

[0029] The wordline encoder circuit 106 is an M×N encoder (in this example, a 4×2 encoder) that generates true and complement encoded outputs. M equals the number of wordlines, and N equals the number of bits in the row address and the number of bits in the encoded address. In the illustrated embodiment, the wordline encoder circuit 106 is implemented as a ROM-based encoder, which has the advantages of fast switching operation, little to no current consumption in static conditions, and low current during switching. The wordline encoder circuit 106 includes a plurality of MOSFET devices 202. A plurality of transistors 202 are provided for each wordline 14, wherein the gates of the plurality of transistors 202 are connected to the wordline, and wherein a first conductive terminal (e.g., a drain terminal) of each transistor is connected to an output address line 204 biased at Vdd or left disconnected (floating), and wherein a second conductive terminal (e.g., a source terminal) of each transistor is connected to ground. Each output address line 204 is connected to Vdd via an appropriate pull-up device (e.g., a resistor, shown schematically here).

[0030] Regarding the example 4×2 real encoder for generating the encoded address EAddr from the word line signal: for the transistor pair driven by word line 14a and connected to the address lines EA0 and EA1, the first conductive terminal of the transistor pair is connected to Vdd; for the transistor pair driven by word line 14b and connected to the address lines EA0 and EA1, the first conductive terminal of the first transistor in the pair is disconnected and the first conductive terminal of the second transistor in the pair is connected to Vdd; for the transistor pair driven by word line 14c and connected to the address lines EA0 and EA1, the first conductive terminal of the first transistor in the pair is connected to Vdd and the first conductive terminal of the second transistor in the pair is disconnected from Vdd; and for the transistor pair driven by word line 14d and connected to the address lines EA0 and EA1, the first conductive terminal of the transistor pair 202 is disconnected. This is shown by way of example only, and it should be understood that those skilled in the art can design any suitable M×N encoder to be used as the real encoder of the word line encoder circuit 106.

[0031] Regarding an example 4×2's complement encoder for generating a logically inverted encoded address EAddrb from a word line signal: for a transistor pair driven by word line 14a and connected to address lines EA0b and EA1b, the first conductive terminal of the transistor pair 202 is disconnected; for a transistor pair driven by word line 14b and connected to address lines EA0b and EA1b, the first conductive terminal of the first transistor in the pair is connected to Vdd, and the first conductive terminal of the second transistor in the pair is disconnected; for a transistor pair driven by word line 14c and connected to address lines EA0b and EA1b, the first conductive terminal of the first transistor in the pair is disconnected, and the first conductive terminal of the second transistor in the pair is connected to Vdd; and for a transistor pair driven by word line 14d and connected to address lines EA0b and EA1b, the first conductive terminal of the transistor pair 202 is connected to Vdd. This is shown by way of example only, and it should be understood that one skilled in the art can design any suitable M×N encoder for use as a complement encoder for word line encoder circuit 106.

[0032] Using and evaluating both the true encoded address EAddr and the complement encoded address EAddrb has operational advantages. With access to both the EAddr signal and the EAddrb signal, comparator circuit 108 can detect three different fault conditions: a) a broken word line, b) an incorrect word line is selected, and c) multiple word lines are selected simultaneously. It will be noted that either EAddr or EAddrb can be used to detect fault conditions a) and b). However, detection of fault condition c) requires both EAddr and EAddrb.

[0033] By considering Figures 4A-4CThe example shown in the figure can better understand Figure 3 1. Operation of the broken wordline fault detection circuit 102. For this example, assume that wordline 14b has a fault within the memory array 12 in the form of a physical break in the wordline 14 itself. This is generally represented schematically by an "X" mark on the failed wordline 14b, and this results in a floating portion 32 of wordline 14b being connected to the broken wordline fault detection circuit 102.

[0034] Figure 4A It is shown that the address 20 has been pre-decoded by the control circuit 110 to generate the row address RAddr<1,0>. The row decoder 18 decodes this RAddr<1,0> to select the word line 14b. In response to this selection, the word line driver circuit of the row decoder 18 will drive the word lines 14a, 14c and 14d to ground (logical low "0") and drive the word line 14b to Vdd (logical high "1"). At the opposite side of the memory array 12, the word lines 14a, 14c and 14d will also be grounded (logical low "0"). However, due to the open word line fault "X" in the word line 14b, any voltage between ground and Vdd may exist on the floating portion 32 of the word line 14b, and therefore the logic state of the floating portion 32 of the word line 14b is undefined (in Figure 4A indicated by a “U” in the figure).

[0035] Now refer to Figure 4B Now, assume that there is an accumulation of charge on the floating portion 32 of the faulty word line 14b, so that the logic state of the floating portion 32 of the word line 14b is no longer undefined. In fact, due to the charge accumulation, a sufficient voltage may be formed on the floating portion 32 so that the floating portion 32 is in a logic high "1" state (at Figure 4B, 14b). Assuming that the clamp circuit 104 is not present or inoperable, the charge accumulation will produce a word line signal <0,1,0,0>, which will be encoded by the word line encoder circuit 106 to generate the encoded address EAddr<1,0> and the encoded address EAddrb<0,1>. This occurs because the transistors 202 for the EA0 and EA1b address lines are both not turned on (thus EA0=1 and EA1b=1), and the transistors gated by the word line 14b in the “U1” state for the EA1 and EA0b address lines are turned on (thus EA1=0 and EA0b=0). The comparator circuit 108 compares the encoded address EAddr<0,1> with the row address RAddr<0,1> and finds that the addresses match. The comparator circuit 108 also compares the complement encoded address EAddrb<1,0> with the complement row address RAddrb<1,0> and finds that the addresses match. Since the address matches, the output flag is not set. Because the flag is not set, this indicates that the circuit 102 has not detected a fault on word line 14b. Figure 4B The failure to detect a fault on word line 14b in the example shown in is of concern. However, the open word line fault detection circuit 102 is configured to address this fault using the clamp circuit 104.

[0036] Now refer to Figure 4C As previously described, sufficient charge accumulation on the floating portion 32 of the failed word line 14b may result in a logic high "U1" logic state of the floating portion 32 of the word line 14b (see Figure 4B). To address this possibility, control circuit 110 asserts clamp signal Clp, which activates transistor 200 within clamp circuit 104. As a result, all word lines 14a-14d are shorted to ground. In particular, the activation of transistor 200b connected to word line 14b ensures that any accumulated charge on the floating portion 32 of the failed word line 14b is discharged, and the floating portion 32 is therefore driven to ground (logical low "0"). As a result, the word line signal <0,0,0,0> will be encoded by word line encoder circuit 106 to generate encoded address EAddr<1,1> and encoded address EAddrb<1,1>. This occurs because transistors 202 for the EA0, EA1, EA0b, and EA1b address lines are not turned on (thus, EA0=1, EA1=1, EA0b=1, and EA1b=1). Comparator circuit 108 compares the encoded address EAddr<0,1> with the row address RAddr<1,1> and finds an address mismatch. Comparator circuit 108 also compares the complement encoded address EAddrb<1,0> with the complement row address RAddrb<1,1> and finds an address mismatch. Because there is at least one detection of a mismatch by comparator circuit 108, the output flag is set. This indicates that circuit 102 has detected a fault on word line 14b.

[0037] Signals Clp and Rst are present on a common signal line 208. It should be noted that this common signal line 208 is routed to pass along the length of the column of the memory array 12 in one direction to make electrical contact with the gate terminal of the transistor 200, and then loop back in the opposite direction along the length of the column of the memory array 12 in a return path. This long path of the common signal line 208 introduces an RC time delay in the transition of the logic states of the signals Clp and Rst. As described above, the time delay is important to ensure that sufficient voltage is formed on the EAddr and EAddrb signals before being latched by the comparator circuit 108. The long path is also important to ensure that the signal Rst generated from the farthest clamp NMOS 200 of the clamp circuit 104 is not affected by the voltage drop.

[0038] Figure 3 The embodiment shows a memory circuit 100 including only a single memory bank formed by the array 12. The broken wordline fault detection circuit 102 can also support fault detection operations in more complex memory architectures including multiple memory banks. Figure 5 This embodiment is shown in FIG. Here, the memory circuit includes two memory banks formed by array 12a and array 12b. Row decoder 18 is used to decode row address RAddr and select word line 14 for two memory banks. Open word line fault detection circuit 102 can be provided for each memory bank and can be used as shown in FIG. Figure 3Each included circuit 102a and 102b will generate corresponding Flag0 and Flag1 respectively.

[0039] In one embodiment, the circuitry for generating the bits of the encoding address EAddr may be split between the two circuits 102a and 102b. For example, for an M×N encoder configuration, N / 2 bits of the encoding address EAddr may be generated by circuit 102a, and a different N / 2 bits of the encoding address EAddr may be generated by circuit 102b. Figure 6 An example of this is shown with a 4×2 encoder configuration, where circuit 102 a includes a wordline encoder circuit 106 a that generates true and complement bits (EA0 and EA0 b) for a portion of the encoded address (in this case, one bit, i.e., N=2 / 2), and circuit 102 b includes a wordline encoder circuit 106 b that generates true and complement bits (EA1 and EA1 b) for another portion of the encoded address (in this case, another bit). Comparator circuit 108 a compares the portion of the encoded address (having bits EA0 and EA0 b) with the corresponding portion of the row address (having bits A0 and A0 b) to detect a match and, if no match is detected, controls the setting of Flag0. Comparator circuit 108 b compares the portion of the encoded address (having bits EA1 and EA1 b) with the corresponding portion of the row address (having bits A1 and A1 b) to detect a match and, if no match is detected, controls the setting of Flag1.

[0040] Although the present invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A circuit comprising: a first memory array comprising a plurality of word lines; a row decoder located on one side of the first memory array and configured to selectively drive the plurality of word lines in response to a row address; as well as a first word line failure detection circuit located on an opposite side of the first memory array, the first word line failure detection circuit comprising: a first clamp circuit configured to clamp the plurality of word lines at the opposite side of the first memory array to ground in response to assertion of a clamp signal; a first encoder circuit configured to encode signals on the plurality of word lines at the opposite side of the first memory array to generate a first encoded address; and a first comparator circuit configured to receive the clamp signal and, in response to assertion of the clamp signal, compare the first encoded address with the row address and, if the first encoded address does not match the row address, set a first error flag indicating the presence of a broken word line fault between the one side of the first memory array and the opposite side of the first memory array; wherein the clamp signal propagates over a signal line from an output of a control circuit to the first clamp circuit, and further from the first clamp circuit to an input of the first comparator circuit, and wherein the clamp signal propagates on the signal line to generate a reset signal, and in response to a logic transition of the reset signal at the first comparator circuit, the first comparator circuit acts to latch the first encoded address and the logical inversion of the first encoded address, and performs a comparison of the first encoded address with the row address.

2. The circuit of claim 1 , further comprising a control circuit configured to activate the first clamp circuit and apply the row address to the row decoder by assertion of the clamp signal, and then deactivate the first clamp circuit before the first encoder circuit operates to encode the signals on the plurality of word lines and generate the first encoded address.

3. The circuit of claim 2 , wherein the first clamp circuit comprises a plurality of transistors connected to the plurality of word lines at the opposite sides of the first memory array, the plurality of transistors having gate terminals coupled to receive the clamp signals output from the control circuit and configured to electrically connect the plurality of word lines to ground.

4. The circuit of claim 1, wherein the first encoder circuit is an MxN encoder, where M equals the number of word lines and N equals the number of bits in the row address.

5. The circuit of claim 1 , wherein the first encoder circuit is further configured to encode signals on the plurality of word lines to generate a complemented first coded address, and wherein the first comparator circuit is further configured to compare the complemented first coded address with a complement of the row address and set the first error flag if the complemented first coded address does not match the complement of the row address.

6. The circuit of claim 1 , wherein the clamping of the plurality of word lines to ground discharges accumulated charge on a portion of a word line that is floating due to the presence of the open word line fault between the one side of the first memory array and the opposite side of the first memory array.

7. The circuit according to claim 1, further comprising: a second memory array comprising the plurality of word lines; wherein the row decoder is located on one side of the second memory array; as well as a second word line fault detection circuit located on an opposite side of the second memory array, the second word line fault detection circuit comprising: a second clamping circuit configured to clamp the plurality of word lines at the opposite side of the second memory array to ground; a second encoder circuit configured to encode signals on the plurality of word lines at the opposite side of the second memory array to generate a second encoded address; and A second comparator circuit is configured to compare the second encoded address with the row address and set a second error flag if the second encoded address does not match the row address, the second error flag indicating the presence of the open word line fault.

8. The circuit of claim 7 , further comprising a control circuit configured to activate the first clamp circuit and the second clamp circuit by assertion of the clamp signal and apply the row address to the row decoder, and then deactivate the first clamp circuit and the second clamp circuit before the first encoder circuit and the second encoder circuit operate to encode the signals on the plurality of word lines and generate the first encoded address and the second encoded address.

9. The circuit of claim 8 , wherein each of the first clamp circuit and the second clamp circuit comprises a plurality of transistors connected to the plurality of word lines at the opposite sides of the first memory array, the plurality of transistors having gate terminals coupled to receive the clamp signals output from the control circuit and configured to electrically connect the plurality of word lines to ground.

10. The circuit of claim 7, wherein each of the first and second encoder circuits is an MxN encoder, where M equals the number of word lines and N equals the number of bits in the row address.

11. The circuit of claim 7, wherein each of the first and second encoder circuits is an MxN encoder, where M equals the number of word lines and N equals a fraction of the number of bits in the row address.

12. The circuit of claim 11, wherein the fraction is one divided by the number of memory arrays.

13. The circuit of claim 7 , wherein the first encoder circuit and the second encoder circuit are further configured to encode signals on the plurality of word lines to generate a complemented first encoded address and a complemented second encoded address, respectively, and wherein the first comparator circuit and the second comparator circuit are further configured to compare the complemented first encoded address and the complemented second encoded address, respectively, with the complement of the row address, and set the first error flag and the second error flag if the addresses do not match.

14. A method for detecting a word line failure condition, comprising: decoding a row address to selectively drive a plurality of word lines of a first memory array at one side of the first memory array; clamping the plurality of word lines to ground at opposite sides of the first memory array in response to assertion of a clamp signal; encoding signals on the plurality of word lines at the opposite side of the first memory array to generate a first encoded address; in response to assertion of the clamp signal, comparing the first encoded address with the row address; setting a first error flag if the first encoded address does not match the row address, the error flag indicating the presence of a broken word line fault between the one side of the first memory array and the opposite side of the first memory array; as well as Propagating the clamping signal to the clamping circuit for performing the clamping through a signal line, and further propagating the signal to the comparison circuit for performing the comparison; wherein the clamp signal propagates on the signal line to generate a reset signal; and in response to a logic transition of the reset signal at the comparison circuit, the comparison circuit acts to latch the first encoding address and the logical inversion of the first encoding address, and performs a comparison of the first encoding address with the row address.

15. The method according to claim 14, further comprising: Prior to encoding the signals on the word lines, the clamps of the word lines are released.

16. The method of claim 14 , wherein encoding further comprises encoding signals on the plurality of word lines to generate a complemented first coded address, and wherein comparing further comprises comparing the complemented first coded address with a complement of the row address, and wherein setting further comprises setting the first error flag if the complemented first coded address does not match the complement of the row address.

17. The method of claim 14 , wherein clamping the plurality of word lines to ground discharges accumulated charge on a portion of a word line that is floating due to the presence of the open word line fault between the one side of the first memory array and the opposite side of the first memory array.

18. The method of claim 14 , wherein decoding further selectively drives the plurality of word lines of the second memory array on one side of the second memory array, the method further comprising: clamping the plurality of word lines to ground at opposite sides of the second memory array; encoding signals on the plurality of word lines at the opposite side of the second memory array to generate a second encoded address; comparing the second encoded address with the row address; as well as If the second encoded address does not match the row address, a second error flag is set, the second error flag indicating the presence of a broken word line failure between the one side of the second memory array and the opposite side of the second memory array.

19. The method of claim 18, further comprising releasing the clamps of the plurality of word lines before encoding the signals on the plurality of word lines.

20. The method of claim 18 , wherein encoding further comprises encoding signals on the plurality of word lines to generate a complemented second coded address, and wherein comparing further comprises comparing the complemented second coded address with a complement of the row address, and wherein setting further comprises setting the second error flag if the complemented second coded address does not match the complement of the row address.

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