Semiconductor device

Abstract

A semiconductor device which can reduce power consumption while improving accuracy of learning and inference is provided. The semiconductor device is connected to data lines PBL, NBL, and includes a product operation memory unit 1 for storing data of ternary values and performing a product-sum operation between the stored data and data in the data lines PBL, NBL and input data INP.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2019-020844 filed on February 7, 2019, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a semiconductor device. For example, the present invention relates to a semiconductor device that needs to perform a large amount of product-sum and operation such as AI (Artificial Intelligence). BACKGROUND

[0004] In recent years, with the development of machine learning by deep learning, AI has been applied in various places. However, this method requires a large amount of product-sum and operation, so that the product-sum and operation processing is accelerated, for example, by a GPU (Graphics Processing Unit) or the like. In addition to the product-sum and operation processing, a large amount of data transfer processing occurs in conjunction with the data transfer processing. In order to perform these processes, a problem that power consumption becomes very large occurs.

[0005] If this problem can be solved, AI can be used as an edge of IoT (Internet of Things) or the like in a sensor-side system, and AI can be used more diversely.

[0006] As a technology for reducing data transfer processing generated in association with product-sum and operation, there is a technology described in "A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement", VLSI circuit 2018, June 18, 2018 (Non-Patent Literature 1). SUMMARY

[0007] In non-patent document 1, in order to reduce data transmission processing, the multiplier in the product operation is stored in a memory cell of a static volatile memory (hereinafter referred to as "SRAM"). In addition, in non-patent document 1, the multiplier and the multiplicand in the product operation are both represented by binary values ​​"0" and "1", and the binary values ​​are defined as "-1" and "1" in order to achieve low power consumption. Therefore, the result of the negative exclusive OR (XNOR) is multiplied by "-1" and "1". In addition, in non-patent document 1, by connecting a plurality of memory cells to a data line, the sum of the product operations in the corresponding memory cells is observed as the voltage of the data line. As a result, the number of data transmission processing related to the multiplier is reduced in the product operation part of the product-sum operation, and the part of the sum operation is realized by reading the data lines from a plurality of memory cells at one time.

[0008] However, when considering multi-bit product-sum operations such as floating-point numbers, for example, if the multi-bit is binary, there is a problem that the accuracy of machine learning and inference deteriorates due to excessive compression. In addition, there is a problem that the time required for learning, etc. becomes enormous.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. A semiconductor device according to one embodiment is as follows.

[0010] Specifically, a semiconductor device includes a memory cell connected to a data line, stores ternary data, and performs a product-sum operation on the stored data, input data to the memory cell, and data on the data line. Examples of ternary values ​​include +1, 0, and -1. According to one embodiment, a semiconductor device can be provided that can reduce power consumption while improving the accuracy of learning and inference. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 1 is a diagram showing the configuration of a memory cell having a product-sum operation function related to the first embodiment.

[0012] Figure 2 is a schematic diagram showing the configuration of a product operation memory unit related to the first embodiment.

[0013] Figure 3 is a plan view showing the layout of a semiconductor device related to the second embodiment.

[0014] Figures 4A to 4D is a diagram showing the layout of a semiconductor device related to the second embodiment.

[0015] Figure 5A and Figure 5B is a plan view showing the layout of a semiconductor device related to the third embodiment.

[0016] Figure 6 is a schematic diagram showing a configuration of a semiconductor device relating to the fourth embodiment.

[0017] Figure 7A and Figure 7B is a plan view showing a layout of a semiconductor device relating to the fourth embodiment.

[0018] Figures 8A to 8D is a sectional view showing a cross section of a semiconductor device relating to the fourth embodiment.

[0019] Figure 9 is a schematic diagram showing a configuration of a product operation memory cell relating to the fifth embodiment.

[0020] Figure 10 is a schematic diagram showing a configuration of a product operation memory cell according to the sixth embodiment;

[0021] Figure 11 is a diagram showing a configuration of a semiconductor device according to the seventh embodiment.

[0022] Figure 12A and Figure 12B is a diagram for explaining a semiconductor device according to the eighth embodiment.

[0023] Figure 13 is a diagram showing a configuration of a semiconductor device according to the ninth embodiment.

[0024] 14A to 14D is a diagram showing a configuration of a semiconductor device according to the ninth embodiment.

[0025] Figure 15A and Figure 15B is a timing chart for explaining A / D conversion according to the ninth embodiment.

[0026] Figure 16A and Figure 16B is a diagram showing a configuration of a semiconductor device according to the tenth embodiment;

[0027] Figure 17A and Figure 17B is a diagram for explaining the tenth embodiment.

[0028] 18A to 18D is a diagram for explaining A / D conversion according to the eleventh embodiment.

[0029] Figure 19 is a schematic diagram showing a configuration of a semiconductor device according to the eleventh embodiment.

[0030] Figure 20A and Figure 20B is a timing chart of a semiconductor device according to the eleventh embodiment.

[0031] Figure 21 is a circuit diagram showing the configuration of a reference cell according to a twelfth embodiment of the present invention.

[0032] Figure 22 are diagrams showing external terminals included in the semiconductor devices according to the first to twelfth embodiments. DETAILED DESCRIPTION

[0033] Hereinafter, each embodiment of the present invention will be described below with reference to the accompanying drawings. Note that the present disclosure is merely an example, and those skilled in the art can easily conceive that appropriate changes while maintaining the gist of the present invention are naturally included in the scope of the present invention. In addition, although the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity of description, the drawings are merely examples and do not limit the interpretation of the present invention.

[0034] In the present specification and the drawings, the same reference numerals are given to the same elements as those described above with reference to the above drawings, and detailed descriptions thereof may be appropriately omitted.

[0035] (First embodiment)

[0036] <Configuration of Memory Cells with Product-Sum Operation Function>

[0037] Figure 1 : is a diagram showing the configuration of a memory cell having a product-sum operation function (hereinafter referred to as a product operation memory cell) according to the first embodiment. Figure 1 The figure shows two product operation memory cells connected to the data lines (first data line and second data line) PBL and NBL. Since the product operation memory cells 1 have the same configuration as each other, Figure 1 Only one product operation memory unit 1 is shown. The product operation memory unit 1 includes two memory units (a first memory unit and a second memory unit) 2 and 3 for storing ternary values. In addition to the memory units 2 and 3, the product operation memory unit 1 also includes three switches (a first switch to a third switch) 4 to 6 and a constant current source 7.

[0038] Memory cells 2 and 3 are SRAM memory cells and are connected to the memory cells that are later Figure 2, and logical values ​​are written to memory cells 2 and 3 using the paired complementary data lines and word lines described in

[15] . Switches 4 and 5 correspond to memory cells 2 and 3, and when, for example, a logical value "1" is stored in the corresponding memory cell, switches 4 and 5 turn on. Switch 4 is connected between node n1 and data line PBL, and switch 5 is connected between node n1 and data line NBL. Switch 6 is connected between node n1 and constant current source 7, and constant current source 7 is connected to ground voltage Vs. Switch 6 corresponds to input data INP supplied to input wiring INP_L, and when input data INP is, for example, a logical value "1," switch 6 turns on.

[0039] When both memory cells 2 and 3 store a logical value of "0," the product operation memory cell 1 is considered to store a logical value of "0." When memory cell 2 stores a logical value of "1" and memory cell 3 stores a logical value of "0," the product operation memory cell 1 is considered to store a logical value of "+1." Furthermore, when memory cell 2 stores a logical value of "0" and memory cell 3 stores a logical value of "1," the product operation memory cell 1 is considered to store a logical value of "-1."

[0040] As a result, when logic value "0" is stored in product operation memory unit 1, switches 4 and 5 turn to off state, and no current flows from data lines PBL, NBL to constant current source 7 even if input data INP is logic value "1".

[0041] On the other hand, when the logical value "+1" is stored in product operation memory cell 1, switch 4 turns on and switch 5 turns off. At this point, if input data INP is a logical value of "1," current flows from data line PBL to constant current source 7 via switches 4 and 6, which are in the on state, and the voltage on data line PBL decreases. At this point, the voltage on data line NBL does not decrease. On the other hand, if input data INP is a logical value of "0," switch 6, which was in the on state, turns off, preventing current from flowing from data lines PBL and NBL to constant current source 7 and preventing the voltage on data lines PBL and NBL from decreasing.

[0042] When the logic value "-1" is stored in the product operation memory cell 1, the switch 5 turns to the on state and the switch 4 turns to the off state. At this time, if the input data INP is the logic value "1", a current flows from the data line NBL to the constant current source 7 via the switches 5 and 6 in the on state, the voltage of the data line NBL decreases, and the voltage of the data line PBL does not decrease. On the other hand, at this time, if the input data INP is the logic value "0", the switch 6 in the on state turns to the off state so that no current flows from the data lines PBL, NBL to the constant current source 7 and the voltages of the data lines PBL and NBL do not decrease.

[0043] It can be considered that the memory cell 2 functions to store the logic value "+1" in the product operation memory cell 1 and the memory cell 3 functions to store the logic value "-1" in the product operation memory cell 1.

[0044] As a result, a product operation is performed between the ternary value stored in the product operation memory cell 1 and the value of the input data INP. In other words, six states 0 x 0, 0 x (+1), 0 x (-1), 1 x 0, 1 x (+1), and 1 x (-1) are formed according to the logic value of the input data and the logic value of the product operation memory cell. In this case, a product operation is performed between the logic value of the input data and the logic value stored in the product operation memory cell 1, and when the result of the product operation is the logic value "1", a current flows between the data line PBL and the constant current source 7, and the voltage of the data line PBL decreases. On the other hand, when the result of the product operation is the logic value "-1", a current flows between the data line NBL and the constant current source 7, and the voltage of the data line NBL decreases.

[0045] In Figure 1 , the product operation memory cell 1 shown at the lower side of the page operates in a similar manner to perform a product operation between the ternary logic value stored in the product operation memory cell 1 and the logic value of the input data INP, and to draw a current from the data lines PBL, NBL according to the result of the product operation.

[0046] In each of the data lines PBL, NBL, the current according to the product operation result of the product operation memory cell 1 shown at the upper side of the page and the current according to the product operation result of the product operation memory cell 1 shown at the lower side of the page are superimposed, and the current and the voltage are determined in each of the data lines PBL, NBL. That is, a sum operation is performed so that the products obtained in the two product operation memory cells 1 are summed up through the data lines PBL, NBL. The result of the sum-of-products operation as a result of the sum operation is output through the data lines PBL, NBL.

[0047] Figure 2is a schematic diagram showing the configuration of a product operation memory unit related to the first embodiment. Figure 2 Only shown Figure 1 One of the two product operation memory cells 1 shown is a product operation memory cell. The configuration of the memory cell will be described by taking the memory cell 2 as an example. The memory cell 2 is a so-called SRAM memory cell composed of six transistors. That is, the memory cell 2 includes a plurality of P-channel field effect transistors (referred to as P-type FETs) and a plurality of N-channel field effect transistors (referred to as N-type FETs). Figure 2 In the drawings described later, a P-type FET is distinguished from an N-type FET by marking a gate electrode with a circle. When the channel type is not distinguished, a field effect transistor is hereinafter referred to as a FET.

[0048] Memory cell 2 includes a first inverter circuit IV1 composed of a P-type FET P1 and an N-type FET N1, and a second inverter circuit IV2 composed of a P-type FET P2 and an N-type FET N2. The first inverter circuit IV1 and the second inverter circuit IV2 are connected between a power supply voltage Vd and a ground voltage Vs. The input of the first inverter circuit IV1 is connected to the output of the second inverter circuit IV2, and the input of the second inverter circuit IV2 is connected to the output of the first inverter circuit IV1. In other words, the first inverter circuit IV1 and the second inverter circuit IV2 are cross-connected to form a latch circuit. Transmission N-type FETs N3 and N4 are connected between the inputs of the second inverter circuit IV2 and the first inverter circuit IV1 and the pair of complementary data lines BB and BT. The gate electrodes of the transmission N-type FETs N3 and N4 are connected to the word line PWL.

[0049] When writing data to memory cell 2, a pair of complementary data lines BB and BT and a word line PWL are used. Specifically, when writing data to memory cell 2, complementary voltages (high and low) corresponding to the logical value of the data to be written are supplied to the complementary data lines BB and BT, and a high voltage is supplied to word line PWL. As a result, the complementary voltages of the pair of complementary data lines BB and BT are supplied to the latch circuit formed by the first inverter circuit IV1 and the second inverter circuit IV2 via transmission N-type FETs N3 and N4, and a logical value of "0" or "1" is written to memory cell 2. The logical value held by memory cell 2 is output from node n2.

[0050] Memory cell 3 has the same configuration as memory cell 2, but the gate electrode of the pass N-type FET N3 and the gate electrode of the pass N-type FET N4 are connected to a word line NWL different from the word line PWL described above. Therefore, by setting the word line NWL to a high level at a timing different from the timing of the word line PWL, a logical value different from the logical value of memory cell 2 can be written to memory cell 3. In the first embodiment, memory cell 2 for storing a logical value of "+1" in the product operation memory cell 1 is controlled by word line PWL, and memory cell 3 for storing a logical value of "-1" in the product operation memory cell 1 is controlled by word line NWL.

[0051] Figure 1 , the switch 4 described in FIG. 1 includes an N-type FET N5, the switch 5 includes an N-type FET N6, and the switch 6 includes an N-type FET N7. That is, the source-drain path of the N-type FET N5 is connected between the node n1 and the data line PBL, and its gate electrode is connected to the node n2 of the memory cell 2. The source-drain path of the N-type FET N6 is connected between the node n1 and the data line NBL, and its gate electrode is connected to the node n2 of the memory cell 3. In addition, the source-drain path of the N-type FET N7 is connected between the node n1 and the voltage line CVSS, and its gate electrode is supplied with the input data INP. Although not particularly limited, a constant current source 7 (not shown) is connected to the voltage line CVSS. Of course, the ground voltage Vs may be supplied to the voltage line CVSS.

[0052] In the first embodiment, loads 10 and 11 are connected between data lines PBL and NBL and a power supply voltage Vd, respectively. Current is supplied to the data lines PBL and NBL via the loads 10 and 11 .

[0053] <Writing a Logical Value to a Product Operation Memory Cell and Product Operation> When writing a logical value "+1" to product operation memory cell 1, word line PWL is set to a high level while a high level is supplied to complementary data line BT and a low level is supplied to complementary data line BB. As a result, memory cell 2 is selected, and the pass N-type FETs N3 and N4 in memory cell 2 turn on. A low level is supplied to the input of second inverter circuit IV2. Consequently, the latch circuit in memory cell 2 latches the high state of node n2. Subsequently, word line NWL is set to a high level while a high level is supplied to complementary data line BB and a low level is supplied to complementary data line BT. Consequently, memory cell 3 is selected, and the pass N-type FETs N3 and N4 in memory cell 3 turn on. A high level is supplied to the input of second inverter circuit IV2. Consequently, the latch circuit in memory cell 3 latches the low state of node n2.

[0054] As a result, the N-type FET N5 turns to the on state, and the N-type FET N6 turns to the off state. In this state, for example, if the input data INP is at a high level, the N-type FET N7 turns to the on state, and the N-type FETs N5 and N7 form a current path for allowing current to flow from the data line PBL to the voltage line CVSS.

[0055] While the case of writing a logical value "+1" to the product operation memory cell 1 has been described, the case of writing a logical value "-1" and the case of writing a logical value "0" are similar. When the logical value "-1" is written to the product operation memory cell 1, if the input data INP is at a high level, a current path connecting the data line NBL and the voltage line CVSS is formed by the N-type FETs N6 and N7. On the other hand, when the logical value "0" is written to the product operation memory cell 1, even if the input data INP is at a high level, a current path connecting the data lines PBL and NBL and the voltage line CVSS is not formed.

[0056] <Sum operation> Figure 2 A large number of product operation memory cells 1 are shown connected to data lines PBL and NBL. As a result, a current corresponding to the sum of the number of current paths formed in the corresponding product operation memory cells flows through the data lines PBL and NBL. That is, a current corresponding to the sum of products on the logical value "+1" side flows into the data line PBL, and a current corresponding to the sum of products on the logical value "-1" side flows into the data line NBL. As a result, the result of the product-sum operation on the logical value "+1" side is output to the data line PBL, and the result of the product-sum operation on the logical value "-1" side is output to the data line NBL. Therefore, the desired product-sum operation result can be obtained by performing analog-to-digital conversion (A / D conversion) on the difference between the current in the data line PBL and the current in the data line NBL. Of course, the current flowing through each of the data lines PBL and NBL can be A / D converted to obtain the difference in the obtained digital signal.

[0057] In the first embodiment, the ternary logical values ​​of "+1," "0," and "-1" used in the product-sum operation are stored in the product operation memory unit 1. Therefore, it is possible to prevent the data used in learning or inference from being overly compressed, and the accuracy of learning or inference can be improved. Furthermore, a large number of product-sum operations can be performed by changing the input data INP without changing the logical values ​​stored in the product operation memory unit 1. Therefore, the number of data transfer processes can be reduced. Furthermore, since the sum operation is implemented by drawing current from each of the data lines PBL and NBL by the product operation memory unit 1, multiple sum operations can be performed in one operation. As a result, the number of data transfer processes can be further reduced, and power consumption can be reduced.

[0058] (Second embodiment) Figure 3 is a plan view showing the layout of a semiconductor device related to the second embodiment. Figure 3 Shown is a reference Figure 2 The layout of the product operation memory cell 1 is described. In the second embodiment, the product operation memory cell 1 is formed using a so-called planar FET. Figure 3 In the second embodiment, the memory cells 2 and 3 are arranged symmetrically about an imaginary straight line CNT indicated by a double-dot chain line passing through the center of the cell region CAR.

[0059] exist Figure 3 In FIG, the area surrounded by the solid line indicates the wiring forming the gate electrode of the FET, and the area surrounded by the dotted line indicates the semiconductor region forming the source region or the drain region of the FET. The area surrounded by the dotted line indicates the metal wiring formed by the metal wiring layer (conductive layer) of the first layer M1. In addition, the area surrounded by the solid line and marked with a cross indicates the contact area. The contact area electrically connects, for example, two layers overlapping with the contact area. In FIG. Figure 3 In, reference Figure 2 The symbols of the P-type FET and N-type FET described are attached to the gate electrode portion. The gate electrode portion to which the symbol is attached constitutes the gate electrode of the FET constituting the symbol.

[0060] The gate electrodes of the P-type FETs P1 and P2 and the N-type FETs N1 to N7 that constitute the product operation memory cell are arranged so as to be parallel to the imaginary straight line CNT. The gate electrodes of the P-type FET P1 and the N-type FET N1 on the complementary data line BB side are extended to form the gate electrode of the N-type FET N5 or N6 that constitutes the switch. In other words, the gate electrodes of the P-type FET P1 and the N-type FET N1 that constitute memory cells 2 and 3 are integrally formed with the gate electrode of the N-type FET N5 or N6 that constitutes the switch. Furthermore, the two N-type FETs N7 that constitute switch 6 are arranged in parallel to maintain symmetry between memory cells 2 and 3.

[0061] exist Figure 3 In the layout shown, the contact regions connecting the data lines PBL and NBL to the semiconductor regions are arranged at the boundaries of the cell regions CAR. Similarly, the contact regions connecting the complementary data lines BB and the semiconductor regions are also arranged at the boundaries of the cell regions CAR. Figure 3 The adjacent product operation memory cells 1 shown in FIG are arranged so that Figure 3The product operation memory cell 1 shown in FIG is mirror-inverted about the virtual Y-axis straight lines Y1 and Y2 shown by the double-dot chain line. As a result, the data lines PBL, NBL and the complementary data line BB can be shared between adjacent product operation memory cells 1.

[0062] In the first embodiment, Figure 3 Another four metal wiring layers M2 to M5 are stacked on the area shown in . These four metal wiring layers will be described with reference to the drawings.

[0063] Figures 4A to 4D is a diagram showing the layout of a semiconductor device related to the second embodiment. Figure 4A Shown by Figure 3 The wiring is performed by the metal wiring layer of the second layer M2 formed on the upper layer of the metal wiring layer of the first layer M1, and Figure 4B Wiring performed by a metal wiring layer of a third layer M3 formed in an upper layer of the metal wiring layer of the second layer M2 is shown. Figure 4C The wiring of the metal wiring layer of the fourth layer M4 formed in the upper layer of the metal wiring layer of the third layer M3 is shown, and Figure 4D Wiring of the metal wiring layer of the fifth layer M5 formed in an upper layer of the metal wiring layer of the fourth layer M4 is shown.

[0064] exist Figures 4A to 4D In FIG, the area surrounded by a solid line and marked with a cross indicates a through-hole area. In the through-hole area, an opening is provided in the insulating layer between the metal wiring on the lower layer side and the metal wiring on the upper layer side, and the metal wiring on the lower layer side and the metal wiring on the upper layer side are electrically connected to each other through the opening. That is, in Figure 4A In FIG, the metal wiring of the first layer shown by the thick dot-dash line and the metal wiring of the second layer shown by the thin dot-dash line are connected via the through-hole region, and Figure 4B In FIG, the metal wiring of the second layer shown by the thin dot-dash line and the metal wiring of the third layer shown by the thick dot-dash line are connected via the through-hole region. Figure 4C In FIG, the metal wiring of the third layer shown by the thick double-dashed line and the metal wiring of the fourth layer shown by the thin double-dashed line are connected via the through-hole region, and Figure 4D , the metal wiring of the fourth layer indicated by the thin two-dot chain line and the metal wiring of the fifth layer indicated by the thick two-dot chain line are connected via the via region.

[0065] In the second embodiment, Figure 4A The metal wiring formed by the metal wiring layer of the second layer M2 shown in FIG. Figure 4B The metal wiring is formed by forming the metal wiring layer of the third layer M3 shown.

[0066] In the second embodiment, the wiring for realizing the function of the product-sum operation (ie, Figure 2 The data lines PBL, NBL and voltage lines CVSS shown in FIG are formed by two different metal wiring layers. Figure 4A The metal wiring formed by the second layer M2 metal wiring layer and the Figure 4C The metal wiring formed by the metal wiring layer of the fourth layer M4 shown serves as the data lines PBL and NBL and the voltage line CVSS, and extends in the same direction. As a result, the wiring for implementing the product-sum operation has a configuration in which two metal wiring lines are connected in parallel, reducing wiring resistance. <Summation Operation> As described above, the result of the product-sum operation is converted into current. Therefore, if the wiring resistance is large, the current value varies depending on the position of the product operation memory cell forming the current path, making it desirable to reduce wiring resistance as in the second embodiment.

[0067] like Figure 4D As shown, the metal wiring for providing the ground voltage Vs is formed by the fifth metal wiring layer M5. Figure 4D As shown, the metal wiring supplying the ground voltage Vs is arranged so as to partially cover the data lines PBL, NBL and the voltage line CVSS. As a result, the metal wiring supplying the ground voltage Vs serves as a noise shield for the data lines PBL, NBL and the voltage line CVSS.

[0068] According to the second embodiment, the product operation memory cell 1 can be formed in a smaller area. In addition, the resistance of the product-sum operation function can be improved with respect to variations in line resistance and the like.

[0069] (Third Embodiment) In the third embodiment, the product operation memory cell 1 is composed of a three-dimensional FET called a FinFET. Figure 5A and Figure 5B is a plan view showing the layout of a semiconductor device related to the third embodiment. Figure 5A and Figure 5B Shown in Figure 2 The product operation memory cell 1 shown is composed of a fin FET. Figure 5A , a region surrounded by a solid line indicates a gate electrode, a region surrounded by a dotted line indicates a fin, and a region surrounded by a thin double-dot chain line indicates a metal wiring formed by the metal wiring layer of the first layer M1 .

[0070] exist Figure 5AIn the figure, the area surrounded by the thin dot-dash line indicates the gate local interconnect (LIC) region for connecting the gate electrode to another region, and the area surrounded by the thick dot-dash line indicates the fin (Fin) LIC region for connecting the fin to another region. In addition, the area surrounded by the solid line and marked with a cross indicates the contact area. During the process of manufacturing FinFETs, the connection between the fin and the metal line is connected through the LIC region rather than the contact region.

[0071] In the third embodiment, similar to the second embodiment, memory cells 2 and 3 are arranged symmetrically about a virtual straight line CNT, and adjacent product-operation memory cells are mirror-imaged and inverted about virtual Y-axis straight lines Y1 and Y2. In the third embodiment, the N-type FETs N5 and N6 that constitute the switch are separated from the N-type FET N7 that constitutes the switch. That is, in the figure, the N-type FET N7 is arranged above the N-type FETs N5 and N6, and the common source region of the N-type FETs N5 and N6 and the drain region of the N-type FET N7 are connected via the LIC region.

[0072] In the product operation memory cell of the second embodiment, wiring is performed using the metal wiring layer of the first layer M1 to the metal wiring layer of the fifth layer M5, but in the third embodiment, connection is performed by metal wiring formed by the metal wiring layers of the first and second layers. Figure 5B The metal wiring formed by the second metal wiring layer is shown. Figure 5B In the figure, the area surrounded by the bold double-dotted chain line indicates the metal wiring formed by the second metal wiring layer M2. In the third embodiment, the word lines PWL and NWL, the input wiring INP_L for supplying input data INP, and the wiring for supplying ground voltage Vs are formed by the second metal wiring layer. Of course, similar to the second embodiment, the data lines NBL and PBL and the voltage line CVSS can be connected to the metal wiring formed by the upper metal wiring layer to reduce wiring resistance.

[0073] According to the third embodiment, the semiconductor device having the product operation memory cell can be implemented by FinFET.

[0074] (Fourth Embodiment) In the fourth embodiment, the data line sets PBL and NBL are shared by a plurality of product operation memory cells 1 connected to the same input wiring INP_L. That is, a plurality of product operation memory cells 1 are connected to the data line sets PBL and NBL and one input wiring INP_L, a product operation memory cell is selected from the plurality of product operation memory cells 1 by a selection signal, and the data lines PBL and NBL and the input wiring INP_L are used by the selected product operation memory cell.

[0075] Figure 6is a schematic diagram showing a configuration of a semiconductor device related to the fourth embodiment. The semiconductor device 100 includes a plurality of product operation memory cells connected to data lines PBL, NBL. In Figure 6 two product operation memory cells 1_0 and 1_1 connected to data lines PBL, NBL are illustrated. Since the configurations of the product operation memory cells 1_0 and 1_1 are the same, only the detailed configuration of the product operation memory cell 1_0 is shown. Figure 6 two product operation memory cells 1_0 and 1_1 connected to data lines PBL, NBL are illustrated. Since the configurations of the product operation memory cells 1_0 and 1_1 are the same, only the detailed configuration of the product operation memory cell 1_0 is shown.

[0076] The product operation memory cell 1_0 is similar to the product operation memory cell 1 shown in Figure 2 N-type FETs N8 and N9 are added for selection, and a column address YA0 is supplied as a selection signal to the N-type FETs N8 and N9. The source-drain path of the N-type FET N8 is connected between the N-type FET N5 and the data line PBL, and the source-drain path of the N-type FET N9 is connected between the N-type FET N6 and the data line NBL. The column address YA0 is commonly supplied to the gate electrodes of the N-type FETs N8 and N9. Thus, when the product operation memory cell 1_0 is selected by setting the column address YA0 to a high level, the N-type FETs N5, N6 are connected to the data lines PBL, NBL, and a product operation is performed. A product operation is performed between the logical value stored in the product operation memory cell 1_0 and the logical value of the input data INP, and a sum operation is performed between the result of the product operation and the logical values in the data lines PBL, NBL. At this time, the column address YA1 is set to a low level so that the column address product operation memory cell 1_1 is not selected.

[0077] When the column address product operation memory cell 1_1 is selected by the column address YA1, a product operation is performed between the logical value stored in the product operation memory cell 1_1 and the logical value of the input data INP, and a sum operation is performed between the result of the product operation and the logical values in the data lines PBL, NBL.

[0078] In the fourth embodiment, the product operation memory cells 1_0 and 1_1 are connected to different complementary data lines BB0, BT0, BB1, and BT1. Thus, even if the word lines NWL and PWL are shared by the product operation memory cells 1_0 and 1_1, the product operation memory cells 1_0 and 1_1 can be written with different ternary logical values. Of course, the complementary data lines can be shared between the product operation memory cells 1_0 and 1_1, and the word lines can be different. In the fourth embodiment, the input wiring INP_L for supplying the input data INP to the product operation memory cells 1_0 and 1_1 is shared, but of course different input wirings can be used.

[0079] exist Figure 6 In the embodiment, by providing column addresses YA0 and YA1 to the product operation memory units 1_0 and 1_1, the address space formed by the product operation memory unit 1 can be expanded. Therefore, for example, a plurality of data for performing a sum-of-products operation is pre-stored in the product operation memory units 1_0 and 1_1, and the data for performing the sum-of-products operation can be selected by the column address.

[0080] <Modified example> In the modified example, column addresses YA0 and YA1 are simultaneously set to a high level. This makes it possible to perform a summation operation among the product operation result in the product operation memory unit 1_0, the product operation result in the product operation memory unit 1_1, and the data in the data lines PBL and NBL. Assuming that a combined product operation memory unit is configured by combining the product operation memory units 1_0 and 1_1, a combined product operation memory unit can store five values ​​exceeding ternary values, such as "+2", "+1", "-1", "-1", and "+2", instead of the ternary values ​​"+1", "-0", and "-1", and a product operation can be performed between the logical values ​​of the five values ​​and the input data INP. Although a combination of two product operation memory units has been shown, more product operation memory unit combinations can be used to store more multi-valued data in the product operation memory unit.

[0081] Figure 7A and Figure 7B is a plan view showing the layout of a semiconductor device related to the fourth embodiment. Figure 7A and Figure 7B Shows when Figure 6 The layout of the product operation memory cell 1_0 shown in FIG5 is formed by FinFET in the same manner as FIG5. Here, Figure 7A Similar to Figure 5A , and the difference is that a wiring for providing a column address YA and N-type FETs N8 and N9 for selection are added. Figure 7B In, similar to Figure 5B , the metal wiring formed by the metal wiring layer of the second layer M2 is shown as an area surrounded by a thick double-dot chain line.

[0082] Figures 8A to 8D : is a cross-sectional view showing a cross section of a semiconductor device related to the fourth embodiment. That is, Figure 8A Shown Figure 7A and Figure 7B The AA′ section in Figure 8B Shown Figure 7A and Figure 7B The BB′ section in Figure 8C Shown Figure 7A and Figure 7B The CC′ section in Figure 8D Shown Figure 7A and Figure 7B DD′ section in. Figures 8A to 8C As shown, the metal wiring formed by the metal wiring layer of the second layer M2 is arranged so as to overlap and electrically connect with the metal wiring formed by the metal wiring layer of the first layer M1. As a result, the resistance of the metal wiring is reduced.

[0083] The second and higher metal wiring layers can be Figures 4B to 4D The same method as shown above suppresses the increase in resistivity of metal wiring due to miniaturization. In this case as well, for example, Figure 4C As shown, the data lines NBL, PBL and the voltage line CVSS are formed by the third layer or higher of the metal wiring layer. Figures 8A to 8D In FIG, the insulating film between intermediate layers (eg, between the metal wiring layers M1 and M2) is omitted.

[0084] According to the fourth embodiment, the memory capacity can be increased by expanding the address space of the memory composed of the product operation memory cell. The data stored in the product operation memory cell can be further multivalued, and the accuracy of learning and inference can be improved. In addition, the user can select a larger memory capacity or improve accuracy by manipulating the column address, which increases the degree of freedom.

[0085] (Fifth Embodiment) Product Operation Memory Unit Stores Data to be Multiplied by Input Data INP In the fifth embodiment, a product operation memory unit capable of efficiently performing multi-valued product on data is provided.

[0086] The product operation memory cell described in the fourth embodiment allows for increased memory capacity and flexible multi-value changes to data. However, when only multi-leveling is performed, the number of FETs constituting the product operation memory cell increases. For example, in the fourth embodiment, when 15-value data of "+7" to "-7" are stored in one combined product operation memory cell, as shown in FIG. Figure 6 As shown, six FETs are required to construct each of memory cells 2 and 3. To implement the selection and product-sum functions, FETs for switches and FETs for selection are also required. Therefore, 12 FETs for the memory cells, as well as FETs for selection and product-sum functions, are required to construct a single product-operating memory cell. To store 15 values ​​of data, seven product-operating memory cells constitute a combined product-operating memory cell. Therefore, a combined product-operating memory cell requires (2 memory cells (12 FETs) + FETs for selection and product-sum functions) × 7 FETs.

[0087] Figure 91 is a circuit diagram showing the configuration of a product operation memory unit related to the fifth embodiment. The product operation memory unit 20 includes four memory cells 21_0 to 21_3 and twelve N-type FETs N10_1 to N10_3, N11_1 to N11_3, N12_1 to N12_3, and N13_1 to N13_3. The memory cells 21_0 to 21_3 have, for example, Figure 2 The memory cells 21_0 to 21_3 are configured in the same manner as shown. Therefore, each of the memory cells 21_0 to 21_3 is composed of six FETs.

[0088] The gate electrodes of the N-type FETs (second switches) N10_1 to N10_3 are connected to one output of the memory cell 21_0, and the gate electrodes of the N-type FETs (second switches) N11_1 to N11_3 are connected to the other output of the memory cell 21_0. One output of the memory cell 21_1 corresponds to the output of the memory cell 21_0 connected to the gate electrodes of the N-type FETs (second switches) N11_1 to N11_3. Figure 2 The node between the N-type FET N1 and the P-type FET P1 is shown, and the other output corresponds to Figure 2 Node n2 is shown in .

[0089] The source-drain path of the N-type FET N10_1 and the source-drain path of the N-type FET N11_1 are connected in series between the data lines PBL and NBL. The source-drain path of the N-type FET (first switch) N12_1 and the source-drain path of the N-type FET N13_1 are connected in series between the voltage line CVSS and the node connecting the N-type FETs N10_1 and N11_1. Input data INP is supplied to the gate electrode of the N-type FET (third switch) N13_1, and the gate electrode of the N-type FET N12_1 is connected to the node n2 of the memory cell 21_1 (see FIG. 2 ). Figure 2 ). The N-type FETs N10-2, N11-2, N12-2, N13-2 and the memory cell 21-2 are also connected in the same manner as the above-mentioned N-type FETs N10-1, N11-1, N12-1, N13-1 and the memory cell 21-1. The N-type FETs N10_3, N11_3, N12_3, N13_3 and the memory cell 21_3 are also connected in the same manner as the above-mentioned N-type FETs N10_1, N11_1, N12_1, N13_1 and the memory cell 21_1.

[0090] The memory cell (second memory cell) 21_0 stores a sign bit indicating the sign of the multi-valued data stored in the product operation memory cell 20. The memory cells (first memory cells) 21_1 to 21_3 store bits indicating the absolute value of the multi-valued data to be stored. In the fifth embodiment, the multi-valued data is represented by bits weighted to "1", "2", and "4", and the bit representing the weight "1" is stored in the memory cell 21_1, the bit representing the weight "2" is stored in the memory cell 21_2, and the bit representing the weight "4" is stored in the memory cell 21_3.

[0091] N-type FETs N10_1 to N10_3, N11_1 to N11_3, N12_1 to N12_3, and N13_1 to N13_3 are configured to flow currents corresponding to the weights stored in the corresponding memory cells. For example, when the sizes of the N-type FETs N10_1, N11_1, N12_1, and N13_1 corresponding to the memory cell 21_1 are set to a reference size, the sizes of the N-type FETs N10_2, N11_2, N12_2, and N13_2 corresponding to the memory cell 21_2 are set to twice the reference size. The sizes of the N-type FETs N10_3, N11_3, N12_3, and N13_3 corresponding to the memory cell 21_3 are set to four times the reference size.

[0092] For example, when input data INP is a high-level logic value "1," a low-level logic value "0" is output from memory cells 21_2 and 21_3, and a high-level logic value "1" is output from memory cell 21_1, N-type FETs N12_1 and N13_1 turn on, and a reference current representing "1" flows through these N-type FETs. At this time, the sign bit stored in memory cell 21_0 turns N-type FETs N10_1 to N10_3 or N11_1 to N11_3 on. As a result, a reference current flows from data line PBL or NBL to voltage line CVSS.

[0093] Similarly, for example, when input data INP is a high-level logic value "1," a high-level logic value "1" is output from memory cells 21_2 and 21_3, and a low-level logic value "0" is output from memory cell 21_1, N-type FETs N12_2, N13_2, N12_3, and N13_3 turn on. At this time, due to the sign bit, N-type FETs N10_1 to N10_3 or N11_1 to N11_3 turn on. As a result, a current six times the reference current flows from data line PBL or NBL to voltage line CVSS.

[0094] In this way, a product operation between the input data INP and the data stored in the product operation memory cell 20 is performed, and a current corresponding to the result of the product operation flows from the data line PBL or NBL to the voltage line CVSS, and a summation calculation can be performed.

[0095] Figure 9 The illustrated product operation memory cell 20 includes 4 memory cells and 12 N-type FETs. Since each memory cell includes six FETs, the number of FETs required for the product operation memory cell 20 is 4 x 6 + 12 = 36. Even if only the number of FETs constituting the memory cell is counted, the number of FETs required in the fourth embodiment is 2 x 7 x 6 = 84. Even if only the number of FETs constituting the memory cell is considered, 14 memory cells can be reduced to 4.

[0096] Although omitted in Figure 9 , as described with reference to Figure 2 , the memory cells 21_0 to 21_3 are connected to the word line and the complementary data line. A memory cell is selected from the memory cells 21_0 to 21_3 by the word line and the complementary data line, and a sign bit or an absolute value bit is written to the selected memory cell. In Figure 9 the example, the number of absolute value bits is 3 bits, and the number of sign bits is 1 bit. Therefore, 3 bits are decoded to represent "0" to "7", and 15 values of "+7" to "0" to "-7" can be represented by assigning positive and negative signs by the sign bit.

[0097] According to the fifth embodiment, since more values of data can be stored in the product operation memory cell constituted by a small number of FETs, the area of the product operation memory cell can be reduced.

[0098] (Sixth Embodiment)

[0099] Figure 10 is a circuit diagram illustrating a configuration of a product operation memory cell according to the sixth embodiment. In the sixth embodiment, a product operation memory cell for performing a summation operation by voltage is provided. In Figure 10 , reference numeral 30 denotes a product operation memory cell. The product operation memory cell 30 includes two memory cells 2 and 3, NAND circuits 31 and 32 corresponding to the memory cells 2 and 3, switches 34 to 37 controlled based on an enable signal EN, and capacitor elements 38 and 39 corresponding to the memory cells 2 and 3.

[0100] As Figure 10As shown, the memory cell 2 is used to store the logical value "+1" in the product operation memory cell 30, and the memory cell 3 is used to store the logical value "-1" in the product operation memory cell 30. The output of the memory cell 2 and the input data INP are provided to the NAND circuit 31, and the NAND circuit 31 performs a NAND operation and outputs its result. Similarly, the output of the memory cell 3 and the input data INP are provided to the NAND circuit 32, and the NAND circuit 32 performs a NAND operation and outputs its result.

[0101] The output of NAND circuit 31 is supplied to one electrode of capacitor 38 via switch 35, and the output of NAND circuit 32 is supplied to one electrode of capacitor 39 via switch 37. The other electrodes of capacitors 38 and 39 are supplied with ground voltage Vs. One electrode of capacitor 38 is connected to data line PBL via switch 34, and one electrode of capacitor 39 is connected to data line NBL via switch 36.

[0102] The switches 35 and 37 are controlled to be in the on state or the off state by the enable signal EN. The logic inversion enable signal / EN is provided to the switches 34 and 36. Figure 10 In the embodiment of the present invention, the inverter circuit 33 logically inverts the enable signal EN and outputs the inverted enable signal / EN. The inverter circuit 33 may be provided in the product operation memory unit 30, or the inverter circuit 33 may be provided in common in a plurality of product operation memory unit circuits 30.

[0103] exist Figure 10 In the illustrated product operation memory unit 30, when the enable signal EN is at a low-level logic value of "0," the results of the NAND operation performed in the NAND circuits 31 and 32 are stored in the corresponding capacitor elements 38 and 39. When the enable signal EN is at a high-level logic value of "1," a sum operation is performed on the stored results and the data on the data lines PBL and NBL. This will be described in detail below.

[0104] When the enable signal EN is at a low level, switches 35 and 37 are supplied with the enable signal / EN at a high level, causing switches 35 and 37 to turn on. As a result, the outputs of NAND circuits 31 and 32 are electrically connected to one of the electrodes of capacitors 38 and 39. At this time, switches 34 and 36 are turned off by the low enable signal EN, and one of the electrodes of capacitors 38 and 39 is electrically isolated from data lines PBL and NBL. As a result, capacitor 38 is charged based on the result of the NAND operation between the logic value stored in the corresponding memory cell 2 and the logic value of input data INP. Similarly, capacitor 39 is charged based on the result of the NAND operation between the logic value stored in the corresponding memory cell 3 and the logic value of input data INP.

[0105] Next, when the enable signal EN changes to a high level, switches 35 and 37 are turned off, and switches 34 and 36 are turned on, so that the data lines PBL and NBL are electrically connected to one of the electrodes of the capacitor elements 38 and 39. When the capacitor element 38 is connected to the data line PBL, charge is dispersed between the parasitic capacitance of the data line PBL and the capacitor element 38, and the voltage of the data line PBL is determined. Similarly, the voltage of the data line NBL is determined by the charge dispersion performed between the capacitor element 39 and the parasitic capacitance of the data line NBL.

[0106] Next, cases where the results of the product operation in the product operation memory unit 30 are "0", "+1", and "-1" will be described.

[0107] When input data INP is "0" or the data stored in both memory cells 2 and 3 is "0," the result of the multiplication operation becomes "0." At this time, since the outputs of NAND circuits 31 and 32 are at a high level, such as power supply voltage Vd, power supply voltage Vd charges capacitors 38 and 39 via switches 35 and 37. For example, by issuing a product-sum instruction in the semiconductor device, enable signal EN changes from a low level to a high level. As a result, capacitors 38 and 39 are connected to data lines PBL and NBL.

[0108] On the other hand, when the result of the multiplication operation is "+1", the capacitor element 38 corresponding to the memory cell 2 is discharged to a low level, such as the ground voltage Vs. When the result of the multiplication operation is "-1", the capacitor element 39 corresponding to the memory cell 3 is discharged to a low level. In response to the enable signal EN becoming high, the capacitor elements 38 and 39 are connected to the data lines PBL and NB, respectively.

[0109] Multiple product operation memory cells are connected to data lines PBL and NBL. Therefore, the difference between the number of capacitive elements charged to the power supply voltage Vd connected to the data lines PBL and NBL and the number of capacitive elements discharged to the ground voltage Vs becomes a product-sum result. Specifically, the difference between the voltages of the data lines PBL and NBL becomes the product-sum result.

[0110] In the sixth embodiment, since the summation operation is performed using the capacitance element, the influence of the variation of the current of the FET or the like can be reduced.

[0111] (Seventh embodiment)

[0112] Figure 11 : is a diagram showing the configuration of a semiconductor device according to a seventh embodiment. Examples of semiconductor devices include a microprocessor that performs a large number of product-sum operations. Although a microcomputer includes a plurality of circuit blocks, Figure 11 Only the circuit blocks necessary for explanation are shown. Figure 11 In the figure, reference numeral 40 denotes a memory macro (hereinafter referred to as memory macro) having a product-sum operation function formed in the semiconductor device.

[0113] The memory macro 40 includes: a memory array 41 in which the product operation memory cells described in the first to sixth embodiments are arranged in a matrix; an A / D converter 42; an INP latch (input data holding circuit) and a driver 48 for latching and driving input data; and a MAC controller 43 for controlling the A / D converter 42 and the INP latch and driver 48. The memory macro 40 includes a row decoder and word driver 44, a data write / sense unit 45, an input / output latch unit 46, and a read / write control unit 47. The read / write control unit 47 mainly controls the row decoder and word driver 44, the data write / sense unit 45, and the input / output latch circuit unit 46, and also performs overall control of the memory macro 40.

[0114] The memory array 41 includes a plurality of memory cell arrays 41_0 to 41_n. The A / D converter 42 includes a plurality of A / D conversion circuits 42_0 to 42_n. Similarly, the data write / sense unit 45 is also configured by a plurality of data write / sense unit circuits 45_0 to 45_n, and the input / output latch circuit portion 46 is also configured by a plurality of input / output latch unit circuits 46_0 to 46_n.

[0115] The memory cell columns 41_0 to 41_n, the A / D conversion circuits 42_0 to 42_n, the data write / sense unit circuits 45_0 to 45_n, and the input / output latch unit circuits 46_0 to 46_n correspond one to one. For example, the memory cell column 41_0, the A / D conversion circuit 42_0, the data write / sense unit circuit 45_0, and the input / output latch unit circuit 46_0 correspond one to one.

[0116] The memory cell column 41_0 includes, for example, complementary data lines (second data lines) BB and BT, data lines (first data lines) PBL and NBL, and a plurality of product operation memory cells 1 connected to the complementary data lines BB and BT and the data lines PBL and NBL. Figure 11 The A / D conversion circuit 42_0 corresponding to the memory cell column 41_0 converts the difference in current amount between the data lines PBL, NBL provided in the corresponding memory cell column 41_0 into a digital signal and outputs the result of the product-sum operation as MQ output data MQ[0].

[0117] The input data to be stored in the product operation memory cell 1 arranged in the corresponding memory cell column 41_0 is supplied as input data D[0] to the input / output latch unit circuit 46_0. The input / output latch unit circuit 46_0 latches the supplied input data D[0], supplies the latched input data D[0] to the complementary data lines BB and BT provided in the corresponding memory cell column 41_0 via the corresponding data write / sense unit circuit 45_0, and writes the input data D[0] into the product operation memory cell 1. Although not particularly limited, the input / output latch circuit 46_0 latches the data written in the product operation memory cell 1 via the data write / sense unit circuit 45_0 using the complementary data lines BB and BT provided in the memory cell column 41_0, and outputs the latched data as output data Q[0].

[0118] Although the memory cell column 41_0, the A / D conversion circuit 42_0, the data write / sensing unit circuit 45_0 and the corresponding input / output latch unit circuit 46_0 have been described as an example, the remaining memory cell columns 41_1 to 41_n, the A / D conversion circuits 42_1 to 42_n, the data write / sensing unit circuits 45_1 to 45_n and the corresponding input / output latch unit circuits 46_1 to 46_n are also similar.

[0119] exist Figure 11In FIG. 4 , BWM[0] to BWM[n] are bit write enable signals for shielding the writing of input data in units of input / output latch circuits. For example, when input data D[0] to D[n] are supplied to the input / output latch circuit unit 46 in parallel, bit write enable signal BWM[0] is disabled. As a result, the input / output latch circuit 46_0 operates so as not to write the supplied input data D[0].

[0120] exist Figure 11 MEM[0] to MEM[n] are product sum operation mask signals for masking product sum operations in units of A / D conversion circuits. For example, by disabling the product sum operation mask signal MEM[0], the product sum operation is set not to be performed in the memory cell column 41_0.

[0121] In the memory array 41, the Figure 2 For example, multiple word lines NWL and PWL are shown. Figure 11 The row decoder and word driver 44 are connected to a plurality of word lines and, when writing input data D[0] to D[n] to a plurality of product operation memory cells and when reading input data, select a word line from the plurality of word lines and provide a high level to the selected word line. The row decoder and word driver 44 selects two word lines NWL and PWL ( Figure 2 ) as a set. The product operation memory connected to the selected word line is written and read with input data.

[0122] The memory cell array 41 is provided with a memory cell array for providing input data INP ( Figure 2 ) multiple input wiring. Input wiring in Figure 11 The INP latch and driver 48 are connected to a plurality of input wirings. The input data ID[0] to ID[m] to be multiplied are provided to the INP latch and driver 48. The INP latch and driver 48 latches the input data ID[0] to ID[m] provided thereto and provides the latched input data ID[0] to ID[m] to the input wirings as input data INP. As a result, the input data INP corresponding to the input data ID[0] to ID[m] is provided to a plurality of product operation memory cells arranged in each of the memory cell columns 41_0 to 41_n. In each product operation memory cell, a product operation is performed between the stored data and the input data INP, a sum operation of the product operation results is performed for each memory cell column, and the result is output as MQ output data MQ[0] to MQ[n].

[0123] According to the seventh embodiment, since the A / D conversion circuit is provided for each memory cell row, a plurality of product-sum operations can be performed simultaneously and the speed of the product-sum operations can be increased.

[0124] (Eighth embodiment)

[0125] In the eighth embodiment, a semiconductor device is provided in which the input data INP is multi-valued. For example, in the fifth embodiment, a configuration in which the number (data) stored in the product operation memory unit is multi-valued has been described. In contrast, in the eighth embodiment, a configuration in which the multiplicand of the number stored in the product operation memory unit is multi-valued will be described.

[0126] Figure 12A and Figure 12B 1 is a diagram for explaining a semiconductor device according to an eighth embodiment. Figure 12A is a block diagram showing the configuration of a semiconductor device 50 according to a seventh embodiment, and Figure 12B Is used to explain Figure 12A Graphs illustrating the operation of the semiconductor device 50 are shown.

[0127] because Figure 12A Similar to Figure 11 , mainly explaining the differences. Figure 11 In contrast, the INP latch and driver 48 have been changed in FIG12. That is, Figure 11 The INP latch and driver 48 shown in FIG. 4 are changed to an INP latch circuit 48_1 , a D / A conversion circuit 48_2 , and an INP driver circuit 48_3 .

[0128] The input data ID[0] to ID[m] supplied to the semiconductor device 50 are multi-value digital signals. The INP latch circuit 48_1 latches the input data ID[0] to ID[m] and supplies the latched input data to the D / A conversion circuit 48_2. The D / A conversion circuit 48_2 converts each of the supplied input data ID[0] to ID[m] into a corresponding analog value and outputs the analog value to the INP driver circuit 48_3. The INP driver circuit 48_3 outputs the analog value corresponding to the supplied input data ID[0] to ID[m] as the input data INP( Figure 2 ) is provided to the input wiring arranged in the memory cell array 41.

[0129] The product operation memory unit supplied with the analog value input data INP via the input wiring performs a product operation between the stored data and the supplied analog value input data INP. Figure 2In the illustrated product operation memory cell 1, when the stored data is a logic value of "+1" or "-1," a current corresponding to a supplied analog value flows from the data line PBL or NBL to the voltage line CVSS via the N-type FET N5 or N6. In the product operation memory cell 1, a current-type product operation is performed, and a current-type summation operation is performed on the data line PBL or NBL.

[0130] Figure 12B 1 is a diagram showing the relationship between the input data supplied to the product operation memory unit and the current flowing from the data lines PBL and NBL to the product operation memory unit. Figure 2 As shown in FIG, input data is supplied to the gate electrode of the N-type FET N7, and a current corresponding to the drain current flowing through the N-type FET N7 flows from the data line PBL to the voltage line CVSS. Since the drain current flowing through the FET N7 is nonlinear, as shown in FIG. Figure 12B As shown, the drain current is nonlinear with respect to voltage.

[0131] In the eighth embodiment, the analog values ​​supplied to the input wiring are adjusted so that the current flowing from the data lines PBL and NBL to the product operation memory cell is linear with respect to the voltage values ​​represented by the input data ID[0] to ID[m]. For example, this adjustment can be performed by adjusting the conversion characteristics of the D / A converter circuit 48_2 or by adjusting the analog value output from the D / A converter circuit 48_2 in the INP driver circuit 48_3. In this way, the multiplicand in the product operation can also be multivalued.

[0132] According to the eighth embodiment, since the multiplicand in the product operation can also be multi-valued, the accuracy of learning and inference can be further improved.

[0133] (Ninth embodiment)

[0134] In the ninth embodiment, an example of the memory cell column described in the eighth embodiment and an A / D conversion circuit corresponding to the memory cell column will be described.

[0135] Figure 13 and 14A to 14D is a diagram showing the configuration of a semiconductor device according to a ninth embodiment. Figure 13 A memory cell column and its related parts are shown. Figure 13 The picture shows Figure 8A Memory cell column 41_0 and its related parts shown in FIG.

[0136] The memory cell column 41_0 includes data lines PBL, NBL, a plurality of product operation memory cells Tbc connected to each of the data lines PBL, NBL, and two types of reference cells R1 and R0.5. Figure 13 In the example of , as the reference cell R1, 128 reference cells R1(0) to R1(127) and one reference cell R0.5 are provided in the memory cell column 41_0. Figure 13 , AL[0] to AL

[147] represent input data supplied to input wirings arranged to intersect the memory cell column 41_0.

[0137] As the product operation memory unit Tbc, use Figure 14A The product operation memory unit shown. Figure 14A The configuration of the product operation memory unit shown is similar to Figure 6 The same as shown, so their explanation is omitted.

[0138] In the memory cell column 41_0, four product operation memory cells are connected to the same input wiring. Figure 14A Reference numeral YA in the figure shows a column address for selecting one product operation memory cell Tbc from four product operation memory cells Tbc connected to the same input wiring. To select one product operation memory cell from the four product operation memory cells Tbc, the column address YA is composed of four bits YA[0:3]. In the product operation memory cell selected by the column address YA, the input data AL[0] to AL

[147] provided via the input wiring becomes the input data INP to be used for performing a product operation using the data stored in the selected product operation memory cell.

[0139] Figure 14B The configuration of reference cell R1 is shown. Similar to product operation memory cell Tbc, reference cell R1 includes N-type FETs N14 to N17, with source-drain paths connected in series between data lines PBL and NBL, and N-type FET N18 connected between voltage line CVSS and the node connecting N-type FETs N15 and N16. Reference cell R1 has a structure similar to that of product operation memory cell Tbc. The difference is that power supply voltage Vd is supplied to the gate electrodes of N-type FETs N14 and N17 instead of column address YA, select signals RN and RP are supplied instead of the outputs of memory cells 2 and 3, and control signal CD is supplied instead of input data INP. Reference cell R1 has a structure similar to that of product operation memory cell Tbc, so that reference cell R1 has a driving force equal to the driving force (=1) of product operation memory cell Tbc with respect to data lines PBL and NBL.

[0140] Figure 14CFIG2 shows the configuration of reference cell R0.5. Reference cell R0.5 has a configuration similar to reference cell R1. The difference is that in reference cell R0.5, N-type FETs N18_1 to N18_3 are connected between the node connecting N-type FETs N15 and N16 and voltage line CVSS. As a result, the driving force of reference cell R0.5 with respect to data lines PBL and NBL is half (0.5) the driving force of reference cell R1, i.e., product operation memory cell Tbc.

[0141] return Figure 13 , a description will be given. Figure 13 6, reference numeral 60 denotes a control logic unit, reference numeral 61 denotes a comparator circuit, reference numeral 62 denotes a Schmitt trigger NAND circuit, and reference numeral N19 denotes an N-type FET. Data lines PBL and NBL are connected to comparator circuit 61 and Schmitt trigger NAND circuit 62. Voltage line CVSS in product operation memory cell Tbc and voltage line CVSS in reference cells R1 and R0.5 are connected to ground voltage Vs via N-type FET N19.

[0142] The comparison result OUT from the comparator circuit 61 and the control signal PS from the Schmitt trigger NAND circuit 62 are provided to the control logic unit 60. The control logic unit 60 outputs the column address YA[0:3], a control signal for controlling the comparator circuit 61, a product-sum operation enable signal MACEBF for controlling the N-type FET N19, select signals RN and RP, and a control signal CD. As will be described later, the control logic unit 60 and the comparator circuit 61 provide an A / D conversion function. In other words, the control logic unit 60 and the comparator circuit 61 can be considered to constitute an A / D conversion circuit. The result obtained by this A / D conversion circuit becomes the result of the product-sum operation and is output as MQ output data MQ[0].

[0143] like Figure 2 As shown in FIG. 1 , product operation memory cell Tbc stores ternary value data. That is, product operation memory cell Tbc stores any logical value of "+1," "0," or "-1." Binary data is provided as input data INP. That is, "0" or "1" is provided to product operation memory cell Tbc as input data INP.

[0144] In the ninth embodiment, as shown in equation (1), the product-sum operation is calculated by separating the product-sum value on the "+1" side from the product-sum value on the "-1" side. Here, MQ represents MQ output data as a result of the product-sum operation, INP(i) represents the logical value of the i-th input data INP, Tbc(i, YA) represents the logical value stored in the i-th product operation memory cell and its column address is YA. In addition, Tbcp(i) represents the i-th product operation memory cell storing the logical value "+1", and Tbcn(i) represents the i-th product operation memory cell storing the logical value "-1".

[0145] [Equation 1]

[0146] MQ=∑{INP(i)×Tbc(i, YA)}=∑{INP(i)×Tbcp(i)}-∑{INP(i)×Tbcn(i)}...Equation (1)

[0147] Here, Tbcp(i) is represented by equation (2), and Tbcn is represented by equation (3).

[0148] [Equation 2]

[0149]

[0150] [Equation 3]

[0151]

[0152] <A / D转换>Next, the operation of A / D conversion will be described using an example. In the ninth embodiment, A / D conversion is performed in eight steps. Figure 15A and Figure 15B : is a timing chart for explaining A / D conversion according to the ninth embodiment. Figure 15A and Figure 15B In FIG, the horizontal axis represents time. In addition, the first to the eighth represent the above eight steps.

[0153] In the product-sum operation, assume that the product-sum value on the "+1" side is "46" and the product-sum value on the "-1" side is "17." The current in the data line PBL indicates the product-sum value "46," and the current in the data line NBL indicates the product-sum value "17." In this case, the difference in the product-sum value is "29." MQ output data MQ[0] corresponding to the difference is output from the control logic unit 60.

[0154] exist Figure 15A ​In the first step (1st), comparator circuit 61 compares the currents of data lines PBL and NBL. Since "46" > "17", control logic unit 60 outputs a logic value of "0" indicating a "+" sign as MQ output data. Since the current of data line PBL is higher, control logic unit 60 sets select signal RP to a high level and select signal RN to a low level. Furthermore, control logic unit 60 connects reference cell R0.5 to data line PBL and a specified number of reference cells to data line NBL. The specified number here is "64", which is half the number of 128 reference cells R1.

[0155] In the second step (2nd), control logic unit 60 turns on N-type FETs N18_1 to N18_3 connected to data line PBL in reference cell R0.5 via control signal CD. Furthermore, control logic unit 60 turns on N-type FETs N18 of 64 reference cells R1 connected to data line NBL in response to control signal CD. The value on data line PBL is 46 + 0.5 = 46.5, and the value on data line NBL is 17 + 64 = 81. Comparator circuit 61 compares "46.5" with "81." As a result of the comparison, since the value on data line NBL is larger, control logic unit 60 outputs a logic value of "0" as MQ output data MQ[0].

[0156] In the third step 3rd, the control logic unit 60 specifies "32," which is half of "64," as the designated number, and turns on the N-type FETs N18 and N18_1 to N18_3 via the control signal CD. Therefore, the value of the data line PBL is "46.5" as described above, but the value of the data line NBL is 17 + 32 = 49. Since the comparison of the comparator circuit 61 determines that the value of the data line NBL is greater, the control logic unit 60 outputs the logical value "0" as the MQ output data MQ[0].

[0157] Similarly, in the fourth step (4th), similar to the third step (3rd), the control logic unit 60 specifies the number of reference cells R1 and outputs the control signal CD. However, in the fourth step (4th), half the number (16) is specified as the number of reference cells R1. Therefore, the comparator circuit 61 compares the value "46.5" on the data line PBL with the value (17 + 16 = 33) on the data line NBL. In the fourth step (4th), since the value of the data line PBL is greater than the value of the data line NBL, the control logic unit 60 outputs a logic value of "1" as the MQ output data MQ[0].

[0158] In the fifth step 5th, the control logic unit 60 specifies "24" as the number of reference cells R1. As a result, the value of the data line NBL becomes 17+24=41, and the comparison of the comparator circuit 61 determines that the value of the data line PBL is greater than the value of the data line NBL, so that the control logic circuit 60 outputs a logic value "1" as the MQ output data MQ[0].

[0159] Thereafter, from the sixth step 6th to the eighth step 8th, while the number of designated reference cells R1 is changed to "28," "30," and "29," the data line PBL and the data line NBL are compared. By comparison, when the value of the data line PBL is greater than the value of the data line NBL, the control logic unit 60 outputs a logic value "1" as the MQ output data MQ[0], and when the value of the data line NBL is greater than the value of the data line PBL, the control logic unit 60 outputs a logic value "0" as the MQ output data MQ[0].

[0160] The result of the product-sum operation is converted into a serial 8-bit. The first bit is the sign bit, and after the sign bit, the serial bits are output from the most significant bit to the least significant bit.

[0161] Next, refer to Figure 15B , an exemplary case where the sign bit is "-" will be described. Here, a case will be described in which the product-sum value on the "+1" side is "17" and the product-sum value on the "-1" side is "46", that is, a case in which the value in the data line PBL is "17" and the value in the data line NBL is "46". Since "17" < "46", the control logic unit 60 outputs a logic value "1" representing the sign "-" as the MQ output data MQ[0] in the first step 1st. Since the value in the data line NBL is large, the selection signal RP is set to a low level and the selection signal RN is set to a high level. In addition, the reference cell R0.5 is connected to the data line NBL, and a specified number of reference cells R1 are connected to the data line PBL.

[0162] The control logic unit 60 performs the following steps after the second step 2nd. Figure 15A The control logic unit 60 performs a similar operation as in the example above, but since the sign is "-", the control logic unit 60 outputs an inverted logic value as the MQ output data MQ[0]. That is, when the value of the data line PBL is greater than the value of the data line NBL, the control logic unit 60 outputs a logic value "0" as the MQ output data MQ[0], and when the value of the data line NBL is greater than the value of the data line PBL, the control logic unit 60 outputs a logic value "1" as the MQ output data MQ[0]. As a result, Figure 15B As shown, the serially converted digital signal is output as MQ output data MQ[0].

[0163] As described above, in the ninth embodiment, the difference between the data lines PBL, NBL is searched by using the binary division method and the result is converted into a serial digital signal and output.

[0164] In the ninth embodiment, when Figure 15A and Figure 15B When the data length of the MQ output data MQ[0] shown in the figure reaches the data length desired by the user, the processing can be terminated. This can reduce the wasted power and time required for A / D conversion.

[0165] In the ninth embodiment, in order to further reduce power consumption, a Schmitt trigger type NAND circuit 62 is provided. The Schmitt trigger type NAND circuit 62 has the following features: Figure 14D That is, the Schmitt trigger type NAND circuit 62 is composed of P-type FETs P3 to P5 and N-type FETs N18 to N23.

[0166] The Schmitt trigger NAND circuit 62 functions as a circuit for detecting when the "AND" on the "+1" side is "0" and the "AND" on the "-1" side is "0." In machine learning and inference, due to product-sum operations, the product-sum value is often "0" on both the "+1" and "-1" sides. In the configuration according to the ninth embodiment, when the product-sum value is "0," there is no path for drawing charge from the data lines PBL and NBL toward the ground voltage Vs. Therefore, the voltage of the data lines PBL and NBL remains at the power supply voltage Vd. By using the Schmitt trigger NAND circuit 62, whose logic threshold increases toward the power supply voltage Vd, it is possible to detect when both data lines PBL and NBL are at the power supply voltage Vd level. The detection result is communicated to the control logic unit 60 via the control signal PS. The Schmitt trigger NAND circuit 62 is controlled by the product-sum operation enable signal MACEBF in conjunction with the N-type FET N19. That is, when the N-type FET N19 turns to the on state, the Schmitt trigger type NAND circuit 62 is controlled to be operable.

[0167] When the control signal PS indicates that both the data lines PBL and NBL are at the power supply voltage Vd level, the control logic unit 60 outputs a logic value "0" as the MQ output data MQ[0] without performing the above-described A / D conversion operation.

[0168] In the ninth embodiment, for example, 148 input data AL[0] to AL

[147] are supplied to the input wirings substantially simultaneously. In the memory cell column 41_0, 148 multiplication operations are performed substantially simultaneously, and sum operations of the results of the 148 multiplication operations are also performed substantially simultaneously.

[0169] According to the ninth embodiment, since the user can freely change the data length of the MQ output data MQ[0], the degree of freedom of adjustment related to the trade-off between power consumption and performance can be increased. In addition, when AND becomes "0", the logical value "0" is output as the MQ output data without performing the A / D conversion operation, making it possible to reduce power consumption.

[0170] (Tenth embodiment) Figure 16A and Figure 16B as well as Figure 17A and Figure 17B is a diagram showing the configuration of a semiconductor device according to a tenth embodiment. Figure 15A Similar to Figure 13 , and thus mainly explains the differences. Figure 16A In FIG, the source-drain paths of the P-type FETs P6 and P7 are connected between the data lines PBL and NBL and the power supply voltage Vd, and constitute a bias circuit for biasing the data lines PBL and NBL. Figure 16A middle, Figure 13 The comparator circuit 61 shown in FIG. 6 is shown as a buffer circuit 61 .

[0171] like Figure 16A and Figure 16B As shown, for the memory cells, 148 rows×4 columns=592 product operation memory cells Tbc, 128 reference cells R1, and 1 reference cell R0.5 are connected to the data lines PBL and NBL.

[0172] Figure 17A and Figure 17B It is a diagram for explaining the tenth embodiment. Figure 17A The configuration of the comparator is shown in FIG. The comparator includes an N-type FET pair, a load, and a current source. The N-type FET pair forms a differential FET, and the comparator amplifies and outputs the potential difference at the gate electrode of the differential FET. In the tenth embodiment, the FETs constituting the switches in the product operation memory cell Tbc, the reference cell R1, and R0.5 are used as the differential FETs of the comparator. To explain the product operation memory cell Tbc as an example, as shown in FIG. Figure 17A As shown by the dotted lines in FIG. 1 , the N-type FETs N6, N7, and N9 constituting the switch function as one FET in the differential FET pair, and the N-type FETs N5, N7, and N8 constituting the switch function as the other FET in the differential FET pair. The P-type FETs P6 and P7 connected to the data lines PBL and NBL can be considered as a current supply unit for supplying current to the differential FETs, and the N-type FET N19 can be considered as a switching circuit for the differential FETs. In the tenth embodiment, the circuit including the P-type FETs P6, P7 and the N-type FET N19 is referred to as a source switch S-SW.

[0173] Although some of the FETs constituting the product operation memory cell are used as examples of the FETs constituting the comparator, the same applies to the reference cells R1 and R0.5. In the reference cell R1, the N-type FETs N16 to N18 serve as one differential FET, and the N-type FETs N14, N15, and N18 serve as another differential FET. In the reference cell R0.5, the N-type FETs N16, N17, and N18_1 to N18_3 serve as one differential FET, and the N-type FETs N14, N15, and N18_1 to N18_3 serve as another differential FET.

[0174] As a result, when the product-sum value on the "+1" side or the "-1" side is small, the comparator can amplify the potential difference between the data lines PBL and NBL and can expand the operation margin. Figure 17B As shown, by arranging the source switches S-SW in a distributed manner, malfunctions due to data bias of the data lines PBL, NBL and the voltage line CVSS can be reduced.

[0175] like Figure 16A As shown, reference cell R0.5 is controlled by control signal CD0.5, and reference cell R1 is controlled by seven control signals CD[0:6]. Here, one reference cell R1 is connected to control signal CD[0], two reference cells R1 are connected to control signal CD[1], and four reference cells R1 are connected to control signal CD[2]. In addition, eight reference cells R1 are connected to control signal CD[3], 16 reference cells R1 are connected to control signal CD[4], 32 reference cells R1 are connected to control signal CD[5], and 64 reference cells R1 are connected to control signal CD[6]. That is, control signals CD[0:6] are weighted.

[0176] exist Figure 17B In the embodiment, the Tbc array composed of the product operation memory cells Tbc and the R1 array composed of the reference cells R1 can also be considered to be distributed and arranged. As described above, through the distributed arrangement, failures caused by data bias can be reduced in the Tbc array and the R1 array.

[0177] According to the tenth embodiment, when the product sum value of the "+1" side and the "-1" side is small, the potential difference between the data lines PBL and NBL can be amplified, and the operating margin can be expanded. In addition, malfunctions can be reduced by allocating the source switch S-SW, the Tbc array, and the R1 array.

[0178] (Eleventh embodiment)

[0179] In the ninth embodiment, an example in which a user can arbitrarily change the data length of the MQ output data MQ[0] is shown. In other words, an example in which a user arbitrarily compresses the data length of the MQ output data MQ[0] has been described as the ninth embodiment. In the eleventh embodiment, a configuration in which a user can select other data compression is provided.

[0180] 18A to 18D is a diagram for explaining A / D conversion according to the eleventh embodiment.

[0181] Similarly to the explanation in the ninth embodiment, assume that the A / D conversion circuit converts to 8 bits. As shown in Figure 18A , when the data length of the maximum resolution is 8 bits, the values of the product-sum operation result one-to-one correspond to the output values represented by the MQ output data MQ[0].

[0182] On the other hand, as described in the ninth embodiment, when the A / D conversion operation is stopped midway (for example, at the sixth cycle (corresponding to Figure 15A and Figure 15B the sixth step 6th), the range of values represented by the 6-bit output values is from "-31" to "+31". The state at this time is shown in Figure 18B . In Figure 18B , the dotted line indicates the case of the maximum resolution, and when stopped at the sixth cycle, as shown by the solid line, the state becomes that the true value represented by the maximum resolution is compressed to 1 / 4. In other words, the characteristics of the A / D conversion circuit are represented by the function of the state in which the output is compressed to 1 / 4 with respect to the true value.

[0183] However, in some applications, until a predetermined value, a function can be expected as the A / D conversion such that a value equal to the true value is output. For example, when six cycles are specified, as shown in Figure 18C , a function can be expected in which the range of "-31" to "+31" becomes equal to the true value and becomes constant outside the range.

[0184] Figure 18D By exemplifying the case in which the output value is "+38", the case of Figure 18B and the case of Figure 18C are shown. In Figure 18D , condition 1 indicates the case in which up to the seventh bit is specified to indicate the true value, and condition 2 indicates the case in which compression as shown in Figure 18B is specified. Condition 1 has the true value up to the seventh bit, and condition 2 has a value of 1 / 2 of the true value of the seventh bit. Since these variations depend on the application, it is necessary to be able to select one of them.

[0185] Figure 19 is a diagram showing the configuration of a semiconductor device according to the eleventh embodiment. Figure 19The circuit diagram shows a portion related to a set of data lines PBL and NBL. Figure 20A and Figure 20B 1 is a timing chart of the semiconductor device according to the eleventh embodiment. Figure 20A shows the case where the data length is specified as 8 bits, and Figure 20B It shows that the data length is set to 7 bits and the Figure 18C The conversion situation shown.

[0186] The data lines PBL and NBL pair are connected to a precharge circuit formed by P-type FETs P30 to P32. The data lines PBL and NBL are connected to a differential sense amplifier via a transfer switch pair. The transfer switch pair consists of N-type FETs N30 and N34 and P-type FETs P36 and P37, which are controlled by a differential sense amplifier activation signal MACSAFB. The differential sense amplifier consists of N-type FETs N31 to N33 and P-type FETs P33 to P33. When the P-type FET P33 and N-type FET N33 are turned on by the differential amplifier activation signal MACSAEB, the differential sense amplifier amplifies and latches the potential difference between the data lines PBL and NBL provided via the transfer switch pair. The potential difference amplified by the comparator described in the tenth embodiment is provided to the data lines PBL and NBL.

[0187] The output of the differential sense amplifier is supplied to a switching selector consisting of NAND circuits ND30 and ND31, inverter circuits IV30 to IV32, P-type FETs P38 to P41, and N-type FETs N35 to N38. Depending on whether the control signal BLSEL supplied to the NAND circuits ND30 and ND31 is high or low, the output of the NAND circuit ND30 or ND31 becomes low. For example, when the output of the NAND circuit ND30 becomes low, the amplified voltage of the data line PBL is selected, and the MQ output data MQ[0] is output via the inverter circuit IV33. On the other hand, when the output of the NAND circuit ND31 is low, the amplified voltage of the data line NBL is selected, and the selected voltage is output as the MQ output data MQ[0] via the inverter circuit IV33. This is because, as described in the ninth embodiment, inversion occurs depending on whether the sign is "+" or "-."

[0188] The output of the switch selector is latched by a latch circuit comprising a NOR circuit NR30, P-type FETs P42 and P43, and N-type FETs N39 and N40. The logic value of the MQ output data MQ[0] is held by the latch circuit, and the output of the latch circuit is provided to latch circuits FF31 to FF34 as a control signal MQC.

[0189] The sum-of-products mask signal MEM is inverted and latched by latch circuit FF30 to become the inverted mask signal ME. NAND circuit ND32 generates differential amplifier activation signal MACSAEB using the inverted mask signal ME and differential sense amplifier control signal MACSAE. Furthermore, NAND circuit ND33 generates sum-of-products enable signal MACEBF based on the inverted mask signal ME and the sum-of-products mode enable signal MACE. The precharge circuit is controlled by a control signal having the same phase as sum-of-products enable signal MACEBF.

[0190] The latch circuits FF32 to FF34 generate a control signal CD for determining the number of reference cells R1 to be turned on. Although the control signal CD is 7 bits, Figure 19 Only the latch circuits that generate CD[4] to CD[6] as the 3-bit control signal CD are shown.

[0191] exist Figure 20A First, reset signal RST is set high to initialize the state. As a result, product-sum operation mask signal MEM is inverted and latched by latch circuit FF30. Furthermore, latch circuits FF31 through FF34 are reset. Next, differential sense amplifier control signal MACSAE goes high. This causes the potential difference between data lines PBL and NBL to be latched by the differential sense amplifier. At this point, since latch circuit FF31 is reset, control signal BLSEL goes high.

[0192] Therefore, when the state latched by the differential sense amplifier at this time is as follows: the product sum value on the "+1" side > the product sum value on the "-1" side (the voltage of the data line PBL > the voltage of the data line NBL), the logic value "0" is output as MQ data.

[0193] Thereafter, when the control signal CNT1 is asserted, the control signal BLSEL, which is the output of the latch circuit FF31, becomes low, and the inverter circuits IV34 and IV35 generate a high-level selection signal PR and a low-level selection signal PN. Since the MQ output data is output from the data line NBL side, when the product-sum value on the "+1" side is less than the product-sum value on the "-1" side, a logical value "0" is output. Thus, the control signal CNT[7] is asserted, and the control signal CD[6] becomes high. By making the control signal CD[6] high, 64 reference cells R1 are turned on. At the next timing, the control signal CNT[6] is asserted, and the control signal CD[5] becomes high. As a result, 32 reference cells R1 are in the on state. As described above, by asserting the control signals CNT[7] to CNT[4], a logical value corresponding to the product-sum value can be obtained while adjusting the number of reference cells R1 turned to the on state.

[0194] Next, we will refer to Figure 20B To describe the case where the data length is reduced to 7 bits. Figure 18C The transition shown may be achieved by de-asserting control signal CNT[7] from the desired control signal CNT[n].

[0195] More specifically, when the sign bit is output after the initialization is completed, the control signal CNT[6] is asserted together with the control signal CNTI. The control signal CNT[6] is also connected to the enable E of the latch circuit FF32 for outputting the control signal CD[6], but by setting the control signal C1ST to the logic value "1" only for the first time, the latch circuit FF32 is prevented from operating for the control signal CNT[6]. Therefore, the control signal CD[6] is kept at a low level. As a result, the resolution changes from "-63" to "+63" and is the same as Figure 18C In the same manner as shown, a value equal to the true value is output with a data length of up to 7 bits. As described above, the user can change the data length of the output MQ output data MQ[0], and the data length is variable.

[0196] The control signal PS described in the ninth embodiment is connected to the reset terminal of the latch circuit FF30. Figure 14D When the Schmitt trigger NAND circuit 62 shown outputs the control signal PS, the inverted mask signal ME output from the latch circuit FF30 goes low. Consequently, the product-sum operation enable signal MACEBF goes low, and the product-sum operation is not performed. When the inverted mask signal ME is set to a low level, the latch circuit for MQ output data, which includes the P-type FET P43 and the NOR circuit NR30, is reset. Specifically, the P-type FET P43 turns conductive, providing a high level from the latch circuit for MQ output data to the inverter circuit IV33, thereby fixing the MQ output data to a low-level logical value of "0."

[0197] According to the eleventh embodiment, since the user can freely change the length of the output data, the degree of freedom in adjusting the trade-off between power and performance is improved. In addition, the Schmitt trigger NAND circuit 62 detects whether the result of the sum-of-products operation in the product operation memory cell connected to the paired data line is a logical value of "0". When it is "0", the control signal PS sets the MQ output data to a predetermined logical value and does not perform the A / D conversion operation, making it possible to reduce power consumption.

[0198] (Twelfth embodiment) Figure 21 1 is a circuit diagram showing the configuration of a reference cell according to the twelfth embodiment. 14A to 14DAs described above, the reference cell R1 has a configuration similar to that of the product operation memory cell. Therefore, the characteristics of the reference cell R1 also change according to the changes in the characteristics of the product operation memory cell Tbc. Therefore, for the reference cell R1, there is almost no need to consider the change in the characteristics.

[0199] On the other hand, the reference cell R0.5 is set so that the current flowing through the series-connected FETs is limited, and half of the current of the product operation memory cell flows. Therefore, if the characteristics of the series-connected FETs vary due to manufacturing variations, there is a concern that the current flowing through the reference cell R0.5 will not correspond to half of the current of the product operation memory cell. In the twelfth embodiment, Figure 14C The N-type FETs N18_1 to N18_8 shown in FIG are changed to Figure 21 N-type FETs N50_1 to N50_4, N51_1 to N51_3, and N52_1 to N52_2 are shown. Here, a control signal CD is supplied to the gate electrodes of the N-type FETs N52_1 and N52_2. On the other hand, the gate electrodes of the N-type FETs N50_1 to N50_4 are connected to the trimming terminal TRM0 for current adjustment, and the gate electrodes of the N-type FETs N51_1 to N51_3 are connected to the trimming terminal TRM1 for current adjustment.

[0200] The trimming terminals TRM0 and / or TRM1 are connected to the gate electrodes of, for example, N-type FETs N52_1 and N52_2 so that the current flowing through the reference cell R0.5 is half the current flowing through the product operation memory cell Tbc. The trimming terminals TRM0 and TRM1 can be considered as terminals that modify the characteristics of the reference cell R0.5.

[0201] According to the twelfth embodiment, the influence of manufacturing variations can be reduced.

[0202] Figure 22 FIG1 shows the external terminals of the semiconductor device according to the first embodiment to the twelfth embodiment. Although the semiconductor device related to the first embodiment to the twelfth embodiment has a large number of external terminals, Figure 22 Only external terminals related to the signals described in the first to twelfth embodiments are representatively shown. Figure 22 Shows the external terminal names, their numbers, input / output distinctions, and functions.

[0203] exist Figure 22In the embodiment of the present invention, the MACE terminal is supplied with a product-sum operation mode enable signal MACE indicating whether the product-sum operation mode is enabled, the RST terminal is supplied with a reset signal RST, and the YA terminal is supplied with a column address YA. The D terminal is supplied with input data D to be written to the product operation memory cell, and the MEM terminal is supplied with a product-sum operation mask signal MEM for masking the product-sum operation. The data stored in the product operation memory cell is output from the Q terminal, and the product-sum operation output data (MQ output data) as the result of the product-sum operation is output from the MQ terminal.

[0204] certainly, Figure 22 The external terminals shown are just one example and are not limited to this example.

[0205] Although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can of course be made without departing from the gist thereof.

Claims

1. A semiconductor device comprising: a first product operation memory unit connected to a pair of data lines including a first data line and a second data line and storing a first logic value; a second product operation memory unit connected to the pair of data lines and storing a second logic value; a first input line connected to the first product operation memory unit and providing first input data to the first product operation memory unit; a second input line connected to the second product operation memory unit and providing second input data to the second product operation memory unit; wherein each of the first logic value and the second logic value is a ternary value, wherein the first product operation memory unit performs a first product operation on the first logic value and the first input data, and outputs a result of the first product operation to the paired data lines; wherein the second product operation memory unit performs a second product operation on the second logic value and the second input data, and outputs a result of the second product operation to the paired data lines, The results of the first product operation and the second product operation are superimposed on the paired data lines.

2. The semiconductor device according to claim 1, further comprising: a first switch connected to the first data line and controlled by the first logic value; a second switch connected to the second data line and controlled by the second logic value; as well as a third switch controlled by the input value and connected to the voltage line; wherein the first data line is connected to the voltage line via the first switch and the third switch corresponding to the first logic value, and The second data line is connected to the voltage line via the second switch and the third switch corresponding to the second logic value.

3. The semiconductor device according to claim 2, wherein the first data line and the second data line are formed in a first metal wiring layer, and The voltage line is formed in a second metal wiring layer different from the first metal wiring layer.

4. The semiconductor device according to claim 3, wherein the first metal wiring layer and the second metal wiring layer are adjacent to each other, and The first data line, the second data line and the voltage line extend in the same direction.

5. A semiconductor device comprising: a plurality of product-sum operation memory units, each storing ternary value data; as well as a data line connected to the plurality of product-sum operation memory units, wherein each of the plurality of product-sum operation memory units performs a product-sum operation on input data input to the product-sum operation memory unit and storage data stored in the product-sum operation memory unit, wherein the results of the product-sum operation of the plurality of product-sum operation memory units are output to the data line, The product-sum operation memory unit outputs a voltage indicating a result of the product-sum operation.

6. The semiconductor device according to claim 5 , wherein each of the plurality of sum-of-products memory cells comprises: A first memory unit stores absolute value data; as well as The second memory unit stores symbol data.

7. The semiconductor device according to claim 6, The data lines include a first data line and a second data line, Each of the plurality of sum-of-products operation memory units comprises: a plurality of first switches controlled by the absolute value data stored in the plurality of first memory units; a plurality of second switches controlled by the symbol data stored in the second memory unit; as well as a plurality of third switches, controlled by the input data, wherein the first data line is connected to a voltage line via the first switch and the third switch corresponding to the absolute value data and the input data, wherein the second data line is connected to the voltage line via the second switch and the third switch corresponding to the sign data and the input data, The absolute value data is weighted data. The size of each of the plurality of first switches, the plurality of second switches, and the plurality of third switches corresponds to a weight of the corresponding absolute value data.

8. A semiconductor device comprising: a plurality of product-sum operation memory units, each storing ternary value data; as well as a plurality of first data lines, each connected to the plurality of product-sum operation memory units; wherein each of the plurality of product-sum operation memory units performs a product-sum operation on storage data stored in the product-sum operation memory unit and input data input to the product-sum operation memory unit, The semiconductor device further comprises: a plurality of analog / digital conversion circuits connected to each of the plurality of first data lines and converting an analog signal of the connected first data line into a digital signal; An input data holding circuit for holding a plurality of input data; wherein the data held in the input data holding circuit is supplied as the input data to the product-sum operation memory unit, and The result of the product-sum operation is provided to the analog / digital conversion circuit via the first data line.

9. The semiconductor device according to claim 8, further comprising a plurality of second data lines, Data is written into the plurality of product-sum operation memory units via the plurality of second data lines.

10. The semiconductor device according to claim 8, further comprising: a digital / analog conversion circuit connected to the input data holding circuit and converting the input data into an analog signal, and The analog signal from the digital / analog conversion circuit is input to the product-sum operation memory unit.

11. The semiconductor device according to claim 8, wherein each of the plurality of first data lines comprises a paired data line, The semiconductor device further comprises: a reference unit connected to the paired data lines and providing a reference to one of the paired data lines; as well as comparators, connected to the paired data lines, The potential difference between the paired data lines is amplified by the comparator, and data based on the amplified potential difference is serially output.

12. The semiconductor device according to claim 11, wherein the reference cell comprises: a first reference unit having a driving force identical to that of the product-sum operation memory unit; as well as a second reference cell having a driving force half that of the sum-of-products memory cell, The data based on the potential difference is output such that a sign bit is followed by the most significant bit to the least significant bit in series.

13. The semiconductor device according to claim 12, The semiconductor device detects whether the result of the product-sum operation of the multiple product-sum operation memory cells connected to the paired data lines is "0", and when the product-sum operation of the multiple product-sum operation memory cells connected to the paired data lines is "0", the semiconductor device outputs a predetermined logical value as the result of the product-sum operation.

14. The semiconductor device according to claim 12, wherein a length of the data output serially is variable.

15. The semiconductor device according to claim 11, further comprising: a cell array in which the plurality of sum-of-products memory cells are arranged; a reference array in which the reference cells are arranged; as well as a source switch comprising a bias circuit and a switch circuit for biasing the paired data lines, wherein the cell array, the reference array and the source switch are distributed, and Part of the plurality of transistors constituting the product-sum operation memory unit and part of the plurality of transistors constituting the reference unit are used as transistors constituting the comparator. 16 . The semiconductor device according to claim 11 , wherein the reference cell includes a terminal capable of changing characteristics thereof.

17. The semiconductor device according to claim 15, further comprising: A MACE terminal is provided with a product-sum operation mode enable signal, wherein the product-sum operation mode enable signal indicates whether a product-sum mode for performing the product-sum operation is enabled; The RST terminal is provided with a reset signal; A YA terminal is supplied with an address designating the product-sum operation memory cell of the cell array; A D terminal is supplied with data written to the product-sum operation memory unit; as well as The MQ terminal outputs the result of the product-sum operation.

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