Surface mount semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a method for manufacturing the same, the semiconductor device comprising: a semiconductor die, wherein the semiconductor die comprises a first main surface having a first contact terminal arranged thereon and an opposite second main surface having a second contact terminal arranged thereon; a first lead frame having opposite first and second main surfaces, wherein the first main surface is fixedly attached to the first contact terminal of the semiconductor die; a second lead frame having opposite first and second main surfaces, wherein the first main surface is fixedly attached to the second contact terminal of the semiconductor die; and wherein the first lead frame comprises an integrally formed external contact portion extending from its first main surface to a plane substantially coplanar with the second main surface of the second lead frame.

Description

Technical Field

[0001] The present disclosure relates to surface mount semiconductor devices and methods of manufacturing surface mount semiconductor devices. In particular, the present disclosure relates to leadless surface mount semiconductor devices and associated manufacturing methods. Background Art

[0002] Semiconductor devices can be mounted or placed directly on the surface of a carrier such as a printed circuit board (PCB). Such semiconductor devices are known as surface mounted devices (SMDs). The use of SMDs allows for increased speed in producing complete electronic circuits formed on PCBs using automated placement techniques, thereby reducing the manufacturing time of PCB-mounted electronic circuits.

[0003] SMDs can be arranged in a variety of packages, such as leadless dual flat no-lead (DFN), quad flat no-lead (QFN) packages, etc. QFN and DFN packages are commonly used for discrete devices due to their small footprint and low package height. For example, in the case of such leadless packages containing power semiconductor dies, heat dissipation of the semiconductor die is an important design consideration to prevent the die from overheating. Devices such as transient voltage suppression (TVS) protection devices are used to protect integrated circuits (ICs) from electrical overloads. In use, these devices are connected between an external input terminal and the input terminal of the IC and can be operated to drain unwanted current to the ground or other rails so that any internally provided IC protection is not overloaded and damaged.

[0004] The heat caused by the current flowing within the protection device can limit the robustness of the device. The temperature within the protection device depends on factors such as the dissipated power, the device's heat capacity, and the device's thermal resistance.

[0005] The so-called Dual Cool TM A device package style that provides bottom-side and top-side cooling to the semiconductor die via heat sinks exposed on the top and bottom sides of the device package.

[0006] However, there are many design and manufacturing challenges to achieve heat exposure. The most notable is precisely controlling the adhesive bond that attaches the semiconductor die to each heat sink. If there is any variation in the bond thickness along the bond length (called the bond line thickness), this will cause the heat sink to tilt relative to the semiconductor die on which it is mounted. During molding of the semiconductor die, the tilted heat sink can cause molding compound flash, which at least partially covers the portion of the heat sink that should be exposed. This can reduce heat dissipation from the die. Summary of the Invention

[0007] Various example embodiments address problems such as those discussed above and / or other problems that will be apparent from the following disclosure, which relates to improving an assembly process to implement a semiconductor device having a heat sink with top and bottom sides exposed.

[0008] In certain example embodiments, aspects of the present disclosure relate to a semiconductor device including a top-side and bottom-side exposed heat spreader attached to contact terminals on respective top and bottom sides of a semiconductor die.

[0009] According to an embodiment, a semiconductor device is provided, comprising: a semiconductor die, wherein the semiconductor die includes a first main surface having a first contact terminal arranged thereon and an opposite second main surface having a second contact terminal arranged thereon; a first lead frame having opposite first and second main surfaces, wherein the first main surface is fixedly attached to the first contact terminal of the semiconductor die; a second lead frame having opposite first and second main surfaces, wherein the first main surface is fixedly attached to the second contact terminal of the semiconductor die; and wherein the first lead frame includes an integrally formed external contact portion extending from its first main surface to a plane that is substantially coplanar with the second main surface of the second lead frame.

[0010] According to another embodiment, a method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor die, wherein the semiconductor die includes a first major surface having a first contact terminal disposed thereon and an opposing second major surface having a second contact terminal disposed thereon; providing a first leadframe having opposing first and second opposing major surfaces, wherein the first major surface is fixedly attached to the first contact terminal of the semiconductor die; providing a second leadframe having opposing first and second major surfaces, wherein the first major surface is fixedly attached to the second contact terminal of the semiconductor die; wherein the first leadframe includes an integrally formed external contact portion extending from its first major surface to a plane substantially coplanar with the second major surface of the second leadframe.

[0011] A semiconductor device may include a mold material constructed and arranged to encapsulate a semiconductor die.

[0012] The first lead frame and the second lead frame may be first and second heat sinks, respectively, which are constructed and arranged such that respective second main surfaces are exposed at respective first and second main surfaces of the semiconductor device through a mold material.

[0013] The second major surface of the first leadframe may be substantially coplanar with the mold material at the first major surface of the semiconductor device.

[0014] The integrally formed external contact portion of the first lead frame may extend along a length of the sidewall from the first main surface to the second main surface of the semiconductor device.

[0015] The second lead frame includes an integrally formed external contact portion that may extend partially along a length of the sidewall from the second main surface toward the first main surface of the semiconductor device.

[0016] The integrally formed external contact portion is arranged as a contact portion, which is constructed and arranged to be fixedly mounted to a carrier surface.

[0017] The length of the external contact portion of the first lead frame may be greater than the length of the external contact portion of the second lead frame.A cross section of each of the first lead frame and the second lead frame may be substantially L-shaped.

[0018] A first conductive adhesive layer may be disposed between the first contact terminal and the first major surface of the first lead frame; and a second conductive adhesive layer may be disposed between the second contact terminal and the first major surface of the second lead frame.

[0019] The thickness of the first conductive adhesive layer may be uniform over a contact area between the first contact terminal and the first major surface of the first lead frame, and the thickness of the second conductive adhesive layer may be uniform over a contact area between the second contact terminal and the first major surface of the second lead frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order that the manner in which the features of the present disclosure may be understood in detail, a more particular description will be given with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments and should not be considered as limiting the scope thereof. The drawings are intended to facilitate understanding of the present disclosure and are not necessarily drawn to scale. The advantages of the claimed subject matter will become apparent to those skilled in the art when this specification is read in conjunction with the accompanying drawings, in which like reference numerals are used to represent like elements, and wherein:

[0021] Figure 1 shows a cross section of a semiconductor device according to one embodiment;

[0022] Figure 2a shows a perspective view of a first side of a packaged semiconductor device according to one embodiment;

[0023] Figure 2b A perspective view illustrating a second side of a packaged semiconductor device according to an embodiment; and

[0024] Figures 3a to 3iExample process steps for fabricating a packaged semiconductor die are shown in accordance with an embodiment. DETAILED DESCRIPTION

[0025] Figure 1 A cross-section of a leadless semiconductor device 100 is shown in accordance with one embodiment.

[0026] The semiconductor device 100 includes a semiconductor die 102. A first contact terminal 104 is disposed on a first main surface of the semiconductor die 102, and a second contact terminal 106 is disposed on a second main surface of the semiconductor die 102 opposite the first main surface.

[0027] The first contact terminals 104 of the semiconductor die 102 are fixed and electrically attached to the first lead frame 108, and the second contact terminals of the semiconductor die 102 are fixed and electrically attached to the second lead frame 110. The first contact terminals 104 and the second contact terminals 106 of the semiconductor die 102 are attached to the respective first and second lead frames 108, 110 by means of a conductive adhesive 112, so as to form adhesive bonding layers at the junctions of the contact terminals 104 with the lead frame 108 and at the junctions of the contact terminals 106 with the lead frame 110. In this way, the first and second lead frames 108, 110 provide mechanical support for the semiconductor die 102 while also making electrical connections to the first and second contact terminals 104, 106.

[0028] The first lead frame 108 and the second lead frame 110 are arranged as electrically conductive heat sinks and may be formed of a metallic material, for example, they may include an electrically conductive metal such as copper.

[0029] The first lead frame 108 includes a planar semiconductor die attach portion 116 for electrically and mechanically attaching thereto the first contact terminals 104 of the semiconductor die 102 (as described above). As such, the semiconductor die attach portion 116 extends substantially parallel to a plane containing the first contact terminals 104 of the semiconductor die 102.

[0030] The first lead frame 108 further includes an external connection portion 118 integrally formed with the die attach portion 116. The external connection portion 118 extends away from the die attach portion 116. The external connection portion 118 may extend in a direction substantially orthogonal to the die attach portion 116. Figure 1 As shown, external connection portion 118 extends downwardly from die attach portion 116 through semiconductor die 102 .

[0031] Likewise, the second leadframe 110 includes a semiconductor die attach portion 120 for electrically and mechanically attaching thereto the second contact terminals 106 of the semiconductor die 102. As such, the semiconductor die attach portion 120 extends substantially parallel to a plane containing the second contact terminals 106 of the semiconductor die 102.

[0032] The second lead frame 110 further includes an external connection portion 122 integrally formed with the die attach portion 120. The external connection portion 122 extends away from the die attach portion 120. The external connection portion 122 may extend in a direction substantially orthogonal to the die attach portion 120. Figure 1 As shown, the external connection portion 122 extends upward from the chip attach portion 120 to one side of the semiconductor chip 102 .

[0033] The electrical connection portion 118 of the first leadframe 108, as it extends from the die attach portion 116, has a thickness t that corresponds to the thickness of the die attach portion 120 of the second leadframe 110, the thickness of the die 102, and the thickness of the combined adhesive bonding layer at the respective contact terminals 104, 106 of the semiconductor die 102. In this manner, the cross-section of the first leadframe can be seen to be L-shaped.

[0034] The thickness of the electrical connection portion 122 of the second lead frame 110 is less than the thickness t of the electrical connection portion 118 of the first lead frame 108 when extending from the die attach portion 116. Similar to the first lead frame 108, the second lead frame 110 is also seen to be L-shaped in cross section.

[0035] First leadframe 108 is configured to conduct electrical current to / from semiconductor die 102 and electrical connection portions 118 of first leadframe 108. Electrical connection portions 118 are also configured so that they can be surface mounted on electrical contacts of a carrier, such as a printed circuit board (not shown). In this regard, electrical connection portions 118 include bottom contact surfaces 124 and side contact surfaces 126. Bottom contact surfaces 124 and side contact surfaces 126 are configured so that they can be soldered to electrical contacts of the carrier. When semiconductor device 100 is soldered or glued to a carrier, solder / glue joint menisci can extend upward from the corresponding electrical contacts of the carrier to contact surfaces 126. The solder / glue joints will also extend above the electrical contacts of the carrier in the area of ​​bottom contact surfaces 124.

[0036] Likewise, the second leadframe 110 is also configured to conduct electrical current to / from the semiconductor die 102. The electrical connection portion 122 of the second leadframe 110 also includes a bottom contact surface 128 and a side contact surface 130. The bottom contact surface 128 and the side contact surface 130 are configured so that they can be soldered to electrical contacts of the carrier in the same manner as the bottom contact surface 124 and the side contact surface 126 of the first leadframe 108.

[0037] According to an embodiment, after the contact terminals 104 , 106 are attached to the respective first and second lead frames 108 , 110 , a mold material (or encapsulation) 114 is disposed to encapsulate the semiconductor die 102 .

[0038] The above arrangement allows visual inspection of the solder joints connecting the electrical connection portions 118 , 122 of the leadless semiconductor device according to the embodiment by, for example, automated optical inspection (AOI) to inspect solder joint coverage after a solder reflow process.

[0039] The contact surface 124 of the first lead frame 108 is arranged to be substantially coplanar with the contact surface 128 of the second lead frame 110. In addition, the contact surface 124 of the first lead frame 108 and the contact surface 128 of the second lead frame 108 are flat across their respective surface areas. Furthermore, the semiconductor die 102 is prevented from tilting relative to the first lead frame 108 and the second lead frame 110 by precisely dispensing the conductive adhesive 112 (e.g., by stencil printing).

[0040] like Figure 1 as well as Figure 2a and Figure 2b As shown, the mold material (or encapsulation) 114 extends partially over the top and bottom major surfaces of the leadless semiconductor device 100 . Figure 2a The mold material 114 is shown partially covering and including a portion of the top major surface of the semiconductor device 100. The remainder of the top major surface includes the exposed upper surface of the die attach portion 116 of the first lead frame 108. The exposed surface of the die attach portion 116 is opposite the side to which the semiconductor die is attached. Similarly, Figure 2bThe mold material 114 is shown partially covering and including a portion of the bottom major surface of the semiconductor device 100. The remainder of the bottom major surface includes the exposed lower surface of the die attach portion 120 of the second lead frame 110. The exposed surface of the die attach portion 120 is opposite to the side to which the semiconductor die is attached. This arrangement of the exposed surfaces of the first lead frame 108 and the second lead frame 110 improves the dissipation of heat generated in the semiconductor die 102 during operation while also allowing electrical connection of the semiconductor device 100 to the carrier. The semiconductor device 100 is fixedly mounted and connected to the carrier by, for example, soldering the bottom contact surface 128 and the side contact surface 130 of the second lead frame to corresponding connections on the carrier. Similarly, the bottom contact surface 124 and the side contact surface 126 of the first lead frame can be fixedly connected to corresponding connections on the carrier. As Figure 1 As shown, the side contact surface 130 of the second lead frame partially extends upward on the side wall of the semiconductor device. Figure 2a As can be seen in FIG. 1 , the bottom surface contact corresponding to the side contact surface 130 of the second lead frame is not shown.

[0041] The arrangement of die attach portions 116 , 120 exposed through the mold material provides improved heat dissipation while maintaining a consistent bondline thickness over areas of the adhesive bondline connecting the die attach portions of the respective first and second leadframes to the respective contact terminals 104 , 106 of the semiconductor die 102 .

[0042] Figures 3a to 3i Exemplary process steps of a method for manufacturing a semiconductor device according to an embodiment are shown. The method can allow for the manufacture of multiple devices.

[0043] In the first step, as Figure 3a As shown, the method includes providing a plurality of connected second lead frames 110 arranged in a matrix. The size of the second lead frame 110 is appropriately set for mounting a semiconductor die thereon. Figure 3b As shown, a suitable conductive die attach material 112 is then provided on the second lead frame 110. The conductive die attach material 112 may be solder or a conductive adhesive and may be dispensed on the second lead frame 110 by, for example, stencil printing. The conductive die attach material 112 allows the second contact terminal 106 of the semiconductor die 102 to be electrically and mechanically connected to the second lead frame 110. Figure 3c As shown, the semiconductor die is then placed on the conductive die attach material 112 disposed on the second lead frame 110 .

[0044] After placing the semiconductor die 102 on the second lead frame 110 , another electrically conductive die attach material 112 is provided on the first contact terminals 104 of the semiconductor die 102 by, for example, stencil printing. Figure 3d Another conductive die attach material 112 may be the same as that described above with respect to Figure 3c The materials used in the die attach steps discussed are the same and can be printed using similar methods.

[0045] In the reference Figure 3c After dispensing the conductive die attach material 112 as discussed, Figure 3e The first lead frame 108 is mounted on the semiconductor die as shown. Figure 3e The assembled device is placed in a fixture housing (not shown). The fixture housing may include a top portion that contacts the first lead frame 108 and a bottom portion that contacts the second lead frame 110. Locators or locating pins may be arranged on the top fixture or the bottom fixture, and have corresponding holes on the first lead frame 108 and the second lead frame 110 to accommodate the locating pins arranged on the top or bottom fixture. This can fix the fixture in the appropriate position to prevent the lead frame, the top portion and the bottom portion of the fixture from tilting during the reflow process. The clamping process also helps to maintain the consistent thickness of the bonding layer mentioned above. The clamping process may be applicable to the body bonding technology.

[0046] The thus formed device can then undergo solder reflow to electrically and mechanically connect the lead frames 108, 110 to the corresponding contact terminals 104, 106 of the semiconductor die 102. In the case where the conductive die attach material 112 is an adhesive, the reflow process can be an adhesive curing process. As with the arrangement of the second lead frames 110, the first lead frames 108 can also be arranged in a matrix. The first lead frames 108 are appropriately sized for mounting to the semiconductor die 102.

[0047] Then the process Figure 3f Continuing with the above, the arrangement is encapsulated (or molded) in an encapsulant 114 that fills the space around the substrate around the semiconductor die 102. The encapsulation process may be any suitable process, such as mold mapping with film assisted molding (FAM), but it will result in the same process as described above for Figure 1 The exposed surface of the lead frame.

[0048] After the packaging process, the matrix arrangement performs a first series of cuts (indicated by lines xx) along the sidewalls of the device to expose the side contact surfaces 126 of the first lead frame 108 and the side contact surfaces 130 of the second lead frame 110. Figure 3hThis exposure of the side contact surfaces 126, 130 allows for electroplating of the contact surfaces.

[0049] After the electroplating, the matrix arrangement performs a second series of cuts orthogonal to the first series of cuts to singulate the semiconductor devices 100 according to the embodiment and thus achieve the following: Figure 1 、 2a and a single device as shown in 2b.

[0050] Based on the above disclosure, those skilled in the art will appreciate that the semiconductor device according to the embodiment provides exposed heat sink portions on both sides of the device while also allowing soldering to a carrier such as a PCB where the solder joints can be seen from the side of the device.

[0051] Particular and preferred aspects of the invention are set out in the accompanying independent claims. Combinations of features from the dependent claims and / or independent claims may be combined as appropriate and not only as set out in the claims.

[0052] The scope of the present disclosure includes any novel feature or combination of features disclosed therein, whether explicitly or implicitly, or any generalization thereof, whether or not relevant to the claimed invention or alleviating any or all of the problems solved by the invention. The applicants hereby give notice that new claims may be formulated to such features during the prosecution of the present application or of any further application derived therefrom. In particular, with reference to the appended claims, features of dependent claims may be combined with features of the independent claims, and features of the independent claims may be combined in any appropriate manner and not merely in the specific combinations recited in the claims.

[0053] Features that are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination.

[0054] The term "comprising" does not exclude other elements or steps, and the terms "a" or "an" do not exclude a plurality. Reference signs in the claims should not be construed as limiting the scope of the claims.

Claims

1. A semiconductor device comprising: a semiconductor die, wherein the semiconductor die comprises a first major surface and an opposing second major surface, a first contact terminal being arranged on the first major surface of the semiconductor die, and a second contact terminal being arranged on the second major surface of the semiconductor die; a first leadframe having opposing first and second major surfaces, wherein the first major surface of the first leadframe is fixedly attached to the first contact terminal of the semiconductor die; a second leadframe having opposing first and second major surfaces, wherein the first major surface of the second leadframe is fixedly attached to the second contact terminal of the semiconductor die; and wherein the first lead frame includes an integrally formed external contact portion extending from a first major surface of the first lead frame to a plane coplanar with a second major surface of the second lead frame, The semiconductor device further includes a mold material constructed and arranged to encapsulate the semiconductor die, wherein the first lead frame and the second lead frame are respectively a first heat sink and a second heat sink, which are constructed and arranged so that the corresponding second main surfaces are exposed at the corresponding first main surface and the second main surface of the semiconductor device through the mold material, wherein the second main surface of the first lead frame is coplanar with the mold material at the first main surface of the semiconductor device, wherein the second main surface of the second lead frame is coplanar with the mold material at the second main surface of the semiconductor device, wherein the integrally formed external contact portion of the first lead frame extends along a length of the sidewall from the first main surface of the semiconductor device to the second main surface of the semiconductor device, wherein the second lead frame includes an integrally formed external contact portion extending partially along the length of the sidewall from the second main surface of the semiconductor device toward the first main surface of the semiconductor device, wherein the length of the external contact portion of the first lead frame is greater than the length of the external contact portion of the second lead frame, and Wherein, the cross sections of the first lead frame and the second lead frame are L-shaped.

2. The semiconductor device according to claim 1, wherein The integrally formed external contact portion is arranged as a contact portion, which is constructed and arranged to be fixedly mounted to a carrier surface.

3. The semiconductor device according to claim 1 , further comprising: a first conductive adhesive layer disposed between the first contact terminal and the first major surface of the first lead frame; and a second conductive adhesive layer disposed between the second contact terminal and the first major surface of the second lead frame.

4. The semiconductor device according to claim 3, wherein The thickness of the first conductive adhesive layer is uniform over the contact area between the first contact terminal and the first major surface of the first lead frame, and the thickness of the second conductive adhesive layer is uniform over the contact area between the second contact terminal and the first major surface of the second lead frame.

5. A method for manufacturing a semiconductor device according to any one of claims 1 to 4, the method comprising: Providing a semiconductor die, wherein the semiconductor die includes a first main surface and an opposite second main surface, a first contact terminal is arranged on the first main surface of the semiconductor die, and a second contact terminal is arranged on the second main surface of the semiconductor die; providing a first lead frame having opposing first and second major surfaces, wherein the first major surface of the first lead frame is fixedly attached to the first contact terminal of the semiconductor die; providing a second lead frame having opposing first and second major surfaces, wherein the first major surface of the second lead frame is fixedly attached to the second contact terminal of the semiconductor die; The first lead frame includes an integrally formed external contact portion extending from a first major surface thereof to a plane coplanar with a second major surface of the second lead frame.

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