Power semiconductor device packages

Abstract

The present invention is entitled "Power Semiconductor Device Package". In general terms, a semiconductor device package may include a leadframe. The semiconductor device package may also include a first semiconductor die coupled to a first side of a first portion of the leadframe and a second semiconductor die coupled to a second side of the first portion of the leadframe. The semiconductor device package may also include a first substrate coupled to the second side of the first semiconductor die. The first substrate may further be coupled to the first side of the second portion of the leadframe and the first side of the third portion of the leadframe. The semiconductor device package may further include a second substrate coupled to the second side of the second semiconductor die. The second substrate may further be coupled to the second side of the second portion of the leadframe and the second side of the third portion of the leadframe.

Description

Technical Field

[0001] The present description relates to semiconductor device package apparatus. More particularly, the present description relates to a semiconductor device package including multiple semiconductor dies with isolated (eg, electrically isolated) double-sided cooling. Background Art

[0002] The trend in power semiconductor devices (e.g., power semiconductor devices for electric vehicles (EVs) and / or hybrid electric vehicles (HEVs)) is towards higher voltage, higher power devices, such as power semiconductor devices implemented in silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc., for example in the EV and / or HEV automotive markets. For example, the trend is to use such power semiconductor devices in powertrain inverters, direct current-to-direct current (DC-DC) converters, and / or on-board chargers (OBCs). Because the power capacity of such devices can be 10 times (or more) that of silicon devices, this trend presents certain challenges, such as manufacturing semiconductor device packages that can allow for higher current / power ratings, provide sufficiently low impedance (e.g., inductance), and have high heat dissipation performance. Summary of the Invention

[0003] In a general aspect, a device may include a leadframe having a first portion, a second portion, and a third portion. The device may also include a first semiconductor die having a first side coupled to a first side of the first portion of the leadframe and a second semiconductor die having a first side coupled to a second side of the first portion of the leadframe. The device may further include a first substrate having a first side coupled to the second side of the first semiconductor die. The first side of the first substrate may further be coupled to the first side of the second portion of the leadframe and the first side of the third portion of the leadframe. The device may further include a second substrate having a first side coupled to the second side of the second semiconductor die. The first side of the second substrate may further be coupled to the second side of the second portion of the leadframe and the second side of the third portion of the leadframe.

[0004] In another general aspect, a device may include a first direct bonded-metal (DBM) substrate and a first semiconductor die mounted on the first DBM substrate in a flip-chip manner. The device may also include a second DBM substrate and a second semiconductor die mounted on the second DBM substrate in a flip-chip manner. The device may further include a leadframe having a first portion including a die attach paddle (DAP), a second portion, and a third portion. The first semiconductor die may be coupled to a first side of the DAP. The second semiconductor die may be coupled to a second side of the DAP. The first DBM substrate may be coupled to a first side of the second portion of the leadframe and a first side of the third portion of the leadframe. The second DBM substrate may be coupled to a second side of the second portion of the leadframe via a first spacer and to a second side of the third portion of the leadframe via a second spacer.

[0005] In another general aspect, a method may include constructing a first subassembly, the method comprising: coupling a first side of a first semiconductor die to a first direct bond metal (DBM) substrate; coupling a second side of the first semiconductor die to a first side of a first leadframe portion; coupling the first DBM substrate to a first side of a second leadframe portion; and coupling the first DBM substrate to a second side of a third leadframe portion. The method may also include constructing a second subassembly, comprising: coupling a first side of a second semiconductor die to a second DBM substrate; coupling a first spacer to the second DBM substrate; and coupling a second spacer to the second DBM substrate. The method may further include constructing an assembly by coupling the second subassembly to the first subassembly, comprising: coupling the second side of the second semiconductor die to a second side of the first leadframe portion; coupling the first spacer to the second side of the second leadframe portion; and coupling the second spacer to the second side of the third leadframe portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram illustrating a semiconductor device package according to an embodiment.

[0007] Figure 2 It shows that you can Figure 1 Schematic diagram of a circuit implemented in a semiconductor device package.

[0008] Figure 3 It shows that according to the embodiment Figure 1 FIG. 1 is a cross-sectional view of a semiconductor device package.

[0009] Figure 4 is shown in accordance with an embodiment of the present invention. Figure 1FIG. 1 is a diagram of a bonding metal pattern of a substrate in a semiconductor device package of a semiconductor device package.

[0010] Figure 5 is shown in accordance with an embodiment of the present invention. Figure 1 A diagram of an aspect of a semiconductor device package and a bonding metal pattern of another substrate in a semiconductor device package.

[0011] Figures 6A to 6B is a diagram illustrating a power semiconductor die that may be implemented in the semiconductor device packages described herein.

[0012] 7A to 7C are diagrams showing various views of a direct bond metal (DBM) substrate that may be included in a semiconductor device package according to an embodiment.

[0013] Figure 8 is a diagram illustrating a lead frame strip including a plurality of lead frames that may be included in a semiconductor device package according to an embodiment.

[0014] Figure 9 is a diagram illustrating a semiconductor device package coupled to a printed circuit board according to an embodiment.

[0015] Figure 10 is a diagram illustrating a method of producing a semiconductor device package such as the semiconductor device package described herein according to an embodiment. DETAILED DESCRIPTION

[0016] The present disclosure is directed to embodiments of semiconductor device packages (and associated methods of manufacture) that can address the challenges associated with the trend toward higher power semiconductor devices. For example, the methods described herein can address the challenges discussed above, for example, by providing semiconductor device packages that allow for higher current / power ratings, provide sufficiently low electrical impedance (e.g., inductance), and have high heat dissipation capabilities. For example, the methods described herein can provide for implementing multiple (e.g., connected in parallel) power semiconductor devices (e.g., power transistors) in a single semiconductor device package. The methods described herein also allow for double-sided cooling, which can improve heat dissipation performance.

[0017] Furthermore, the methods described herein can provide electrical isolation between substrates (e.g., multiple substrates) in a semiconductor device package. Such electrical isolation can provide certain advantages, such as for printed circuit board layout in high voltage applications. For example, in some embodiments, such electrical isolation can allow for more efficient printed circuit board layout, for example, by allowing high voltage devices implemented in the semiconductor device package described herein to be placed closer to associated circuit boards of other devices.

[0018] Compared to current embodiments of power semiconductor devices, the methods described herein can provide a compact package solution with low impedance (e.g., inductance, etc.) and longer creepage distance for high voltage applications. In some embodiments, creepage distance can refer to the shortest distance between a signal lead connected to electrical ground and a signal lead connected to a high voltage power supply (e.g., 400V or higher), where such creepage distance is measured between the electrical connections of such signal leads when the semiconductor device package is coupled to (mounted, fixed, soldered to, etc.) a printed circuit board (PCB). Longer creepage distance can be beneficial because it can prevent current leakage (current creep) and / or arcing between pins connected to high voltage and pins connected to ground. For example, in some embodiments, the creepage distance can be the shortest distance between (multiple) signal leads connected to the drain terminal of a power metal oxide semiconductor field effect transistor (MOSFET) and (multiple) signal leads connected to the source terminal of the MOSFET.

[0019] Figure 1 FIG is a diagram illustrating a semiconductor device package (package) 100 according to an embodiment. For purposes of illustration and discussion, Figure 1 , aspects of the package 100 that may not be visible in example embodiments are shown, such as elements that may be disposed inside the package 100 (eg, within a molding compound). Figure 1 Also included is section line 3-3, which in an example embodiment may correspond to Figure 3 Cross-sectional view shown.

[0020] In the drawings, similar reference numerals are used to indicate similar or analogous elements used in the illustrated example embodiments. However, in some embodiments, variations of these elements are possible. For example, different substrate layouts (e.g., bonding metal) layouts are possible, different lead frame configurations are possible, different power semiconductor devices can be implemented in package 100, package 100 can include additional semiconductor dies (e.g., a respective diode connected in parallel with each of the two power semiconductor transistors included in package 100), etc.

[0021] like Figure 1 As shown, the package 100 may include a lead frame having a plurality of portions 110a, 110b, 110c, and 110d. The portions 110a to 110d may be collectively referred to as the lead frame 110. Figure 1As shown, each portion of lead frame 110 can include one or more signal leads (e.g., signal leads, etc.). For example, in this example, lead frame portion 110a includes five (5) signal leads, lead frame portion 110b includes three (3) signal leads, and lead frame portions 110c and 110d each include one (1) signal lead. In some embodiments, lead frame 110 can include additional or fewer portions. In some embodiments, one or more of lead frame portions 110a through 110d can include a different number of leads.

[0022] exist Figure 1 In an example embodiment, the lead frame portion 110a may include a die attach pad (DAP), such as, for example Figure 3 As shown, a first power semiconductor device (e.g., a first MOSFET included on a first semiconductor die) can be coupled (electrically coupled, soldered, etc.) to a first side of the DAP, and a second power semiconductor device (e.g., a second MOSFET included on the first semiconductor die) can be coupled (electrically coupled, soldered, etc.) to a second side (opposite to the first side) of the DAP. In some embodiments, the DAP can serve as a common drain terminal for the first MOSFET and the second MOSFET, such as Figure 2 Terminal 210a in circuit 200 is shown.

[0023] Likewise Figure 1 As shown, the package 100 may further include a substrate 120 that is coupled (electrically coupled) to the first power semiconductor device (e.g., to the source of the first MOSFET, the gate of the first MOSFET, and / or the source sense terminal of the first MOSFET). In some embodiments, such as in the example device 100, the substrate 120 may further provide electrical connections between the first MOSFET and the lead frame portions 110b, 110c, and 110d. For example, in some embodiments, the substrate 120 may provide an electrical connection between the source of the first MOSFET and the lead frame portion 110b, an electrical connection between the gate of the first MOSFET and the lead frame portion 110c, and an electrical connection between the lead frame portion 110d and the source of the first MOSFET (e.g., as a source sense terminal).

[0024] In some embodiments, the substrate 120 may be a direct bonded metal (DBM) substrate, such as a direct-bonded copper (DBC) substrate. Figure 1As shown, substrate 120 may include a metal pattern 125 exposed through molding compound 130 of package 100. In some embodiments, a heat sink may be coupled to metal pattern 125 to provide heat dissipation for package 100 (e.g., to dissipate heat generated by a power semiconductor device implemented in package 100).

[0025] Although not in Figure 1 , but the package 100 may include a second substrate (e.g., similar to the substrate 120 and the first power semiconductor device discussed above) electrically coupled to the second power semiconductor device. For example, the second power semiconductor device may be a second MOSFET, and the second substrate may provide an electrical connection between the source of the second MOSFET and lead frame portion 110b, provide an electrical connection between the gate of the second MOSFET and lead frame portion 110c, and provide an electrical connection between lead frame portion 110d and the source of the source MOSFET (e.g., as a source sense terminal). In this example, lead frame portion 110b may serve as a common source terminal for the first MOSFET and the second MOSFET, lead frame portion 110c may serve as a common gate terminal for the first MOSFET and the second MOSFET, and lead frame portion 110d may serve as a common source sense terminal for the first MOSFET and the second MOSFET. In this example, the second substrate may also include a metal pattern similar to the metal pattern 125 to facilitate connection from an opposite side of the package 100 (e.g., with respect to the first MOSFET and the second MOSFET). Figure 1 Thus, the package 100 can be said to implement double-sided cooling. In some embodiments, the metal pattern of the second substrate can be coupled to (e.g., soldered to) a power pattern (e.g., a power plane) (e.g., a ground plane) of a printed circuit board (PCB) on which the package 100 is implemented. Figure 9 shown).

[0026] Figure 2 It shows that you can Figure 1 Schematic diagram of a circuit 200 implemented in a semiconductor device package. Figure 2 As shown, the circuit 200 may include terminals 210a, 210b, 210c, and 210d, a first power semiconductor device (eg, MOSFET) 240, and a second power semiconductor device (eg, MOSFET) 250. Figure 2The power semiconductor devices 240 and 250 in FIG. 1 are shown as MOSFET devices by way of example, but in some embodiments, the first power semiconductor device 240 may include a diode, an insulated gate bipolar transistor (IGBT), a bipolar transistor, and / or a MOSFET device. Similarly, the second power semiconductor device 250 may include a diode, an insulated gate bipolar transistor (IGBT), a bipolar transistor, and / or a MOSFET device.

[0027] In some embodiments, power semiconductor devices 240 and 250 can be implemented on respective first and second semiconductor dies, wherein each semiconductor die can be coupled to a respective substrate (e.g., a respective DBM substrate). For example, each semiconductor die can be flip-chip mounted on a respective substrate. In this example, each semiconductor die can also be coupled to a respective side of a DAP pad of a leadframe portion (e.g., portion 110a of leadframe 110 discussed above).

[0028] like Figure 2 As shown, in circuit 200, terminals 210a to 210d are each common to both power semiconductor devices 240 and 250. Figure 2 In an example embodiment, terminal 210a can be a common drain terminal, terminal 210b can be a common source terminal, terminal 210c can be a common gate terminal, and terminal 210d can be a common source sense terminal. In an example embodiment, terminal 210a can be implemented by lead frame portion 110a, terminal 210b can be implemented by lead frame portion 110b, terminal 210c can be implemented by lead frame portion 110c, and terminal 210d can be implemented by lead frame portion 110d. In some embodiments (for example, where power semiconductor devices 240 and 250 are implemented as IGBTs), terminal 210a can be a common collector terminal, terminal 210b can be a common emitter terminal, terminal 210c can be a common gate terminal, and terminal 210d can be a common emitter sense terminal. In some embodiments, the emitter sense terminal can be omitted (excluded, etc.).

[0029] Figure 3 It shows Figure 1 FIG. 1 is a cross-sectional view of an example embodiment of a semiconductor device package 100 . Figure 3 The view corresponds to Figure 1 The section line 3-3 is shown in FIG. Figure 3In the examples and figures of FIG, package 100 includes a leadframe portion 110a, a leadframe portion 110b, a DBM substrate 120, a molding compound 130, a first semiconductor die 340 (e.g., implementing a first power semiconductor device), and a second semiconductor die 350 (e.g., implementing a second power semiconductor device). For illustrative purposes, first semiconductor die 340 and second semiconductor die 350 will be described as implementing a first power MOSFET and a second power MOSFET, respectively. In some embodiments, different power semiconductor devices can be implemented by semiconductor die 340 and 350.

[0030] like Figure 3 As shown, leadframe portions 110a and 110b (and leadframe portions 110c and 110d, not shown) can include gull-wing signal leads. Such signal leads can provide good thermo-mechanical reliability for package 100. For example, such gull-wing leads are flexible, which can reduce damage to package 100 and / or reduce solder connections between the signal leads and a PCB (or another substrate) on which package 100 is disposed, or to an associated PCB or substrate to which the package is coupled or on which the package is disposed, due to thermal cycling of package 100 and / or due to mismatches in thermal expansion coefficients between materials contained in package 100.

[0031] like Figure 3 As shown, leadframe portion 110a can include a die attach pad (DAP) 310. In this example, a first side (e.g., a backside drain contact) of semiconductor die 340 can be coupled to (soldered to, etc.) a first side of DAP 310, and a first side (e.g., a backside drain contact) of semiconductor die 350 can be coupled to (soldered to, etc.) a second side of DAP 310. In this example, DAP 310 (and leadframe portion 110a) will serve as a common drain terminal for the MOSFETs of semiconductor die 340 and 350.

[0032] like Figure 3 As shown, in this example, the package 100 may further include a conductive (eg, copper) spacer 315 and a second DBM substrate 320. Figure 3 In the example embodiment of the package 100 shown, the second side of the semiconductor die 340 can be coupled to the bonding metal pattern 127 disposed on the first side of the DBM substrate 120. Similarly, the second side of the semiconductor die 350 can be coupled to the bonding metal pattern 327 disposed on the first side of the DBM substrate 320. In this example, the bonding metal patterns 127 and 327 (which are shown in FIG. Figure 4 、 Figure 5 and Figure 7B) may at least partially provide respective electrical connections between source terminals of semiconductor dies 340 and 350 and leadframe portion 110 b , respective electrical connections between gate terminals of semiconductor dies 340 and 350 and leadframe portion 110 c (not shown), and respective electrical connections between source terminals of semiconductor dies 340 and 350 and leadframe portion 110 d (not shown), for example, as a common source sense terminal. Figure 3 As shown, spacer 315 can be used to electrically couple the second substrate to leadframe portion 110b. In some embodiments, additional spacers can be used to couple (electrically couple) the second substrate to other corresponding leadframe portions (e.g., leadframe portions 110c and 110d). Spacer 315 (e.g., and additional spacers) allows semiconductor dies 340 and 350 to be connected to a single (e.g., multi-part) leadframe, such as leadframe 110, in addition to substrates 120 and 320 (e.g., such as the example substrates described herein). Such an arrangement can allow multiple power semiconductor devices (e.g., such as leadframe 110) to be implemented in a single semiconductor device package (such as package 100) or other semiconductor packages that include a single leadframe (such as leadframe 110). Figure 2 Implementation of the circuit shown).

[0033] exist Figure 3 In the example of FIG, the second substrate 320 located on the second side opposite the bonding metal pattern 327 may include a bonding metal pattern 325 that is exposed through the molding compound 130 similar to the bonding metal pattern 125 of the DBM substrate 120. The metal patterns 125 and 325 may facilitate double-sided cooling of the package 100, such as using the methods described herein. Depending on the specific implementation (e.g., the desired heat dissipation capability), different materials may be used for the substrates 120 and 320. For example, the substrates 120 and 320 may include ceramic, aluminum nitride, silicon nitride, aluminum oxide, beryllium oxide, etc. Further, due to the arrangement of the substrates 120 and 320 and their corresponding metal patterns 125 and 325, in this example, the metal pattern 125 is electrically isolated from the metal pattern 325. Furthermore, the metal patterns 125 and 325 are also electrically isolated from the metal patterns 127 and 325, as well as the semiconductor dies 340 and 350 and the lead frame 110. As described herein, this may provide advantages in high voltage applications, such as efficiency with respect to PCB layout and / or proximity to other components of package 100 on the PCB.

[0034] like Figure 3 As shown, in this example, the molding compound 130, which may be an epoxy molding compound or other molding compound, may encapsulate (completely encapsulate) the spacer 315 (and Figure 3 Other spacers not shown in the figure), the first semiconductor die 340 and the second semiconductor die 350. Figure 3 As further shown, for this example, the molding compound 130 may partially encapsulate (at least partially encapsulate) the lead frame 110, the DBM substrate 120, and the DBM substrate 320. For example, the signal leads (e.g., gull-wing leads) of the lead frame 110 may extend outside the molding compound 130, while other portions of the lead frame 110 (including the DAP 310) are encapsulated within the molding compound 130. Furthermore, as shown in FIG. Figure 3 As shown, the metal pattern 125 (of the substrate 120 ) and the metal pattern 325 (of the substrate 320 ) are exposed through the molding compound, while other portions of the substrates 120 and 320 are encapsulated within the molding compound 130 .

[0035] For this example, Figure 3 Also shown is a creepage distance CD between lead frame portion 110a (e.g., the common drain of the MOSFET) and lead frame portion 110b (e.g., the common source of the MOSFET). In some embodiments, CD can be greater than or equal to 10 mm, greater than or equal to 15 mm, greater than or equal to 30 mm, greater than or equal to 25 mm, etc. In this example, because multiple power semiconductor dies (e.g., power MOSFETs) are coupled to opposite sides of DAP 310, package 100 can have very low electrical impedance (inductance), for example, due to the connection length and electrical path width between the MOSFET drain contacts of semiconductor dies 340 and 350.

[0036] Figure 4 is shown in accordance with an embodiment of the present invention. Figure 1 FIG. 1 is a diagram of a bonding metal pattern (eg, bonding metal pattern 127 ) of a substrate (eg, substrate 120 ) in a semiconductor device package 100 of FIG. Figure 5 is shown in accordance with an embodiment of the present invention. Figure 1 FIG. 1 is a diagram of a bonding metal pattern (eg, bonding metal pattern 327) of another substrate (eg, substrate 320) in a semiconductor device package of the semiconductor device package 100. For illustration and with Figures 1 to 3 For the purpose of comparison, Figures 1 to 3 The corresponding reference numerals for the elements of the illustrated package 100 are included in Figure 4 and Figure 5 However, no longer relative to Figure 4 and Figure 5 Discuss those elements in detail.

[0037] as Figure 1 , Figure 4 and Figure 5Aspects of the package 100 shown (e.g., patterns 127 and 327) may not be visible in example embodiments. For example, patterns 127 and 327 may be disposed within the interior of the package 100 (e.g., within the molding compound 130 and on opposite sides of the substrates 120 and 320 that are exposed through the molding compound 130). Thus, in embodiments of the package 100, such as in Figure 4 and Figure 5 In the example embodiment shown, patterns 127 and 217 would not be visible externally.

[0038] Figure 4 It is shown that it can be implemented in, for example Figure 1 and 3 The exemplary bonding metal pattern 127 on the substrate 120 is shown. Figure 5 It is shown that it can be implemented in, for example Figure 3 An exemplary bonding metal pattern 327 is shown on the substrate 320. Figure 3 Examples and discussion Figure 4 and Figure 5 , wherein the first semiconductor die 340 and the second semiconductor die 350 implement a first power MOSFET and a second power MOSFET, respectively. Figure 4 , the pattern 127 includes a first portion 127b, a second portion 127c and a third portion 127d. Similarly, referring to Figure 5 , the pattern 327 includes a first portion 327b, a second portion 327c and a third portion 327d. Figure 4 and Figure 5 As can be seen, in some embodiments, patterns 127 and 327 can have mirror symmetry. This mirror symmetry can allow semiconductor dies 340 and 350 having the same layout to be used in package 100 and connected to lead frame portions 110b, 110c, and 110b, such as Figure 4 and Figure 5 As shown (eg, to implement circuit 200 ).

[0039] For example, in this example, portions 127 b and 327 b of patterns 125 and 325 can be electrically coupled to respective source connections of the MOSFETs of semiconductor dies 340 and 350 and can also be electrically coupled to (soldered to, etc.) leadframe portion 110 b (e.g., with or without conductive spacers, depending on the particular embodiment and / or the particular substrate and leadframe). Portions 127 c and 327 c of patterns 125 and 325 can be electrically coupled to respective gate connections of semiconductor dies 340 and 350 and can also be electrically coupled to (soldered to, etc.) leadframe portion 110 c (e.g., with or without conductive spacers, depending on the particular embodiment and / or the particular substrate and leadframe). Moreover, portions 127 d and 327 d of patterns 125 and 325 may be electrically coupled to respective source connections of semiconductor dies 340 and 350 and may also be electrically coupled to (soldered to, etc.) lead frame portion 110 d as a source sense terminal (e.g., with or without conductive spacers, depending on the particular embodiment and / or the particular substrate and lead frame).

[0040] Figure 6A is a diagram illustrating a power semiconductor die 600 that may be implemented in embodiments of semiconductor device packages described herein, such as package 100. In this example, as in the examples discussed above, semiconductor die 600 may include a power MOSFET device and may be used to implement, for example, Figures 3 to 5 The semiconductor dies 340 and 350 are as shown in FIG. Figure 6A As shown, die 600 can have a gate connection 610 centrally located along one edge of die 600. Die 600 can also include multiple source connections 620 on the same side of die 600 as gate connection 610, with drain contacts on the back side of die 600. Figure 6B As shown, turning the die 600 upside down results in the gate connection 610 being along the Figure 6A The edges of the die 600 discussed are in the same relative position (e.g., centrally located). By arranging the source connections 620 of the die 600 so that they are properly aligned with the metal patterns 127 (e.g., portions 127 b and 127 d) and 327 (e.g., portions 327 b and 327 d), semiconductor dies having the same layout and mirror-symmetric patterns 127 and 327 can be used to implement the package 100, such as in the embodiments described herein.

[0041] 7A to 7C is a diagram illustrating a direct bonded metal (DBM) substrate that may be included in a semiconductor device package according to an embodiment. For example, 7A to 7C By way of example it is shown Figure 5 The embodiment of the substrate 320 shown. Figure 7AAs shown, a bonding metal pattern 325 (eg, for heat dissipation) may be provided on the first side of the substrate 320. Figure 7B As shown, metal pattern 327 (including portions 327b, 327c, and 327d) may be disposed on a second side of substrate 320, wherein the second side of substrate 320 is opposite to the first side of substrate 320. For example, Figure 7C 3. The pattern 325 is shown disposed on a first side of the substrate 320, while the pattern 327 is disposed on an opposite side of the substrate 320, resulting in the pattern 325 being electrically isolated from the pattern 327. In some embodiments, Figure 4 The substrate 120 of EMBODIMENT 1 (and in embodiments of the package 100 ) may be similarly implemented, wherein the bonding metal pattern 127 of the substrate 120 is mirror-symmetrical to the bonding metal pattern 327 .

[0042] Figure 8 is a diagram illustrating a lead frame strip 800 including a plurality of lead frames 110 according to an embodiment, each of which may be included in a semiconductor device package (eg, an embodiment of package 100). Figure 8 In the figure, the dotted box 810 is used to indicate the process of assembling the manufacturing process (such as Figure 10 1 and 3. DBM substrates (such as substrates 120 and 320) and semiconductor dies coupled to those substrates may be coupled to leadframe 110 in the process shown. Figure 1 and Figures 3 to 5 The portions of the lead frame 110 shown (e.g., portions 110a to 110d) may also be indicated in FIG. Figure 8 However, in Figure 8 , the leadframe 110 is shown in a leadframe strip 800 of the leadframe 110 (eg, prior to trimming and forming) (eg, to define individual signal leads and / or to form gull-wing shaped signal leads).

[0043] Figure 9 is a diagram illustrating a semiconductor device package (eg, an embodiment of package 100 ) coupled to a PCB 900 according to an embodiment. Figure 9 , showing the implementation after being coupled to (eg, soldered to) PCB 900. Figure 3 The package 100 shown. Figure 9 As shown, a signal lead (eg, a gull-wing signal lead) may be soldered to the PCB 900 using solder connections 920. Figure 9As shown, the bonding metal pattern 325 of the substrate 320 can be coupled to a PCB power pattern (e.g., a PCB power plane) 910 of the PCB 900. In some embodiments, the PCB power pattern 910 can be electrically grounded (e.g., can be the ground plane of the PCB 900). In this example, the PCB power pattern 910 can improve heat dissipation of the package 100 and, together with a heat sink that can be coupled to the bonding metal pattern 125 of the substrate 120, can provide effective double-sided cooling for the package 100.

[0044] Figure 10 1 is a diagram illustrating a method 1000 of producing a semiconductor device package such as described herein according to an embodiment. For illustrative purposes, relative to producing a semiconductor device package such as described herein, Figure 1 and Figures 3 to 5 The method 1000 is described with reference to the embodiment of the package 100 shown. Figure 1 and Figures 3 to 5 Method 1000 is described. In some embodiments, method 1000 can be used to produce semiconductor device packages having other configurations. In some embodiments, one or more of the operations of method 1000 can be performed using an appropriate alignment tool or fixture. Further, for example, leadframes 110 of leadframe strip 800 can be used together to produce multiple semiconductor device packages.

[0045] In method 1000, a first subassembly may be produced through operations 1005 to 1025. Further, in method 1000, a second subassembly may be produced through operations 1030 to 1045. At operation 1050, the two subassemblies may be combined (coupled, mated, etc.) to form a single (integrated) assembly.

[0046] exist Figure 10 In operation 1005, a first subassembly can be produced starting with a substrate 120. At operation 1010, a solder print pattern 1012 can be formed on the bonding metal pattern 127 of the substrate 120. In some embodiments, the solder print at operation 1010 can be performed using a high lead (high Pb) content solder paste (e.g., a lead content greater than 85%), a sintering material, or other conductive material for coupling the first semiconductor die 340 to the substrate 120. At operation 1015, the semiconductor die 340 can be flip-chip mounted on the solder print of operation 1010, and a reflow operation can be performed to couple (electrically and securely) the semiconductor die 340 to the substrate 120.

[0047] At operation 1020, a solder preform or solder paste 1022 may be placed on the lead frame 110 (eg, on portions 110a through 110d, as shown). Figure 10). In some embodiments, the solder preform or solder paste 1022 of operation 1020 can include tin (Sn)-silver (Ag)-copper (Cu) solder (SAC solder preform or paste). The solder preform or solder paste 1022 of operation 1020 can have a lower melting point than the solder, sintering material, or other material used in operation 1010. This difference in melting point can prevent the material from operation 1010 from reflowing again when the material from operation 1020 (and operation 1045) is reflowed at operation 1050 to form an integrated assembly. At operation 1025, the substrate 120 and the semiconductor die 340 can be flip-chip mounted onto the solder preform or solder paste 1022.

[0048] In method 1000, the second subassembly can be produced starting with substrate 320 at operation 1030. At operation 1035, a solder print pattern 1037 can be formed on the bonding metal pattern 327 of substrate 320. In some embodiments, the solder print at operation 1030 (as in operation 1010) can be performed using a high lead (high Pb) content solder paste (e.g., a lead content greater than 85%), a sintering material, or other conductive material for coupling the first semiconductor die 350 to the substrate 320. At operation 1040, the semiconductor die 350 can be flip-chip mounted on the solder print of operation 1035. Further, at operation 1040, a spacer 1042 (for forming corresponding electrical connections between the bonding metal pattern 327 and the lead frame portions 110b to 110d) can be placed on the corresponding portion of the solder printing of operation 1035, and a reflow operation can be performed to couple (electrically and fixedly couple) the semiconductor die 350 and the spacer 1042 to the substrate 320.

[0049] At operation 1045, a solder preform or solder paste 1047 can be placed over the die 350 and the spacer 1042. As with operation 1020, in some embodiments, the solder preform or solder paste 1047 of operation 1045 can include a SAC solder preform or solder paste, and thus the solder preform or solder paste 1047 of operation 1045 has a melting point lower than the melting point of the solder, sintering material, or other material used at operation 1035 (and operation 1010). This difference in melting point can prevent the material from operations 1010 and 1035 from reflowing again when the material from operation 1020 (and operation 1045) is reflowed at operation 1050 to form an integrated assembly.

[0050] At operation 1050, the subassembly from operation 1025 and the subassembly from operation 1045 may be aligned with one another in the arrangement shown in operation 1050 of method 1000 (e.g., using an alignment fixture). A reflow operation may then be performed (e.g., at the lower melting point of the materials used in operations 1020 and 1045). The reflow at operation 1050 may produce an integrated assembly including the two subassemblies discussed above. At operation 1060, a molding operation may be performed to encapsulate the integrated assembly of operation 1050 (such as shown in operation 1060 of method 1000) in a molding compound 130 (e.g., an epoxy or other molding compound). At operation 1065, grinding may be performed to remove a thickness G of the molding compound 130, for example, to expose the bonding metal pattern 125 of the substrate 120. Figure 10 , the signal leads of the semiconductor device package 100 are not shown for operations 1060 and 1065. After the grinding operation at 1065, further operations (e.g., singulation, cleaning, deburring, desizing, electrical testing, etc.) may be performed at operation 1070 to complete the fabrication of the semiconductor device package 100 of this example.

[0051] In a general aspect, a semiconductor device package may include a leadframe having a first portion, a second portion, and a third portion; a first semiconductor die having a first side coupled to a first side of the first portion of the leadframe; and a second semiconductor die having a first side coupled to a second side of the first portion of the leadframe. The semiconductor device package may further include a first substrate having a first side coupled to the second side of the first semiconductor die, the first side of the first substrate further coupled to the first side of the second portion of the leadframe and the first side of the third portion of the leadframe; and a second substrate having a first side coupled to the second side of the second semiconductor die, the first side of the second substrate further coupled to the second side of the second portion of the leadframe and the second side of the third portion of the leadframe.

[0052] Implementations can include one or more of the following features.For example, the first semiconductor die can include a first power transistor device; and the second semiconductor die can include a second power transistor device electrically connected in parallel with the first power transistor device.

[0053] The first power transistor device may be a first metal oxide field effect transistor (MOSFET); and the second power transistor device may be a second MOSFET. The first portion of the lead frame may be electrically coupled to a drain terminal of the first MOSFET and a drain terminal of the second MOSFET. The second portion of the lead frame may be electrically coupled to a source terminal of the first MOSFET and a source terminal of the second MOSFET. The third portion of the lead frame may be electrically coupled to a gate terminal of the first MOSFET and a gate terminal of the second MOSFET.

[0054] The lead frame may include a fourth portion.The fourth portion of the lead frame may be electrically coupled to the source sense terminal of the first MOSFET and the source sense terminal of the second MOSFET.

[0055] The first power transistor device may be a first insulated gate bipolar transistor (IGBT); and the second power transistor device may be a second IGBT. The first portion of the lead frame may be electrically coupled to a collector terminal of the first IGBT and a drain terminal of the second IGBT. The second portion of the lead frame may be electrically coupled to an emitter terminal of the first IGBT and an emitter terminal of the second IGBT. The third portion of the lead frame may be electrically coupled to a gate terminal of the first IGBT and a gate terminal of the second IGBT.

[0056] The first semiconductor die may include a first metal oxide field effect transistor (MOSFET); and the second semiconductor die may include a second MOSFET. The first portion of the lead frame may be electrically coupled to a drain terminal of the first MOSFET and a drain terminal of the second MOSFET. The second portion of the lead frame may be electrically coupled to a source terminal of the first MOSFET via the first substrate, and may be electrically coupled to a source terminal of the second MOSFET via the second substrate and the first spacer. The third portion of the lead frame may be electrically coupled to a gate terminal of the first MOSFET via the first substrate, and may be electrically coupled to a gate terminal of the second MOSFET via the second substrate and the second spacer.

[0057] The lead frame may include a fourth portion. The fourth portion of the lead frame may be electrically coupled to the source sense terminal of the first MOSFET via the first substrate, and may be electrically coupled to the source sense terminal of the second MOSFET via the second substrate and the third spacer.

[0058] In general terms, a semiconductor device package may include a first direct bonded metal (DBM) substrate and a first semiconductor die mounted on the first DBM substrate in a flip-chip manner. The semiconductor device package may further include a second DBM substrate; and a second semiconductor die mounted on the second DBM substrate in a flip-chip manner. The semiconductor device package may also include a leadframe having a first portion including a die attach pad (DAP), a second portion, and a third portion. The first semiconductor die may be coupled to a first side of the DAP. The second semiconductor die may be coupled to a second side of the DAP. The first DBM substrate may be coupled to a first side of the second portion of the leadframe and a first side of the third portion of the leadframe. The second DBM substrate may be coupled to a second side of the second portion of the leadframe via a first spacer, and coupled to a second side of the third portion of the leadframe via a second spacer.

[0059] Embodiments can include one or more of the following features. For example, the first semiconductor die can include a first metal oxide field effect transistor (MOSFET). The second semiconductor die can include a second MOSFET. The DAP can be electrically coupled to a drain terminal of the first MOSFET and a drain terminal of the second MOSFET. The second portion of the lead frame can be electrically coupled to a source terminal of the first MOSFET via the first DBM substrate and to a source terminal of the second MOSFET via the second DBM substrate. The third portion of the lead frame can be electrically coupled to a gate terminal of the first MOSFET via the first DBM substrate and to a gate terminal of the second MOSFET via the second DBM substrate.

[0060] The lead frame may include a fourth portion. The fourth portion of the lead frame may be electrically coupled to the source sense terminal of the first MOSFET via the first DBM substrate and electrically coupled to the source sense terminal of the second MOSFET via the third spacer and the second DBM substrate.

[0061] It should be understood that in the foregoing description, when an element such as a layer, region or substrate is mentioned as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is mentioned as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there are no intermediate elements or layers. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the specific embodiments, elements shown as being directly on an element, directly connected to, or directly coupled to can be mentioned in this manner. The claims of this application may be revised to describe the exemplary relationships described in the specification or shown in the drawings.

[0062] As used in this specification, singular forms may include plural forms unless the context clearly indicates otherwise. Spatially relative terms (e.g., above, above, above, below, below, below, below, on top of, below, etc.) are intended to encompass different orientations of the device in use or operation, in addition to the orientations shown in the drawings. In some embodiments, the relative terms above and below may include vertically above and vertically below, respectively. In some embodiments, the term adjacent can include lateral adjacent or horizontal adjacent.

[0063] Some embodiments may be implemented using various semiconductor processing and / or packaging technologies. Some embodiments may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates including, but not limited to, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc.

[0064] Although certain features of the described embodiments have been described as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented by way of example only and not limitation, and that various changes in form and detail may be made. Except for mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein can include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A semiconductor device package, comprising: a lead frame having a first portion, a second portion, and a third portion; a first semiconductor die having a first side coupled to a first side of the first portion of the leadframe; a second semiconductor die having a first side coupled to a second side of the first portion of the leadframe; a first substrate comprising a ceramic, the first substrate having a first side coupled to the second side of the first semiconductor die, the first side of the first substrate further coupled to the first side of the second portion of the leadframe and the first side of the third portion of the leadframe; a second substrate comprising ceramic, the second substrate having a first side coupled to the second side of the second semiconductor die, the first side of the second substrate further coupled to the second side of the second portion of the leadframe and the second side of the third portion of the leadframe; and a molding compound that completely encapsulates the first semiconductor die and the second semiconductor die; and partially encapsulates the lead frame, the first substrate, and the second substrate, The lead frame includes a plurality of signal leads disposed outside the molding compound, and The second side of the first substrate and the second side of the second substrate are exposed through the molding compound.

2. The semiconductor device package of claim 1 , wherein the first portion of the lead frame comprises a die attach pad, The first semiconductor die is coupled to a first side of the die attach pad, and The second semiconductor die is coupled to a second side of the die attach pad.

3. The semiconductor device package according to claim 1, wherein: The first semiconductor die includes a first power transistor device; and The second semiconductor die includes a second power transistor device electrically connected in parallel with the first power transistor device.

4. The semiconductor device package according to claim 1, wherein: the second side of the first substrate being electrically isolated from the first side of the first substrate; The second side of the second substrate is electrically isolated from the first side of the second substrate; and The second side of the first substrate is electrically isolated from the second side of the second substrate.

5. The semiconductor device package according to claim 1, wherein: The second side of the first substrate and the second side of the second substrate are configured to dissipate heat generated by the first semiconductor die and the second semiconductor die.

6. The semiconductor device package according to claim 1, wherein: the first portion of the leadframe comprising a first plurality of signal leads disposed along a first edge of the semiconductor device package, each signal lead of the first plurality of signal leads having a corresponding circuit board contact surface; the second portion of the leadframe comprising a second plurality of signal leads disposed along a second edge of the semiconductor device package, each signal lead of the second plurality of signal leads having a corresponding circuit board contact surface; and A shortest distance between a contact surface of the first plurality of signal leads and a contact surface of the second plurality of signal leads is greater than 10 millimeters.

7. The semiconductor device package according to claim 1, wherein: The second substrate is coupled to the second side of the second portion of the lead frame via a first spacer; and The second substrate is coupled to a second side of the third portion of the lead frame via a second spacer.

8. A semiconductor device package, comprising: a first directly bonded metal substrate; a first semiconductor die mounted on the first direct bonded metal substrate in a flip-chip manner; a second directly bonded metal substrate; a second semiconductor die mounted on the second direct bonded metal substrate in a flip-chip manner; and a lead frame having a first portion including a die attach pad, a second portion, and a third portion, the first semiconductor die coupled to a first side of the die attach pad; the second semiconductor die coupled to a second side of the die attach pad, The first direct bond metal substrate is coupled to a first side of the second portion of the lead frame and a first side of the third portion of the lead frame, The second direct-bonded metal substrate is coupled to the second side of the second portion of the lead frame via a first spacer and to the second side of the third portion of the lead frame via a second spacer, and The first spacer is vertically arranged relative to the second side of the second part of the lead frame between the second directly bonded metal substrate and the second side of the second part of the lead frame, and the second spacer is vertically arranged relative to the second side of the third part of the lead frame between the second directly bonded metal substrate and the second side of the third part of the lead frame.

9. The semiconductor device package according to claim 8, wherein: The first direct-bonded metal substrate is a first direct-bonded copper substrate; and The second direct-bonded metal substrate is a second direct-bonded copper substrate.

10. The semiconductor device package according to claim 8, wherein: The first semiconductor die is mounted on the metal pattern of the first direct-bonded metal substrate in a flip-chip manner; and The second semiconductor die is mounted on the metal pattern of the second direct-bonded metal substrate in a flip-chip manner, The second metal pattern directly bonded to the metal substrate is mirror-symmetrical to the metal pattern directly bonded to the metal substrate.

11. A method for producing a semiconductor device package, the method comprising: Construct the first subassembly, including: coupling a first side of a first semiconductor die to a first direct bond metal substrate; coupling the second side of the first semiconductor die to the first side of the first leadframe portion; coupling the first direct bond metal substrate to a first side of a second leadframe portion; and coupling the first direct bond metal substrate to a second side of a third leadframe portion; Construct the second subassembly, including: coupling the first side of the second semiconductor die to the second direct bond metal substrate; coupling a first spacer to the second direct-bonded metal substrate; and coupling a second spacer to the second direct bonded metal substrate; and Constructing an assembly by coupling the second subassembly to the first subassembly, comprising: coupling a second side of the second semiconductor die to a second side of the first leadframe portion; coupling the first spacer to the second side of the second leadframe portion; and coupling the second spacer to the second side of the third leadframe portion, The first spacer is vertically arranged relative to the second side of the second lead frame portion between the second directly bonded metal substrate and the second side of the second lead frame portion, and the second spacer is vertically arranged relative to the second side of the third lead frame portion between the second directly bonded metal substrate and the second side of the third lead frame portion.

12. The method according to claim 11, wherein: The first subassembly and the second subassembly are each constructed using a first conductive material having a first melting point; the second subassembly being coupled to the first subassembly using a second conductive material having a second melting point less than the first melting point; The first conductive material is one of a sintered material or a lead-containing solder material; and The second conductive material is a lead-free solder material.

13. The method according to claim 11, further comprising: The assembly is molded with a molding compound such that: The first semiconductor die, the second semiconductor die, and the first direct bonded metal substrate are completely encapsulated in the molding compound; and The lead frame and the second direct-bonded metal substrate are partially encapsulated in the molding compound, the lead frame includes a plurality of signal leads at least partially disposed outside the molding compound, and a surface of the second direct-bonded metal substrate is exposed outside the molding compound; and The molding compound is ground to expose a surface of the first direct-bonded metal substrate through the molding compound.

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