Wide bandgap power semiconductor device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor devices, and discloses a wide bandgap power semiconductor device and a preparation method thereof. The method comprises: providing a substrate layer of a first conductivity type; forming a first doped region which is deep into the substrate layer and comprises a plurality of doped layers which are sequentially nested from outside to inside, wherein the doping concentrations of the plurality of doped layers are sequentially increased from outside to inside; forming a second doped region in the doped layer on the innermost side of the first doped region; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface of the substrate layer. According to the invention, the first doped region which is located between the substrate layer and the second doped region and has the doping concentration gradually increased from outside to inside is formed through a mode of multiple times of ion implantation, so that transverse electric field constraint is constructed, transverse depletion of a channel region and a short channel effect under the condition of large voltage are inhibited, the channel width is reduced, and the performance of the device is improved. And the device performance and reliability are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically to wide-bandgap power semiconductor devices and their fabrication methods. Background Technology

[0002] Wide bandgap semiconductor materials, with their superior physical and electrical properties, have become one of the core directions for the research and application of next-generation semiconductor devices. Silicon carbide (SiC), as a typical wide bandgap semiconductor material, possesses numerous outstanding advantages, including a large bandgap, high thermal conductivity, high breakdown field strength, high electron saturation velocity, and strong radiation resistance. Compared to traditional silicon-based devices, SiC devices exhibit significant advantages in energy conversion efficiency, power density, operating temperature, and environmental adaptability. They have irreplaceable application value and broad market prospects in critical fields with stringent device performance requirements, such as photovoltaic power generation, electric vehicles, and aerospace. Among various SiC devices, silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) are increasingly widely used due to their simple driving, fast switching speed, and low conduction loss, and have a huge market potential.

[0003] However, with the rapid iteration and upgrading of semiconductor technology, the continuous improvement of device integration has become an inevitable trend in the industry. The size of chip cells is being continuously reduced. When the channel size of SiC MOSFETs is reduced to less than 0.5μm, a series of significant microscopic physical effects will inevitably occur inside the device, severely restricting further improvement in device performance and reliability. For example, firstly, a short-channel effect will occur. When the drain voltage increases, a significant potential difference will appear in the channel region, leading to lateral depletion of the channel, which in turn causes problems such as excessive leakage current and weakened gate control over the channel, seriously affecting the switching characteristics and control accuracy of the device. Secondly, the reduction in channel size increases the electric field strength inside the device, and the number of hot carriers increases significantly. The bombardment of hot carriers will exacerbate device damage, affecting the device's lifespan and long-term reliability. In addition, the subthreshold current increases accordingly, and the static power consumption of the device increases significantly, which violates the development trend of low power consumption in semiconductor devices. Especially in energy-sensitive applications such as photovoltaic power generation and electric vehicles, this problem will directly affect the energy utilization efficiency of the entire system. Summary of the Invention

[0004] This invention provides a wide bandgap power semiconductor device and its fabrication method to solve the problem that existing wide bandgap semiconductor devices cannot simultaneously achieve high integration and ensure device performance and reliability.

[0005] In a first aspect, the present invention provides a method for fabricating a wide-bandgap power semiconductor device, comprising: A substrate layer of a first conductivity type is provided, the substrate layer including opposing first and second surfaces; Multiple ion implantations are performed on one side of the first surface of the substrate to form a first doped region extending from the first surface into a portion of the substrate. The first doped region includes multiple doped layers nested sequentially from the outside to the inside, with the doping concentration of the multiple doped layers increasing sequentially from the outside to the inside. The first doped region is a second conductivity type opposite to the first conductivity type. A second doped region is formed in the innermost doped layer of the first doped region, and the second doped region is of the first conductivity type. An isolation layer is formed on the first surface, and the isolation layer is connected to the first doped region and the second doped region; Control electrodes are formed on the isolation layer; A first electrode is formed on a first surface, and the first electrode is connected to a first doped region and a second doped region; A second electrode is formed on the second surface of the substrate layer.

[0006] Beneficial effects: In the fabrication method of the wide bandgap power semiconductor structure of the present invention, a first doped region with a doping concentration gradient is formed between the substrate layer and the second doped region through multiple ion implantations. Furthermore, the doping concentration of the first doped region also increases gradient from the low concentration substrate layer to the high concentration second doped region. This structure with a doping concentration gradient in the channel width direction creates a lateral electric field constraint. On the one hand, it optimizes the electric field strength in the surface region and the electric field concentration effect under the gate oxide, avoiding a large potential difference in the channel region, reducing the static power consumption of the device, and helping to improve the switching efficiency of the device. It also prevents excessive hot carriers in the channel region from affecting the device's lifespan. On the other hand, it can also suppress lateral depletion in the channel region, helping to reduce the channel width, while reducing the risk of electric field breakdown and preventing leakage. It can also suppress the short-channel effect under high voltage conditions, improving device performance and reliability.

[0007] In one alternative embodiment, multiple ion implantations are performed on one side of the first surface of the substrate to form a first doped region extending from the first surface to a certain depth into the substrate, including: A first ion implantation is performed on one side of the first surface of the substrate to form a first doped layer within the substrate; A second ion implantation is performed on one side of the first surface of the substrate to form a second doped layer within the first doped layer; A third ion implantation is performed on one side of the first surface of the substrate to form a third doped layer within the second doped layer; the doping concentrations of the first, second, and third doped layers increase sequentially, and the doped area on the first surface and the doping depth in the longitudinal direction decrease sequentially.

[0008] Beneficial effects: Taking the first doped region as an example, three ion implantations with gradually decreasing range are performed on the first surface of the substrate to form a first doped region with three doped layers flush with the first surface inside the substrate. The doping concentration of the first, second, and third doped layers increases sequentially, consistent with the increasing concentration trend from the substrate to the second doped region. This reasonably reduces the channel potential difference of the second doped region near the first surface between the substrate and the second doped region, which helps to optimize the channel width reduction scheme, effectively suppress the short-channel effect, and help to achieve a balance between reducing the on-resistance of the device and stabilizing the threshold voltage, thus ensuring the performance and long-term reliability of the device.

[0009] In one alternative implementation, the implantation doses of the first ion implantation, the second ion implantation, and the third ion implantation increase sequentially, while the implantation energy decreases sequentially.

[0010] Beneficial effects: The above conditions can ensure that the doping concentration of the first doped layer, the second doped layer and the third doped layer increase sequentially and the depth decreases sequentially.

[0011] In one optional embodiment, the implantation energy range of the first ion implantation is 100 keV to 5 MeV, and the implantation dose range is 1E12cm. -2 ~1E18cm -2 The second ion implantation has an implantation energy range of 100 keV to 5 MeV and an implantation dose range of 1E13 cm⁻¹. -2 ~1E18cm -2 The third ion implantation has an implantation energy range of 100 keV to 5 MeV and an implantation dose range of 3E13 cm⁻¹. -2 ~1E18cm -2 .

[0012] In one alternative embodiment, a first ion implantation is performed on one side of a first surface of the substrate layer to form a first doped layer within the substrate layer, including: A first mask layer is formed on the entire first surface of the substrate layer; The first mask layer is patterned to form a first mask structure with a first opening, and the first surface of the first opening is exposed. A first ion implantation is performed on one side of the first surface to form a first doped layer within the first surface exposed by the first opening.

[0013] In one alternative embodiment, a second ion implantation is performed on one side of the first surface of the substrate layer to form a second doped layer within the first doped layer, including: A second mask structure is formed on the first surface using a self-aligned process. The second mask structure has a second opening on the surface that exposes a portion of the first doped layer. A second ion implantation is performed on one side of the first surface to form a second doped layer within the first doped layer exposed by the second opening.

[0014] In one alternative embodiment, a third ion implantation is performed on one side of the first surface of the substrate layer to form a third doped layer within the second doped layer, including: A third mask structure is formed on the first surface using a self-aligned process. The third mask structure has a third opening on the surface that exposes a portion of the second doped layer. A second ion implantation is performed on one side of the first surface to form a third doped layer within the second doped layer exposed by the third opening.

[0015] Beneficial effects: The use of self-aligned process helps to reduce process steps and alignment errors, as well as save lithography costs, and can further effectively reduce the length of the channel region, thereby reducing the channel resistance.

[0016] In one optional embodiment, the first doped region and the second doped region constitute a cell structure, and the wide bandgap power semiconductor device includes a plurality of spaced cell structures; after the second doped region is formed in the innermost doped layer of the first doped region and before the isolation layer is formed on the first surface, the device further includes: A third doped region is formed in the substrate layer between adjacent cell structures. The thickness of the third doped region extends from the first surface into the substrate layer. The third doped region is of the first conductivity type and its doping concentration is less than that of the substrate layer. An isolation layer is adapted to cover the surface of the third doped region.

[0017] Beneficial effects: The doping concentration of the third doped region is greater than that of the substrate layer but less than that of the second doped region, and it is formed close to the first surface to serve as part of the device's drift region, connecting the channel and the second electrode, thereby achieving the effect of withstanding a larger breakdown voltage and controlling current flow.

[0018] In one alternative embodiment, after forming the control electrode on the isolation layer and before forming the first electrode on the first surface, the method further includes forming an insulating layer on the outside of the control electrode to isolate the control electrode from the first electrode.

[0019] Secondly, the present invention also provides a wide bandgap power semiconductor device, fabricated using the above-described method for fabricating a wide bandgap power semiconductor device, comprising: a substrate layer, a first doped region, a second doped region, an isolation layer, a control electrode, a first electrode, and a second electrode. The substrate layer includes opposing first and second surfaces and is of a first conductivity type. The first doped region extends from the first surface to a portion of the substrate layer and includes multiple doped layers nested sequentially from the outside in, with the doping concentration of the multiple doped layers increasing sequentially from the outside in. The first doped region is of a second conductivity type opposite to the first conductivity type. The second doped region is formed within the innermost doped layer of the first doped region and is of the first conductivity type. The isolation layer is formed on the first surface and is connected to the first and second doped regions. The control electrode is formed on the isolation layer. The first electrode is formed on the first surface and is connected to the first and second doped regions. The second electrode is formed on the second surface of the substrate layer.

[0020] Beneficial effects: The wide bandgap power semiconductor of the present invention features a doping concentration gradient in the first doped region located between the substrate layer and the second doped region. Furthermore, the doping concentration of the first doped region also increases gradient from the low concentration substrate layer to the high concentration second doped region. This structure, with a doping concentration gradient along the channel width, creates a lateral electric field constraint. On one hand, it avoids large potential differences in the channel region, reducing the device's static power consumption and improving its switching efficiency. It also prevents excessive hot carriers in the channel region from affecting the device's lifespan. On the other hand, it suppresses lateral depletion in the channel region, helping to reduce the channel width and lowering the risk of electric field breakdown, preventing leakage. It also suppresses short-channel effects under high voltage conditions, improving device performance and reliability. Attached Figure Description

[0021] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic flowchart of a method for fabricating a wide bandgap power semiconductor device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure after a first mask layer is provided on the substrate layer according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure after forming the first mask structure and the first doped layer according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure after forming the second mask structure and the second doped layer according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure after forming the third mask structure and the third doped layer according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after forming the fourth mask structure and the second doped region according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure after the third doped region is formed by removing the mask structure according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure after forming the isolation layer, control electrode, and insulating layer according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure after the first electrode is formed according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of a wide bandgap power semiconductor device after the formation of the second electrode, according to an embodiment of the present invention.

[0023] Explanation of reference numerals in the attached figures: 1. Substrate layer; 11. First surface; 12. Second surface; 2. First doped region; 21. First doped layer; 22. Second doped layer; 23. Third doped layer; 3. Second doped region; 4. Isolation layer; 5. Control electrode; 6. First electrode; 7. Second electrode; 8. Third doped region; 9. Insulating layer; 10. Cell unit; 100, First mask structure; 101, First opening; 100a, First mask layer; 200. Second mask structure; 201. Second opening; 300. Third mask structure; 301. Third opening; 400. Fourth mask structure; 401. Fourth opening. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] like Figures 1 to 10 As shown, this embodiment provides a method for fabricating a wide bandgap power semiconductor device. Figure 1 The diagram below illustrates the process of this preparation method, which includes the following steps: Step S101: Provide a substrate layer 1 of a first conductivity type, the substrate layer 1 including a first surface 11 and a second surface 12 opposite to each other.

[0026] like Figure 2 As shown, exemplarily, the substrate layer 1 in this embodiment can be a silicon carbide layer. The substrate layer 1 includes a first surface 11 and a second surface 12 disposed opposite to each other in the longitudinal direction, that is, the upper surface is the first surface 11 and the lower surface is the second surface 12. The first conductivity type can be an n-type conductivity type or a p-type conductivity type.

[0027] Step S102: Multiple ion implantations are performed on one side of the first surface 11 of the substrate layer 1 to form a first doped region 2 extending from the first surface 11 into a partial depth of the substrate layer 1; the first doped region 2 includes multiple doped layers nested sequentially from the outside to the inside, the doping concentration of the multiple doped layers increasing sequentially from the outside to the inside, and the first doped region 2 is a second conductivity type opposite to the first conductivity type.

[0028] like Figure 2 and Figure 5 As shown, by setting shielding in different areas on the first surface 11, gradually decreasing exposed areas are formed on the first surface 11, and multiple ion implantations are performed accordingly, ultimately forming a first doped region 2 with a doping concentration gradient within the substrate layer 1. That is, the formation of the first doped region 2 includes multiple doped layers nested from the outside to the inside. The upper surfaces of the multiple doped layers are all flush with the first surface 11. For example, the first doped layer formed has the largest lateral area and the deepest vertical depth, and the lateral area and vertical depth of the subsequently formed doped layers gradually decrease. Moreover, the projected area of ​​the later-formed doped layer is completely located inside the earlier-formed doped layer, so that the multi-layer doped layer presents a structural feature where the outer doped layer surrounds the inner doped layer, and the doping concentration of the multiple doped layers increases from the outside to the inside, so that the first doped region 2 as a whole presents a doped structure with a doping concentration gradient that increases from the outside to the inside. The first doped region 2 has a second conductivity type opposite to the first conductivity type of the substrate layer 1. Of the first conductivity type and the second conductivity type, one is an n-type conductivity type and the other is a p-type conductivity type. In this embodiment, the substrate layer 1 is an n-type conductivity type and the first doped region 2 is a p-type conductivity type as an example for explanation.

[0029] In step S103, a second doped region 3 is formed in the innermost doped layer of the first doped region 2, and the second doped region 3 is of the first conductivity type.

[0030] like Figure 6 and Figure 7As shown, similarly, by partially shielding the first surface 11 again, a portion of the innermost doped layer of the second doped region 3 is exposed. Then, ion implantation is performed again on one side of the first surface 11. This time, the implanted ions enter a portion of the second doped layer 22, forming a second doped region 3 in the longitudinal direction that extends from a portion of the innermost doped layer of the first doped region 2 into a portion of its thickness. The surface of the second doped region 3 is also flush with the first doped region 2. The conductivity type of the second doped region 3 is opposite to that of the first doped region 2, but the same as that of the substrate layer 1. However, the doping concentration of the second doped region 3 is greater than that of the substrate layer 1.

[0031] In other words, in the final formed first doped region 2 and second doped region 3, from the perspective of conductivity type, the first doped region 2 has multiple doped layers with the same conductivity type, all of which are p-type conductivity in this embodiment. The second doped region 3 is located inside the first doped region 2 and has the same conductivity type as the substrate layer 1 outside the first doped region 2, which is n-type conductivity in this embodiment. From the perspective of the arrangement in the substrate layer 1, each doped layer in the first doped region 2 presents a ring structure on the horizontal plane, with the inner doped layer located inside the outer doped layer, and the outer diameter of the inner doped layer being equal to the inner diameter of the inner doped layer. The second doped region 3 is further located inside the innermost doped layer, and its outer diameter is equal to the inner diameter of the innermost doped layer. Therefore, the first doped region 2 with a doping concentration gradient forms a channel between the substrate layer 1 and the second doped region 3 in the region near the first surface 11. On the one hand, compared with a single high doping concentration structure, the first doped region 2 with a doping concentration gradient in this embodiment is more matched with the doping concentration performance of the substrate layer 1 to the second doped region 3, avoiding a large potential difference in the channel region, which helps to improve the switching efficiency of the device, reduce the static power consumption of the device, and also avoid excessive hot carriers in the channel region affecting the lifetime. On the other hand, compared with a single low doping concentration structure, the first doped region 2 with a doping concentration gradient in this embodiment can suppress the lateral depletion of the channel region, which helps to reduce the channel width while avoiding leakage current, and can also suppress the short-channel effect under high voltage conditions.

[0032] In step S104, an isolation layer 4 is formed on the first surface 11, and the isolation layer 4 is connected to the first doped region 2 and the second doped region 3.

[0033] like Figure 8 As shown, an isolation layer 4 is formed on the first surface 11. The isolation layer 4 simultaneously covers portions of the first doped region 2 and the second doped region 3, thereby achieving connection with all doped layers in the first doped region 2 and the second doped region 3. In this embodiment, the isolation layer 4 can be a gate oxide layer formed of silicon oxide.

[0034] Step S105: Form a control electrode 5 on the isolation layer 4.

[0035] like Figure 8 As shown, a control electrode 5 made of metal material is disposed on the isolation layer 4. The control electrode 5 can be a gate or a base.

[0036] In step S106, a first electrode 6 is formed on the first surface 11, and the first electrode 6 is connected to the first doped region 2 and the second doped region 3.

[0037] like Figure 9 As shown, since the multiple doped layers in the first doped region 2 and the second doped region 3 are nested sequentially, the first electrode 6 can be set in other areas outside the doped region covered by the isolation layer 4 on the first surface 11. The first electrode 6 connects with each doped layer of the first doped region 2 and the second doped region 3. The first electrode 6 is also made of metal material.

[0038] Step S107: A second electrode 7 is formed on the second surface 12 of the substrate layer 1.

[0039] like Figure 10 As shown, a second electrode 7 is disposed on the entire surface of the second surface 12. The control electrode 5, the first electrode 6, and the second electrode 7 can be made of the same metal material or different metal materials. Of the first electrode 6 and the second electrode 7, one is the source or emitter, and the other is the drain or collector.

[0040] In the fabrication method of the wide bandgap power semiconductor structure in this embodiment, a first doped region 2 with a varying doping concentration is formed between the substrate layer 1 and the second doped region 3 through multiple ion implantations. Furthermore, the doping concentration of the first doped region 2 also increases gradually from the low concentration of the substrate layer 1 to the high concentration of the second doped region 3. This structure, with a varying doping concentration in the channel width direction, creates a lateral electric field constraint. On the one hand, this optimizes the electric field strength in the surface region and the electric field concentration effect under the gate oxide, avoiding a large potential difference in the channel region, reducing the static power consumption of the device, and helping to improve the switching efficiency of the device. It also prevents excessive hot carriers in the channel region from affecting the device's lifespan. On the other hand, it also suppresses lateral depletion in the channel region, helping to reduce the channel width, while reducing the risk of electric field breakdown and preventing leakage. It can also suppress the short-channel effect under high voltage conditions, improving device performance and reliability.

[0041] In one embodiment, taking the first doped region 2 as an example that includes three doped layers, the step S102, which involves multiple ion implantations on one side of the first surface 11 of the substrate layer 1 to form the first doped region 2 extending from the first surface 11 to a certain depth in the substrate layer 1, includes: Step S1021: First ion implantation is performed on one side of the first surface 11 of the substrate layer 1 to form a first doped layer 21 in the substrate layer 1. Step S1022: Perform a second ion implantation on one side of the first surface 11 of the substrate layer 1 to form a second doped layer 22 within the first doped layer 21. In step S1023, a third ion implantation is performed on one side of the first surface 11 of the substrate layer 1 to form a third doped layer 23 within the second doped layer 22; the doping concentrations of the first doped layer 21, the second doped layer 22 and the third doped layer 23 increase sequentially, and the doping area on the first surface 11 and the doping depth in the longitudinal direction decrease sequentially.

[0042] like Figures 2 to 6 As shown, three ion implantations with gradually decreasing range are performed on the first surface 11 of the substrate layer 1 to form a first doped region 2 with three doped layers flush with the first surface 11 inside the substrate layer 1. The doping concentrations of the first doped layer 21, the second doped layer 22, and the third doped layer 23 increase sequentially, consistent with the increasing concentration trend from the substrate layer 1 to the second doped region 3. This reasonably reduces the channel potential difference of the second doped region 3 in the region near the first surface 11 between the substrate layer 1 and the second doped region 3, which helps to optimize the channel width reduction scheme, effectively suppress the short-channel effect, and help to achieve a balance between reducing the on-resistance of the device and stabilizing the threshold voltage, thus ensuring the performance and long-term reliability of the device.

[0043] In one embodiment, the implantation doses of the first ion implantation, the second ion implantation, and the third ion implantation are sequentially increased and the implantation energy is sequentially decreased, so as to ensure that the doping concentrations of the first doped layer 21, the second doped layer 22, and the third doped layer 23 are sequentially increased and their depths are sequentially decreased.

[0044] Specifically, in one embodiment, the implantation energy range of the first ion implantation is 100 keV to 5 MeV, and the implantation dose range is 1E12cm. -2 ~1E18cm -2 The second ion implantation has an implantation energy range of 100 keV to 5 MeV and an implantation dose range of 1E13 cm⁻¹. -2 ~1E18cm -2 The third ion implantation has an implantation energy range of 100 keV to 5 MeV and an implantation dose range of 3E13 cm⁻¹. -2 ~1E18cm -2 .

[0045] In other words, the implantation energy ranges for the first, second, and third ion implantations in this embodiment are the same. This does not mean that the ion implantation energies of these three rounds are identical. This is because ion implantation to form a doped layer usually involves multiple implantations with varying energy peaks. For example, the first ion implantation includes multiple continuous implantations at different energies to obtain a stable first doped layer 21. Therefore, the first, second, and third ion implantations can be performed multiple times within the aforementioned range to obtain three doped layers with decreasing depths. The implantation energy range is 100 keV to 5 MeV, which helps ensure that the depth of each doped layer in the first doped region 2 is appropriate, ensuring the device's switching performance. Similarly, the dosages of the three rounds of ion implantation are determined within their respective ranges to determine an appropriate gradient range. Specific values ​​can be determined for devices with different requirements, as long as the goal is to obtain three doped layers with gradually increasing doping concentrations.

[0046] In one embodiment, such as Figure 2 and Figure 3 As shown, step S1021, which involves performing a first ion implantation on one side of the first surface 11 of the substrate 1 to form a first doped layer 21 within the substrate 1, includes: Step S1021a: A first mask layer 100a is formed on the entire first surface 11 of the substrate layer 1.

[0047] like Figure 2 As shown, exemplarily, the aforementioned substrate 1 may be an epitaxially formed silicon carbide layer, and the first mask layer 100a may be a hard mask that completely covers the first surface 11 of the substrate 1.

[0048] Step S1021b: The first mask layer 100a is patterned to form a first mask structure 100 with a first opening 101, and the first surface 11 of the first opening 101 is exposed.

[0049] like Figure 3 As shown, by way of example, the first mask layer 100a is patterned and etched to form a first opening 101 corresponding to the region where the first doped region 2 is located, for forming the path of the first ion implantation.

[0050] In step S1021c, a first ion implantation is performed on one side of the first surface 11 to form a first doped layer 21 within the first surface 11 exposed by the first opening 101.

[0051] like Figure 3 As shown, a p-type first ion implantation is performed on one side of the first surface 11 to form a first doped layer 21 with a certain depth in the substrate layer 1 corresponding to the first opening 101, which is also the first p-well.

[0052] In summary, a hard mask can be used to pattern the first mask structure 100 through photolithography and etching. Hard masks are convenient for forming high-precision target patterns, and the process is simple and efficient.

[0053] In one embodiment, such as Figure 4 As shown, step S1022, which involves performing a second ion implantation on one side of the first surface 11 of the substrate layer 1 to form a second doped layer 22 within the first doped layer 21, includes: In step S1022a, a second mask structure 200 is formed on the first surface 11 using a self-aligned process. The second mask structure 200 has a second opening 201 that exposes a portion of the surface of the first doped layer 21.

[0054] For example, a self-aligned process can be used to directly form the second mask structure 200 inside the first mask structure 100, forming a second opening 201 with an area smaller than the first opening 101. The second opening 201 exposes a portion of the surface of the first doped layer 21. Using a self-aligned process eliminates the need to remove the previously formed first mask structure 100, reducing process steps and alignment errors, helping to save photolithography costs, and further effectively reducing the length of the channel region, thereby reducing channel resistance. Alternatively, after removing the first mask structure 100, a new hard mask layer can be grown to form the second mask structure 200, achieving high-precision second mask structure 200 forming.

[0055] In step S1022b, a second ion implantation is performed on one side of the first surface 11 to form a second doped layer 22 within the first doped layer 21 exposed by the second opening 201.

[0056] Similarly, a second p-type ion implantation is performed on one side of the first surface 11, forming a second doped layer 22 with a certain depth, i.e., a second p-well, in the first doped layer 21 corresponding to the second opening 201. At this time, the original rectangular first doped layer is formed into a rectangular second doped layer 22, and the first doped layer 21 with a ring structure is located outside the second doped layer 22.

[0057] In one embodiment, such as Figure 5 As shown, step S1023, which involves performing a third ion implantation on one side of the first surface 11 of the substrate layer 1 to form a third doped layer 23 within the second doped layer 22, includes: In step S1023a, a third mask structure 300 is formed on the first surface 11 using a self-aligned process. The third mask structure 300 has a third opening 301 that exposes a portion of the surface of the second doped layer 22.

[0058] Similarly, by way of example, a self-aligned process can be used to directly form a third mask structure 300 inside the second mask structure 200, forming a third opening 301 with an area smaller than the second opening 201. The surface of the second doped layer 22 exposed by the third opening 301 is eliminated. Using a self-aligned process eliminates the need to remove the previously formed first mask structure 100 and second mask structure 200, reducing process steps and alignment errors, helping to save photolithography costs, and further effectively reducing the length of the channel region, thereby reducing the channel resistance. Of course, after removing the first mask structure 100 and the second mask structure 200, a new hard mask can be grown to form the third mask structure 300, achieving high-precision forming of the third mask structure 300.

[0059] In step S1023b, a second ion implantation is performed on one side of the first surface 11 to form a third doped layer 23 within the second doped layer 22 exposed by the third opening 301.

[0060] Similarly, a p-type third ion implantation is performed on one side of the first surface 11, forming a third doped layer 23 with a certain depth in the second doped layer 22 corresponding to the third opening 301, which is also the third p-well. At this time, the original rectangular second doped layer is formed into a rectangular third doped layer 23 and the second doped layer 22 with a ring structure in the horizontal cross section outside the third doped layer 23.

[0061] Based on this, a rectangular second doped region 3 is formed within the third doped layer 23 through the fourth mask structure 400 and the fourth opening 401, ultimately resulting in a first doped region 2 with nested first doped layers 21, second doped layers 22, and third doped layers 23, as shown below. Figure 6 As shown; then remove all mask structures to expose the entire first surface 11, as shown. Figure 7 As shown.

[0062] It is known that, as Figures 7 to 10 As shown, the first doped region 2 and the second doped region 3 of the above-mentioned heavy doping constitute a cell structure, and the wide bandgap power semiconductor device includes a plurality of cell structures spaced apart in the horizontal direction.

[0063] Based on this, in one embodiment, such as Figure 7 As shown, after step S103 of forming the second doped region 3 in the innermost doped layer of the first doped region 2, and before step S104 of forming the isolation layer 4 on the first surface 11, the method further includes: A third doped region 8 is formed in the base layer 1 between adjacent cell structures. The thickness of the third doped region 8 extends from the first surface 11 into the base layer 1. The third doped region 8 is of the first conductivity type and its doping concentration is less than that of the base layer 1. The isolation layer 4 is adapted to cover the surface of the third doped region 8.

[0064] For example, the surface of the region where the cell structure is located can be blocked by a new mask structure, and then light doping can be performed in the region between the cell structures to form a third doped region 8 in the substrate layer 1 with a doping concentration greater than that of the substrate layer 1 and less than that of the second doped region 3. The surface of the third doped region 8 is flush with the first surface 11, and the depth can be consistent with the depth of the cell structure. The third doped region 8 has the same conductivity type as the substrate layer 1 and the second doped region 3.

[0065] The third doped region 8 can serve as part of the device's drift region, connecting the channel and the second electrode 7. It has the function of withstanding a large breakdown voltage and controlling current flow. For example, the third doped region 8 can optimize the device's breakdown voltage performance by adjusting the doping concentration and length. When the device is in the off state, the third doped region 8 can deplete the carriers, forming a wide depletion layer, thereby withstanding a high reverse voltage. In addition, the third doped region 8 also works with the channel region to control the current flow. When the device is turned on, electrons enter the third doped region 8 from the source through the channel and then flow to the drain. The conductivity of the third doped region 8 affects the device's on-resistance and current capability.

[0066] In one embodiment, such as Figure 8 and Figure 9 As shown, after step S105 of forming control electrode 5 on isolation layer 4 and before step S106 of forming first electrode 6 on first surface 11, the method further includes: forming insulating layer 9 on the outside of control electrode 5 to isolate control electrode 5 and first electrode 6.

[0067] For example, the insulating layer 9 can be an insulating material such as silicon oxide to effectively protect the control electrode 5 and ensure that the control electrode 5 can efficiently control the doped region inside the device.

[0068] like Figure 10As shown, this embodiment also provides a wide bandgap power semiconductor device, fabricated using the aforementioned method for fabricating wide bandgap power semiconductor devices. The device includes: a substrate layer 1, a first doped region 2, a second doped region 3, an isolation layer 4, a control electrode 5, a first electrode 6, and a second electrode 7. The substrate layer 1 includes a first surface 11 and a second surface 12 facing each other, and the substrate layer 1 is of a first conductivity type. The first doped region 2 extends from the first surface 11 to a certain depth into the substrate layer 1, and the first doped region 2 includes multiple doped layers nested sequentially from the outside in, with the doping concentration of the multiple doped layers increasing sequentially from the outside in. The first doped region 2 is of a second conductivity type opposite to the first conductivity type. The second doped region 3 is formed within the innermost doped layer of the first doped region 2, and the second doped region 3 is of the first conductivity type. The isolation layer 4 is formed on the first surface 11 and is connected to the first doped region 2 and the second doped region 3. The control electrode 5 is formed on the isolation layer 4. The first electrode 6 is formed on the first surface 11 and is connected to the first doped region 2 and the second doped region 3. The second electrode 7 is formed on the second surface 12 of the substrate layer 1.

[0069] In this embodiment of the wide bandgap power semiconductor, the doping concentration gradient of the first doped region 2 located between the substrate layer 1 and the second doped region 3 varies. Furthermore, the doping concentration of the first doped region 2 also increases gradually from the low concentration of the substrate layer 1 to the high concentration of the second doped region 3. This structure, with a doping concentration gradient variation in the channel width direction, can, on the one hand, avoid a large potential difference in the channel region, reduce the static power consumption of the device, and help improve the switching efficiency of the device. It can also prevent excessive hot carriers in the channel region from affecting the lifespan of the device. On the other hand, it can also suppress lateral depletion in the channel region, which helps to reduce the channel width, reduce the risk of electric field breakdown, avoid leakage, and suppress the short-channel effect under high voltage conditions, thereby improving device performance and reliability.

[0070] Further functional descriptions of the above structures are the same as those of the corresponding embodiments described above, and will not be repeated here.

[0071] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for fabricating a wide bandgap power semiconductor device, characterized in that, include: A substrate layer (1) of a first conductivity type is provided, the substrate layer (1) including opposing first surfaces (11) and second surfaces (12); Multiple ion implantations are performed on one side of the first surface (11) of the substrate layer (1) to form a first doped region (2) extending from the first surface (11) to a partial depth of the substrate layer (1); the first doped region (2) includes multiple doped layers nested sequentially from the outside to the inside, the doping concentration of the multiple doped layers increasing sequentially from the outside to the inside, and the first doped region (2) is a second conductivity type opposite to the first conductivity type; A second doped region (3) is formed in the innermost doped layer of the first doped region (2), and the second doped region (3) is of the first conductivity type; An isolation layer (4) is formed on the first surface (11), and the isolation layer (4) is connected to the first doped region (2) and the second doped region (3); A control electrode (5) is formed on the isolation layer (4); A first electrode (6) is formed on the first surface (11), and the first electrode (6) is connected to the first doped region (2) and the second doped region (3); A second electrode (7) is formed on the second surface (12) of the substrate layer (1).

2. The method for fabricating a wide bandgap power semiconductor device according to claim 1, characterized in that, Multiple ion implantations are performed on one side of the first surface (11) of the substrate layer (1) to form a first doped region (2) extending from the first surface (11) to a certain depth into the substrate layer (1), including: A first ion implantation is performed on one side of the first surface (11) of the substrate layer (1) to form a first doped layer (21) within the substrate layer (1). A second ion implantation is performed on one side of the first surface (11) of the substrate layer (1) to form a second doped layer (22) within the first doped layer (21). A third ion implantation is performed on one side of the first surface (11) of the substrate layer (1) to form a third doped layer (23) within the second doped layer (22); the doping concentrations of the first doped layer (21), the second doped layer (22) and the third doped layer (23) increase sequentially, and the doping area on the first surface (11) and the doping depth in the longitudinal direction decrease sequentially.

3. The method for fabricating a wide bandgap power semiconductor device according to claim 2, characterized in that, The implantation dose increases sequentially for the first ion implantation, the second ion implantation, and the third ion implantation, while the implantation energy decreases sequentially.

4. The method for fabricating a wide bandgap power semiconductor device according to claim 3, characterized in that, The implantation energy range of the first ion implantation is 100 keV to 5 MeV, and the implantation dose range is 1E12cm. -2 ~1E18cm -2 The second ion implantation has an implantation energy range of 100 keV to 5 MeV and an implantation dose range of 1E13 cm⁻¹. -2 ~1E18cm -2 The third ion implantation has an implantation energy range of 100 keV to 5 MeV and an implantation dose range of 3E13 cm⁻¹. -2 ~1E18cm -2 .

5. The method for fabricating a wide bandgap power semiconductor device according to claim 2, characterized in that, The first ion implantation on one side of the first surface (11) of the substrate layer (1) to form a first doped layer (21) within the substrate layer (1) includes: A first mask layer (100a) is formed on the entire surface of the first surface (11) of the base layer (1). The first mask layer (100a) is patterned to form a first mask structure (100) with a first opening (101), the first opening (101) exposing a portion of the first surface (11). A first ion implantation is performed on one side of the first surface (11) to form a first doped layer (21) within the first surface (11) exposed by the first opening (101).

6. The method for fabricating a wide bandgap power semiconductor device according to claim 2, characterized in that, A second ion implantation is performed on one side of the first surface (11) of the substrate layer (1) to form a second doped layer (22) within the first doped layer (21), including: A second mask structure (200) is formed on the first surface (11) using a self-aligned process. The second mask structure (200) has a second opening (201) that exposes a portion of the surface of the first doped layer (21). A second ion implantation is performed on one side of the first surface (11) to form a second doped layer (22) within the first doped layer (21) exposed by the second opening (201).

7. The method for fabricating a wide bandgap power semiconductor device according to claim 2, characterized in that, A third ion implantation is performed on one side of the first surface (11) of the substrate layer (1) to form a third doped layer (23) within the second doped layer (22), including: A third mask structure (300) is formed on the first surface (11) using a self-aligned process. The third mask structure (300) has a third opening (301) that exposes a portion of the surface of the second doped layer (22). A second ion implantation is performed on one side of the first surface (11) to form a third doped layer (23) within the second doped layer (22) exposed by the third opening (301).

8. The method for fabricating a wide bandgap power semiconductor device according to any one of claims 1-7, characterized in that, The first doped region (2) and the second doped region (3) constitute a cell structure, and the wide bandgap power semiconductor device includes a plurality of such cell structures spaced apart; after the second doped region (3) is formed in the innermost doped layer of the first doped region (2), and before the isolation layer (4) is formed on the first surface (11), the device further includes: A third doped region (8) is formed in the base layer (1) between adjacent cell structures. The third doped region (8) extends from the first surface (11) to a depth of the thickness of the base layer (1). The third doped region (8) is of a first conductivity type and its doping concentration is less than that of the base layer (1). The isolation layer (4) is adapted to cover the surface of the third doped region (8).

9. The method for fabricating a wide bandgap power semiconductor device according to claim 8, characterized in that, After the control electrode (5) is formed on the isolation layer (4) and before the first electrode (6) is formed on the first surface (11), the method further includes: An insulating layer (9) is formed on the outside of the control electrode (5) to isolate the control electrode (5) from the first electrode (6).

10. A wide bandgap power semiconductor device, fabricated using the method for fabricating a wide bandgap power semiconductor device according to any one of claims 1-9, characterized in that, include: The substrate (1) includes opposing first surfaces (11) and second surfaces (12), and the substrate (1) is of a first conductivity type; The first doped region (2) extends from the first surface (11) to a certain depth into the substrate layer (1); the first doped region (2) includes a plurality of doped layers nested from the outside to the inside, the doping concentration of the plurality of doped layers increasing from the outside to the inside, and the first doped region (2) is a second conductivity type opposite to the first conductivity type; The second doped region (3) is formed in the innermost doped layer of the first doped region (2), and the second doped region (3) is of the first conductivity type; An isolation layer (4) is formed on the first surface (11), and the isolation layer (4) is connected to the first doped region (2) and the second doped region (3); A control electrode (5) is formed on the isolation layer (4); A first electrode (6) is formed on the first surface (11), and the first electrode (6) is connected to the first doped region (2) and the second doped region (3); The second electrode (7) is formed on the second surface (12) of the substrate layer (1).

Images