Clock circuit system, computing chip, computing power board and data processing device

Abstract

The present disclosure relates to a clock circuit system, a computing chip, a computing power board, and a data processing device. The clock circuit system includes a main clock circuit and a local clock circuit. The main clock circuit includes a plurality of cascaded clock driver circuits, and each clock driver circuit includes one or more delay elements that delay a clock signal. The local clock circuit includes a first input terminal coupled to a first port of the main clock circuit; a second input terminal coupled to a second port of the main clock circuit; and a logic gate element. There is at least one delay element of the main clock circuit between the first port and the second port. The present disclosure can generate a pulse signal with good performance using a streamlined clock circuit system.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic circuits, and more particularly to a clock circuit system, as well as a computing chip, a computing power board, and a data processing device that apply the clock circuit system. Background Art

[0002] Adopting a pipeline structure is a common method in chip design. Using a pipeline structure can effectively improve the efficiency / throughput of executing data processing tasks. In the field of general-purpose CPUs, it is usually a pipeline related to instruction execution, so the processing times of each stage of the pipeline structure are not exactly the same. However, in many fields that rely on pure hardware computing (such as data processing, artificial intelligence (AI) computing, etc.), strict timing requirements are usually imposed. For example, the time of each stage of the pipeline needs to be precisely controlled to be consistent. Therefore, in these fields, the clock circuit system for providing a clock signal to the pipeline structure often has a specific structure and function.

[0003] When performing computing-intensive data processing tasks such as data processing and artificial intelligence (AI) computing, computing hardware often needs to run for a long time. For example, a data processing device may need to continuously execute a large number of hash operations. Such computing hardware will significantly consume power and bring corresponding costs, such as electricity costs. The power consumption ratio is defined as the power consumed per unit computing power of computing hardware, and it is one of the important performance indicators for measuring computing hardware. When the computing hardware includes or is implemented as a computing chip, the power consumption ratio can be reduced by reducing the number of components used in the computing chip. Advantageously, the chip area of the computing chip can also be reduced. Summary of the Invention

[0004] Embodiments of the present disclosure aim to generate a pulse signal with good performance using a streamlined clock circuit system, and the pulse signal can be used for a pipeline structure that executes computing-intensive data processing tasks.

[0005] According to a first aspect of the present disclosure, a clock circuit system is provided. The clock circuit system includes a master clock circuit and one or more local clock circuits. The master clock circuit includes a plurality of cascaded clock driving circuits, and each clock driving circuit includes one or more delay elements for delaying a clock signal. The master clock circuit is configured to drive the clock signal to propagate along the plurality of clock driving circuits. Each of the one or more local clock circuits is associated with a corresponding clock driving circuit in the master clock circuit and includes: a first input terminal coupled to a first port of the master clock circuit to draw a first clock signal from the master clock circuit; a second input terminal coupled to a second port of the master clock circuit to draw a second clock signal from the master clock circuit; and a logic gate element coupled to the first input terminal and the second input terminal and configured to generate a pulse signal based on the first clock signal and the second clock signal. Wherein, the second port is downstream of the first port in the master clock circuit, and at least one delay element in the corresponding clock driving circuit of the master clock circuit exists between the first port and the second port.

[0006] According to this first aspect of the present disclosure, the local clock circuit further includes one or more additional delay elements for delaying the second clock signal, and the one or more additional delay elements are disposed between the logic gate element and the second input terminal.

[0007] According to this first aspect of the present disclosure, the local clock circuit has one of the following various configurations: a first configuration, wherein the first port and the second port associated with the local clock circuit are in the same stage of clock driving circuits in the master clock circuit; a second configuration, wherein the first port and the second port associated with the local clock circuit are in two adjacent stages of clock driving circuits in the master clock circuit; or a third configuration, wherein at least one stage of clock driving circuits in the master clock circuit exists between the first port and the second port associated with the local clock circuit.

[0008] According to this first aspect of the present disclosure, the one or more local clock circuits include a first local clock circuit and a second local clock circuit, and the first local clock circuit and the second local clock circuit each have different configurations among the first configuration, the second configuration, and the third configuration.

[0009] According to this first aspect of the present disclosure, no delay element is disposed between the logic gate element and the first input terminal and the second input terminal of the local clock circuit.

[0010] According to this first aspect of the present disclosure, the logic gate element is selected from one of an AND gate, a NAND gate, an OR gate, and a NOR gate; and the selection of the logic gate element is determined based on at least the following: the type and number of the at least one delay element between the first port and the second port; the type and number of the delay elements between the logic gate element and the second input terminal; and / or the type of the required pulse signal.

[0011] According to this first aspect of the present disclosure, the one or more delay elements include at least one of a buffer and an inverter.

[0012] According to this first aspect of the present disclosure, the local clock circuit is coupled to a corresponding stage of pipeline circuit in a pipeline structure for performing data processing tasks to provide the pulse signal to the corresponding stage of pipeline circuit.

[0013] According to this first aspect of the present disclosure, the pulse signal is provided to one or more groups of registers in the corresponding stage of pipeline circuit, and an additional buffer or inverter is provided between the output terminal of the local clock circuit and each register in the one or more groups of registers.

[0014] According to this first aspect of the present disclosure, the register is a latch-type register, and the latch-type register can be triggered by a high-level pulse or a low-level pulse of the pulse signal.

[0015] According to this first aspect of the present disclosure, the data processing tasks include performing a hashing algorithm or performing AI calculations.

[0016] According to this first aspect of the present disclosure, the hashing algorithm includes the SHA-256 algorithm.

[0017] According to a second aspect of the present disclosure, a computing chip is disclosed, and the computing chip includes any one of the clock circuit systems as described herein.

[0018] According to a third aspect of the present disclosure, a computing power board is disclosed, and the computing power board includes the computing chip as described herein.

[0019] According to a fourth aspect of the present disclosure, a data processing device is disclosed, and the data processing device includes the computing power board as described herein.

[0020] According to various aspects of the present disclosure, a pulse signal with good performance can be generated with a streamlined clock circuit system and low power consumption. Other features and advantages of the present disclosure will become clear through the following detailed description of the exemplary embodiments of the present disclosure with reference to the accompanying drawings. Description of the Drawings

[0021] The accompanying drawings forming a part of the specification illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0022] Referring to the accompanying drawings, the present disclosure can be more clearly understood from the following detailed description, wherein:

[0023] Figure 1 A block diagram of a system according to an embodiment of the present disclosure is shown;

[0024] Figure 2 An exemplary configuration of a clock circuit system is shown;

[0025] Figure 3 An example of generating a pulse signal based on a first clock signal and a second clock signal having a delay between each other is shown;

[0026] Figures 4A - 4D An exemplary configuration of an improved clock circuit system is shown;

[0027] Figure 5 An exemplary configuration of a further improved clock circuit system is shown;

[0028] Figure 6 A schematic diagram of a pipeline structure that can be used to implement the SHA-256 algorithm is shown;

[0029] Figure 7 A schematic block diagram of a computing chip according to an embodiment of the present disclosure is shown;

[0030] Figure 8 A schematic block diagram of a computing power board according to an embodiment of the present disclosure is shown; and

[0031] Figure 9 A schematic block diagram of a data processing device according to an embodiment of the present disclosure is shown.

[0032] Note that in the embodiments described below, sometimes the same reference numerals are used commonly between different drawings to denote the same parts or parts having the same functions, and their repeated description is omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0033] For ease of understanding, the positions, sizes, and ranges, etc. of the various structures shown in the accompanying drawings and the like sometimes do not represent the actual positions, sizes, and ranges, etc. Therefore, the disclosed content is not limited to the positions, sizes, and ranges, etc. disclosed in the accompanying drawings and the like. In addition, the accompanying drawings do not have to be drawn to scale, and some features may be enlarged to show the details of specific components. Detailed Embodiments

[0034] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that: Unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure.

[0035] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way a limitation on the present disclosure or its application or use. That is, the circuits and methods for implementing the hashing algorithm herein are shown in an exemplary manner to illustrate different embodiments of the circuits or methods in the present disclosure, and are not intended to be limiting. Those skilled in the art will understand that they merely illustrate exemplary ways in which the present disclosure can be implemented, rather than exhaustive ways.

[0036] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the authorization specification.

[0037] Figure 1 A block diagram of a system 100 according to an embodiment of the present disclosure is shown. The system 100 may include a clock circuit system 1000, a clock source 2000, and a pipeline structure 3000. The clock circuit system 1000 may be coupled to the clock source 2000 and the pipeline structure 3000.

[0038] In the system 100, instead of providing a separate clock signal for each stage of the pipeline circuit of the pipeline structure 3000, the clock source 2000 provides an initial clock signal to the clock circuit system 1000, and the clock circuit system 1000 provides corresponding clock signals for each stage of the pipeline circuit of the pipeline structure 3000. To this end, the clock circuit system 1000 may be designed to include multiple stages of clock driving circuits, and each stage of the clock driving circuit may provide a clock signal for an associated stage of the pipeline circuit. This multiple-stage clock driving circuit of the clock circuit system 1000 may be referred to as a master clock circuit, or also as a "master clock tree". The master clock circuit may extend as the stages of the pipeline circuit of the pipeline structure extend.

[0039] Specifically, in Figure 1In the example, the main clock circuit of the clock circuit system 1000 may include a plurality of clock driving circuits 1100, 1200, 1300 connected in series. The initial clock signal provided by the clock source 2000 may be provided to the first-stage clock driving circuit 1100. The output clock signal of the first-stage clock driving circuit 1100 may be provided to the second-stage clock driving circuit 1200. The output clock signal of the second-stage clock driving circuit 1200 may be provided to the third-stage clock driving circuit 1300. The subsequent-stage clock driving circuit generates a new clock signal in response to receiving the clock signal of the previous-stage clock driving circuit. The clock signal generated by each stage of the clock driving circuit may be provided to the associated stage of the pipeline circuit. In this way, the main clock circuit enables the clock signal derived from the same initial clock signal to propagate through dozens or hundreds of stages of the clock driving circuits, thereby providing corresponding clock signals for each stage of the pipeline structure including dozens or even hundreds of stages of pipeline circuits. As Figure 1 shown, the clock driving circuits 1100, 1200, 1300 may provide corresponding clock signals to the pipeline circuits 3100, 3200, 3300 in the pipeline structure 3000, respectively.

[0040] To implement the function of driving and propagating the clock signal, each stage of the clock driving circuit of the main clock circuit may be configured to include one or more circuit elements connected in series. Within each stage of the clock driving circuit, the clock signal may sequentially propagate through these circuit elements. As Figure 1 shown, the clock driving circuit 1100 may include circuit elements 1110, 1120, 1130 connected in series in sequence, the clock driving circuit 1200 may include circuit elements 1210, 1220, 1230 connected in series in sequence, and the clock driving circuit 1300 may include circuit elements 1310, 1320, 1330 connected in series in sequence. These circuit elements may be active elements. The active elements may compensate for the power of the input signal, thereby maintaining the amplitude of the clock signal propagating through the clock driving circuit.

[0041] Typical active components for a clock driving circuit may include inverters and buffers. Those skilled in the art know that the output signal of an inverter has an opposite level phase relative to the input signal of the inverter. That is, in response to an input signal at a high level, the output signal of the inverter will be at a low level; while in response to an input signal at a low level, the output signal of the inverter will be at a high level. Different from an inverter, the output signal of a buffer has the same level phase relative to the input signal of the buffer. As needed, the circuit elements 1110, 1120, 1130 in the clock driving circuit 1100 can all be inverters, all be buffers, or any combination of inverters and buffers. Preferably, the clock driving circuit 1200 and the clock driving circuit 1300 should have the same configuration as the clock driving circuit 1100, which can maintain the consistency of each stage of the clock driving circuit, thus helping to ensure the precise timing of the clock signals provided by each stage of the clock driving circuit.

[0042] Note that the input-output response of actual circuit elements (such as inverters and buffers) will not be ideal. For example, there will be a certain delay in the response (output signal) of each circuit element relative to the excitation (input signal). Therefore, each of the circuit elements 1110, 1120, 1130, 1210, 1220, 1230, 1310, 1320, 1330 in the clock driving circuit will delay the clock signal passing through the circuit element. These circuit elements can also be referred to as delay elements. The delay characteristics of the circuit elements can be used to generate specific signals, which will be further described later.

[0043] In many scenarios, the clock signal directly output by the clock driving circuit of the master clock circuit cannot be directly used for the pipeline circuit. For example, the clock signal propagating along the master clock circuit is usually a square wave signal (e.g., a square wave with a duty cycle of 50%), while the pipeline circuit may employ latch-type registers. Latch-type registers need to be triggered by a pulse signal. A pulse signal is a signal that only has a short-time high-level state (or short-time low-level state) within each clock cycle. The square wave signal output by the master clock circuit is not suitable for directly triggering the latch-type registers in the pipeline circuit. In this case, the clock signal output by each stage of the clock driving circuit of the master clock circuit needs to be preprocessed before being provided to the pipeline circuit.

[0044] To preprocess the clock signal output by the clock driver circuit of the master clock circuit, the clock circuit system 1000 may further include local clock circuits 4100, 4200, and 4300. Each local clock circuit may be associated with a corresponding clock driver circuit and with a corresponding pipeline circuit. Different from the clock driver circuits in the master clock circuit being connected in series with each other, each local clock circuit may be respectively coupled between the corresponding clock driver circuit and the corresponding pipeline circuit. For example, the local clock circuit 4100 may be coupled between the clock driver circuit 1100 and the pipeline circuit 3100, the local clock circuit 4200 may be coupled between the clock driver circuit 1200 and the pipeline circuit 3200, and the local clock circuit 4300 may be coupled between the clock driver circuit 1300 and the pipeline circuit 3300. The local clock circuit may draw a clock signal from the corresponding clock driver circuit, preprocess the clock signal to generate an appropriate signal (e.g., a pulse signal), and provide the generated appropriate signal to the corresponding pipeline circuit. The following combines Figure 2 Specific examples of the configuration of the local clock circuit are described in detail, and in combination with Figures 4A - 4D And Figure 5 Improved embodiments regarding the configuration of the local clock circuit are further described.

[0045] It should be noted that Figure 1 The structure of the system 100 shown is merely exemplary. For example, although Figure 1 The pipeline structure 3000 in includes 3 levels of pipeline circuits, but the pipeline structure according to the embodiments of the present disclosure may include more or fewer pipeline circuits, such as 2 levels, 10 levels, 50 levels, or more than 100 levels of clock driver circuits. Correspondingly, the master clock circuit according to the embodiments of the present disclosure is not limited to including 3 clock driver circuits, but may include more or fewer clock driver circuits, such as 2, 10, 50, or more than 100 clock driver circuits. Figure 1 In, an additional module 1400 that receives the output clock signal of the clock driver circuit 1300 is represented by a box with ellipsis. The additional module 1400 may represent a plurality of clock driver circuits not specifically shown or may represent a tail-end load element. If the additional module 1400 represents a plurality of clock driver circuits not specifically shown, each clock driver circuit in the plurality of clock driver circuits will also include a plurality of series-connected circuit elements and may also have an associated local clock circuit.

[0046] In addition, Figure 1 The border of the clock circuit system 1000 in is shown as a dotted line, meaning Figure 1The boundaries shown are merely exemplary. For example, in an alternative embodiment, the clock source 2000 may be part of the clock circuit system 1000. In another alternative embodiment, the local clock circuits 4100, 4200, 4300 may be located inside the corresponding first-level pipeline circuits. However, from a functional perspective, such local clock circuits can still be regarded as part of the clock circuit system 1000.

[0047] Figure 2 An exemplary configuration of the clock circuit system 1000 is shown. Compared with Figure 1 ... Figure 2 The size of the local clock circuit 4200 is enlarged to specifically show the configuration of the local clock circuit 4200. As Figure 2 shown, the local clock circuit 4200 may include one or more delay elements 4221, 4222, 4223 and a logic gate element 4230. Each of the delay elements 4221, 4222, 4223 may be an inverter or a buffer. The input terminal 4211 of the local clock circuit 4200 may be coupled to the clock driving circuit 1200 associated with the local clock circuit 4200 in the main clock circuit, so as to receive the clock signal output by the clock driving circuit 1200. The logic gate element 4230 may be a logic gate element with two input terminals. A first signal path and a second signal path may exist between the input terminal 4211 and the two input terminals of the logic gate element 4230. The delay elements 4221, 4222, 4223 may be arranged on the second signal path. The clock signal received by the input terminal 4211 may be directly input to one input terminal of the logic gate element 4230 as a first clock signal via the first signal path, and may be input to the other input terminal of the logic gate element 4230 as a second clock signal via the delay elements 4221, 4222, 4223 on the second signal path. Due to the existence of the delay elements 4221, 4222, 4223, there will be a certain delay for the second clock signal relative to the first clock signal. The amount of this delay is associated with the delay elements 4221, 4222, 4223. The logic gate element 4230 may perform a logic operation on the first clock signal and the second clock signal that have a delay between each other, so as to generate a pulse signal. The generated pulse signal may be provided to the corresponding pipeline circuit (for example, Figure 1 the pipeline circuit 3200).

[0048] Figure 3 An example of generating a pulse signal PLS based on a first clock signal CLK1 and a second clock signal CLK2 that have a delay between each other is shown. As Figure 3As shown, both the first clock signal CLK1 and the second clock signal CLK2 can be square wave signals. Although both the first clock signal CLK1 and the second clock signal CLK2 are from the input terminal 4211, due to the existence of the delay elements 4221, 4222, and 4223, the second clock signal CLK2 can be in antiphase with the first clock signal CLK1, and the delay of the second clock signal CLK2 relative to the first clock signal CLK1 is d. The two signals CLK1 and CLK2 can be input into the logic gate element 4230. The logic gate element 4230 can be an AND gate (AND2). This AND gate performs a logical "AND" operation on CLK1 and CLK2 to obtain the signal PLS, that is, PLS = AND2(CLK1, CLK2). The obtained PLS is a high-level pulse signal, and its pulse width is d. A high-level pulse signal refers to a signal with a short-term high-level state.

[0049] The phase difference and delay between the first clock signal CLK1 and the second clock signal CLK2 are associated with the type and number of delay elements on the second signal path. If an odd number of inverters are provided on the second signal path, the obtained second clock signal CLK2 will have a phase opposite to that of the first clock signal CLK1. In addition, the delay of the second clock signal CLK2 relative to the first clock signal CLK1 depends on the sum of the delays of all the delay elements provided on the second signal path. It should be understood that although Figure 2 it is shown that the local clock circuit 4200 includes 3 delay elements, more or fewer delay elements can also be used. The pulse width of the obtained pulse signal is associated with the delay between the two input signals, and thus is also associated with the sum of the delays of all the delay elements provided on the second signal path.

[0050] It should be noted that although Figure 3 the obtained PLS is a high-level pulse signal, different logic gate elements (NAND2) can also be used to obtain a low-level pulse signal. The high-level pulse signal can be provided to a latch-type register that can be triggered by a high-level pulse, while the low-level pulse signal can be provided to a latch-type register that can be triggered by a low-level pulse.

[0051] It should also be noted that although Figure 3 the case where the first clock signal CLK1 and the second clock signal CLK2 are in antiphase is shown, in other embodiments, the first clock signal CLK1 and the second clock signal CLK2 may also be in phase. The type of logic gate element can be selected accordingly, such as an OR gate (OR2) or a NOR gate (NOR2).

[0052] In addition, although Figure 3The shown delay and pulse width are significant relative to the period width of the clock signal, but this is only for the purpose of clarity. In an actual circuit, the delay caused by the delay element and the pulse width of the generated pulse signal may be smaller relative to the period of the clock signal. For example, the delay caused by each delay element may be on the order of dozens of picoseconds, while one clock period of the clock signal may be on the order of several nanoseconds.

[0053] Although Figure 2 The shown local clock circuit 4200 can generate the pulse signal required by the pipeline circuit, but this local clock circuit still has room for improvement. The local clock circuit 4200 requires necessary delay elements to be set in the local clock circuit itself. These delay elements will occupy chip area and increase the power consumption of the chip. For a pipeline circuit including dozens or hundreds of stages (and correspondingly including dozens or hundreds of local clock circuits), the number of delay elements used cannot be ignored. Also, when the available chip area is limited or the total power is limited, it may not be possible to set enough delay elements in the local clock circuit. In this case, the delay d of the second clock signal CLK2 relative to the first clock signal CLK1 may be too small, which may result in the pulse width of the generated pulse signal being too narrow. The trigger register requires a minimum pulse width, and a wide pulse width helps to reliably trigger the register. If the pulse width of the pulse signal generated by the local clock circuit is too narrow, it may not be able to effectively trigger the register in the pipeline circuit, which may cause the pipeline circuit to fail to correctly execute the data processing task.

[0054] Figure 4A An exemplary configuration of an improved clock circuit system 1000A according to an embodiment of the present disclosure is shown. Similar to the previously described clock circuit system 1000, the clock circuit system 1000A may include a main clock circuit and one or more local clock circuits 4100, 4200, 4300. The main clock circuit may include a plurality of cascaded clock driver circuits 1100, 1200, 1300. The main clock circuit is configured to drive the clock signal to propagate along the plurality of clock driver circuits 1100, 1200, 1300. Each clock driver circuit may respectively include one or more circuit elements 1110, 1120, 1130, 1210, 1220, 1230, 1310, 1320, 1330, and these circuit elements can drive the propagation of the clock signal and on the other hand also cause a delay of the clock signal. Each of the local clock circuits 4100, 4200, 4300 in the clock circuit system 1000A is respectively associated with a corresponding clock driver circuit in the main clock circuit. The local clock circuits 4100, 4200, 4300 of the clock circuit system 1000A may have the same as Figure 2Example of different configurations. Hereinafter, the local clock circuit 4200 will be described as an example.

[0055] According to an embodiment of the present disclosure, the local clock circuit 4200 may have two different input terminals 4212 and 4213 for drawing a clock signal from the master clock circuit. The input terminal 4212 and the input terminal 4213 may be respectively coupled to a first port and a second port in the master clock circuit. The second port may be downstream of the first port in the master clock circuit, and there is at least one circuit element in the clock driving circuit of the master clock circuit between the first port and the second port that can cause a delay in the clock signal. In this configuration, the second clock signal drawn by the input terminal 4213 of the local clock circuit 4200 from the second port will have a delay relative to the first clock signal drawn by the input terminal 4212 from the first port. This delay is caused by one or more circuit elements in the clock driving circuit of the master clock circuit and does not depend on the delay elements in the local clock circuit 4200.

[0056] As Figure 4A shown, the input terminal 4212 of the local clock circuit 4200 may be coupled to the output terminal (first port) of the second circuit element 1220 in the clock driving circuit 1200 to draw the first clock signal, while the input terminal 4213 of the local clock circuit 4200 may be coupled to the output terminal (second port) of the third circuit element 1230 in the clock driving circuit 1200 to draw the second clock signal. There is a circuit element 1230 between the first port and the second port. Since the circuit element 1230 itself is a delay element (inverter or buffer), the clock signal output from the output terminal of the circuit element 1230 (i.e., the second clock signal drawn by the input terminal 4213) will have a certain delay relative to the clock signal output from the output terminal of the circuit element 1220 (i.e., the first clock signal drawn by the input terminal 4212).

[0057] According to an embodiment of the present disclosure, the local clock circuit 4200 may have a logic gate element 4230. The logic gate element 4230 may perform a logic operation on each input signal. The first clock signal and the second clock signal drawn by the input terminals 4212 and 4213 may be provided to the logic gate element 4230. One input terminal of the logic gate element 4230 may be connected to the input terminal 4212 through a first signal path to receive the first clock signal. The other input terminal of the logic gate element 4230 may be connected to the input terminal 4213 through a second signal path to receive the second clock signal. The logic gate element 4230 may be configured to perform a logic operation on the two input clock signals to generate a pulse signal, as regarding Figure 3As discussed above. One or more delay elements 4221, 4222, 4223 may be provided on the second signal path to further delay the second clock signal on the second signal path. In this way, the delay between the two clock signals received by the two input terminals of the logic gate element 4230 includes not only the delay caused by the delay elements 4221, 4222, 4223 in the local clock circuit 4200, but also additionally includes the delay caused by the circuit element 1230 in the clock driving circuit 1200. This increases the delay between the two clock signals received by the two input terminals of the logic gate element 4230 without adding delay elements. Accordingly, the pulse width of the pulse signal generated by the logic gate element 4230 is increased, so as to provide a better pulse signal for the pipeline circuit.

[0058] According to an embodiment of the present disclosure, the two input terminals 4212 and 4213 of the local clock circuit 4200 may be connected to any two other first port and second port on the clock driving circuit of the main clock circuit, as long as there is at least one circuit element in the clock driving circuit between the first port and the second port that can delay the clock signal. The first port and the second port may have various configurations.

[0059] As an exemplary configuration, the first port and the second port respectively coupled to the two input terminals 4212 and 4213 of the local clock circuit 4200 may be located in the same stage of the clock driving circuit of the main clock circuit. Figure 4A An embodiment of this exemplary configuration is shown. As an alternative embodiment, the input terminal 4212 of the local clock circuit 4200 may not be connected to the output terminal of the circuit element 1220, but to the output terminal of the circuit element 1210. In this case, the delay between the two clock signals received by the two input terminals of the logic gate element 4230 will further include the delay caused by the circuit element 1220, thereby further increasing the pulse width of the generated pulse signal.

[0060] As another exemplary configuration, the first port and the second port respectively coupled to the two input terminals 4212 and 4213 of the local clock circuit 4200 may be located in two adjacent stages of the clock driving circuit of the main clock circuit. Figure 4B An exemplary configuration of the improved clock circuit system 1000B is shown. As Figure 4B shown, the input terminal 4212 of the local clock circuit 4200 may be connected to the output terminal (first port) of the circuit element 1220 of the clock driving circuit 1200, while the input terminal 4213 of the local clock circuit 4200 may be connected to the output terminal (second port) of the circuit element 1310 of the adjacent clock driving circuit 1300.

[0061] As yet another exemplary configuration, there may be at least one stage of clock driver circuitry of the master clock circuit between a first port and a second port that are respectively coupled to two input terminals 4212 and 4213 of the local clock circuit 4200. Figure 4C An exemplary configuration of the improved clock circuit system 1000C is shown. As Figure 4C shown, the input terminal 4212 of the local clock circuit 4200 may be connected to the output terminal (first port) of the clock driver circuit 1100, and the input terminal 4213 of the local clock circuit 4200 may be connected to the output terminal (second port) of the circuit element 1310 of the clock driver circuit 1300. There is an entire one-stage clock driver circuit 1200 between the first port and the second port. This situation can be advantageous because it can utilize the existing output ports of the clock driver circuit without having to draw out a clock signal from inside the clock driver circuit and without affecting the load inside each stage of the clock driver circuit.

[0062] According to an embodiment of the present disclosure, the positions of the first port and the second port can be determined based on the nature of the desired pulse signal. The nature of the pulse signal may include pulse width, signal type, and so on. For example, the number of circuit elements of the clock driver circuit that should exist between the first port and the second port can be determined based on the desired pulse width of the pulse signal. When the desired pulse width is relatively wide, the first port and the second port can be spaced farther apart, so that there are more circuit elements that can cause delay between the two ports. When the type of the desired pulse signal is a high-level pulse signal, the positions of the first port and the second port can be selected such that the sum of the number of inverters between the first port and the second port and the number of inverters (if any) on the second signal path of the local clock circuit is odd, so that the two clock signals input to the logic gate element are inverted (for example, Figure 3 the situation shown).

[0063] In Figures 4A - 4C , the delay elements 4221, 4222, 4223 are drawn with dashed boxes, which means that one or more of them may not be necessary. Since the delay of one or more circuit elements in the master clock circuit has been introduced, one or more of the one or more delay elements 4221, 4222, 4223 inside the local clock circuit 4200 can be removed. For example, in Figure 4AIn [the circuit], the delay originally provided by components 4221, 4222, and 4223 can be provided by components 1230, 4221, and 4222. Thus, component 4223 can be removed while still meeting the delay requirements between the two clock signals input to logic gate component 4230. As another example, the delay originally provided by components 4221, 4222, and 4223 can be provided by components 1220, 1230, and 4221, thereby removing components 4222 and 4223. In some exemplary configurations, the delay elements inside local clock circuit 4200 can all be removed, as discussed below with respect to Figure 4D as described.

[0064] Figure 4D An exemplary configuration of an improved clock circuit system 1000D according to an embodiment of the present disclosure is shown. In Figure 4D this [configuration], the input terminal 4212 of local clock circuit 4200 can be coupled to the input terminal (the first port) of clock drive circuit 1200 to draw a first clock signal, while the input terminal 4213 of local clock circuit 4200 can be coupled to the output terminal (the second port) of the third circuit element 1230 in clock drive circuit 1200 to draw a second clock signal. Moreover, no delay elements are provided between logic gate component 4230 of local clock circuit 4200 and the input terminals 4212 and 4213 of local clock circuit 4200. In this example, the delay between the two clock signals received by the two input terminals of logic gate component 4230 can be entirely provided by components 1210, 1220, and 1230 in clock drive circuit 1200 of the master clock circuit, without the need to provide delay elements (such as 4221, 4222, 4223) in local clock circuit 4200. If the total delay of the circuit elements between the first port and the second port can provide a pulse signal with a sufficient pulse width, the Figure 4D configuration shown can be preferably adopted, which can eliminate the delay elements in the local clock circuit, thereby minimizing the footprint and power of the local clock circuit.

[0065] Compared with the example of Figure 2 , the advantages of clock circuit systems 1000A - 1000D exist in at least two aspects. On the one hand, without changing the arrangement of the delay elements in the local clock circuit, a greater delay can be provided, thereby obtaining a pulse signal with a wider pulse width. On the other hand, when the required delay remains unchanged, it is allowed to reduce the number of delay elements in the local clock circuit or remove them completely, which will significantly reduce power consumption, component cost, and chip area.

[0066] Figure 5 A schematic diagram of an improved clock circuit system 1000E according to an embodiment of the present disclosure is shown. Figure 5 The configuration of [this] is the same as that ofFigure 4D Similarly, the difference is that the output of the logic gate element 4230 is not directly provided to the pipeline circuit, but can be first provided to additional circuit elements 4241 and 4242. The circuit elements 4241 and 4242 can be inverters or buffers. As described previously, the circuit elements 4241 and 4242 can function as active elements to drive signals, thereby maintaining the amplitude of the output signal. The circuit elements 4241 and 4242 can provide their respective output signals to a corresponding set of elements (e.g., registers). In the case where there are a large number of registers in the pipeline circuit, Figure 5 such a configuration is advantageous. This is because the output signal provided by a single logic gate element 4230 may not be sufficient to drive a large number of registers. Therefore, it is necessary to use the active circuit elements 4241 and 4242 to convert the output signal provided by the single logic gate element 4230 into multiple output signals.

[0067] It should be noted that although Figure 5 two circuit elements 4241 and 4242 of the local clock circuit 4200 are shown, the local clock circuit 4200 can include more such circuit elements without limitation. Also, the local clock circuits 4100 and 4300 can each have similar circuit elements (not shown). Further, Figures 4A - 4D one or more local clock circuits of each clock circuit system in

[0068] In Figures 4A - 4D as well as Figure 5 the local clock circuit 4200 is taken as an example for discussion, and the local clock circuits 4100 and 4300 adopt the same configuration as the local clock circuit 4200, and the specific description of the local clock circuits 4100 and 4300 is omitted. However, it should be understood that each local clock circuit in the local clock circuits 4100, 4200, 4300 can adopt any of the above various exemplary configurations without limitation. For example, the local clock circuit 4100 can adopt the configuration described with respect to Figure 4A while the local clock circuit 4200 can adopt the configuration described with respect to Figure 4B and the local clock circuit 4300 can adopt the configuration described with respect to Figure 4C Other hybrid configurations are also possible.

[0069] According to an embodiment of the present disclosure, the logic gate element used by each local clock circuit can be one selected from an AND gate, a NAND gate, an OR gate, and a NOR gate. Those skilled in the art know that various devices and technologies can be used to implement the logic gate element without limitation.

[0070] According to embodiments of the present disclosure, the type of the selected logic gate element can be determined based on multiple factors, including but not limited to: the type (inverter or buffer), quantity, and delay amount of circuit elements between a first port and a second port connected to two input terminals of a local clock circuit; the type (inverter or buffer), quantity, and delay amount of delay elements on a second signal path of the logic gate element; the type of the required pulse signal (high-level pulse trigger or low-level pulse trigger), and so on. For example, if the sum of the number of inverters between the first port and the second port and the number of inverters on the second signal path is odd, an AND gate or a NAND gate can be selected. If the sum is even, an OR gate or a NOR gate can be selected. A logic gate element can be implemented by a combination of several logic gate elements. For example, an AND gate and a NAND gate can differ by one inverter, and an OR gate and a NOR gate can also differ by one inverter.

[0071] Various clock circuit systems 1000 according to embodiments of the present disclosure can be used in combination with a pipeline structure 3000. Driven by respective clock signals provided by the clock circuit system 1000, each stage of the pipeline circuit of the pipeline structure 3000 can perform various data processing tasks. Here, the data processing tasks include but are not limited to data storage, data operation, and so on.

[0072] According to embodiments of the present disclosure, the data processing tasks performed by the pipeline structure 3000 can include various compute-intensive tasks. Compute-intensive tasks require computing hardware to run for a long time and require a large number of pipeline circuits to be implemented on a computing chip to perform parallel computing. Therefore, they are sensitive to the performance, power consumption, and chip area of the clock signal. Advantageously, data processing tasks that can utilize the present disclosure include but are not limited to performing hash algorithm calculations or performing artificial intelligence (AI) calculations.

[0073] A hash algorithm is an algorithm that takes variable-length data as input and produces a fixed-length hash value as output. In a hash algorithm, input data of any length is padded so that the length of the padded data is an integer multiple of a certain fixed length (e.g., 512 bits), that is, the padded data can be divided into multiple data blocks with the above fixed length. The content of the padding bits includes the bit length information of the original data. Then the hash algorithm performs arithmetic processing on each fixed-length data block respectively, such as multiple rounds of operations including data expansion and / or compression operations. When all data blocks have been used, a final fixed-length hash value is obtained.

[0074] The hash algorithm executed by the pipeline structure 3000 may be the SHA-256 algorithm. Since 1993, the National Institute of Standards and Technology in the United States has designed and released multiple versions of the Secure Hash Algorithm (SHA). SHA-256 is exactly one of the secure hash algorithms with a hash length of 256 bits.

[0075] For a hash algorithm that includes multiple rounds of operations (such as the SHA-256 algorithm), a pipeline structure with multiple operation levels can be used to achieve high-speed operations. For example, when executing the SHA-256 algorithm, since 64 rounds of repeated operations are to be performed on each 512-bit data block, a 64-level pipeline structure can be adopted to perform parallel operations on 64 groups of data.

[0076] Figure 6 FIG. shows a schematic diagram of the pipeline structure 6000 that can be used to implement the SHA-256 algorithm. The pipeline structure 6000 may be a specific use case of the pipeline structure 3000 described above. To implement the SHA-256 algorithm, the pipeline structure 6000 may be a 32-level, 64-level, or 128-level pipeline. As Figure 6 shown, the t-th operation level, the (t + 1)-th operation level, and the (t + 2)-th operation level in the pipeline structure 6000 are divided by a dashed line. Each operation level can be implemented by a corresponding one-level pipeline circuit. Each operation level may also include operation logic. Each operation level may further include multiple registers A to H for storing intermediate values and multiple registers R0 to R15 for storing extended data respectively. One or more of these registers may be latch-type registers. During the process of executing the SHA-256 algorithm, the latch-type registers in each pipeline circuit in the pipeline structure 6000 can be triggered based on the corresponding pulse signals provided by the clock circuit system described above, so as to update the data stored therein. Depending on the type of the latch-type register, the pulse signal provided by the clock circuit system may be a high-level pulse signal or a low-level pulse signal. Preferably, in order to be able to trigger multiple registers in each operation level, these registers can be divided into one or more groups, and each group among them can be triggered by the output signal of the corresponding one of the Figure 5 multiple circuit elements shown (i.e., circuit elements 4241 and 4242).

[0077] The clock circuit system according to an embodiment of the present disclosure may be included in various devices, including but not limited to computing chips, computing power boards, data processing devices, etc. Since the clock circuit system according to an embodiment of the present disclosure is adopted, these devices can obtain multiple clock signals with a stable duty cycle at a low cost and with a simple circuit structure, thereby ensuring the performance of these devices when performing specific computing tasks.

[0078] Figure 7 FIG. 2 shows a schematic block diagram of a computing chip 7000 according to an embodiment of the present disclosure. The computing chip 7000 may include a clock circuit system 7100, a clock source 7200, and a pipeline structure 7300. The clock circuit system 7100 may be a specific embodiment of the clock circuit system described above (e.g., any one of 1000, 1000A, 1000B, 1000C, 1000D, 1000E). The clock source 7200 may be a specific embodiment of the clock source 2000 described above. The pipeline structure 7300 may be a specific embodiment of the pipeline structure 3000 or 6000 described above. The clock circuit system 7100 may be coupled to the clock source 7200 and the pipeline structure 7300. The clock circuit system 7100 may receive an initial clock signal from the clock source 7200 and generate a plurality of clock signals accordingly. The plurality of clock signals may be provided to the pipeline structure 7300 to perform a specific computing task. The specific computing task may be, for example, performing the SHA-256 algorithm. In Figure 7 FIG. 3, the clock source 7200 is shown in a dashed box, indicating that the clock source 7200 may also be located outside the computing chip 7000.

[0079] Figure 8 FIG. 8 shows a schematic block diagram of a computing power board 8000 according to an embodiment of the present disclosure. The computing power board 8000 may include one or more computing chips 8100. The computing chip 8100 may be a specific embodiment of the computing chip 7000. The plurality of computing chips 8100 may perform computing tasks in parallel.

[0080] Figure 9 FIG. 12 shows a schematic block diagram of a data processing device 9000 according to an embodiment of the present disclosure. The data processing device 9000 may be configured to perform the SHA-256 algorithm. The data processing device 9000 may include one or more computing power boards 9100. The computing power board 9100 may be a specific embodiment of the computing power board 8000. The plurality of computing power boards 9100 may perform computing tasks in parallel, such as performing the SHA-256 algorithm.

[0081] In all the examples shown and discussed herein, any specific values should be construed as merely exemplary and not as limitations. Thus, other examples of the exemplary embodiments may have different values.

[0082] In the specification and claims, words such as "front", "rear", "top", "bottom", "above", "below", etc., if present, are used for descriptive purposes and not necessarily to describe a fixed relative position. It should be understood that such words are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations different from those shown or otherwise described herein.

[0083] As used herein, the word "exemplary" means "serving as an example, instance, or illustration", rather than as a "model" to be precisely replicated. Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any theory, whether expressed or implied, given in the above technical field, background art, summary of the invention, or detailed description.

[0084] As used herein, the word "substantially" means including any minor variations caused by design or manufacturing defects, tolerances of devices or components, environmental effects, and / or other factors. The word "substantially" also allows for differences from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in an actual implementation.

[0085] The above description may refer to elements or nodes or features that are "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that one element / node / feature is directly connected (or directly communicates) to another element / node / feature electrically, mechanically, logically, or otherwise. Similarly, unless otherwise expressly stated, "coupled" means that one element / node / feature can be connected to another element / node / feature in a direct or indirect manner mechanically, electrically, logically, or otherwise to allow interaction, even if the two features may not be directly connected. That is, "coupled" is intended to encompass both direct and indirect connections of elements or other features, including connections using one or more intermediate elements.

[0086] It should also be understood that when the words "comprising / including" are used herein, it indicates the presence of the stated features, wholes, steps, operations, units, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, units, and / or components and / or their combinations.

[0087] Those skilled in the art should realize that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed among additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of a particular operation, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and substitutions are also possible. Therefore, the present specification and the drawings should be regarded as illustrative rather than restrictive.

[0088] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of the present disclosure. The embodiments disclosed herein can be combined arbitrarily without departing from the spirit and scope of the present disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A clock circuit system for providing a pulse signal to a pipeline structure that repetitively performs multiple rounds of hashing operations, the pipeline structure including multiple stages of pipeline circuits, each stage of pipeline circuit including one or more sets of latch-type registers, characterized in that, The clock circuit system includes: A main clock circuit, the main clock circuit including a plurality of cascaded clock driver circuits, each clock driver circuit including one or more delay elements for delaying a clock signal, the main clock circuit being configured to drive the clock signal to propagate along the plurality of clock driver circuits; and One or more local clock circuits, each local clock circuit in the one or more local clock circuits being associated with a corresponding clock driver circuit in the main clock circuit and connected to a corresponding stage of the multi-stage pipeline circuit, and each local clock circuit including: A first input terminal, coupled to a first port of the main clock circuit to draw a first clock signal from the main clock circuit; A second input terminal, coupled to a second port of the main clock circuit to draw a second clock signal from the main clock circuit; and A logic gate element, coupled to the first input terminal and the second input terminal, and configured to generate a pulse signal based on the first clock signal and the second clock signal, the pulse signal being a short pulse, and the width ratio of each short pulse to the clock period being less than 50%; Wherein, an output terminal of the logic gate element is coupled to a corresponding stage of the pipeline structure to supply the short pulse to one or more sets of latch-type registers in the corresponding stage of the pipeline circuit, such that the one or more sets of latch-type registers are triggered by the short pulse; Wherein, the second port is downstream of the first port in the main clock circuit, and at least one delay element in the corresponding clock driver circuit of the main clock circuit exists between the first port and the second port; Wherein, the width of the short pulse is at least partially based on the at least one delay element between the first port and the second port.

2. The clock circuit system according to claim 1, characterized in that, The local clock circuit further includes one or more additional delay elements for delaying the second clock signal, and the one or more additional delay elements are disposed between the logic gate element and the second input terminal.

3. The clock circuit system according to claim 1, wherein The local clock circuit has one of the following various configurations: A first configuration, wherein the first port and the second port associated with the local clock circuit are in the same stage of the clock driver circuit of the main clock circuit; A second configuration, wherein the first port and the second port associated with the local clock circuit are in two adjacent stages of the clock driver circuit of the main clock circuit; Or A third configuration, wherein at least one stage of the clock driver circuit of the main clock circuit exists between the first port and the second port associated with the local clock circuit.

4. The clock circuit system according to claim 3, wherein, The one or more local clock circuits include a first local clock circuit and a second local clock circuit, and the first local clock circuit and the second local clock circuit each have different configurations among the first configuration, the second configuration, and the third configuration.

5. The clock circuit system according to claim 1, characterized in that, No delay element is disposed between the logic gate element and the first input terminal and the second input terminal of the local clock circuit.

6. The clock circuit system according to claim 1, characterized in that, The logic gate element is selected from one of an AND gate, a NAND gate, an OR gate, and a NOR gate; and the selection of the logic gate element is determined based on at least the following: the type and number of the at least one delay element between the first port and the second port; the type and number of the delay element between the logic gate element and the second input terminal; and / or the type of the required short pulse.

7. The clock circuit system as described in claim 1, wherein The one or more delay elements include at least one of a buffer and an inverter.

8. The clock circuit system according to claim 1, wherein An additional buffer or inverter is provided between the output terminal of the logic gate element and each latch-type register in the one or more groups of latch-type registers.

9. The clock circuit system according to claim 8, wherein The short pulse is a high-level pulse or a low-level pulse.

10. The clock circuit system according to claim 1, characterized in that, The pipeline structure also performs artificial intelligence calculations.

11. The clock circuit system according to claim 1, characterized in that, The hashing algorithm includes the SHA-256 algorithm.

12. A computing chip, characterized in that, The computing chip includes the clock circuit system according to any one of claims 1-11.

13. A computing power board, characterized in that, It includes the computing chip according to claim 12.

14. A data processing device, characterized in that, It includes the computing power board according to claim 13.

Images