Display device

Abstract

The present disclosure relates to a display device, the display device comprising: a display substrate including a display area and a pad area provided on the periphery of the display area; and a display panel including at least one wiring pad provided in the pad area of the display substrate, wherein the wiring pad includes: a main pad portion extending in a first direction; a first protruding pad portion protruding from a first side of the main pad portion in a second direction intersecting the first direction; and a second protruding pad portion protruding from a second side of the main pad portion in the second direction, and the first protruding pad portion is arranged to be closer to the display area than the second protruding pad portion.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2019-0020781, filed on February 21, 2019, the content of which is incorporated herein by reference in its entirety. Technical Field

[0002] Exemplary embodiments of the present disclosure relate to a display device. Background Art

[0003] A display device visually displays data. The display device includes a substrate divided into a display area and a non-display area. In the display area, a plurality of pixels are disposed on the substrate, and in the non-display area, a plurality of pads are disposed on the substrate. A chip on film (“COF”) on which a driving circuit or the like is mounted is bonded to the pads that transmit driving signals to the pixels.

[0004] The COF includes a plurality of leads bonded to the pads, and the leads may be joined to individual pads. The joining of the leads may be performed using an ultrasonic bonding process. Summary of the Invention

[0005] However, when the degree of misalignment between the leads and the pads during the bonding process varies during the manufacture of each display device, the total bonding area between the leads and the pads may vary from one display device to another, and as a result, film on chip (“COF”) bonding defects or resistance irregularities may occur in the bonding portion.

[0006] Exemplary embodiments of the present disclosure provide a display device including a consistent bonding area between the lead-out line and the panel pad.

[0007] However, the exemplary embodiments of the present disclosure are not limited to the exemplary embodiments described herein. The above and other exemplary embodiments of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] Exemplary embodiments of the present disclosure provide a display device including: a display substrate including a display area and a pad area disposed at the periphery of the display area; and a display panel including a wiring pad disposed in the pad area of the display substrate, wherein the wiring pad includes: a main pad portion extending in a first direction; a first protruding pad portion protruding from a first side of the main pad portion in a second direction intersecting the first direction; and a second protruding pad portion protruding from a second side of the main pad portion in the second direction, and the first protruding pad portion is disposed closer to the display area than the second protruding pad portion.

[0009] In an exemplary embodiment, the first direction may be a direction from the display area toward an end of the pad area where the wiring pad is provided, and a second side of the main pad portion in the second direction may be opposite to a first side of the main pad portion in the second direction.

[0010] In an exemplary embodiment, the wiring pad may further include a third protruding pad portion protruding from a first side of the main pad portion in the second direction and a fourth protruding pad portion protruding from a second side of the main pad portion in the second direction.

[0011] In an exemplary embodiment, the third protruding pad portion may be provided between the second protruding pad portion and the fourth protruding pad portion, and may be provided closer to the display area than the fourth protruding pad portion.

[0012] In an exemplary embodiment, the second protruding pad portion may be provided between the third protruding pad portion and the fourth protruding pad portion, and the third protruding pad portion may be located closer to the display area than the fourth protruding pad portion.

[0013] In an exemplary embodiment, the wiring pad may further include a third protruding pad portion protruding from a second side of the main pad portion in the second direction, and an area of the first protruding pad portion may be the same as an area of the second protruding pad portion and an area of the third protruding pad portion.

[0014] In an exemplary embodiment, the main pad portion may include a first sub-main pad portion provided on a second side of the first protruding pad portion in the second direction and a second sub-main pad portion provided on a first side of the second protruding pad portion in the second direction and spaced apart from the first sub-main pad portion in the first direction.

[0015] In an exemplary embodiment, the first protruding pad portion and the second protruding pad portion may have the same area and the same shape as each other.

[0016] In an exemplary embodiment, the display device may further include: a printed circuit board attached to the pad area of the display substrate and including lead-out lines connected to the wiring pads.

[0017] In an exemplary embodiment, the lead-out lines may overlap with the main pad portion of the wiring pad in a thickness direction, and may at least partially overlap with at least one of the first protruding pad portion and the second protruding pad portion in the thickness direction.

[0018] In an exemplary embodiment, the lead wire may be directly connected to the wiring pad.

[0019] In an exemplary embodiment, the lead wire may be ultrasonically bonded to the wiring pad.

[0020] In an exemplary embodiment, the wiring pad may overlap with a signal line passing through the display area in the thickness direction and may be electrically connected to the signal line, and the signal line is a gate signal line.

[0021] In an exemplary embodiment, the display device may further include: a pad insulating film disposed between the signal line and the wiring pad in the pad area, and having a plurality of contact holes defined therein that at least partially expose the signal line, wherein the wiring pad is electrically connected to the signal line through the plurality of contact holes.

[0022] In an exemplary embodiment, a plurality of wiring pads may be arranged along the first direction and include a power wiring pad and a data wiring pad, the power wiring pad being electrically connected to a power voltage line in the display area through a signal line, and the data wiring pad being electrically connected to a data line in the display area through the signal line.

[0023] In an exemplary embodiment, the display device may further include: a panel alignment mark disposed on a first side of the array of the plurality of wiring pads in the first direction, and having an alignment hole defined therein.

[0024] In an exemplary embodiment, the printed circuit board may include a circuit alignment mark, the circuit alignment mark being ultrasonically bonded to the panel alignment mark and including a circuit alignment hole therein.

[0025] Exemplary embodiments of the present disclosure provide a display device, the display device including a display area and a pad area disposed at the periphery of the display area, the display area including thin film transistors, the display device including: a substrate; a first conductive layer disposed on the substrate; a first insulating layer disposed on the first conductive layer; a second conductive layer disposed on the first insulating layer; a second insulating layer disposed on the second conductive layer; and a third conductive layer disposed on the second insulating layer, wherein the first conductive layer includes gate electrodes of the thin film transistors disposed in the display area and gate signal lines disposed in the pad area, the second conductive layer includes source electrodes and drain electrodes of the thin film transistors and a plurality of wiring pads disposed in the pad area, the plurality of wiring pads overlapping with the gate signal lines in the thickness direction and being electrically connected to the gate signal lines, each of the plurality of wiring pads including: a main pad portion extending in a first direction; a first protruding pad portion protruding from a first side of the main pad portion in a second direction intersecting the first direction; and a second protruding pad portion protruding from a second side of the main pad portion in the second direction, and the first protruding pad portion is disposed closer to the display area than the second protruding pad portion.

[0026] In an exemplary embodiment, the first direction may be a direction from the display area toward an end of the pad area where the plurality of wiring pads are disposed, and the second side of the main pad portion in the second direction may be opposite to the first side of the main pad portion in the second direction.

[0027] In an exemplary embodiment, the display device may further include: a printed circuit board attached to the pad area of the display substrate and including lead-out lines connected to the plurality of wiring pads, wherein the lead-out lines overlap with the main pad portions of the plurality of wiring pads in the thickness direction, and at least partially overlap with at least one of the first protruding pad portion and the second protruding pad portion of the plurality of wiring pads in the thickness direction.

[0028] Other features and embodiments will be apparent from the following detailed description, drawings, and claims. Description of the Drawings

[0029] By referring to the drawings to describe the embodiments of the present disclosure in detail, the above and other exemplary embodiments and features of the present disclosure will become more apparent. In the drawings:

[0030] Figure 1 is a plan view of an exemplary embodiment of a display device according to the present disclosure;

[0031] Figure 2A is Figure 1 a cross-sectional view of a display device, and Figure 2B and Figure 2C are Figure 2A enlarged views of parts of the display device in

[0032] Figure 3 shows Figure 1 a plan view of the pad region of the display device of

[0033] Figure 4 shows Figure 1 a partial plan view of the printed circuit board (“PCB”) of the display device of

[0034] Figure 5 shows Figure 3 the pad region of Figure 4 and the PCB of

[0035] Figure 6 show Figure 5 an enlarged plan view of region A of

[0036] Figure 7 is a cross-sectional view taken along line VII-VII' of Figure 6 of

[0037] Figure 8 is a cross-sectional view taken along line VIII-VIII’ of Figure 6 of

[0038] Figure 9 shows Figure 3 the pad region of Figure 4 and the PCB of

[0039] Figure 10 show Figure 9 an enlarged plan view of region B of

[0040] Figure 11 is a cross-sectional view taken along line XI-XI' of Figure 10 of

[0041] Figure 12 is a cross-sectional view taken along line XII-XII' of Figure 10 of

[0042] Figure 13 shows Figure 3 the pad region of Figure 4A plan view of a case where the PCBs are attached to each other but misaligned (i.e., α > 0);

[0043] Figure 14 is a magnified plan view showing Figure 13 region C of;

[0044] Figure 15 is a cross-sectional view taken along Figure 14 line XV-XV' of;

[0045] Figures 16A to 16C is a magnified plan view showing an exemplary embodiment of a pad region of a display device according to the present disclosure;

[0046] Figure 17 is a magnified plan view showing another exemplary embodiment of a pad region of a display device according to the present disclosure;

[0047] Figure 18 is a magnified plan view showing another exemplary embodiment of a pad region of a display device according to the present disclosure;

[0048] Figure 19 is a magnified plan view showing another exemplary embodiment of a pad region of a display device according to the present disclosure;

[0049] Figure 20 is a magnified plan view showing another exemplary embodiment of a pad region of a display device according to the present disclosure;

[0050] Figure 21 is a magnified plan view showing another exemplary embodiment of a pad region of a display device according to the present disclosure;

[0051] Figure 22 is a magnified plan view showing another exemplary embodiment of a pad region of a display device according to the present disclosure;

[0052] Figure 23 is a partial plan view showing another exemplary embodiment of a PCB of a display device according to the present disclosure;

[0053] Figure 24 is a plan view of another exemplary embodiment of a display device according to the present disclosure; and

[0054] Figure 25 is a cross-sectional view of another exemplary embodiment of a display device according to the present disclosure. Detailed Description

[0055] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or there can be intervening elements between them. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements.

[0056] It will be understood that although the terms “first,” “second,” “third,” etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections are not to be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a “first element,” “component,” “region,” “layer,” or “section” discussed below may be termed a second element, component, region, layer, or section without departing from the teachings herein.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, including “at least one of (a) kind.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprises,” “comprising,” “includes,” and / or “including” are used in this specification, they specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0058] In addition, relative terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe the relationship of one element to another element as shown in the figures. It will be understood that the relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the figures. In an exemplary embodiment, when the device is flipped in one of the figures, an element described as being on the “lower” side of other elements will then be positioned on the “upper” side of the other elements. Thus, depending on the specific orientation of the figure, the exemplary term “lower” can cover both the “lower” and “upper” orientations. Similarly, when the device in one of the figures is flipped, an element described as being “beneath” or “under” other elements will then be positioned “above” the other elements. Thus, the exemplary terms “beneath” or “under” can cover both the upper and lower orientations.

[0059] For ease of description, spatial relative terms such as "below", "beneath", "under", "above", and "on" may be used herein to describe the relationship of one element or feature shown in the drawings to another element (or elements) or feature (or features). It will be understood that the spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings. In an exemplary embodiment, when the device in the drawings is flipped, an element described as "below" or "beneath" other elements or features will then be positioned "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be otherwise positioned (rotated 90 degrees or at other orientations), and accordingly, the spatial relative descriptors used herein are to be interpreted accordingly.

[0060] Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximate" as used herein includes the stated value and means within an acceptable deviation range of a particular value determined by a person of ordinary skill in the art. In an exemplary embodiment, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning consistent with their meaning in the relevant art and the context of this disclosure, and will not be interpreted in an idealized or overly formal sense.

[0062] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, the embodiments described herein should not be construed as limited to the particular shapes of regions shown herein, but will include, for example, deviations in shape due to manufacturing. In an exemplary embodiment, regions shown or described as flat will generally have rough and / or non-linear features. Additionally, the sharp corners shown may be rounded. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the exact shape of a region nor are they intended to limit the scope of the claims.

[0063] Figure 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure, Figure 2A is Figure 1 a cross-sectional view of the display device of Figure 3 showsFigure 1 A plan view of a pad region of a display device, and Figure 4 is a partial plan view of a printed circuit board (“PCB”) of the display device showing Figure 1 . Specifically, Figure 2A is a cross-sectional view of a pixel region and a panel pad region P_PA of the display device showing Figure 1 .

[0064] As a display device for displaying still images or moving images, the display device 1 can be used in portable electronic devices such as mobile phones, smart phones, tablet personal computers (“PCs”), smart watches, watch phones, mobile communication terminals, electronic notebook computers, e-books, portable multimedia players (“PMPs”), navigation devices or ultra-mobile PCs (“UMPCs”), and the display device 1 can also be used in various other products such as televisions (“TVs”), notebook computers, monitors, billboards or Internet of Things (“IoT”) devices.

[0065] Referring to Figures 1 to 4 , the display device 1 can include a display panel 100 for displaying an image, a PCB 300 connected to the display panel 100, and a main circuit board 500 connected to the PCB 300.

[0066] In an exemplary embodiment, for example, an organic light emitting diode (“OLED”) display panel can be used as the display panel 100. Hereinafter, the display panel 100 will be described as an OLED display panel, but the present disclosure is not limited thereto. In an alternative exemplary embodiment, various other display panels such as a liquid crystal display (“LCD”) panel, a quantum dot OLED (“QD-OLED”) display panel, a quantum dot LCD (“QD-LCD”), a quantum dot nano light emitting diode (“QNED”) display panel or a micro LED (“mLED”) display panel can be used as the display panel 100.

[0067] The display panel 100 includes a display area DA and a non-display area NA provided at the periphery of the display area DA. The display area DA includes a plurality of pixel areas. In a plan view, the display area DA may have a rectangular shape having right-angled corners or having rounded corners. The display area DA may have a short side and a long side. The short side of the display area DA may extend in a first direction DR1. The long side of the display area DA may extend in a second direction DR2. The planar shape of the display area DA is not particularly limited, and the display area DA may have various shapes other than the rectangular shape, such as a circular shape and an oval shape. The non-display area NA may be provided adjacent to both short sides and both long sides of the display area DA. In this case, the non-display area NA may surround all sides of the display area DA and may form an edge of the display area DA. However, the present disclosure is not limited thereto. In an alternative exemplary embodiment, the non-display area NA may be provided adjacent to only two short sides or two long sides of the display area DA.

[0068] The non-display area NA of the display panel 100 may include a panel pad area P_PA. The panel pad area P_PA may be provided adjacent to one of the short sides of the display area DA, but the present disclosure is not limited thereto. In an alternative exemplary embodiment, the panel pad area P_PA may be provided adjacent to both short sides and / or both long sides of the display area DA.

[0069] The printed circuit board (PCB) 300 may include a printed substrate film 310 and a driver integrated circuit ("IC") 390 provided on the printed substrate film 310. The printed substrate film 310 may include an insulating material.

[0070] The PCB 300 may include a circuit area CA. The circuit area CA may include a first circuit area CA1 attached to the panel pad area P_PA of the display panel 100, a second circuit area CA2 provided on a first side (e.g., the lower side) of the first circuit area CA1 in the second direction DR2, and a third circuit area CA3 to which the main circuit board 500 is attached and provided on a first side of the second circuit area CA2 in the second direction DR2. The driver IC 390 may be provided on a first surface of the second circuit area CA2 of the PCB 300. In an exemplary embodiment, the driver IC 390 may be, for example, a data driver IC and may be implemented in a form such as chip on film ("COF").

[0071] The main circuit board 500 may include a circuit pad area C_PA attached to the third circuit area CA3 of the PCB 300. In the circuit pad area C_PA of the main circuit board 500, a plurality of circuit pads may be provided, and the plurality of circuit pads may be connected to lead-out lines provided in the third circuit area CA3 of the PCB 300.

[0072] Referring to Figure 2A , the display device 1 may further include a panel bottom sheet 200 disposed at the bottom of the display panel 100. The panel bottom sheet 200 may be attached to the rear surface of the display panel 100. The panel bottom sheet 200 may include one or more functional layers. The functional layer may be a layer that performs a heat dissipation function, an electromagnetic wave shielding function, a grounding function, a buffering function, a strength enhancing function, a support function, and / or a digitizing function. The functional layer may be a sheet layer including a sheet, a film layer including a film, a thin film layer, a coating layer, a panel, or a plate. The functional layer may have a single-layer structure or a stack of multiple thin films or coating layers. The functional layer may be, for example, a support member, a heat dissipation layer, an electromagnetic wave shielding layer, a shock absorption layer, or a digital converter.

[0073] As Figure 2A shown, the PCB 300 may be bent in a downward direction in the third direction DR3. A part of the PCB 300 and the main circuit board 500 may be disposed below the panel bottom sheet 200. The bottom surface of the panel bottom sheet 200 may be bonded to the main circuit board 500 via an adhesive layer, but the present disclosure is not limited thereto.

[0074] The display panel 100 may include a display substrate 101, a plurality of conductive layers, a plurality of insulating layers for insulating the conductive layers, and an organic layer EL.

[0075] The display substrate 101 may be disposed in the display area DA and the non-display area NA and span the display area DA and the non-display area NA. The display substrate 101 may support various elements disposed above it. The display substrate 101 may be a rigid substrate including a rigid material such as soft glass or quartz, but the present disclosure is not limited thereto. In an alternative exemplary embodiment, the display substrate 101 may be a flexible substrate including a flexible material such as polyimide (“PI”).

[0076] The buffer layer 102 may be disposed on the display substrate 101. The buffer layer 102 may prevent external moisture and oxygen from penetrating through the display substrate 101. In an exemplary embodiment, for example, the buffer layer 102 may include at least one of a silicon nitride (SiN x ) film, a silicon oxide (SiO2) film, and a silicon oxynitride (SiO x N y ) film.

[0077] The semiconductor layer 105 may be disposed on the buffer layer 102. The semiconductor layer 105 may form the channel of a thin film transistor (“TFT”). When required, the semiconductor layer 105 may be disposed in each pixel in the display area DA, and even in the non-display area NA. The semiconductor layer 105 may include source / drain regions and an active region. In an exemplary embodiment, for example, the semiconductor layer 105 may include polysilicon.

[0078] The first insulating layer 111 may be disposed on the semiconductor layer 105. The first insulating layer 111 may be disposed on the entire surface of the display substrate 101. The first insulating layer 111 may be a gate insulating film having a gate insulating function. In an exemplary embodiment, the first insulating layer 111 may include a silicon compound, a metal oxide, or the like. In an exemplary embodiment, for example, the first insulating layer 111 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like, and these materials may be used alone or in combination with each other.

[0079] The first conductive layer 120 may be disposed on the first insulating layer 111. The first conductive layer 120 may include the gate electrode GE of the TFT, the first electrode CE1 of the sustain capacitor Cst, and the gate signal line GSL. In an exemplary embodiment, for example, the first conductive layer 120 may include at least one metal, the at least one metal including at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 120 may be a single-layer film or a stack of multiple films.

[0080] The second insulating layers 112a and 112b may be disposed on the first conductive layer 120. The second insulating layers 112a and 112b may insulate the first conductive layer 120 from the second conductive layer 130. The second insulating layers 112a and 112b may include at least one of the foregoing exemplary materials of the first insulating layer 111. In the panel pad region P_PA, a plurality of contact holes CNT (refer to Figure 6 ) for partially exposing the gate signal line GSL may be defined in the second insulating layer 112b.

[0081] The second conductive layer 130 may be disposed on the second insulating layers 112a and 112b. The second conductive layer 130 may include the second electrode CE2 of the sustain capacitor Cst. The second conductive layer 130 may include at least one of the foregoing exemplary materials of the first conductive material. The first electrode CE1 and the second electrode CE2 of the sustain capacitor Cst may form a capacitor through the second insulating layers 112a and 112b.

[0082] The third insulating layer 113 may be disposed on the second conductive layer 130. The third insulating layer 113 may include at least one of the aforementioned exemplary materials of the first insulating layer 111. In some exemplary embodiments, the third insulating layer 113 may include an organic insulating material. The organic insulating material may include at least one of the exemplary materials of the first via layer VIA1 to be described later.

[0083] The third conductive layer 140 may be disposed on the third insulating layer 113. The third conductive layer 140 may include a source electrode SE, a drain electrode DE, a high potential voltage electrode ELVDDE, and a wiring pad PAD. In an exemplary embodiment, for example, the third conductive layer 140 may include at least one of Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu. The third conductive layer 140 may be a single-layer film, but the present disclosure is not limited thereto. In an alternative exemplary embodiment, the third conductive layer 140 may be a stack of multiple films. In an exemplary embodiment, for example, the third conductive layer 140 may have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0084] The wiring pad PAD of the third conductive layer 140 may overlap with the gate signal line GSL of the first conductive layer 120 in the thickness direction (the third direction DR3), and may be electrically connected to the gate signal line GSL through the contact hole CNT of the second insulating layer 112b. The wiring pad PAD may include surface irregularities. The protruding portion of the wiring pad PAD may be the portion of the wiring pad PAD that overlaps with the second insulating layer 112b in the thickness direction, and the recessed portion of the wiring pad PAD may be the portion of the wiring pad PAD that does not overlap with the second insulating layer 112b in the thickness direction.

[0085] The first via layer VIA1 may be disposed on the third conductive layer 140. The first via layer VIA1 may include an organic insulating material. In an exemplary embodiment, for example, the organic insulating material may include at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, and benzocyclobutene (“BCB”).

[0086] The structure above the third conductive layer 140 (e.g., the first via layer VIA1 and the elements to be described later disposed on the first via layer VIA1) may not be disposed in the panel pad region P_PA, or may be removed from the panel pad region P_PA. Accordingly, the top surface of the wiring pad PAD may be exposed in the panel pad region P_PA.

[0087] The PCB 300 may further include a lead-out wire LE disposed on the first surface of the first circuit region CA1 and a circuit lead-out wire C_LE disposed on the first surface of the third circuit region CA3. The lead-out wire LE is connected to the wiring pad PAD. The lead-out wire LE may be directly connected to the exposed top surface of the wiring pad PAD. In an exemplary embodiment, for example, the lead-out wire LE may be bonded to the wiring pad PAD through an ultrasonic bonding process.

[0088] The ultrasonic bonding process may be performed by an ultrasonic device 700. The ultrasonic device 700 may include a vibration generator 710, a vibrator 720 connected to the vibration generator 710, a booster 730 that amplifies the amplitude of the vibration of the vibrator 720, and a vibration transmitter 740 connected to the vibrator 720.

[0089] The vibration generator 710 may convert electrical energy into vibration energy. The vibrator 720 may vibrate using the vibration energy obtained by the vibration generator 710. The vibrator 720 may vibrate in a predetermined vibration direction and with a predetermined amplitude. The amplitude of the vibration of the vibrator 720 may be amplified in the predetermined vibration direction by the booster 730 connected to the vibrator 720. The vibration transmitter 740 may transmit the vibration of the vibrator 720 to the target element to be bonded. The support member 750 may fix the top and bottom surfaces of the vibrator 720, and thus may prevent the vibrator 720 and the vibration transmitter 740 from vertically fluctuating due to the vibration of the vibrator 720.

[0090] The ultrasonic device 700 may be in contact with the second surface of the PCB 300 and may maintain a predetermined pressurized state in the downward direction, so that the vibration transmitter 740 can effectively transmit the vibration of the vibrator 720 to the PCB 300. As Figure 2C shown, the vibration transmitter 740 of the ultrasonic device 700 may overlap the entire PCB 300 disposed below the ultrasonic device 700 and may perform ultrasonic bonding.

[0091] The ultrasonic device 700 may vibrate in a predetermined vibration direction to cause the lead-out wire LE to vibrate in the predetermined vibration direction. In this case, the wiring pad PAD may also vibrate slightly in the same direction as the lead-out wire LE due to the vibration applied to it through the lead-out wire LE, but the amplitude of the vibration of the wiring pad PAD may be negligible. Therefore, the amplitude of the vibration of the vibration transmitter 740 in the predetermined vibration direction may be substantially the same as the distance that the lead-out wire LE moves above the wiring pad PAD. The predetermined vibration direction may be the second direction DR2. That is, the predetermined vibration direction may be the direction in which the wiring pad PAD and the lead-out wire LE extend.

[0092] If the lead wire LE vibrates above the wiring pad PAD by using ultrasonic waves, a predetermined frictional force is generated at the interface between the wiring pad PAD and the lead wire LE. Therefore, frictional heat is generated. When the frictional heat is sufficient to melt the materials of the wiring pad PAD and the lead wire LE, the melted pad region PADb of the wiring pad PAD adjacent to the lead wire LE and the melted lead region LEb of the lead wire LE adjacent to the pad region PAD can be melted. That is, the wiring pad PAD can include an unmelted pad region PADa and a melted pad region PADb, and the lead wire LE can include an unmelted lead region LEa and a melted lead region LEb.

[0093] The unmelted pad region PADa can be a region that only includes the material of the wiring pad PAD. The unmelted lead region LEa can be a region that only includes the material of the lead wire LE.

[0094] The melted pad region PADb can be a region where the material of the lead wire LE diffuses to mix with the material of the wiring pad PAD, and the melted lead region LEb can be a region where the material of the wiring pad PAD diffuses to mix with the material of the wiring pad PAD. In an exemplary embodiment, for example, when the lead wire LE includes Ag, Au, or Cu and the wiring pad PAD includes Ti / Al / Ti, the melted pad region PADb can be a region where Ti and / or Al from the wiring pad PAD and Ag, Au, or Cu from the lead wire LE are mixed together, and the melted lead region LEb can be a region where Ag, Au, or Cu from the lead wire LE and Ti and / or Al from the wiring pad PAD are mixed together.

[0095] In the melted pad region PADb and the melted lead region LEb, the wiring pad PAD and the lead wire LE solidify and then are joined together. The interface between the wiring pad PAD and the lead wire LE (i.e., the interface between the melted pad region PADb and the melted lead region LEb) can have a non-flat shape.

[0096] In a region where the wiring pad PAD and the PCB 300 are not surface-joined together between the wiring pad PAD and the PCB 300, an underfill resin UFR can be provided, and the underfill resin UFR can contribute to the joining between the wiring pad PAD and the PCB 300. That is, the underfill resin UFR can join the wiring pad PAD and the lead wire LE together in a region other than the ultrasonic joining region as Figure 2B shown. A typical adhesive material can be used as the underfill resin UFR. In an exemplary embodiment, for example, an organic resin can be used as the underfill resin UFR.

[0097] The fourth conductive layer 150 may be disposed on the first via layer VIA1. The fourth conductive layer 150 may include data lines DL, connection electrodes CNE, and a high-potential voltage wiring ELVDDL. The data lines DL may be electrically connected to the source electrodes SE of the TFTs through contacts passing through the first via layer VIA1. The connection electrodes CNE may be electrically connected to the drain electrodes DE of the TFTs through via holes passing through the first via layer VIA1. The high-potential voltage wiring ELVDDL may be electrically connected to a high-potential voltage electrode ELVDDE through a via hole passing through the first via layer VIA1. The fourth conductive layer 150 may include at least one of the foregoing exemplary materials of the third conductive layer 140.

[0098] The second via layer VIA2 is disposed on the fourth conductive layer 150. The second via layer VIA2 may include at least one of the foregoing exemplary materials of the first via layer VIA1.

[0099] The anode electrode ANO is disposed on the second via layer VIA2. The anode electrode ANO may be electrically connected to the connection electrode CNE through a via hole passing through the second via layer VIA2.

[0100] A bank layer BANK may be disposed on the anode electrode ANO. The bank layer BANK may include an opening exposing the anode electrode ANO. The bank layer BANK may include an organic insulating material or an inorganic insulating material. In an exemplary embodiment, for example, the bank layer BANK may include at least one of a photoresist, a polyimide resin, an acrylic resin, a silicon compound, and a polyacrylic resin.

[0101] The organic layer EL may be disposed on the top surface of the anode electrode ANO and in the opening of the bank layer BANK. The cathode electrode CAT is disposed on the organic layer EL and the bank layer BANK. The cathode electrode CAT may be a common electrode disposed in a plurality of pixel regions and spanning the plurality of pixel regions.

[0102] The thin film encapsulation layer 170 is disposed on the cathode electrode CAT. The thin film encapsulation layer 170 may cover the OLED. The thin film encapsulation layer 170 may be a layer in which an inorganic film and an organic film are alternately stacked. In an exemplary embodiment, for example, the thin film encapsulation layer 170 may include a first encapsulation inorganic film 171, an encapsulation organic film 172, and a second encapsulation inorganic film 173 stacked in sequence.

[0103] The structure and shape of a stack of a gate signal line GSL and a wiring pad PAD in a panel pad region P_PA may be changed.

[0104] In some exemplary embodiments, for example, the gate signal line GSL may include multiple patterns, and the wiring pad PAD provided on the gate signal line GSL may have a surface unevenness to reflect the height difference provided by the patterns of the gate signal line GSL.

[0105] In some exemplary embodiments, an auxiliary pad of the second conductive layer 130 may be further provided between the gate signal line GSL and the wiring pad PAD. In this case, the size of the auxiliary pad may be smaller than the size of the wiring pad PAD. The wiring pad PAD, the auxiliary pad, and the gate signal line GSL may overlap each other in the thickness direction and may be electrically connected to each other.

[0106] In addition, in some exemplary embodiments, the gate signal line GSL may be provided as the second conductive layer 130, and the wiring pad PAD may be provided as the fourth conductive layer 150.

[0107] Referring to Figure 3 , multiple wiring pads PAD may be provided, and the multiple wiring pads PAD may be arranged along the first direction DR1.

[0108] The wiring pad PAD may include multiple power pads PW_PAD1 and PW_PAD2, multiple data pads D_PAD1 and D_PAD2, and multiple panel dummy pads DU_PAD. The power pads PW_PAD1 and PW_PAD2 may be electrically connected through the gate signal line GSL and the high-potential voltage wiring ELVDDL and / or the low-potential voltage wiring, and the data pads D_PAD1 and D_PAD2 may be electrically connected through the data line DL and the gate signal line GSL. The panel dummy pad DU_PAD may be isolated from the signal line passing through the display area DA.

[0109] The array of the panel dummy pads DU_PAD may be provided between the arrays of the first data pads D_PAD1 and the second data pads D_PAD2, and the array of the first data pads D_PAD1 may be provided between the arrays of the first power pads PW_PAD1 and the array of the dummy pads DU_PAD, and the array of the second data pads D_PAD2 may be provided between the arrays of the second power pads PW_PAD2 and the array of the dummy pads DU_PAD.

[0110] Each wiring pad PAD may protrude in two different directions. In an exemplary embodiment, each wiring pad PAD may protrude on both sides thereof in the first direction DR1. The shape of the wiring pad PAD, for example, will be described in detail later.

[0111] The panel alignment marks P_ALM1 and P_ALM2 can be provided on both sides of the array of the wiring pads PAD. That is, the first panel alignment mark P_ALM1 can be provided on the first side of the array of the wiring pads PAD in the first direction DR1, and the second panel alignment mark P_ALM2 can be provided on the second side of the array of the wiring pads PAD in the first direction DR1. The panel alignment marks P_ALM1 and P_ALM2 can be used as marks in the process of attaching the PCB 300.

[0112] The panel alignment marks P_ALM1 and P_ALM2 can have the same stacking structure or a similar stacking structure as the wiring pads PAD, but the present disclosure is not limited thereto. In an alternative exemplary embodiment, the panel alignment marks P_ALM1 and P_ALM2 can be composed only of the gate signal lines GSL or only of the wiring pads PAD. Additionally, the panel alignment marks P_ALM1 and P_ALM2 can include a conductive layer different from the gate signal lines GSL and the wiring pads PAD.

[0113] Alignment holes P_ALH can be defined in the panel alignment marks P_ALM1 and P_ALM2. In a plan view, the alignment holes P_ALH can be completely surrounded by the panel alignment marks P_ALM1 and P_ALM2. The planar shape of the alignment holes P_ALH is not limited to Figure 3 the planar shape shown, but can be changed.

[0114] Referring to Figure 4 , a plurality of lead-out lines LE can be provided in the first circuit region CA1 and can be arranged along the first direction DR1. The lead-out lines LE can include a plurality of power lead-out lines PW_LE1 and PW_LE2, a plurality of data lead-out lines D_LE1 and D_LE2, and a plurality of dummy leads DU_LE. The power lead-out lines PW_LE1 and PW_LE2 can be electrically connected to the driver IC 390 and the power pads PW_PAD1 and PW_PAD2, and the data lead-out lines D_LE1 and D_LE2 can be electrically connected to the driver IC 390 and the data pads D_PAD1 and D_PAD2. The dummy leads DU_LE can be electrically isolated from the driver IC 390.

[0115] An array of the dummy leads DU_LE can be provided between an array of the first data lead-out lines D_LE1 and an array of the second data lead-out lines D_LE2. The array of the first data lead-out lines D_LE1 can be provided between an array of the first power lead-out lines PW_LE1 and an array of the dummy leads DU_LE, and the array of the second data lead-out lines D_LE2 can be provided between an array of the second power lead-out lines PW_LE2 and an array of the dummy leads DU_LE.

[0116] The lead-out wire LE may include a metallic material. In an exemplary embodiment, for example, the lead-out wire LE may include at least one metal selected from Mo, Al, Pt, palladium (Pd), Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu.

[0117] Lead alignment marks L_ALM1 and L_ALM2 may be provided on both sides of the array of lead-out wires LE. That is, the second lead alignment mark L_ALM2 may be provided on the first side of the array of lead-out wires LE in the first direction DR1, and the first lead alignment mark L_ALM1 may be provided on the second side of the array of lead-out wires LE in the first direction DR1.

[0118] Alignment holes L_ALH may be defined in the lead alignment marks L_ALM1 and L_ALM2. In a plan view, the alignment holes L_ALH may be completely surrounded by the lead alignment marks L_ALM1 and L_ALM2. Figure 4 It is shown that the alignment holes L_ALH are vertically symmetric with the panel alignment marks P_ALM1 and P_ALM2, but the present disclosure is not limited thereto.

[0119] The wiring pads PAD and the panel alignment marks P_ALM1 and P_ALM2 may be surface-bonded to the lead-out wire LE and the lead alignment marks L_LM1 and L_LM2, respectively, by ultrasonic bonding. Figure 4 The first circuit region CA1 of Figure 3 is flipped 180 degrees (°) and then attached in the thickness direction to

[0120] Hereinafter, an exemplary plan view and a cross-sectional view of a display device 1 including wiring pads PAD ultrasonically bonded to lead wires LE, respectively, and panel alignment marks P_ALM1 and P_ALM2 and lead alignment marks L_LM1 and L_LM2 will be described. Alignment errors may occur in the process of aligning the wiring pads PAD and the panel alignment marks P_ALM1 and P_ALM2 with the lead wires LE and the lead alignment marks L_LM1 and L_LM2, respectively, to ultrasonically bond the wiring pads PAD and the panel alignment marks P_ALM1 and P_ALM2 to the lead wires LE and the lead alignment marks L_LM1 and L_LM2, respectively.

[0121] Figure 5 is a partial plan view showing Figure 3 the pad regions of Figure 4 and the PCB of Figure 6 being attached to each other and properly aligned with each other without misalignment therebetween (i.e., α = 0% (where α represents the alignment error)). Figure 5 is an enlarged plan view showing Figure 7 region A of Figure 6 and is a cross-sectional view taken along line VII-VII' of Figure 8 and Figure 6 is a cross-sectional view taken along line VIII-VIII' of

[0122] Referring to Figures 5 to 8 , as already discussed above, each wiring pad PAD protrudes in two different directions. Hereinafter, taking a first power pad PW_PAD1 as an example, the planar shape and cross-sectional structure of the wiring pad PAD will be described, and the subsequent description of the first power pad PW_PAD1 can be directly applied to other first power pads PW_PAD1, second power pads PW_PAD2, data pads D_PAD1 and D_PAD2, and panel dummy pads DU_PAD.

[0123] The first power pad PW_PAD1 may include main pad portions MR1 and MR2 overlapping with a gate signal line GSL. The main pad portions MR1 and MR2 may extend along a second direction DR2. In the plan view, the first main pad portion MR1 and the second main pad portion MR2 may be spaced apart from each other in the second direction DR2 and may overlap with each other in the second direction DR2. The first main pad portion MR1 may be located closer to the display area DA than the second main pad portion MR2. The main pad portions MR1 and MR2 may be electrically connected to the gate signal line GSL through contact holes CNT of a second insulating layer 112b. The arrangement and number of the contact holes CNT of the second insulating layer 112b may be changed. In the plan view, the main pad portions MR1 and MR2 may have a rectangular shape.

[0124] The pad connection part CR can be provided between the first main pad part MR1 and the second main pad part MR2 to physically connect the first main pad part MR1 and the second main pad part MR2.

[0125] The main pad parts MR1 and MR2 of the first power pad PW_PAD1 and the pad connection part CR can have a width WPA1 in the first direction DR1 and a width WPA2 in the second direction DR2, and the sum of the areas of the main pad parts MR1 and MR2 of the first power pad PW_PAD1 and the area of the pad connection part CR can be WPA1×WPA2.

[0126] The first protruding pad part PR1 is provided on the first side of the first main pad part MR1 in the first direction DR1, and the second protruding pad part PR2 is provided on the second side of the second main pad part MR2 in the first direction DR1. The first protruding pad part PR1 can be located closer to the display area DA than the second protruding pad part PR2. Figure 6 It is shown that the protruding pad parts PR1 and PR2 do not overlap with the gate signal line GSL in the thickness direction, but the present disclosure is not limited thereto. That is, the protruding pad parts PR1 and PR2 can overlap with the gate signal line GSL in the thickness direction.

[0127] The pad connection part CR can include a first edge provided adjacent to the first protruding pad part PR1 and a second edge provided adjacent to the second protruding pad part PR2. The first edge and the second edge of the pad connection part CR can both extend in the second direction DR2. The first edge of the pad connection part CR can be the boundary between the first main pad part MR1 and the first protruding pad part PR1, and the second edge of the pad connection part CR can be the boundary between the second main pad part MR2 and the second protruding pad part PR2. That is, the protruding pad parts PR1 and PR2 can be parts of the pad connection part CR that extend in the first direction DR1 from the first edge and the second edge of the pad connection part CR and can be physically connected to the main pad parts MR1 and MR2 through the first edge and the second edge of the pad connection part CR.

[0128] In a plan view, the first protruding pad portion PR1 and the second protruding pad portion PR2 may have the same area. Additionally, in a plan view, the first protruding pad portion PR1 and the second protruding pad portion PR2 may have the same shape. In a plan view, the first protruding pad portion PR1 and the second protruding pad portion PR2 may have a rectangular shape or a square shape. In an exemplary embodiment, for example, the first protruding pad portion PR1 may have a width WP11 in a first direction DR1 and a width WP12 in a second direction DR2, and the second protruding pad portion PR2 may have a width WP21 in the first direction DR1 and a width WP22 in the second direction DR2. In a plan view, the first protruding pad portion PR1 and the second protruding pad portion PR2 may have the same width and the same area. That is, the area of each of the protruding pad portions PR1 and PR2 may be WP11×WP12. Additionally, the widths of the protruding pad portions PR1 and PR2 in the first direction DR1 may be the same as the widths of the main pad portions MR1 and MR2 in the first direction DR1, but the present disclosure is not limited thereto.

[0129] As Figure 6 shown, the first power lead-out wire PW_LE1 may have a linear shape extending in the second direction DR2. In this case, the width of the first power lead-out wire PW_LE1 in the first direction DR1 may be WL.

[0130] The first power lead-out wire PW_LE1 is joined to the first power pad PW_PAD1. The first power lead-out wire PW_LE1 may be joined to the first power pad PW_PAD1 when its lead center line LCL is aligned with the alignment line AGL. The alignment line AGL is the center line of the first power pad PW_PAD1 in the first direction DR1, and the lead center line LCL may be the center line of the first power lead-out wire PW_LE1 in the first direction DR1.

[0131] As already discussed above, misalignment with an alignment error α may occur in the process of aligning the first power lead-out wire PW_LE1 with the first power pad PW_PAD1. The alignment error α satisfies the following formula:

[0132]

[0133] where L represents the alignment error displacement, and D represents the distance between the alignment line AGL and the lead center line LCL.

[0134] When the first power lead PW_LE1 is properly aligned with the first power pad PW_PAD1, both the distance D and the alignment error displacement L are zero. When the first power lead PW_LE1 is misaligned due to moving towards its first side in the first direction DR1, L = -D (where D > 0). When the first power lead PW_LE1 is misaligned due to moving towards its second side in the first direction DR1, L = +D (where D > 0).

[0135] Referring to Figures 5 to 8 , the first power lead PW_LE1 can completely overlap the main pad portions MR1 and MR2 and the pad connection portion CR of the first power pad PW_PAD1 in the thickness direction, and can partially overlap the protruding pad portions PR1 and PR2 of the first power pad PW_PAD1 in the thickness direction. Referring to Figure 6 , the width in the first direction DR1 of the overlapping region between the first protruding pad portion PR1 and the first power lead PW_LE1 and the width in the first direction DR1 of the overlapping region between the second protruding pad portion PR2 and the first power lead PW_LE1 can be WP111 and WP211 respectively, and the width in the second direction DR2 of the overlapping region between the first protruding pad portion PR1 and the first power lead PW_LE1 and the width in the second direction DR2 of the overlapping region between the second protruding pad portion PR2 and the first power lead PW_LE1 can be WP12 and WP22 respectively. When the first power lead PW_LE1 is properly aligned with the first power pad PW_PAD1, the width WP111 and the width WP211 can be the same.

[0136] As Figure 7 and Figure 8 shown, the first power lead PW_LE1 can be in surface contact with the protruding portion of the surface of the first power pad PW_PAD1 and can be spaced apart from the recessed portion of the surface of the first power pad PW_PAD1. In an alternative exemplary embodiment, the first power lead PW_LE1 can also be in partial surface contact with the recessed portion of the surface of the first power pad PW_PAD1. In the region where the first power lead PW_LE1 and the first power pad PW_PAD1 are in surface contact with each other, the first power lead PW_LE1 and the first power pad PW_PAD1 can be surface-bonded to each other.

[0137] The size of the region where the first power pad PW_PAD1 can be surface-bonded to the first power lead PW_LE1 can be proportional to the size of the region where the first power pad PW_PAD1 and the first power lead PW_LE1 overlap each other in the thickness direction.

[0138] Specifically, the overlapping area in the thickness direction between the first power pad PW_PAD1 and the first power lead PW_LE1 can be the sum of the overlapping area between the first power lead PW_LE1 and the main pad portions MR1 and MR2 and the pad connection portion CR of the first power pad PW_PAD1, and the overlapping area between the first power lead PW_LE1 and the protruding pad portions PR1 and PR2 of the first power pad PW_PAD1, that is, WPA1×WPA2 + 2×WP111×WP12. That is, when the first power lead PW_LE1 and the first power pad PW_PAD1 are properly aligned, the size of the area where the first power lead PW_LE1 and the first power pad PW_PAD1 can be surface-bonded together can be WPA1×WPA2 + 2×WP111×WP12.

[0139] Figure 9 shows Figure 3 the pad area of Figure 4 and the PCB of Figure 10 shows Figure 9 an enlarged plan view of area B of Figure 11 is a cross-sectional view taken along line XI-XI' of Figure 10 and [[ID=SS]]Figure 12 is a cross-sectional view taken along line XII-XII' of Figure 10

[0140] Referring to Figures 9 to 12 , when aligning the first power lead PW_LE1 with the first power pad PW_PAD1, under the condition that the first edge of the first power lead PW_LE1 in the first direction DR1 is set in the area overlapping with the first protruding pad portion PR1 of the first power pad PW_PAD1 and the second edge of the first power lead PW_LE1 in the first direction DR1 is set in the area overlapping with the second protruding pad portion PR2 of the first power pad PW_PAD1, the overlapping area in the thickness direction between the first power lead PW_LE1 and the first power pad PW_PAD1 can be consistently maintained.

[0141] ​Specifically, when the lead center line LCL of the first power lead wire PW_LE1 is misaligned with the alignment line AGL on the first side in the first direction DR1, but only to such an extent that the first edge of the first power lead wire PW_LE1 in the first direction DR1 falls into the area overlapping with the first protruding pad portion PR1 of the first power pad PW_PAD1 and the second edge of the first power lead wire PW_LE1 in the first direction DR1 falls into the area overlapping with the second protruding pad portion PR2, compared with when the first power lead wire PW_LE1 and the first power pad PW_PAD1 are properly aligned, the overlapping areas in the thickness direction of the first main pad portion MR1, the second main pad portion MR2, and the pad connection portion CR of the first power lead wire PW_LE1 and the first power pad PW_PAD1 are maintained, the overlapping area in the thickness direction of the first power lead wire PW_LE1 and the first protruding pad portion PR1 of the first power pad PW_PAD1 increases, and the overlapping area in the thickness direction of the first power lead wire PW_LE1 and the second protruding pad portion PR2 of the first power pad PW_PAD1 decreases. In an exemplary embodiment, for example, when the lead center line LCL of the first power lead wire PW_LE1 is misaligned due to moving away from the alignment line AGL by up to -D, the overlapping area in the thickness direction between the first protruding pad portion PR1 and the first power lead wire PW_LE1 can be (WP111 + D) × WP12, and the overlapping area in the thickness direction between the second protruding pad portion PR2 and the first power lead wire PW_LE1 can be (WP211 - D) × WP22. As discussed above, the width of the first protruding pad portion PR1 in the second direction DR2 (i.e., WP12) and the width of the second protruding pad portion PR2 in the second direction DR2 (i.e., WP22) are the same, and when WP111 and WP211 are the same, the sum of the overlapping areas in the thickness direction between the first power lead wire PW_LE1 and the first protruding pad portion PR1 and the overlapping area in the thickness direction between the first power lead wire PW_LE1 and the second protruding pad portion PR2 can be 2 × WP111 × WP12.

[0142] That is, even when the lead center line LCL of the first power lead wire PW_LE1 is not aligned with the alignment line AGL, but when the first edge of the first power lead wire PW_LE1 in the first direction DR1 falls into the region overlapping with the first protruding pad portion PR1 of the first power pad PW_PAD1 and the second edge of the first power lead wire PW_LE1 in the first direction DR1 falls into the region overlapping with the second protruding pad portion PR2, the size of the region where the first power lead wire PW_LE1 and the first power pad PW_PAD1 can be surface-bonded together can be maintained as WPA1×WPA2 + 2×WP111×WP12, which is the same as when the first power lead wire PW_LE1 and the first power pad PW_PAD1 are properly aligned.

[0143] Figure 13 shows Figure 3 the pad area of Figure ) and the PCB of Figure 14 shows Figure 13 the enlarged plan view of region C of Figure 15 and is Figure 14 a cross-sectional view taken along the line XV-XV' of

[0144] Referring to Figures 13 to 15 , even when the first power lead wire PW_LE1 is not aligned with the first power pad PW_PAD1 in the direction opposite to that in the example of Figures 9 to 12 , under the condition that the first edge of the first power lead wire PW_LE1 in the first direction DR1 falls into the region overlapping with the first protruding pad portion PR1 of the first power pad PW_PAD1 and the second edge of the first power lead wire PW_LE1 in the first direction DR1 falls into the region overlapping with the second protruding pad portion PR2, the overlapping region of the first power lead wire PW_LE1 and the first power pad PW_PAD1 can be consistently maintained.

[0145] Specifically, when the lead center line LCL of the first power lead PW_LE1 is misaligned with the alignment line AGL on the second side in the first direction DR1, but only to such an extent that the first edge of the first power lead PW_LE1 in the first direction DR1 falls into the area overlapping with the first protruding pad portion PR1 of the first power pad PW_PAD1 and the second edge of the first power lead PW_LE1 in the first direction DR1 falls into the area overlapping with the second protruding pad portion PR2, compared to when the first power lead PW_LE1 and the first power pad PW_PAD1 are properly aligned, the overlapping areas in the thickness direction of the first power lead PW_LE1 with the first main pad portion MR1, the second main pad portion MR2, and the pad connection portion CR of the first power pad PW_PAD1 are maintained, the overlapping area in the thickness direction of the first power lead PW_LE1 with the first protruding pad portion PR1 of the first power pad PW_PAD1 is reduced, and the overlapping area in the thickness direction of the first power lead PW_LE1 with the second protruding pad portion PR2 of the first power pad PW_PAD1 is increased. In an exemplary embodiment, for example, when the lead center line LCL of the first power lead PW_LE1 is misaligned due to moving away from the alignment line AGL by up to +D, the overlapping area in the thickness direction between the first protruding pad portion PR1 and the first power lead PW_LE1 can be (WP111 - D)×WP12, and the overlapping area in the thickness direction between the second protruding pad portion PR2 and the first power lead PW_LE1 can be (WP211 + D)×WP22. As discussed above, when the width of the first protruding pad portion PR1 in the second direction DR2 (i.e., WP12) and the width of the second protruding pad portion PR2 in the second direction DR2 (i.e., WP22) are the same, and when WP111 and WP211 are the same, the overlapping area in the thickness direction between the first power lead PW_LE1 and the first protruding pad portion PR1 and the overlapping area in the thickness direction between the first power lead PW_LE1 and the second protruding pad portion PR2 can be 2×WP111×WP12, which is the same as when the first power lead PW_LE1 and the first power pad PW_PAD1 are properly aligned and when the first power lead PW_LE1 is misaligned with the first power pad PW_PAD1 on the first side in the first direction DR1 towards the alignment line AGL.

[0146] If the degree of misalignment between the lead wire LE and the wiring pad PAD changes during the ultrasonic bonding process for bonding the wiring pad PAD and the lead wire LE during the manufacture of the display device 1, the bonding area between the lead wire LE and the wiring pad PAD may undesirably change. Therefore, bonding defects and resistance irregularities may occur. However, since each wiring pad PAD protrudes in two different directions and includes protruding pad portions PR1 and PR2 having the same area and the same shape, even when misalignment occurs, the overlapping area in the thickness direction between the lead wire LE and the wiring pad can still be consistently maintained. That is, the size of the area where the lead wire LE and the wiring pad PAD can be surface-bonded together can be consistently maintained. Therefore, bonding defects and resistance irregularities that may occur between the wiring pad PAD and the lead wire LE can be prevented or at least mitigated.

[0147] Hereinafter, a display device according to other exemplary embodiments of the present disclosure will be described. The same reference numerals indicate the same elements throughout the specification, and their description will be omitted or at least simplified.

[0148] Figures 16A to 16C is an enlarged plan view showing a pad area of a display device according to an embodiment of the present disclosure.

[0149] Figures 16A to 16C The pad area of Figure 1 differs from its counterpart in that the protruding pad portions are respectively provided in a semicircular shape, a triangular shape, or a trapezoidal shape.

[0150] Specifically, referring to Figure 16A , the protruding pad portions PR1_1 and PR2_1 may have a semicircular shape in a plan view. The first protruding pad portion PR1_1 and the second protruding pad portion PR2_1 may have the same area in a plan view and may have exactly the same contour in a plan view.

[0151] Referring to Figure 16B , the protruding pad portions PR1_2 and PR2_2 may have a triangular shape in a plan view. The first protruding pad portion PR1_2 and the second protruding pad portion PR2_2 may have the same area in a plan view and may have exactly the same contour in a plan view.

[0152] Referring to Figure 16C , the protruding pad portions PR1_3 and PR2_3 may have a trapezoidal shape in a plan view. The first protruding pad portion PR1_3 and the second protruding pad portion PR2_3 may have the same area in a plan view and may have exactly the same contour in a plan view.

[0153] In Figures 16A to 16C an exemplary embodiment, each of the first power pads PW_PAD1_1, the first power pads PW_PAD1_2, and the first power pads PW_PAD1_3 has protruding pad portions that protrude in different directions and have the same area and the same shape. Therefore, even when misalignment occurs, the overlapping region in the thickness direction between the lead-out wire and the panel pad can be consistently maintained. That is, the size of the region where the lead-out wire and the panel pad can be surface-bonded together can be consistently maintained. Therefore, bonding defects and resistance irregularities that may occur between the lead-out wire and the panel pad can be prevented or at least mitigated.

[0154] Figure 17 is an enlarged plan view showing another exemplary embodiment of the pad region of a display device according to the present disclosure. Different from the Figure 3 first power pad PW_PAD1 of Figure 17 the first power pad PW_PAD1_4 of

[0155] Specifically, referring to Figure 17 , each first power pad PW_PAD1_4 may include a plurality of first protruding pad portions PR1 and a plurality of second protruding pad portions PR2. The number of the first protruding pad portions PR1 may be the same as the number of the second protruding pad portions PR2. The second protruding pad portions PR2 may be arranged between the first protruding pad portions PR1 along the second direction DR2.

[0156] In Figure 17 an exemplary embodiment, each first power pad PW_PAD1_4 has a plurality of protruding pad portions that protrude in different directions and have the same area and the same shape. Therefore, even when misalignment occurs, the overlapping region in the thickness direction between the lead-out wire and the panel pad can be consistently maintained. That is, the size of the region where the lead-out wire and the panel pad can be surface-bonded together can be consistently maintained. Therefore, bonding defects and resistance irregularities that may occur between the lead-out wire and the panel pad can be prevented or at least mitigated.

[0157] Figure 18 is an enlarged plan view showing another exemplary embodiment of the pad region of a display device according to the present disclosure.

[0158] Figure 18 The first power pad PW_PAD1_5 of Figure 17The difference of the first power pad PW_PAD1_4 is that in each first power pad PW_PAD1_5, the first protruding pad portion PR1 is disposed between another first protruding pad portion PR1 and the second protruding pad portion PR2.

[0159] Figure 19 is an enlarged plan view showing another exemplary embodiment of the pad region of a display device according to the present disclosure.

[0160] Figure 19 The first power pad PW_PAD1_6 of Figure 18 differs from the first power pad PW_PAD1_5 of

[0161] Specifically, referring to Figure 19 , the number of the second protruding pad portions PR2 provided in each first power pad PW_PAD1_6 is greater than the number of the first protruding pad portions PR1_4 provided in each first power pad PW_PAD1_6, but the sum of the areas of the second protruding pad portions PR2 may be the same as the area of the first protruding pad portions PR1_4. That is, the width of the first protruding pad portion PR1_4 in the first direction DR1 may be the same as the width of the second protruding pad portion PR2 in the first direction DR1, and the width of the first protruding pad portion PR1_4 in the second direction DR2 may be the same as the sum of the widths of the second protruding pad portions PR2.

[0162] In Figure 19 's exemplary embodiment, even when misalignment occurs during the process of aligning the lead wire with the panel pad, the sum of the areas where the first protruding pad portion PR1_4 and the second protruding pad portion PR2 of each first power pad PW_PAD1_6 can be surface-bonded can still be consistently maintained. Therefore, bonding defects and resistance irregularities that may occur between the lead wire and the panel pad can be prevented or at least mitigated.

[0163] Figure 20 is an enlarged plan view showing another exemplary embodiment of the pad region of a display device according to the present disclosure.

[0164] Figure 20 The first power pad PW_PAD1_7 of Figure 3 differs from the first power pad PW_PAD1 of Figure 20 in that the first power pad PW_PAD1_7 of does not include a pad connection portion.

[0165] Specifically, referring to Figure 20 , the first main pad portion MR1 and the second main pad portion MR2 of each first power pad PW_PAD1_7 may be spaced apart from each other in the second direction DR2. In the gap between the first main pad portion MR1 and the second main pad portion MR2, contact holes CNT may not be defined in the second insulating layer 112b.

[0166] In Figure 20 's exemplary embodiment, even when misalignment occurs during the process of aligning the lead wire with the panel pad, the sum of the areas where the first protruding pad portion PR1 and the second protruding pad portion PR2 of each first power pad PW_PAD1_7 can be surface-bonded can still be consistently maintained. Therefore, bonding defects and resistance irregularities that may occur between the lead wire and the panel pad can be prevented or at least mitigated.

[0167] Figure 21 is an enlarged plan view showing another exemplary embodiment of the pad region of the display device according to the present disclosure.

[0168] Referring to Figure 21 , in each first power pad PW_PAD1_8, a pad connection portion may not be provided between the first main pad portion MR1 and the second main pad portion MR2, and the first main pad portion MR1 and the second main pad portion MR2 may be directly physically connected.

[0169] In Figure 21 's exemplary embodiment, even when misalignment occurs during the process of aligning the lead wire with the panel pad, the sum of the areas where the first protruding pad portion PR1 and the second protruding pad portion PR2 of each first power pad PW_PAD1_7 can be surface-bonded can still be consistently maintained. Therefore, bonding defects and resistance irregularities that may occur between the lead wire and the panel pad can be prevented or at least mitigated.

[0170] Figure 22 is an enlarged plan view showing another exemplary embodiment of the pad region of the display device according to the present disclosure, and Figure 23 is a partial plan view showing another exemplary embodiment of the PCB of the display device according to the present disclosure.

[0171] In Figure 22 and Figure 23 's display panel 100_1 and PCB 300_1, Figure 22 and Figure 23 's wiring pads PAD_1 and lead wires LE_1 are connected to Figure 3 and Figure 4The wiring pad PAD and the lead LE are different in that the first power pad PW_PAD1_9, the second power pad PW_PAD2_1, the panel dummy pad DU_PAD_1, the first power lead PW_LE1_1, the second power lead PW_LE2_1, and the dummy lead DU_LE_1 are integrated along the first direction DR1.

[0172] In an exemplary embodiment, referring to Figure 22 , for example, the main pad portion and the pad connection portion of the first power pad PW_PAD1_9 are provided as a single unit along the first direction DR1. Similar to Figure 3 the protruding pad portion of each first power pad PW_PAD1 of , the protruding pad portion of the first power pad PW_PAD1_9 can protrude from one side and the other side of the main pad portion of the first power pad PW_PAD1_9 in the first direction DR1 and can have the same area and exactly the same contour in a plan view.

[0173] In Figure 22 and Figure 23 's exemplary embodiment, the integrated first power pad PW_PAD1_9 and the second power pad PW_PAD2_1 overlap with the integrated first power lead PW_LE1_1 and the second power lead PW_LE2_1 in the thickness direction, respectively, and are surface-bonded to the integrated first power lead PW_LE1_1 and the second power lead PW_LE2_1, respectively, and the integrated panel dummy pad DU_PAD_1 overlaps with the integrated dummy lead DU_LE_1 in the thickness direction and is surface-bonded to the integrated dummy lead DU_LE_1. Therefore, the size of the area where the wiring pad PAD_1 and the lead LE_1 can be surface-bonded together can be increased, and thus, bonding defects can be prevented in advance.

[0174] Figure 24 is a plan view of another exemplary embodiment of a display device according to the present disclosure, and Figure 25 is a cross-sectional view of another exemplary embodiment of a display device according to the present disclosure.

[0175] Referring to Figure 24 and Figure 25 , the display panel 100_1 of the display device 2 may further include a bending area BA.

[0176] The display substrate 101 of the display panel 100_1 (referring to Figure 2A) may include an insulating material such as a polymer resin. In an exemplary embodiment, for example, the polymer material may include polyethersulfone (“PES”), polyacrylate (“PA”), polyaryl compound (“PAR”), polyetherimide (“PEI”), polyethylene naphthalate (“PEN”), polyethylene terephthalate (“PET”), polyphenylene sulfide (“PPS”), polyallylate, polyimide (“PI”), polycarbonate (“PC”), cellulose triacetate (“CAT”), cellulose acetate propionate (“CAP”), or a combination thereof. The display substrate 101 may be a flexible substrate that is bendable, foldable, or rollable. The flexible substrate may include, for example, PI, but the present disclosure is not limited thereto.

[0177] The bending region BA may be provided between the array of a plurality of pixels and the first panel pad region P_PA_1. The bending region BA may be provided in the non-display region NA. The display panel 100_1 may be folded in one direction along a folding line that is a reference line provided in the bending region BA. The folding line may be a straight line parallel to the lower (or upper) side of the display panel 100_! As Figure 25 shown, the bending region BA of the display panel 100_1 may be bent downward in the third direction DR3.

[0178] However, the present disclosure is not limited thereto. That is, the display region DA and the first panel pad region P_PA_1 may be connected to each other without the bending region BA. In other words, the display panel 100_1 may not have the bending region BA and may be flat over the entire display region DA and the entire non-display region NA.

[0179] In the first panel pad region P_PA_1, a plurality of wiring pads PAD are provided. The driver IC 900 is provided on the wiring pads PAD. In the second panel pad region P_PA_2, a plurality of panel pads may be provided, and the main circuit board 500_1 may be attached to the panel pads.

[0180] In an exemplary embodiment, for example, the driver IC 900 may be implemented in the form of chip on plastic (“COP”) or chip on glass (“COG”).

[0181] The driver IC 900 may include a plurality of bumps connected to the wiring pads PAD. In an exemplary embodiment, for example, the bumps may include at least one of Au, Ni, and tin (Sn).

[0182] The protrusions of the driver IC 900 can be in direct contact with and bonded to the wiring pad PAD without other layers or components. The protrusions of the driver IC 900 and the wiring pad PAD can be bonded together by ultrasonic bonding.

Claims

1. A display device, wherein: The display device includes: A display substrate comprising a display area and a pad area disposed at the periphery of the display area; and The display panel includes a wiring pad provided in the pad area of the display substrate, the wiring pad including: A main pad portion extending in a first direction; a first protruding pad portion protruding from a first side of the main pad portion in a second direction intersecting the first direction; and a second protruding pad portion protruding from a second side of the main pad portion in the second direction; and a printed circuit board attached to the pad area of the display substrate and including lead wires connected to the wiring pads, wherein the lead line completely overlaps the main pad portion of the wiring pad in a thickness direction and at least partially overlaps at least one of the first protruding pad portion and the second protruding pad portion in the thickness direction, wherein the first protruding pad portion is arranged closer to the display area than the second protruding pad portion, wherein the first protruding pad portion and the second protruding pad portion have the same area and the same shape as each other, and The first edge of the lead line in the second direction is located in an area where the lead line partially overlaps with the first protruding pad, and the second edge of the lead line in the second direction is located in an area where the lead line partially overlaps with the second protruding pad.

2. The display device according to claim 1, wherein The first direction is a direction from the display area toward an end of the pad area where the wiring pad is provided, and The second side of the main pad portion in the second direction is opposite to the first side of the main pad portion in the second direction.

3. The display device according to claim 2, wherein: The wiring pad further includes a third protruding pad portion protruding from the first side of the main pad portion in the second direction and a fourth protruding pad portion protruding from the second side of the main pad portion in the second direction.

4. The display device according to claim 3, wherein The third protrusion pad portion is disposed between the second protrusion pad portion and the fourth protrusion pad portion, and is disposed closer to the display area than the fourth protrusion pad portion.

5. The display device according to claim 3, wherein The second protrusion pad portion is disposed between the third protrusion pad portion and the fourth protrusion pad portion, and The third protrusion pad portion is disposed closer to the display area than the fourth protrusion pad portion, wherein the third protruding pad portion and the fourth protruding pad portion have the same area and the same shape as each other, and The first edge of the lead line is located in a region where the lead line partially overlaps with the third protruding pad, and the second edge of the lead line is located in a region where the lead line partially overlaps with the fourth protruding pad. The display device according to claim 2 , wherein: The main pad portion includes a first sub main pad portion disposed at a second side of the first protruding pad portion in the second direction and a second sub main pad portion disposed at a first side of the second protruding pad portion in the second direction and spaced apart from the first sub main pad portion in the first direction.

7. The display device according to claim 1, wherein The lead-out wires are directly connected to the wiring pads.

8. The display device according to claim 7, wherein: The lead wires are ultrasonically bonded to the wiring pads.

9. The display device according to claim 2, wherein: The wiring pad overlaps with a signal line passing through the display area in a thickness direction and is electrically connected to the signal line, and The signal line is a gate signal line.

10. The display device according to claim 9, wherein The display device further includes: a pad insulating film provided between the signal line and the wiring pad of the pad region and having a plurality of contact holes defined therein for at least partially exposing the signal line, The wiring pad is electrically connected to the signal line through the plurality of contact holes.

11. The display device according to claim 2, wherein: A plurality of wiring pads are arranged along the first direction and include power wiring pads electrically connected to power voltage lines in the display area through signal lines and data wiring pads electrically connected to data lines in the display area through the signal lines.

12. The display device according to claim 11, wherein The display device further includes: A panel alignment mark is provided on a first side of the array of the plurality of wiring pads in the first direction and has an alignment hole defined therein.

13. The display device according to claim 12, wherein: The display device further includes: A printed circuit board includes a circuit alignment mark ultrasonically bonded to the panel alignment mark and having a circuit alignment hole defined therein.

14. A display device, wherein: The display device includes a display area and a pad area arranged on the periphery of the display area, the display area includes a thin film transistor, and the display device includes: substrate; a first conductive layer disposed on the substrate, the first conductive layer comprising a gate electrode of the thin film transistor disposed in the display area and a gate signal line disposed in the pad area; a first insulating layer, disposed on the first conductive layer; a second conductive layer disposed on the first insulating layer, the second conductive layer including a source electrode and a drain electrode of the thin film transistor and a plurality of wiring pads disposed in the pad region; a second insulating layer disposed on the second conductive layer; and a third conductive layer, disposed on the second insulating layer, in, The plurality of wiring pads overlap the gate signal line in a thickness direction and are electrically connected to the gate signal line, each of the plurality of wiring pads comprising: A main pad portion extending in a first direction; a first protruding pad portion protruding from a first side of the main pad portion in a second direction intersecting the first direction; and a second protruding pad portion protruding from a second side of the main pad portion in the second direction; and a printed circuit board attached to the pad area and including lead wires connected to the plurality of wiring pads, wherein the lead-out line completely overlaps with the main pad portion of the plurality of wiring pads in the thickness direction, and at least partially overlaps with at least one of the first protruding pad portion and the second protruding pad portion of the plurality of wiring pads in the thickness direction, wherein the first protruding pad portion is arranged closer to the display area than the second protruding pad portion, wherein the first protruding pad portion and the second protruding pad portion have the same area and the same shape as each other, and The first edge of the lead line in the second direction is located in an area where the lead line partially overlaps with the first protruding pad, and the second edge of the lead line in the second direction is located in an area where the lead line partially overlaps with the second protruding pad.

15. The display device according to claim 14, wherein The first direction is a direction from the display area toward an end portion of the pad area where the plurality of wiring pads are provided, and The second side of the main pad portion in the second direction is opposite to the first side of the main pad portion in the second direction.

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