Ohmic contact and method for making the same

Abstract

An ohmic contact including a material and a method for forming an n-type ohmic contact on an n-type semiconductor substrate at low temperature is disclosed. The material includes a reactant layer, an n-type dopant layer, a capping layer, and in some cases, an adhesive layer. The capping layer may include a metal layer and a diffusion barrier layer. The ohmic contact may be formed on the n-type semiconductor substrate at a temperature between 150° C. and 250° C. and may resist degradation during operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 617,699, filed on January 16, 2018, and U.S. Provisional Patent Application No. 62 / 668,476, filed on May 8, 2018, the contents of which are incorporated herein by reference in their entireties. Technical Field

[0003] The present disclosure relates to ohmic contacts bonded to substrates made of III-V semiconductors and methods for making the same. Background Art

[0004] Semiconductor devices often include many components with different mechanical and physical properties. For example, a vertical cavity surface emitting laser (VCSEL) may include a semiconductor material embedded in a semiconductor material such as gallium arsenide (GaAs), aluminum arsenide (AlAs), and gallium aluminum arsenide (AlAs). x Ga 1-x As)) composed of a current limiting opening of a ceramic material such as aluminum oxide (Al2O3).

[0005] The physical properties of ceramics and semiconductors can differ significantly. For example, the coefficient of thermal expansion (CTE) of the ceramic current confining opening and the semiconductor material in which the ceramic current confining opening is embedded can be substantially different. In such cases, thermal stresses can develop at the ceramic-semiconductor interface during thermal processing, for example, when bonding an electrical contact to a substrate. These stresses can be sufficient to produce microstructural defects at the interface, resulting in reduced device lifetime.

[0006] Lowering the temperature of the heat treatment can effectively reduce the thermal stress developed at the interface. For example, heat treatment at 350°C for bonding electrical contacts often results in microstructural defects, while lower temperatures such as 150°C-250°C can result in fewer defects or eliminate them completely.

[0007] Therefore, there is a need for contact materials that produce ohmic electrical contacts after low temperature thermal processing.The ohmic contact should resist degradation during operation and have the same majority charge carrier type (ie, n-type or p-type) as the substrate to which the ohmic contact is bonded. Summary of the invention

[0008] The present disclosure relates to n-type ohmic electrical contacts bonded to n-type semiconductor substrates at low temperatures and methods for making the same. For example, in one aspect, a method for making an n-type ohmic contact on an n-type semiconductor substrate comprises the following steps:

[0009] o depositing a reactant layer on the n-type semiconductor substrate, the reactant layer comprising a metal reactant;

[0010] o depositing an n-type dopant layer on the reactant layer, the n-type dopant layer comprising an n-type dopant;

[0011] o depositing a capping layer on the reactant layer, the capping layer comprising a metal layer and a diffusion barrier layer; and

[0012] o The n-type semiconductor substrate, the reactant layer, the n-type dopant layer, and the capping layer are heated to a temperature that causes the n-type dopant to diffuse from the n-type dopant layer into the n-type semiconductor substrate to form an interface layer rich in the n-type dopant, and causes the n-type dopant and the metal reactant to diffuse into each other to form a product layer adjacent to the interface layer rich in the n-type dopant.

[0013] In some cases, the method for making an n-type ohmic contact further includes the step of depositing an adhesion layer.

[0014] In another aspect, the n-type ohmic contact comprises an n-type semiconductor substrate, and an interfacial layer rich in n-type dopants embedded in the n-type semiconductor substrate. The interfacial layer rich in n-type dopants comprises n-type dopants. The n-type ohmic contact further comprises a product layer adjacent to the interfacial layer rich in n-type dopants. The product layer comprises a metal reactant and an n-type dopant. The n-type ohmic contact further comprises a capping layer adjacent to the product layer. The capping layer comprises a metal layer and a diffusion barrier layer.

[0015] In some cases, the n-type ohmic contact further includes an adhesion layer between the product layer and the capping layer.

[0016] Other aspects, features, and advantages will be apparent from the following detailed description, the accompanying drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A Depicted are examples of layers deposited on a substrate prior to heating.

[0018] Figure 1B Depicted are example layers after heating. DETAILED DESCRIPTION

[0019] Figure 1A A series of layers are depicted that when processed according to the present disclosure, produce an n-type ohmic contact 100 with an n-type semiconductor substrate 102. The layers include a reactant layer 104, an n-type dopant layer 106, an adhesion layer 108, and a capping layer 110. The capping layer 110 includes a metal layer 112 and a diffusion barrier layer 114. The layers may be deposited by electron beam evaporation, sputtering, or thermal evaporation, but any suitable method may be used, as would be apparent to one of ordinary skill in the art.

[0020] The n-type semiconductor substrate 102 may be composed of one or more Group III elements, one or more Group V elements, and an n-type dopant. Figure 1A and Figure 1B The example n-type semiconductor substrate 102 depicted in the drawings is gallium arsenide (GaAs), but other III-V semiconductor materials are included within the scope of the present disclosure, such as aluminum arsenide (AlAs), gallium aluminum arsenide (AlAs), and x Ga 1-x As), indium antimonide (InSb), and gallium antimonide (GaSb). The n-type dopant may include one or more doping donors, such as silicon, germanium, and tin, to provide a carrier concentration suitable for a particular application. For example, when the n-type semiconductor substrate 102 is integrated in a vertical cavity surface emitting laser, the n-type dopant may be silicon doped to achieve 1×10 17 / cm 3 Up to 2×10 18 / cm 3 The carrier concentration between .

[0021] The reactant layer 104 includes a metal reactant (not depicted). Figure 1A An example metal reactant associated with the example reactant layer 104 in is palladium, but other elements are within the scope of the present disclosure. For example, the metal reactant may be one or more elements selected from the group consisting of: nickel, palladium, and platinum. Figure 1A The example reactant layer 104 in FIG. 5 is 520 angstroms thick, however, other thicknesses are within the scope of the present disclosure. For example, the metal reactant may be deposited such that the reactant layer 104 is between 300 angstroms and 620 angstroms.

[0022] N-type dopant layer 106 includes an n-type dopant (not depicted). The n-type dopant can include one or more types of donors, such as silicon, germanium, and tin. In some cases, the n-type dopant is deposited so that n-type dopant layer 106 is between 900 angstroms and 1860 angstroms. In some cases, n-type dopant layer 106 is between two and three times the thickness of reactant layer 104. In some cases, n-type dopant layer 106 is about 2.4 times the thickness of reactant layer 102. Depicted in Figure 1A The example n-type dopant layer 106 in FIG. 1 is 1250 angstroms thick and the n-type dopant is germanium. The n-type dopant is configured to diffuse through the reactant layer 104 and into the n-type semiconductor substrate 102 and intermix with the reactant layer 104. Thus, the composition and thickness of the n-type dopant layer 106 may depend on the desired amount of n-type dopant diffused into the n-type semiconductor substrate 102, the ratio of the n-type dopant to the metal reactant (e.g., in the reactant layer 104), and the temperature and duration of the subsequent heat treatment.

[0023] The metal layer 112 in the capping layer 110 may include one or more elements selected from the group consisting of: gold and silver. Figure 1A and Figure 1B The example metal layer 112 in FIG. 1 is gold. One or more elements may be deposited such that the thickness of the metal layer is between 500 angstroms and 1500 angstroms. The example metal layer 112 is 1000 angstroms. The metal layer 112 is configured to provide a low contact resistance substrate for additional electrical contact. Figure 1A and Figure 1B Examples include solder 116 in electrical communication with other electrical contacts (not depicted). Other electrical contacts, such as electroplated gold, are included within the scope of the present disclosure. In some cases, two to three microns of gold may be electroplated on metal layer 112.

[0024] The diffusion barrier layer 114 in the capping layer 110 may include one or more elements selected from the group consisting of: nickel, palladium, and platinum. The elements are deposited such that the thickness of the diffusion barrier layer 114 is between 650 angstroms and 850 angstroms. Figure 1A and Figure 1B The example in includes depositing platinum such that the diffusion barrier layer 114 is 750 angstroms thick. The composition and thickness of the diffusion barrier layer 114 may vary depending on the application. For example, in some cases, the solder 116 may include a component (e.g., indium) that may easily diffuse through the layer and into the n-type semiconductor substrate 102, thereby destroying the semiconductor device (e.g., a vertical cavity surface emitting laser) into which the n-type semiconductor substrate 102 is integrated. Thus, the thickness and composition of the diffusion barrier layer 114 may be strongly dependent on factors that affect the diffusion rate, such as the desired operating temperature of the semiconductor device, the bonding / soldering temperature, and the composition of the solder 116 or other electrical contact.

[0025] Adhesion layer 108 may include one or more elements selected from the group consisting of: titanium, zirconium, and hafnium. In some cases, the one or more elements may further include tungsten, tantalum, and / or molybdenum in an alloy, compound, mixture, or composite with any of the one or more elements selected from the group consisting of titanium, zirconium, and hafnium. For example, adhesion layer 108 may include titanium tungsten (TiW). The one or more elements are deposited such that the thickness of the adhesion layer is between 300 angstroms and 5000 angstroms. Depicted in Figure 1A and Figure 1B The example adhesion layer 108 in EMBODIMENT 5 comprises deposited titanium such that the thickness of the adhesion layer 108 is 400 angstroms.

[0026] In some cases, adhesion layer 108 may operate to prevent interdiffusion of n-type dopants and elements in diffusion barrier layer 114. Thus, the thickness and composition of adhesion layer 108 may depend on factors that affect diffusion rates, such as the composition of n-type dopant layer 104 and diffusion barrier layer 114, as well as the temperature and duration of the thermal treatment.

[0027] In some cases, the adhesion layer 108 may operate as a stress compensation layer or a stress balancing layer. The adhesion layer 108 may be characterized by an intrinsic stress that is operable to balance or counteract the intrinsic stress in or at the interface of other components of the n-type ohmic contact 100 (such as the n-type semiconductor substrate 100) or any components integrated into or on the n-type semiconductor substrate 100 (not depicted). In some cases, the adhesion layer 108 may operate to balance or counteract thermal stress in or at the interface of other components of the n-type ohmic contact 100. The adhesion layer 108 may be deposited to have an intrinsic stress via a technique known to impart an intrinsic stress in a material as deposited, such as sputtering. For example, the adhesion layer 108 may include sputtered titanium tungsten. In some cases, the adhesion layer 108 may operate to prevent interdiffusion of n-type dopants and may further operate as a stress compensation layer, while in other cases, the adhesion layer 108 may be omitted entirely.

[0028] Figure 1B An example n-type semiconductor substrate 102, reactant layer 104, n-type dopant layer 106, adhesion layer 108, and capping layer 110 after thermal treatment are depicted. After thermal treatment, an n-type ohmic contact 100 is formed with the n-type semiconductor substrate 102. The n-type semiconductor substrate 102, reactant layer 104, n-type dopant layer 106, adhesion layer 108, and capping layer 110 are heated to a temperature of, for example, 150° C. to 250° C. in an inert (e.g., N2, Ar) or reducing (95:5N2:H) atmosphere. Figure 1B The example n-type ohmic contact 100 depicted in FIG. 1 is the result of a heat treatment at 250° C. in a N 2 atmosphere for 15 minutes. In some cases, a slow ramp rate is employed to avoid thermal shock (eg, a ramp rate of 5° C. / min-8° C. / min may be used).

[0029] As described above, the n-type dopant in the n-type dopant layer diffuses into the n-type semiconductor substrate 102 to form an n-type dopant-rich interface layer 118. Furthermore, the n-type dopant and the metal reactant diffuse into each other to form a product layer 120. In some cases, the product layer 120 includes a product composed of the metal reactant and the n-type dopant in an atomic ratio of 1:4. In some cases, the product layer 120 is between 50% and 90% of the thickness of the reactant layer 104.

[0030] Other modifications may be made to the foregoing embodiments, and features described above in different embodiments may be combined in the same embodiment. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. A method for fabricating an n-type ohmic contact on an n-type semiconductor substrate, the method comprising the following steps: depositing a reactant layer on the n-type semiconductor substrate, the reactant layer comprising a metal reactant; depositing an n-type dopant layer on the reactant layer, the n-type dopant layer comprising an n-type dopant; depositing a capping layer on the reactant layer, the capping layer comprising a metal layer and a diffusion barrier layer; and The n-type semiconductor substrate, the reactant layer, the n-type dopant layer and the capping layer are heated to a temperature such that the n-type dopant diffuses from the n-type dopant layer into the n-type semiconductor substrate to form an interface layer rich in the n-type dopant, and the n-type dopant and the metal reactant diffuse into each other to form a product layer adjacent to the interface layer rich in the n-type dopant.

2. The method of claim 1, further comprising the step of depositing an adhesion layer. 3 . The method of claim 1 , wherein the n-type semiconductor substrate is composed of one or more Group III elements, one or more Group V elements, and one or more n-type dopants. 4 . The method according to claim 1 , wherein the metal reactant comprises one or more elements selected from the group consisting of nickel, palladium, and platinum, wherein the elements are deposited so that the thickness of the reactant layer is a specific thickness.

5. The method of claim 4, wherein the n-type dopant comprises one or more elements selected from the group consisting of silicon, germanium, and tin, wherein the elements are deposited such that the thickness of the n-type dopant layer is between two and three times the specific thickness. 6 . The method of claim 5 , wherein the specific thickness is between 300 angstroms and 620 angstroms and the thickness of the n-type dopant layer is between 900 angstroms and 1860 angstroms.

7. The method of claim 1, wherein the metal layer comprises one or more elements selected from the group consisting of gold and silver, wherein the elements are deposited such that the metal layer has a thickness between 500 angstroms and 1500 angstroms.

8. The method of claim 1, wherein the diffusion barrier layer comprises one or more elements selected from the group consisting of nickel, palladium, and platinum, wherein the elements are deposited such that the diffusion barrier layer has a thickness between 650 angstroms and 850 angstroms.

9. The method of claim 2, wherein the adhesion layer comprises one or more elements selected from the group consisting of titanium, zirconium, and hafnium, wherein the elements are deposited such that the adhesion layer has a thickness between 300 angstroms and 500 angstroms. 10 . The method of claim 1 , wherein the product layer comprises a product consisting of the metal reactant and the n-type dopant in an atomic ratio of 1:

4.

11. The method of claim 10, wherein the product layer is between 50% and 90% of the thickness of the reactant layer.

12. The method of claim 1, wherein the temperature is between 150°C and 250°C.

13. The method of claim 1, wherein the n-type semiconductor substrate, the reactant layer, the n-type dopant layer, and the capping layer are heated to the temperature in an inert or reducing atmosphere.

14. An n-type ohmic contact, comprising: n-type semiconductor substrate; an n-type dopant-rich interfacial layer embedded in the n-type semiconductor substrate, the n-type dopant-rich interfacial layer comprising an n-type dopant; a product layer adjacent to the n-type dopant-rich interfacial layer, the product layer comprising a metal reactant and the n-type dopant; and A capping layer is adjacent to the product layer, the capping layer comprising a metal layer and a diffusion barrier layer.

15. The n-type ohmic contact of claim 14, further comprising an adhesive layer between the product layer and the capping layer. 16 . The n-type ohmic contact of claim 14 , wherein the product layer consists of the metal reactant and the n-type dopant in an atomic ratio of 1:4, and the thickness of the product layer is between 150 angstroms and 558 angstroms.

17. The n-type ohmic contact of claim 14, wherein the n-type dopant comprises one or more elements selected from the group consisting of silicon, germanium, and tin, and the metal reactant comprises one or more elements selected from the group consisting of nickel, palladium, and platinum.

18. The n-type ohmic contact of claim 14, wherein the metal layer comprises one or more elements selected from the group consisting of gold and silver, and the thickness of the metal layer is between two micrometers and three micrometers.

19. The n-type ohmic contact of claim 14, wherein the diffusion barrier layer comprises an element selected from the group consisting of nickel, palladium, and platinum, and the thickness of the diffusion barrier layer is between 650 angstroms and 850 angstroms.

20. The n-type ohmic contact of claim 15, wherein the adhesion layer comprises one or more elements selected from the group consisting of titanium, zirconium, and hafnium, and the thickness of the adhesion layer is between 300 angstroms and 5000 angstroms.

21. The n-type ohmic contact of claim 15, wherein the adhesion layer operates to prevent interdiffusion of the n-type dopants and / or operates as a stress compensation layer.

22. The n-type ohmic contact of claim 21, wherein the adhesion layer comprises titanium tungsten.

23. The n-type ohmic contact of claim 22, wherein the titanium tungsten is deposited on the n-type dopant layer by sputtering such that the titanium tungsten is deposited with intrinsic stress.

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