Atomic layer deposition and etching for critical dimension control in a single plasma chamber

Abstract

The present invention describes methods and apparatus for critical dimension (CD) control of substrate features using integrated atomic layer deposition (ALD) and etching processes. The methods include: etching to form a feature mask pattern on a substrate having a width less than a desired width of a structure to be subsequently formed through the feature mask pattern; conformally depositing a passivation layer by ALD to increase the width of the feature mask pattern to the desired width, and etching a layer of the substrate to a desired depth to form a plurality of structures having the desired width.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of priority of U.S. Patent Application No. 15 / 820,108, filed on November 21, 2017, and entitled "ATOMIC LAYER DEPOSITION AND ETCH IN A SINGLE PLASMA CHAMBER FOR CRITICAL DIMENSION CONTROL", which is hereby incorporated by reference in its entirety and for all purposes. Technical Field

[0003] The present disclosure generally relates to integrated deposition and etching processes in semiconductor device manufacturing, and more particularly, to integrated atomic layer deposition (ALD) and etching processes for critical dimension control in integrated circuit manufacturing. Background Art

[0004] As device and feature sizes in the semiconductor industry continue to shrink, patterning of features with small critical dimensions will continue to become important in the manufacture of advanced integrated circuits (ICs). Current lithography methods may be limited in their ability to pattern small critical dimension features. Summary of the Invention

[0005] The disclosure is directed to a method for critical dimension (CD) control. The method includes: etching a first layer of a substrate in a plasma chamber to form a feature mask pattern having a width less than a desired width of a plurality of structures to be formed by the feature mask pattern. The method further includes: depositing a first passivation layer on the feature mask pattern by atomic layer deposition (ALD) in the plasma chamber, the first passivation layer being deposited to have a thickness that increases the width of the feature mask pattern to the desired width. The method further includes: etching a second layer of the substrate in the plasma chamber to form the plurality of structures having the desired width.

[0006] In some embodiments, the feature mask pattern includes one or more isolated features in an isolated feature region and one or more dense features in a dense feature region, the dense feature region having a higher feature density than the isolated feature region. After depositing the first passivation layer, the CD gain can be the same or substantially similar between the one or more isolated features in the isolated feature region and the one or more dense features in the dense feature region. After etching the second layer of the substrate, the depth variation can be the same or substantially similar between the isolated feature region and the dense feature region. In some embodiments, the method further includes: repeating the operations of depositing the second layer by ALD and etching the second layer in the plasma chamber, wherein after repeating the operations of depositing the second layer by ALD and etching the second layer, the CD gain is the same or substantially similar between the isolated features in the isolated feature region and the dense features in the dense feature region. In some embodiments, the feature mask pattern includes one or more first features having a first material and one or more second features having a second material, the second material being different from the first material, wherein after depositing the first passivation layer, the CD gain is the same or substantially similar between the one or more first features and the one or more second features. In some embodiments, the operations of depositing the second layer by ALD and etching the second layer in the plasma chamber are performed without causing a vacuum break between the operations. In some embodiments, the thickness of the first passivation layer is between about 0.5 nm and about 3 nm. In some embodiments, the method further includes: after etching the second layer of the substrate, depositing a second passivation layer by ALD in the plasma chamber on the plurality of structures, the second passivation layer being deposited to have a thickness corresponding to a desired CD gain. In some embodiments, the first passivation layer comprises silicon oxide (SiO x ). In some embodiments, depositing the first passivation layer by ALD includes: introducing a precursor into the plasma chamber to adsorb onto the feature mask pattern, using a plasma to convert the precursor to form the first passivation layer with a limited amount of adsorption, and repeating the operations of introducing the precursor and converting the precursor until the first passivation layer of the thickness is deposited on the feature mask pattern.

[0007] These and other aspects are further illustrated below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Schematic diagram of an example processing apparatus for performing etching and ALD operations according to some implementations.

[0009] Figures 2A - 2I Schematic diagram of a substrate in an exemplary multi-patterning scheme according to some implementations.

[0010] Figure 3A An exemplary processing flow of substrate transfer using conventional etching and ALD processing is shown.

[0011] Figure 3B An exemplary processing flow of substrate transfer using integrated etching and ALD processing is shown.

[0012] Figure 4 Flowchart of an example method for critical dimension (CD) recovery using etching and ALD processing according to some implementations.

[0013] Figures 5A - 5C Schematic diagram of isolated and dense substrate features that undergo deposition and etching using conventional deposition processing in a plasma chamber.

[0014] Figures 6A - 6C Schematic diagram of isolated and dense substrate features that undergo deposition and etching (using integrated ALD and etching processing according to some implementations).

[0015] Figures 7A - 7C Schematic diagram of substrate features of different materials that undergo deposition and etching using conventional deposition processing in a plasma chamber.

[0016] Figures 8A - 8C Schematic diagram of substrate features of different materials that undergo deposition and etching using integrated ALD and etching processing according to some implementations.

[0017] Figures 9A - 9C Schematic diagram of tapered substrate features that undergo deposition and etching in a separate tool.

[0018] Figures 10A - 10D Schematic diagram of tapered substrate features that undergo deposition and etching using integrated ALD and etching processing according to some implementations. Detailed Description

[0019] Preface

[0020] In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well-known processing operations are not described in detail in order not to obscure the present invention. Although the present invention is described in conjunction with specific embodiments, it is understood that it is not intended to limit the present invention.

[0021] In the present disclosure, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate", and "partially processed integrated circuit" are used interchangeably. One of ordinary skill in the art will understand that the term "partially processed integrated circuit" may refer to a silicon wafer during any of the many stages of integrated circuit processing performed thereon. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes that the present disclosure is implemented on a wafer. However, the present disclosure is not so limited. The workpiece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may utilize the present disclosure include various objects, such as printed circuit boards and the like.

[0022] Integrated Etching / ALD Processing Equipment

[0023] As feature sizes shrink, pitches become smaller, and complementary metal oxide semiconductor (CMOS) technology progresses to smaller nodes, thin conformal deposition techniques will continue to become important. Atomic layer deposition (ALD) is a film-forming technique well-suited for depositing thin conformal films because ALD deposits a single thin layer of material, the thickness of which is limited by the amount of one or more precursor reactants that can adsorb onto the substrate surface prior to their own film-forming chemical reaction (i.e., form an adsorption-limited layer). Each layer formed by ALD is thin and conformal, and the film formed is substantially consistent with the shape of the underlying device structures and features.

[0024] Conventionally, ALD and etching processes are performed on separate tools or platforms. For example, an ALD chamber does not perform an etching process, and an etching chamber does not perform an ALD process. Plasma etching chambers that perform deposition processes utilize plasma-induced deposition processes to form films that are non-conformal and are dependent on the aspect ratio.

[0025] According to some embodiments, Figure 1 is a schematic diagram of an example processing apparatus for performing etching and ALD operations. The processing apparatus 100 may be an inductively coupled plasma processing apparatus. The processing apparatus 100 includes a plasma chamber 132 such as a plasma etching chamber. In some embodiments, Kiyo manufactured by Lam Research Corporation (Fremont, CA) TMThe reactor is an example of a suitable reactor that can be used as a plasma etch chamber.

[0026] Details regarding the processing apparatus 100 for performing etch and ALD operations are described in the following U.S. patent application: U.S. Patent Application No. 15 / 669,871, titled "INTEGRATED ATOMIC LAYER PASSIVATION INTCP ETCH CHAMBER AND IN-SITU ETCH-ALP METHOD," filed on August 4, 2017, by Zhou et al., which is incorporated herein by reference in its entirety and for all purposes.

[0027] The plasma chamber 132 may include an integral chamber structure defined by the chamber walls 114 and the window 106. The window 106 may be made of quartz or other dielectric material. In some embodiments, the plasma chamber 132 includes a substrate support 116 disposed inside the plasma chamber 132. In some embodiments, the substrate support 116 is an electrostatic chuck for supporting the substrate 112 on which deposition / etch processes are performed. The electrostatic chuck may include electrostatic electrodes for clamping and unclamping the substrate 112. A filter and a DC clamping power supply (not shown) may be provided for this purpose. Other control systems for lifting the substrate 112 off the substrate support 116 may also be provided. The substrate support 116 is configured to receive and hold the substrate 112.

[0028] In some embodiments, the substrate support 116 may include a heater (not shown) for heating the substrate 112. The substrate support 116 may operate at an elevated temperature, for example, between about -20°C and about 150°C. The temperature will depend on the processing operation and the specific recipe. In some embodiments, the plasma chamber 132 may also operate at a specific pressure, for example, at a pressure between about 1 mTorr and about 1 Torr.

[0029] In some embodiments, the processing apparatus 100 may include a radio frequency (RF) power supply 120 that can be used to bias / power the substrate support 116. The RF power supply 120 may be defined by one or more RF generators. If multiple RF generators are provided, different frequencies may be used to achieve various tuning characteristics. A bias matching circuit 118 is coupled between the RF power supply 120 and the substrate support 116. In this way, the RF power supply 120 is connected to the substrate support 116.

[0030] A coil 134 is positioned above the window 106. The coil 134 may be made of a conductive material and includes at least one complete turn. Figure 1The coil 134 shown in [figure number] includes at least three turns. The RF power supply 121 is configured to supply RF power to the coil 134. The matching circuit 102 is coupled between the RF power supply 121 and the coil 134. In this way, the RF power supply 121 is connected to the coil 134. In some embodiments, an optional Faraday shield (not shown) is positioned between the coil 134 and the window 106. The Faraday shield can be maintained in a spaced relationship relative to the coil 134. The Faraday shield can be disposed directly above the window 106. The Faraday shield can prevent metal or other substances from depositing on the window 106 of the plasma chamber 132.

[0031] RF power is supplied from the RF power supply 121 to the coil 134 to cause an RF current to flow through the coil 134. The RF current flowing through the coil 134 can generate an electromagnetic field around the coil 134. The electromagnetic field generates an induced current within the plasma chamber 132, and this induced current acts on the gas present in the plasma chamber 132 to generate a plasma. Various ions and / or radicals from the plasma can interact with the substrate 112 to perform deposition or etching operations.

[0032] In some embodiments, the processing apparatus 100 optionally includes a plasma grid (not shown), which can be used to divide the plasma chamber 132 into upper and lower portions. The plasma grid can be used to limit the amount of hot electrons entering the lower portion of the plasma chamber 132. In some embodiments, the processing apparatus 100 is designed to operate such that the plasma present in the lower portion of the plasma chamber 132 is an ion-ion plasma, while the plasma present in the upper portion of the plasma chamber 132 is an electron-ion plasma.

[0033] The processing gas can be introduced into the plasma chamber 132 through the first gas injector 104 from the top of the plasma chamber 132 and / or through the second gas injector 110 from the side of the plasma chamber 132. The processing gas can include a vaporized liquid precursor or a vaporized solid precursor, which can be vaporized in a solid source evaporator (not shown) upstream of the processing apparatus 100. One or more reactant gases can be supplied through the first gas injector 104 and / or the second gas injector 110. In some embodiments, a showerhead can replace the gas injectors 104, 110. It should be understood that additional or other gas supply sources can be provided to supply different gases to the plasma chamber 132 for various types of operations.

[0034] Various ways of injecting gas into the plasma chamber 132 show that the process gas, vaporized liquid precursor, and / or vaporized solid precursor can be provided to the plasma chamber 132 from various positions. In some embodiments, only the first gas injector 104 is used. In some other embodiments, only the second gas injector 110 is used. In some other embodiments, both the first gas injector 104 and the second gas injector 110 are used. In some embodiments, the manifold 122 controls which gases are supplied to each of the different gas lines. The manifold 122 enables any type of gas (reactant, carrier, precursor, etc.) to be provided from any of the different gas lines. In some embodiments, the carrier gas may include gases such as oxygen (O 2 ), nitrogen (N 2 ), and helium (He). These gases can be introduced into the plasma chamber 132 without mixing or can be mixed with other gases before being introduced into the plasma chamber 132.

[0035] The manifold 122 can be used to select, switch, and / or mix the outputs from the corresponding delivery systems in the delivery system 128. In some embodiments, the delivery system 128 may include an etchant gas delivery system 127 and a liquid delivery system 129. The etchant gas delivery system 127 can be configured to output an etchant gas. Examples of etchant gases include (but are not limited to) chlorine (Cl 2 ), hydrogen bromide (HBr), and sulfur hexafluoride (SF 6 ). The liquid delivery system 129 can be configured to provide a liquid precursor that is vaporized and delivered in vapor form during ALD processing. The vaporized liquid precursor can be introduced into the plasma chamber 132 and can be adsorbed on the surface of the substrate 112. The adsorbed precursor can be converted using a plasma to form a film with a limited adsorption capacity. Example liquid precursors may have a chemical composition with the following chemical formula: C x H y N z O a Si b .

[0036] The vacuum pump 130 is connected to the plasma chamber 132 and can be used to pump out the process gas from the plasma chamber 132 and maintain a specific pressure inside the plasma chamber 132. A valve 126 can be set between the discharge portion 124 and the vacuum pump 130 to control the amount of vacuum suction applied to the plasma chamber 132. In some embodiments, the vacuum pump 130 can be a single- or two-stage mechanical dry pump and / or a turbomolecular pump. In some embodiments, the vacuum pump 130 can be started after each ALD process is completed to purge the plasma chamber 132.

[0037] When installing the processing apparatus 100 in a clean room or a manufacturing facility, it can be coupled to the facility (not shown). The facility includes pipelines that provide process gases, vacuum, temperature control, and environmental particle control. When these facilities are installed in a target manufacturing facility, they can be coupled to the processing apparatus 100. In addition, the processing apparatus 100 can be coupled to a transfer chamber that allows a robotic arm to transfer substrates into and out of the plasma chamber 132 using an automated system.

[0038] In some embodiments, the system controller 108 (which may include one or more physical or logical controllers) controls some or all of the operations of the processing apparatus 100. The system controller 108 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or a computer, analog and / or digital input / output connectors, a stepper motor control board, and other similar components. Instructions for performing appropriate control operations are executed on the processor. These instructions may be stored in the memory device associated with the system controller 108, or these instructions may be provided via a network. In certain embodiments, the system controller 108 executes system control software.

[0039] The system control software may include instructions for controlling the timing of the application and / or amplitude of any one or more of the following chamber operating conditions: mixing and / or composition of the gas, chamber pressure, chamber temperature, wafer / wafer support temperature, bias applied to the substrate (which may be zero in many embodiments), frequency and power applied to the coil or other plasma generating components, substrate position, substrate movement speed, and other parameters of a specific process performed by the tool. The system control software can be configured in any suitable manner. For example, subroutines or control objects of various processing tool components can be written to control the operation of the processing tool components that are necessary for performing the processing of various processing tools. The system control software can be encoded in any suitable computer-readable programming language.

[0040] In some embodiments, the system control software includes input / output control (IOC) sequence instructions for controlling the various parameters described above. For example, each stage of a semiconductor manufacturing process may include one or more instructions executed by the system controller 108. For example, instructions for setting the processing conditions of a stage may be included in the corresponding recipe stage. In some embodiments, the recipe stages can be configured in sequence so that the steps in a doping process are performed in a specific order of the processing stage. For example, the recipe can be configured to perform an etching operation and include one or more cycles of ALD processing performed between each of the etching operations.

[0041] In some embodiments, the system controller 108 is configured with instructions for performing one or more of the following: etching a first layer of the substrate 112 in the plasma chamber 132 to form a feature mask pattern having a width less than the desired width of a plurality of structures to be formed by the feature mask pattern; depositing a first passivation layer on the feature mask pattern by ALD in the plasma chamber 132, the first passivation layer being deposited to have a thickness that increases the width of the feature mask pattern to the desired width; and etching a second layer of the substrate 112 in the plasma chamber 132 to form the plurality of structures having the desired width. In the plasma chamber 132, the etching and deposition operations are performed without causing a vacuum break. In some embodiments, the system controller 108 is further configured to perform the operations of depositing and etching by ALD repeatedly in the plasma chamber 132.

[0042] In some embodiments, other computer software and / or programs may be employed. Examples of programs or portions of programs for this purpose include a substrate positioning program, a process gas composition control program, a pressure control program, a heater control program, and an RF power control program.

[0043] In some cases, the system controller 108 controls the gas concentration, substrate movement, and / or the power supplied to the coil 134 and / or the substrate support 116. The system controller 108 can control the gas concentration, for example, by opening and closing relevant valves to generate one or more inlet gas flows that provide the necessary reactants at an appropriate concentration. The substrate movement can be controlled, for example, by instructing the substrate positioning system to move as needed. The power supplied to the coil 134 and / or the substrate support 116 can be controlled to provide a specific RF power level. If a grid is used, the RF power can be adjusted by the system controller 108 to generate an electron-ion plasma in the upper portion of the plasma chamber 132 and an ion-ion plasma in the lower portion of the plasma chamber 132. Additionally, the system controller 108 can be configured to supply power to the substrate support 116 in the case where an electron-ion plasma does not form in the lower portion of the plasma chamber 132.

[0044] The system controller 108 can control these or other aspects based on sensor outputs (e.g., when power, potential, pressure, etc. reach a certain threshold), operation timing (e.g., opening valves at certain moments during processing), or based on instructions received from a user.

[0045] In some implementations, the system controller 108 is part of a system that can be part of the above examples. Such systems can include semiconductor processing equipment, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer chucks, gas flow systems, etc.). These systems can be integrated with electronics for controlling their operations before, during, and after the processing of semiconductor wafers or substrates. The electronics can be referred to as a "controller" that can control various components or sub-components of one or more systems. Depending on the processing requirements and / or system type, the system controller 108 can be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, substrate transfer in and out of tools and other transfer tools, and / or load locks connected or interfaced to a particular system.

[0046] Broadly speaking, the system controller 108 can be defined as electronics having various integrated circuits, logic, memory, and / or software for receiving instructions, issuing instructions, controlling operations, enabling cleaning operations, enabling endpoint measurements, etc. The integrated circuits can include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions sent to the system controller 108 in the form of various individual settings (or program files) that define operation parameters for performing a specific process on or for a semiconductor wafer or system, or for a semiconductor substrate or system. In some embodiments, the operation parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or die of a wafer.

[0047] In some implementations, system controller 108 can be part of or coupled to a computer that is integrated with, coupled to, otherwise networked to, or a combination of the system. For example, system controller 108 can be in the "cloud" or be all or part of a wafer fab host system, which can allow remote access to substrate processing. The computer can implement remote access to the system to monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, examine trends or performance criteria of multiple manufacturing operations, change the parameters of the current process, set processing steps to follow the current process, or initiate a new process. In some examples, a remote computer (such as a server) can provide a process recipe to the system via a network, which can include a local network or the Internet. The remote computer can include a user interface that enables input or programming of parameters and / or settings, which are then sent from the remote computer to the system. In some examples, system controller 108 receives instructions in the form of data that specify the parameters for each processing step to be performed during one or more operations. It should be understood that the parameters can be specific to the type of process to be performed and the type of tool, and system controller 108 is configured to interface with or control the tool. Thus, as described above, system controller 108 can be distributed, for example, by including one or more discrete controllers that are networked together and work towards a common purpose, such as the processing and control described herein. An example of a distributed system controller 108 for such a purpose is one or more integrated circuits on a chamber that communicate with one or more integrated circuits remote (such as at the platform level or as part of a remote computer), which combine to control the processing on the chamber.

[0048] Example systems can include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that can be associated with or used for the manufacture and / or preparation of semiconductor wafers or semiconductor substrates.

[0049] As described above, system controller 108 can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another system controller 108, or tools used in the material transport that shuttles the container of the substrate between tool locations and / or load ports in a semiconductor manufacturing facility, depending on one or more processing steps to be performed by the tool.

[0050] Patterning and Critical Dimension

[0051] As device features are scaled down and the pitch in semiconductor devices becomes smaller, controlling and fine-tuning the critical dimension (CD) of substrate features becomes more important. The CD can also be referred to as the "minimum feature size" or "target design criterion". In some embodiments, the CD can refer to the size of the smallest geometric feature (e.g., the width of an interconnect line, contact window, trench, etc.). In some embodiments, the CD can refer to the narrowest width that can be achieved by a patterning process.

[0052] Patterning methods are used in many semiconductor manufacturing processes to achieve a desired critical dimension. A mask (e.g., a photoresist pattern or a hard mask) can have a CD, which is the width of the smallest feature. In some embodiments, features can be formed when an etching operation is performed through the mask.

[0053] In the pursuit of features with smaller CDs, masks with smaller CDs are needed. Photoresist masks generally have optical properties that depend on the wavelength. A photoresist mask with a longer wavelength has a larger theoretical CD when exposed to light with a longer wavelength, while a photoresist mask with a shorter wavelength has a smaller theoretical CD when exposed to light with a shorter wavelength. However, using a photoresist mask with a shorter wavelength may pose additional problems compared to a photoresist mask with a longer wavelength. For example, a photoresist mask with a shorter wavelength may not have as high a selectivity as a photoresist mask with a longer wavelength and may be more prone to deformation in the case of plasma etching.

[0054] Various patterning schemes (e.g., single patterning or multiple patterning) can be utilized to form or provide the masks of the present disclosure. In particular, multiple patterning has been used to extend lithography beyond its optical limits. Double patterning and quadruple patterning are exemplary techniques for extending lithography beyond its optical limits, and currently double patterning is widely used in the industry for pitches less than about 80 nm. Current double patterning techniques typically use sidewall spacers and two mask processing steps to pattern trenches. The double patterning (especially the patterning of lines) methods in both positive and negative double patterning processes involve the use of spacers and masks. The spacers can be deposited on the patterned core by ALD or by plasma-enhanced atomic layer deposition (PEALD), and the spacers can be used to create patterns with smaller pitches.

[0055] Figures 2A - 2I Schematic diagram of a substrate in an exemplary multiple patterning scheme according to some embodiments. Figure 2AA substrate is shown having the following structure: a core 201 defined or patterned lithographically on a first layer 203, a second layer 205 beneath the first layer 203, and a third layer 207 beneath the second layer 205. Those skilled in the art will understand that the multi-layer stack suitable for semiconductor processing described herein may also include other layers, such as an etch stop layer, a capping layer, and other underlying layers.

[0056] As Figure 2A shown, the patterned core 201 can be a photoresist or can include amorphous carbon or amorphous silicon materials. The patterned core 201 can be deposited above the first layer 203 by any suitable deposition technique, which can involve generating a plasma from deposition gases (such as hydrocarbon precursors) in a deposition chamber. The first layer 203, the second layer 205, or the third layer 207 can be a target layer that is ultimately patterned in a multiple patterning process. The target layer can be a semiconductor, a dielectric, or other layer and can be made of, for example, silicon (Si), silicon oxide (SiO 2 ), silicon nitride (SiN), or titanium nitride (TiN). In Figure 2B , a conformal film 209 is deposited above the patterned core 201. In some embodiments, the conformal film 209 can be deposited by ALD or PEALD. The conformal film 209 can be etched directionally to form spacers 219, as Figure 2C shown. The spacers 219 can be an oxide (such as silicon oxide (SiO 2 ) or titanium oxide (TiO 2 )) or can be a nitride (such as silicon nitride (SiN)). The pattern of the spacers 219 is used to pattern subsequent layers. It should be understood that the term "spacer" as used herein means a masking material adjacent to the core material. In Figure 2D , the patterned core 201 is selectively etched, leaving isolated spacers 219 on the substrate. Selective removal or selective etching as used herein is defined as etching one material relative to another material. For example, in Figure 2D , the patterned core 201 is etched relative to the spacers 219. The pattern of the spacers 219 can have a desired pitch or CD, where the CD can be equal to or less than about 50 nm. In Figure 2E , the patterned spacers 219 are used as a mask to etch the first layer 203, thereby transferring the pattern to the first layer 203 to form a patterned first layer 213. Chemicals can be used to etch the patterned first layer 213, which are suitable for etching the first layer 203 but not for etching the patterned spacers 219. In some embodiments, the patterned first layer 213 can be an amorphous carbon layer, an amorphous silicon layer, or a photoresist, such as polymethyl methacrylate, or poly(methylvaleramide) (PMGI), or novolak resin. In Figure 2FIn this case, the spacer 219 is selectively removed to leave the patterned first layer 213. The patterned first layer 213 can provide a mask with a smaller CD for forming features with a smaller CD. However, the patterned first layer 213 can alternatively provide a second core material for subsequent patterning. In Figure 2G In this case, a second conformal film 220 can be deposited over the patterned first layer 213 (e.g., the second core material). The second conformal film 220 can be a dielectric material deposited by ALD or PEALD. For example, the second conformal film 220 can be silicon oxide. In Figure 2H In this case, the second conformal film 220 is directionally etched to form second spacers 221 on both sides of the patterned first layer 213. In Figure 2I In this case, the patterned first layer 213 is selectively removed to leave the second spacers 221. The second spacers 221 can provide a mask with an even smaller CD for forming features with an even smaller CD.

[0057] The pattern of the spacers 221 can be transferred to the second layer 205. Multiple patterning techniques (e.g., Figures 2A - 2I the techniques shown) can be used to achieve a smaller CD. However, multiple patterning techniques use etching steps and deposition steps, which may require transfer between different tools and platforms, as well as additional cleaning steps between the etching and deposition steps, as Figure 3A shown.

[0058] Figure 3A shows an exemplary process flow for substrate transfer using conventional etching and ALD processing. It should be understood that Figure 3A such a process flow in this case is not limited to the multiple patterning scheme discussed above, but can be applied to other schemes using conventional etching and ALD processing. In Figure 3A In this case, a substrate is provided in an etching chamber and undergoes an etching step in block 301, is transferred to a cleaning chamber to undergo a cleaning step in block 303, is transferred to an ALD chamber to undergo an ALD step in block 305, is transferred back to the same or a different cleaning chamber to undergo a cleaning step in block 307, and is transferred back to the same or a different etching chamber in block 309. During the execution of the etch-deposition-etch sequence, the substrate can undergo 4 substrate transfers through 3 - 5 different chambers. In some embodiments, the etching step in block 301 can define a mask, the ALD step in block 305 can perform CD control, and the etching step in block 309 can define the final structure.

[0059] Using separate chambers for deposition and etching increases the processing time, processing steps, and cost, thus having an adverse impact on productivity. In addition, using separate chambers requires transferring the substrate from one chamber to another, which results in vacuum breakage and an increased likelihood of contact between unwanted materials or particles and the substrate. This can lead to a loss of material functionality and / or integrity on the substrate. In addition, as Figure 3A shown, a cleaning process is generally required between the etching and deposition processes, and this cleaning process may affect the material properties and structure on the substrate. For example, a diluted hydrofluoric (HF) acid cleaning process can affect the mask structure and may have an adverse impact on performance.

[0060] To achieve a smaller CD while avoiding issues associated with performing the etching step and the deposition step in different tools, a plasma etching chamber can be utilized and used for performing deposition. Such deposition processes can include chemical vapor deposition (CVD) and plasma-enhanced chemical vapor deposition (PECVD) processes. However, such deposition processes typically deposit non-conformal films. Specifically, these deposition processes depend on the aspect ratio and deposit more material in more open spaces or wider pitches, resulting in non-uniform deposition of structures or features with different aspect ratios. Specifically, more deposition occurs in isolated features than in non-dense features, where the CD deviation of isolated features is greater than that of dense features.

[0061] Embodiments of the present disclosure relate to integrating an ALD step and an etching step in a plasma chamber. By using in-situ ALD instead of implementing ALD in a separate chamber and not using CVD / PECVD in the same chamber, an independent ALD tool and an additional cleaning tool are eliminated. Furthermore, the processing time and cost are reduced by eliminating the additional substrate transfer and cleaning time. In addition, using in-situ ALD avoids vacuum breakage between substrate transfers (e.g., between non-in-situ deposition and cleaning), and vacuum breakage between substrate transfers may expose the substrate to unwanted materials, atmosphere, and / or moisture. Using in-situ ALD also reduces non-uniform deposition of structures or features with different aspect ratios. In-situ ALD can refer to ALD performed in a plasma etching chamber (e.g., the plasma chamber in the processing device 100 described above Figure 1 .

[0062] Figure 3B shows an exemplary processing flow of substrate transfer using an integrated etching and ALD process. It should be understood that Figure 3B such a processing flow in Figure 3BIn [the method], a substrate is provided in an etching chamber and undergoes an etching step in block 351, remains in the same etching chamber to undergo ALD in block 353, remains in the same etching chamber to undergo an etching step in block 355, and is transferred to a cleaning chamber to undergo a cleaning step in block 357. During the execution of the etch-deposition-etch sequence, the substrate may undergo 1 substrate transfer through 2 different chambers. In some embodiments, the etching step in block 351 may define a mask, the ALD step in block 353 may perform CD control, and the etching step in block 355 may define the final structure.

[0063] Critical Dimension Control Using In - situ ALD and Etching

[0064] Embodiments of the present disclosure relate to a CD control method using in-situ ALD and etching. Specifically, cycles of ALD and etching steps are performed in the same processing chamber or tool. In some embodiments, the cycles of ALD and etching steps are performed in a plasma processing apparatus as Figure 1 described. The ALD cycle performed in the same plasma processing apparatus as the etching provides conformal deposition, which is used to control the CD of one or more features of the substrate.

[0065] Figure 4 FIG. [number] is a flowchart of an exemplary method for critical dimension (CD) recovery using etching and ALD processing according to some embodiments. The operations in process 400 may be performed in a different order and / or with different, fewer, or additional operations.

[0066] In block 410 of process 400, a first layer of the substrate is etched in a plasma chamber to form a mask pattern for the features. The plasma chamber may be configured to perform subsequent etching and deposition processes. Aspects of the plasma chamber may be described with respect to Figure 1 processing apparatus 100 therein. The width of the feature mask pattern is less than the desired width of the plurality of structures to be formed by the feature mask pattern. The feature mask pattern may be patterned by etching and may serve as a mask during subsequent manufacturing steps. In some embodiments, the first layer for defining the feature mask pattern may include a resist or photoresist material. In some embodiments, the first layer for defining the feature mask pattern may include a hard mask material. In some embodiments, the first layer for defining the feature mask pattern may include silicon or other semiconductor materials. Conventional etching and patterning processes may be used to form the feature mask pattern in the first layer.

[0067] In some embodiments of process 400, a substrate is provided in a plasma chamber. The substrate can be positioned on a substrate support in the plasma chamber. In some embodiments, the substrate can be a semiconductor substrate, such as a 200-mm, 300-mm, or 450-mm substrate, including a silicon substrate. In some embodiments, a substrate pre-patterned with a feature mask pattern is provided in the plasma chamber.

[0068] In some embodiments, the feature mask pattern can include one or more isolated features in an isolated feature region of the substrate, and one or more dense features in a dense feature region of the substrate. The one or more dense features in the dense feature region have a greater feature density than the one or more isolated features in the isolated feature region. The one or more dense features can provide features having a higher aspect ratio than the one or more isolated features.

[0069] In some embodiments, the feature mask pattern can include one or more features having a first material, and one or more other features having a second material, where the second material is different from the first material. The feature mask pattern can include two different materials, where the two different materials can react in different ways in a passivation process or an etching process. The two different materials can be used to produce one or more masks having different pitches. For example, the first material can include silicon, while the second material can include silicon-germanium or germanium.

[0070] In some embodiments, at least some of the feature mask patterns can have a tapered profile. The patterning process can produce a mask profile having some degree of taper. In some embodiments, the etching performed in block 410 can straighten the tapered profile and reduce any pinch-off or merging caused by subsequent deposition. In some embodiments, process 400 further includes anisotropically etching at least a portion of the feature mask pattern having a tapered profile to correct the tapered profile prior to subsequent deposition.

[0071] The feature mask pattern can include a plurality of geometries, spacers, or features, each of which has a width corresponding to the critical dimension (CD) of the feature mask pattern. In some embodiments, each of the geometries, spacers, or features of the feature mask pattern has the same or substantially similar width. "Substantially similar" throughout this disclosure, with respect to the width or CD of the feature mask pattern, refers to a value that varies within plus or minus 5% of a given value. Thus, the CD or spacer CD of the feature mask pattern is relatively consistent or fixed across the entire feature mask pattern disposed on the substrate. In some embodiments, the CD or spacer CD between one or more isolated features and one or more dense features can be the same or substantially similar. In some embodiments, the spacer CD of the feature mask pattern is equal to or less than about 5 nm.

[0072] After etching the first layer to form a feature mask pattern, the CD of the feature mask pattern generally does not equal the CD of the multiple structures to be formed using the feature mask pattern. This can be attributed to the effects of faceting, mask erosion, and undercutting caused by lateral etching. In some cases, a higher degree of overetch is deliberately performed to increase the process window of the mask opening etch process, but a smaller CD is obtained. Therefore, the CD of the multiple structures to be formed using the feature mask pattern may be smaller than the CD of the feature mask pattern.

[0073] A passivation technique can be applied to the mask to minimize CD loss due to etching. For example, "flash" passivation or plasma-based passivation in the form of etching byproduct redeposition has been used to minimize the effects of faceting, mask erosion, and undercutting caused by lateral etching. However, plasma-based passivation techniques generally depend on the aspect ratio, which means that more passivation material is deposited in isolated features compared to dense features. Plasma-based passivation techniques also depend on the material, which means that more or less passivation material is deposited between different materials. In addition, plasma-based passivation techniques (such as oxygen "flash" passivation) consume the material on the target feature through oxidation and cause CD loss. "Flash" passivation can refer to igniting a gas such as oxygen (O 2 ) and / or nitrogen (N 2 ) to form a plasma of dissociative radicals that react with the surface and form a passivation layer of material (such as an oxide or nitride) on the surface. Generally speaking, passivation techniques can minimize the effects of faceting, mask erosion, and undercutting caused by lateral etching, but do not control or fine-tune the CD. In other words, conventional passivation techniques can be used to limit CD loss, but the passivation techniques themselves are not suitable for precisely adjusting the CD.

[0074] In block 420 of process 400, a first passivation layer is deposited on the feature mask pattern by atomic layer deposition (ALD) in a plasma chamber. The first passivation layer is deposited to have a thickness that increases the width of the feature mask pattern to a desired width. The ALD of block 420 is performed in the same plasma chamber as the etching of block 410 without introducing a vacuum break in the operating room.

[0075] ALD is a technique for depositing thin layers of material using sequential self-limiting reactions. Typically, an ALD cycle involves the following operations: delivering and adsorbing at least one reactant to the substrate surface and then reacting the adsorbed reactant with one or more reactants to form a partial layer. Unlike CVD techniques, ALD uses surface self-limiting deposition reactions to deposit films in a layer-by-layer manner. A typical ALD cycle can include: (i) dosing a precursor material onto the substrate surface, (ii) purging excess precursor material from the chamber, leaving a self-limiting monolayer on the substrate surface, (iii) delivering a reactant material to react with the adsorbed precursor material, and (iv) purging unreacted reactant material or reaction by-products from the chamber. The dosing step can adsorb the precursor material in a self-limiting manner such that once the active sites are occupied by the precursor material, little or no additional precursor material will adsorb onto the substrate surface. The reactant material can similarly react with the precursor material in a self-limiting or adsorption-limited manner. The purge step can optionally be performed to remove excess precursor material, reaction by-products, and / or unreacted reactant material from the chamber, thus completing the ALD cycle. ALD can be used to provide highly conformal films with high step coverage, even in high aspect ratio features.

[0076] A first passivation layer can be conformally deposited on a feature mask pattern by ALD. The ALD process for conformally depositing the first passivation layer can occur in one or more cycles, where each cycle produces an adsorption-limited amount of passivation material on the feature mask pattern. Each cycle can include a dosing step in which a controlled amount of precursor material is delivered to the substrate surface for adsorption onto the substrate surface in a self-limiting manner. This is also referred to as "soaking" the substrate surface to saturation. Each cycle can further include a conversion step following the dosing step in which a reactant material is provided to react with the precursor material on the substrate surface and form an adsorption-limited amount of passivation material. The reactant material can include a reactant gas, where an RF power source generates a plasma of the reactant gas in a plasma chamber. The reactant gas can include, for example, an oxygen-containing gas (e.g., O 2 ) or a nitrogen-containing gas (e.g., N 2 or NH 3)。The free radicals and other charged species of the reactant gas react with the precursor material to convert the precursor material into a passivation material with a limited adsorption capacity. In some embodiments, the reactant gas is exposed to RF power for a relatively short amount of time (e.g., between about 0.5 seconds and about 5 seconds) to form a plasma, thereby converting the precursor material. This is also referred to as "rapid" operation, which uses the plasma from RF power transmitted in a relatively short amount of time to convert the precursor material on the substrate surface. In some embodiments, a purge step can remove excess precursor material, reaction by-products, and / or unreacted reactant material from the plasma chamber to complete the cycle. In some embodiments, the dosing step and the conversion step can be repeated until the desired thickness of the first passivation layer is deposited.

[0077] The first passivation layer can comprise, for example, an oxide (e.g., SiO x ) or a nitride (e.g., Si x N y ). The first passivation layer is used to protect the feature mask pattern (including the sidewalls of the feature mask pattern) during subsequent etching processes (e.g., the etching process described in block 430).

[0078] The first passivation layer is deposited conformally by ALD and may have a high step coverage, such as a step coverage greater than 85%, greater than 90%, or greater than 95%. The high conformality of the first passivation layer provides a relatively uniform first passivation layer thickness along the surface and sidewalls of the feature mask pattern. In some embodiments, the thickness of the first passivation layer may be between about 0.1 nm and about 5 nm, or between about 0.5 nm and about 3 nm. The thickness of the first passivation layer can increase the width of the feature mask pattern to a desired width in a linear relationship, where the desired width corresponds to the desired CD of the plurality of structures to be formed subsequently. Thus, the CD of the feature mask pattern can be controlled by the thickness of the first passivation layer. In some embodiments, any CD loss due to the etching of the frame 410 can be recovered by the thickness of the deposited first passivation layer. In some embodiments, precise CD adjustment can be performed at the frame 420 to control the CD of the feature mask pattern, thereby controlling the CD of the plurality of structures or features to be formed subsequently. The relevant CD for CD control or recovery can depend on the application of the semiconductor device being manufactured. After etching, the CD of the remaining material can be the relevant CD in some cases, such as the gate or transistor size after patterning and gate etching. Alternatively, the CD of the removed material (e.g., spacer CD) can be the relevant CD in some cases, such as when spacers, trenches, or holes are opened after etching (which may or may not be filled subsequently). The CD gain from the deposited first passivation layer is independent of the aspect ratio and material. In addition, the CD can be adjusted at the frame 420 without affecting the subsequent etching performance. In other words, the CD can be adjusted with a minimal or negligible impact on the CD loading between isolated and dense features and with a minimal or negligible impact on the depth loading between isolated and dense features.

[0079] In block 430 of process 400, a second layer of the substrate is etched in a plasma chamber to form a plurality of structures having a desired width. The etching in block 430 is performed in the same plasma chamber as the etching in block 410 and the ALD in block 420 without causing a vacuum break between operations.

[0080] The second layer can be a target layer for various geometric features for patterning the substrate, where such geometric features can correspond to or be defined by a plurality of structures. Geometric features can include, for example, interconnect lines, trenches, recesses, spacers, holes, etc. A feature mask pattern can be utilized to define a plurality of structures, where the CD of the plurality of structures is the same as or substantially similar to the CD of the feature mask pattern. Throughout this disclosure, "substantially similar" with respect to the CD difference between the feature mask pattern and the plurality of structures refers to a value that varies within plus or minus 5% of a given value. In some embodiments, the CD of the plurality of structures can be equal to or less than about 20 nm, equal to or less than about 15 nm, or equal to or less than about 10 nm. Although the CD described refers to the CD of the plurality of structures defined by the feature mask pattern, it should be understood that the relevant CD can be the pitch CD of the plurality of geometric features (such as trenches, recesses, spacers, and holes) defined by the feature mask pattern.

[0081] The etching performed in the plasma chamber can be anisotropic etching that etches through the second layer to form features in the second layer. The etching can selectively etch the second layer material relative to the materials of the first layer and the first passivation layer. In this way, the etching performed at block 430 selectively etches the second layer without etching the feature mask pattern. In some embodiments, the etching can extend through the second layer to a first depth, where the first depth is less than the final depth. For example, the first depth can be any suitable percentage of the final depth, such as 20%, 30%, 40%, 50%, 60%, etc. of the final depth. Thus, multiple etchings can be performed to reach the final depth.

[0082] In some embodiments, the ALD and etch operations in the plasma chamber are repeated until a final depth is reached. The final depth may extend partially through the second layer or completely through the second layer. In some embodiments, the final depth may extend through additional underlying layers, such as a third layer, a fourth layer, etc. The repeated etch operations may etch through the second layer or a third layer below the second layer. In some embodiments, the ALD and etch operations in the plasma chamber are repeated in a multiple patterning process. For example, each ALD operation after the etch operation may conformally deposit an additional passivation layer (such as a second passivation layer, a third passivation layer, etc.) to further adjust or reduce the CD of the substrate features. Also, each etch operation after the ALD operation may etch through the second layer or an underlying layer (such as a third layer, a fourth layer, a fifth layer, etc.). In some embodiments, process 400 further includes depositing a second passivation layer by ALD on the plurality of structures after etching the second layer of the substrate, and the second passivation layer is deposited to have a thickness corresponding to a desired CD gain. Process 400 may further include etching the second layer or the third layer of the substrate to form a plurality of features (such as trenches) having a desired CD. Such multiple patterning schemes can achieve critical dimension shrinkage in a controlled manner without substrate transfer between the etch-deposition-etch operations.

[0083] The first passivation layer protects the feature mask pattern from the etch in block 430. Protects the sidewalls and surface of the feature mask pattern in cases where the minimum CD loss is independent of the aspect ratio and independent of the material. Further, protects the sidewalls and surface of the feature mask pattern in cases where the CD loading is minimized between different materials and different aspect ratios, where the profile loading is minimized between different materials and different aspect ratios, and where the depth loading is minimized between different materials and different aspect ratios.

[0084] In some embodiments, the following operations are repeated in process 400: deposition by ALD in the plasma chamber in block 420 and etching of the second layer in block 430. In cases where the feature mask pattern includes isolated and dense features, the CD gain is the same or substantially similar after repeating the operations of deposition by ALD and etching the second layer. In cases where the feature mask pattern includes different materials, the CD gain is the same or substantially similar after repeating the operations of deposition by ALD and etching the second layer.

[0085] Figures 5A - 5C Schematic diagrams of isolated and dense substrate features that undergo deposition and etching using a conventional deposition process in a plasma chamber. Figures 6A - 6CSchematic diagrams of isolated and dense substrate features that undergo deposition and etching using an integrated ALD and etching process according to some embodiments. A comparison between isolated and dense substrate features in a conventional etch-deposition-etch process and an in-situ ALD etch-deposition-etch process discloses the effects of CD bias and CD gain in isolated and dense substrate features.

[0086] Figure 5A Shows a partially processed device structure 510 that includes a substrate 502 and feature mask patterns 504a, 504b. The feature mask patterns 504a, 504b can be patterned and defined after etching in a plasma chamber. The feature mask patterns 504a, 504b can distinguish between dense features 504a in a dense feature region of the substrate 502 and isolated features 504b in an isolated feature region of the substrate 502, with the dense features 504a having a higher feature density than the isolated features 504b. The dense features 504a in the dense feature region can define gaps having a higher aspect ratio than the isolated features 504b in the isolated feature region. The feature mask patterns 504a, 504b can have the same or substantially similar CDs, as Figure 5A shown.

[0087] Figure 5B Shows a partially processed device structure 520 that includes a substrate 502, feature mask patterns 504a, 504b, and a first passivation layer 506 deposited on the feature mask patterns 504a, 504b. The first passivation layer 506 can be deposited in a plasma chamber using a conventional deposition process (e.g., CVD or PECVD). Alternatively, a plasma-based "rapid" passivation technique can be used to deposit the first passivation layer 506, where a portion of the feature mask patterns 504a, 504b is consumed by oxidation or nitridation. As Figure 5B shown, the thickness of the first passivation layer 506 is greater on the isolated features 504b in the isolated feature region than on the dense features 504a in the dense feature region. The isolated features 504b receive more deposition than the dense features 504a. Thus, the CD gain is greater in the isolated feature region than in the dense feature region. The partially processed device structure 520 represents the device structure 510 after deposition using a conventional deposition process in a plasma chamber.

[0088] Figure 5CDisclosed is a partially processed device structure 530, which includes a substrate 502, feature mask patterns 504a, 504b, a first passivation layer 506 deposited on the feature mask patterns 504a, 504b, and a plurality of features 508 within the substrate 502. The plurality of features 508 can be formed after an etching process in a plasma chamber. The etching process can anisotropically etch a material layer in the substrate 502 to a desired depth. The plurality of features 508 can be defined by a plurality of structures 509 below the feature mask patterns 504a, 504b. The aspect ratio of the features 508 can be higher in the dense feature region of the substrate 502 than in the isolated feature region. As Figure 5C shown, the CD deviation or CD loading in the isolated feature region is greater than that in the dense feature region. Applying a conventional deposition process in a plasma chamber does not allow for precise CD control because the deposition uniformity depends on the aspect ratio. The partially processed device structure 530 represents the device structure 520 after etching in a plasma chamber.

[0089] Figure 6A Disclosed is a partially processed device structure 610, which includes a substrate 602 and feature mask patterns 604a, 604b. The feature mask patterns 604a, 604b can be patterned and defined after etching in a plasma chamber. The feature mask patterns 604a, 604b can distinguish between the dense features 604a in the dense feature region of the substrate 602 and the isolated features 604b in the isolated feature region of the substrate 602, where the dense features 604a have a higher feature density than the isolated features 604b. The dense features 604a in the dense feature region can define gaps having a higher aspect ratio than the isolated features 604b in the isolated feature region. The feature mask patterns 604a, 604b can have the same or substantially similar CD, as Figure 6A shown.

[0090] Figure 6B Disclosed is a partially processed device structure 620, which includes a substrate 602, feature mask patterns 604a, 604b, and a first passivation layer 606 conformally deposited on the feature mask patterns 604a, 604b. The first passivation layer 606 can be deposited using the in-situ ALD process as described above. As Figure 6B shown, the thickness of the first passivation layer 606 is relatively uniform over the isolated features 604b in the isolated feature region and over the dense features 604a in the dense feature region. The thickness of the first passivation layer 606 can be controlled to restore or adjust the CD of the feature mask patterns 604a, 604b. In this way, the CD of the features to be formed by subsequent etching can be precisely adjusted. As Figure 6BAs shown, the CD gain is the same or substantially similar between the dense feature 604a in the dense feature region and the isolated feature 604b in the isolated feature region. "Substantially similar" throughout this disclosure, with respect to the CD gain or CD bias between the dense feature 604a and the isolated feature 604b using in-situ ALD, refers to a value within 0.5 nm of a given value. The partially processed device structure 620 represents the device structure 610 after deposition using in-situ ALD processing in a plasma chamber.

[0091] Figure 6C Shown is a partially processed device structure 630 that includes a substrate 602, feature mask patterns 604a, 604b, a first passivation layer 606 conformally deposited over the feature mask patterns 604a, 604b, and a plurality of features 608 within the substrate 602. The plurality of features 608 can be formed after an etching process in a plasma chamber. The etching process can anisotropically etch a material layer in the substrate 602 to a desired depth. The plurality of features 608 can be defined by a plurality of structures 609 beneath the feature mask patterns 604a, 604b. The aspect ratio of the features 608 can be higher in the dense feature region of the substrate 602 than in the isolated feature region. As Figure 6C shown, the CD bias or CD loading is the same or substantially similar between the dense feature region and the isolated feature region. Applying in-situ ALD in a plasma chamber allows for precise CD control because the deposition uniformity is independent of the aspect ratio. The partially processed device structure 630 represents the device structure 620 after etching in a plasma chamber.

[0092] Figures 7A - 7C Schematic diagrams of substrate features of different materials that undergo deposition and etching using a conventional deposition process in a plasma chamber. Figures 8A - 8C Schematic diagrams of substrate features of different materials that undergo deposition and etching using an integrated ALD and etching process according to some embodiments. A comparison between features made of different materials in a conventional etch-deposition-etch process and an in-situ ALD etch-deposition-etch process discloses the effects of CD bias and CD gain in features made of different materials.

[0093] Figure 7ADisclosed is a partially processed device structure 710, which includes a substrate 702 and feature mask patterns 704a, 704b. The feature mask patterns 704a, 704b can be patterned and defined after etching in a plasma chamber. The feature mask patterns 704a, 704b can include a first feature 704a having a first material and a second feature 704b having a second material, where the second material is different from the first material. For example, the first material can include silicon, while the second material can include silicon-germanium or germanium. In another example, the first material can include an oxide, while the second material can include carbon. In some embodiments, masks such as the feature mask patterns 704a, 704b can use different materials to produce different pitches. Thus, the first feature 704a can have a first pitch, while the second feature 704b can have a second pitch, where the second pitch is greater than the first pitch. The feature mask patterns 704a, 704b can have the same or substantially similar CDs, as Figure 7A shown.

[0094] Figure 7B Shown is a partially processed device structure 720, which includes a substrate 702, feature mask patterns 704a, 704b, a first passivation layer 706a over the first feature 704a, and a second passivation layer 706b over the second feature 704b. The first passivation layer 706a and the second passivation layer 706b can be formed in a plasma chamber using a conventional plasma-based "rapid" passivation process. The conventional plasma-based "rapid" passivation process exposes the surface of the substrate 702, the first feature 704a, and the second feature 704b to a plasma of dissociated radicals of a gas (such as O 2 or N 2 ) to convert the surface of the substrate 702, the first feature 704a, and the second feature 704b into a passivation material (such as an oxide or a nitride). Different materials may react differently to the conventional plasma-based "rapid" passivation process, resulting in different degrees of passivation between different materials. As Figure 7B shown, the thickness of the second passivation layer 706b is greater than the thickness of the first passivation layer 706a. This may be because the second material is converted into a thicker passivation material compared to the first material. In some embodiments, the conventional plasma-based "rapid" passivation process consumes more of the second material compared to the first material. Thus, the CD gain is more in the second feature 704b than in the first feature 704a. The partially processed device structure 720 represents the device structure 710 after passivation in a plasma chamber.

[0095] Figure 7CA partially processed device structure 730 is shown, which includes a substrate 702, feature mask patterns 704a, 704b, a first passivation layer 706a over the first feature 704a and a second passivation layer 706b over the second feature 704b, and a plurality of features 708 within the substrate 702. The plurality of features 708 may be formed after an etching process in a plasma chamber. The etching process may anisotropically etch a material layer in the substrate 702 to a desired depth. The plurality of features 708 may be defined by a plurality of structures 709 underlying the feature mask patterns 704a, 704b. The thickness of the first passivation layer 706a over the first feature 704a is different from the thickness of the second passivation layer 706b over the second feature 704b. Moreover, the etch resistance of the first passivation layer 706a over the first feature 704a may be different from the etch resistance of the second passivation layer 706b over the second feature 704b. As Figure 7C shown, the CD deviation or CD loading at the second feature 704b is greater than the CD deviation or CD loading at the first feature 704a. Applying a conventional plasma-based "rapid" passivation process in a plasma chamber does not allow for precise CD control because passivation uniformity depends on the material. The partially processed device structure 730 represents the device structure 720 after etching in a plasma chamber.

[0096] Figure 8A A partially processed device structure 810 is shown, which includes a substrate 802 and feature mask patterns 804a, 804b. The feature mask patterns 804a, 804b may be patterned and defined after etching in a plasma chamber. The feature mask patterns 804a, 804b may include a first feature 804a having a first material and a second feature 804b having a second material, the second material being different from the first material. For example, the first material may include silicon, and the second material may include silicon-germanium or germanium. In another example, the first material may include an oxide, and the second material may include carbon. In some embodiments, masks such as the feature mask patterns 804a, 804b may use different materials to produce different pitches. Thus, the first feature 804a may have a first pitch, and the second feature 804b may have a second pitch, where the second pitch is greater than the first pitch. The feature mask patterns 804a, 804b may have the same or substantially similar CD, as Figure 8A shown.

[0097] Figure 8B A partially processed device structure 820 is shown, which includes a substrate 802, feature mask patterns 804a, 804b, and a first passivation layer 806 conformally deposited over the feature mask patterns 804a, 804b. The first passivation layer 806 may be deposited using an in-situ ALD process as described above. As Figure 8BAs shown, the thickness of the first passivation layer 806 is relatively uniform over the first feature 804a and over the second feature 804b. The thickness of the first passivation layer 806 can be controlled to restore or adjust the CD of the feature mask patterns 804a, 804b. In this way, the CD of the features to be formed by subsequent etching can be precisely adjusted. As Figure 8B shown, the CD gain is the same or substantially similar between the first feature 804a made of a first material and having a first pitch, and the second feature 804b made of a second material and having a second pitch. Throughout this disclosure, "substantially similar" with respect to the CD gain or CD deviation between the first feature 804a and the second feature 804b using in-situ ALD means a value within 0.5 nm of a given value. The partially processed device structure 820 represents the device structure 810 after deposition using in-situ ALD processing in a plasma chamber.

[0098] Figure 8C Shows a partially processed device structure 830 that includes a substrate 802, feature mask patterns 804a, 804b, a first passivation layer 806 conformally deposited over the feature mask patterns 804a, 804b, and a plurality of features 808 within the substrate 802. The plurality of features 808 can be formed after an etching process in a plasma chamber. The etching process can anisotropically etch a material layer in the substrate 802 to a desired depth. The plurality of features 808 can be defined by a plurality of structures 809 beneath the feature mask patterns 804a, 804b. Relative to converting some of the first material in the first feature 804a and some of the second material in the second feature 804b via oxidation or nitridation in a conventional plasma-based "rapid" passivation process, the in-situ ALD process reacts with the adsorbed precursor material in a self-limiting manner. The thickness of the first passivation layer 806 over the first feature 804a is the same or substantially similar to the thickness of the first passivation layer 806 over the second feature 804b. Additionally, the etch resistance of the first passivation layer 806 over the first feature 804a and over the second feature 804b is the same because the in-situ ALD process does not convert different materials to form the passivation material. As Figure 8C shown, the CD deviation or CD loading at the first feature 804a is the same or substantially similar to the CD deviation or CD loading at the second feature 804b. Applying in-situ ALD in a plasma chamber allows for precise CD control because the deposition uniformity is material-independent. The partially processed device structure 830 represents the device structure 820 after etching in a plasma chamber.

[0099] Figures 9A - 9C Schematic diagram of a tapered substrate feature undergoing deposition and etching in separate tools. Figures 10A - 10DSchematic illustration of conical substrate features that undergo deposition and etching using integrated ALD and etching processes according to some embodiments. Relative to Figures 9A - 9C depositing layers via ALD in separate chambers or tools as in the above, in-situ ALD as described can enable etch-deposition process cycles to control CD with minimal depth loading between isolated and dense features.

[0100] Figure 9A A partially processed device structure 910 is shown, which includes a substrate 902 and a feature mask pattern 904. Each of the features in the feature mask pattern 904 can have a conical profile. In Figure 9A , the spacing between the feature mask patterns 904 can define at least a portion of a dense feature region, and the spacing to the left of the feature mask pattern 904 can define at least a portion of an isolated feature region. Thus, the feature mask patterns 904 can have different pitches between features. In some embodiments, the feature mask pattern 904 can be patterned and defined after an etching operation. In some embodiments, the feature mask pattern 904 can include a hard mask. The feature mask pattern 904 can have the same or substantially similar CD, as Figure 9A shown.

[0101] Figure 9B A partially processed device structure 920 is shown, which includes a substrate 902, a feature mask pattern 904, and a layer 906 conformally deposited over the feature mask pattern 904. A suitable deposition technique (e.g., ALD) can be utilized to conformally deposit the deposited layer 906. In some embodiments, the layer 906 can be a passivation layer. The passivation layer can include oxides and / or nitrides. Although the layer 906 is conformally deposited, the thickness of the layer 906 along the sidewalls and surface of the feature mask pattern 904 may be non-uniform. The spacing between the feature mask patterns 904 or the spacer CD of the feature mask pattern 904 may be relatively small or narrow. Additionally, the deposition of the layer 906 can result in a relatively thick layer, especially if the deposition is performed in a chamber or tool separate from the etching process. Alternatively, the deposition of the layer 906 may undergo several transfer steps and cleaning steps before reaching the desired thickness. As Figure 9BAs shown, the thick deposition layer 906 combines with the narrow pitch CD in the feature mask pattern 904 having a tapered profile, resulting in the merging of layer 906. The merging of layer 906 may occur in the dense feature region between features 904. The thicker conformal deposition, along with the narrow pitch between features 904 in the dense feature region, leads to "pinch-off" in the dense feature region, where the thickness of layer 906 is greater in the dense feature region than in the isolated feature region. For example, if the pitch CD of the feature mask pattern 904 is less than 5 nm, and if the thickness of layer 906 is greater than 3 nm and is conformally deposited on the feature mask pattern 904, then "pinch-off" or merging of layer 906 occurs in the dense feature region, as Figure 9B shown. Even when depositing using ALD, CD bias or CD loading in the dense feature region may still occur. The partially processed device structure 920 represents the device structure 910 after deposition using ALD in a deposition chamber or tool.

[0102] Figure 9CShows a partially processed device structure 930, which includes a substrate 902, a feature mask pattern 904, a layer 906 at least partially over the feature mask pattern 904, and a first feature 908a extending to a first depth in an isolated feature region of the substrate 902 and a second feature 908b extending to a second depth in a dense feature region of the substrate 902. The features 908a, 908b can be formed after an etching process or “break-through” in an etching chamber or a plasma chamber separate from the deposition chamber. “Break-through” is an anisotropic etching through at least a portion of the substrate 902 to form the features 908a, 908b. The features 908a, 908b can be defined by a plurality of structures 909 under the feature mask pattern 904. After etching, at least some of the layer 906 can remain on the sidewalls of the feature mask pattern 904. The anisotropic etching can remove a portion of the layer 906 to the left of the feature 904 at the surface of the substrate 902 in the isolated feature region, and can remove a portion of the substrate 902 in the isolated feature region, thereby forming the first feature 908a. The anisotropic etching can also remove a portion of the layer 906 between the features 904 at the surface of the substrate 902 in the dense feature region, and can remove a portion of the substrate 902 in the dense feature region, thereby forming the second feature 908b. The first feature 908a extends to a first depth in the isolated feature region, while the second feature 908b extends to a second depth in the dense feature region, where the first depth is greater than the second depth. Since the “break-through” etching in the dense feature region etches through a thicker amount of the layer 906, the second depth is shallower than the first depth. Thus, depth loading occurs between the isolated feature region and the dense feature region. The partially processed device structure 930 represents the device structure 920 after etching in a plasma chamber or an etching chamber.

[0103] Figure 10A Shows a partially processed device structure 1010, which includes a substrate 1002 and a feature mask pattern 1004. Each of the features of the feature mask pattern 1004 can have a tapered profile. In Figure 10A which, the spacing between the feature mask patterns 1004 can define at least a portion of the dense feature region, and the spacing to the left of the feature mask pattern 1004 can define at least a portion of the isolated feature region. Thus, the feature mask pattern 1004 can have different pitches between the features. In some embodiments, the feature mask pattern 1004 can be patterned and defined after an etching operation. In some embodiments, the feature mask pattern 1004 can include a hard mask. The feature mask pattern 1004 can have the same or substantially similar CD, as Figure 10A shown.

[0104] Figure 10BShows a partially processed device structure 1020, which includes a substrate 1002 and a feature mask pattern 1004, wherein the tapered profile of the feature mask pattern 1004 is partially corrected or straightened by etching. Before etching, in some embodiments as shown in Figure 10B , the etching operation may be performed before deposition. Anisotropic etching can remove the edges of the feature mask pattern 1004 to straighten the mask profile and reduce the likelihood of any "pinching" or merging during subsequent deposition. Anisotropic etching can also remove at least a portion of the substrate 1002 in the isolated feature regions and the dense feature regions. The etching operation forms a first shallow feature 1008a in the isolated feature region and a second shallow feature 1008b in the dense feature region, wherein the depth of each of the shallow features 1008a, 1008b is the same or substantially similar. "Substantially similar" throughout this disclosure with respect to the depth of the shallow features 1008a, 1008b means a value that differs from a given value by within plus or minus 5%. The etching operation can be performed in a plasma chamber that is also used for subsequent deposition operations. The partially processed device structure 1020 represents the device structure 1010 after etching in the plasma chamber to correct the feature mask pattern 1004.

[0105] Figure 10C Shows a partially processed device structure 1030, which includes a substrate 1002, a feature mask pattern 1004 with a straightened profile, and a layer 1006 conformally deposited over the feature mask pattern 1004. The deposited layer 1006 can be conformally deposited using in-situ ALD as described above in a plasma chamber. In some embodiments, the layer 1006 can be a passivation layer. The passivation layer can include an oxide and / or a nitride. In particular, since the deposition is performed in the same chamber as the subsequent etching process, the deposition of the layer 1006 can result in a relatively thin layer. For example, the layer 1006 can have a thickness equal to or less than about 3 nm, or between about 0.3 nm and about 2 nm. The desired thickness of the layer 1006 can be achieved by sequentially cycling between deposition-etching operations in the plasma chamber without transferring between different chambers or tools. Additionally, the anisotropic etching in Figure 10B can be performed to widen the pitch between the features 1004, or the pitch CD between the feature mask patterns 1004. As shown in Figure 10CAs shown, the thickness of layer 1006 along the sidewalls and surface of the feature mask pattern 1004 is relatively uniform. In part due to the widened spacer CD, the straightened mask profile, and the thin deposition layer 1006 deposited on the feature mask pattern 1004 using in-situ ALD, layer 1006 avoids "pinching" and merging in the dense feature region. The ALD deposition and anisotropic etching steps can be repeated in a cyclic manner to achieve the final CD target without pinching or depth loading. The CD deviation or CD loading is the same or substantially similar in the dense feature region and the isolated feature region. "Substantially similar" throughout this disclosure with respect to the CD deviation of layer 1006 in the dense feature region and the isolated feature region means a value within 0.3 nm of a given value. The thickness of the conformal deposition layer 1006 can be used to control the CD of subsequent features to be formed in the substrate 1002. The partially processed device structure 1030 represents the device structure 1020 after deposition using ALD in a plasma chamber.

[0106] Figure 10D The partially processed device structure 1040 is shown, which includes a substrate 1002, a feature mask pattern 1004 with a straightened profile, a layer 1006 conformally deposited on the feature mask pattern 1004, a first feature 1018a extending to a first depth in the isolated feature region of the substrate 1002, and a second feature 1018b extending to a second depth in the dense feature region of the substrate 1002. The features 1018a, 1018b can be formed after an etching process or "drilling through" in a plasma chamber. "Drilling through" is an anisotropic etching that etches through at least a portion of the substrate 1002 to form the features 1018a, 1018b. The features 1018a, 1018b can be defined by a plurality of structures 1009 below the feature mask pattern 1004. After etching, at least some of layer 1006 may remain on the sidewalls of the feature mask pattern 1004. The anisotropic etching can remove portions of the substrate 1002 in the dense feature region and the isolated feature region. The first feature 1018a extends to a first depth in the isolated feature region, while the second feature 1018b extends to a second depth in the dense feature region, where the depth variation between the first depth and the second depth is the same or substantially similar. With respect to the depth variation or depth loading between the features 1018a, 1018b in the dense feature region and the isolated feature region, "substantially similar" throughout this disclosure means a value within plus or minus 5% of a given value. In Figure 10DAfter the anisotropic etching performed therein, cycles of additional ALD and etching operations may be repeated in the plasma chamber until the desired CDs of features 1018a, 1018b are reached. This allows for fine-tuning of the CDs of features 1018a, 1018b. The cycles of additional ALD and etching operations may be repeated with minimal depth loading between the isolated feature regions and the dense feature regions. The partially processed device structure 1040 represents the device structure 1030 after etching in the plasma chamber.

[0107] Conclusion

[0108] While the above embodiments have been described in some detail for purposes of clear understanding, it is apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and devices of the embodiments of the present invention. Accordingly, the embodiments of the present invention should be regarded as illustrative rather than restrictive, and the embodiments are not limited to the details given herein.

Claims

1. A method for critical dimension control, comprising: etching a first layer of a substrate in a plasma chamber to form a feature mask pattern having a width smaller than a desired width of a plurality of structures to be formed by the feature mask pattern, wherein the feature mask pattern includes one or more isolated features in an isolated feature region and one or more dense features in a dense feature region, the dense feature region having a higher feature density than the isolated feature region; depositing a first passivation layer on the feature mask pattern by atomic layer deposition in the plasma chamber, the first passivation layer being deposited to have a thickness that increases the width of the feature mask pattern to the desired width; etching a second layer of the substrate in the plasma chamber to form the plurality of structures having the desired width; and repeating the deposition operation by atomic layer deposition and the operation of etching the second layer in the plasma chamber, wherein after repeating the deposition operation by atomic layer deposition and the operation of etching the second layer, the critical dimension gain is the same or substantially similar between the isolated features in the isolated feature region and the dense features in the dense feature region.

2. The method according to claim 1, wherein after depositing the first passivation layer, the critical dimension gain is the same or substantially similar between the one or more isolated features in the isolated feature region and the one or more dense features in the dense feature region.

3. The method according to claim 1, wherein after etching the second layer of the substrate, the depth variation is the same or substantially similar between the isolated feature region and the dense feature region.

4. The method according to claim 1, wherein before depositing the first passivation layer, the critical dimension of the feature mask pattern is the same or substantially similar between the one or more isolated features and the one or more dense features.

5. The method according to any one of claims 1-4, wherein the plurality of structures at least define a first feature having a first aspect ratio and a second feature having a second aspect ratio different from the first aspect ratio, wherein after etching the second layer of the substrate, the critical dimension gain is the same or substantially similar between the first feature and the second feature.

6. The method according to any one of claims 1-4, wherein the feature mask pattern includes one or more first features having a first material and one or more second features having a second material different from the first material, wherein after depositing the first passivation layer, the critical dimension gain is the same or substantially similar between the one or more first features and the one or more second features.

7. The method according to claim 6, further comprising: repeating the operation of depositing the second layer by atomic layer deposition and etching the second layer in the plasma chamber, wherein After repeating the operations of depositing and etching the second layer by ALD, the critical dimension gain is the same or substantially similar between the one or more first features and the one or more second features.

8. The method according to claim 6, wherein the first material comprises silicon and the second material comprises silicon-germanium or germanium.

9. The method according to any one of claims 1-4, wherein, the operations of depositing and etching the second layer by atomic layer deposition in the plasma chamber are performed without causing a vacuum break between the operations.

10. The method according to any one of claims 1-4, wherein the desired width corresponds to the desired critical dimension of the plurality of structures.

11. The method according to any one of claims 1-4, wherein the critical dimension of the plurality of structures is equal to or less than about 20 nm.

12. The method according to any one of claims 1-4, wherein the thickness of the first passivation layer is between about 0.5 nm and about 3 nm.

13. The method according to any one of claims 1-4, wherein one or more of the features of the feature mask pattern have a tapered profile, and wherein the method further comprises: anisotropically etching at least a portion of the feature mask pattern to correct the tapered profile before depositing the first passivation layer by atomic layer deposition.

14. The method according to any one of claims 1-4, wherein the pitch critical dimension of the feature mask pattern is equal to or less than about 5 nm.

15. The method according to any one of claims 1-4, further comprising: after etching the second layer of the substrate, depositing a second passivation layer on the plurality of structures by atomic layer deposition in the plasma chamber, the second passivation layer being deposited to have a thickness corresponding to the desired CD gain.

16. The method according to any one of claims 1-4, wherein the first passivation layer comprises silicon oxide (SiO x ).

17. The method according to any one of claims 1-4, wherein etching the second layer of the substrate etches the second layer to a depth less than the final desired depth.

18. The method according to any one of claims 1-4, wherein depositing the first passivation layer by atomic layer deposition comprises: introducing a precursor into the plasma chamber to adsorb onto the feature mask pattern, using a plasma to convert the precursor to form the first passivation layer with a limited adsorption amount, and repeating the operations of introducing the precursor and converting the precursor until the first passivation layer of the thickness is deposited on the feature mask pattern.

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