Full adder and ripple-carry adder

Abstract

The present invention relates to a full adder and a ripple carry adder. The full adder comprises: a NAND logic circuit configured to receive a first input and a second input and generate a first intermediate result; an OR NAND logic circuit configured to receive a first input, a second input and a first intermediate result of the NAND logic circuit and generate a second intermediate result; a first OR NAND logic circuit configured to receive a second intermediate result and a third input of the OR NAND logic circuit and generate a third intermediate result; an AND OR NAND logic circuit configured to receive a second intermediate result, a third input and a third intermediate result of the OR NAND logic circuit and generate a first output; and a carry generation circuit configured to receive the first intermediate result of the NAND logic circuit and the third intermediate result of the first OR NAND logic circuit and generate a second output.

Description

Technical Field

[0001] The invention relates to a full adder and a ripple-carry adder. Background Art

[0002] The area occupied by a full adder (FA) is proportional to the number of transistors used to implement the full adder. Therefore, as the total number of transistors decreases, the area occupied by the full adder will also decrease. The reduction in the area of ​​the full adder will directly translate into a reduction in chip area and cost savings. Summary of the invention

[0003] The present invention provides a novel circuit implementation of a full adder, which can reduce the number of transistors of the full adder and thus reduce the chip area.

[0004] According to one aspect of the present invention, a full adder is provided, comprising: a NAND logic circuit, configured to receive a first input and a second input, and generate a first intermediate result; an OR NAND logic circuit, configured to receive the first input, the second input and the first intermediate result of the NAND logic circuit, and generate a second intermediate result; a first OR NAND logic circuit, configured to receive the second intermediate result of the OR NAND logic circuit and a third input, and generate a third intermediate result; an AND OR NAND logic circuit, configured to receive the second intermediate result of the OR NAND logic circuit, a third input and the third intermediate result of the first OR NAND logic circuit, and generate a first output; and a carry generation circuit, configured to receive the first intermediate result of the NAND logic circuit and the third intermediate result of the first OR NAND logic circuit, and generate a second output.

[0005] Preferably, when the first input is a positive addend, the second input is a positive augend, and the third input is a negative carry from a lower bit, the first output is a positive remainder, and the second output is a negative carry.

[0006] Preferably, the NAND logic circuit includes: a first PMOS transistor, whose gate terminal is configured to receive a first input and whose drain terminal is coupled to a first node; a second PMOS transistor, whose gate terminal is configured to receive a second input and whose drain terminal is coupled to the first node, wherein a source terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to a power supply terminal; a first NMOS transistor, whose gate terminal is configured to receive the first input and whose drain terminal is coupled to the first node; and a second NMOS transistor, whose gate terminal is configured to receive the second input and whose drain terminal is coupled to a source terminal of the first NMOS transistor, wherein a source terminal of the second NMOS transistor is coupled to a ground terminal, wherein the NAND logic circuit is configured to generate a first intermediate result at the first node.

[0007] Preferably, the NAND logic circuit includes: a third PMOS transistor, whose gate terminal is configured to receive the first intermediate result of the NAND logic circuit and whose drain terminal is coupled to the second node; a fourth PMOS transistor, whose gate terminal is configured to receive the first input, wherein the source terminal of each of the third PMOS transistor and the fourth PMOS transistor is coupled to the power supply terminal; a fifth PMOS transistor, whose gate terminal is configured to receive the second input, whose source terminal is coupled to the drain terminal of the fourth PMOS transistor, and whose drain terminal is coupled to the second node; a third NMOS transistor, whose gate terminal is configured to receive the first intermediate result of the NAND logic circuit and whose drain terminal is coupled to the second node; A terminal of the fourth NMOS transistor is configured to receive a first intermediate result of the NAND logic circuit, and its drain terminal is coupled to the second node; a fourth NMOS transistor, whose gate terminal is configured to receive the first input and its drain terminal is coupled to the source terminal of the third NMOS transistor; and a fifth NMOS transistor, whose gate terminal is configured to receive the second input and its drain terminal is coupled to the source terminal of the third NMOS transistor, wherein the source terminal of each of the fourth NMOS transistor and the fifth NMOS transistor is coupled to the ground terminal, wherein the NAND logic circuit is configured to produce a second intermediate result at the second node.

[0008] Preferably, the first OR-NOT logic circuit includes: a sixth PMOS transistor, whose gate terminal is configured to receive the second intermediate result of the OR-NOT logic circuit, wherein the source terminal of the sixth PMOS transistor is coupled to the power supply terminal; a seventh PMOS transistor, whose gate terminal is configured to receive the third input, whose source terminal is coupled to the drain terminal of the sixth PMOS transistor, and whose drain terminal is coupled to the third node; a sixth NMOS transistor, whose gate terminal is configured to receive the second intermediate result of the OR-NOT logic circuit and whose drain terminal is coupled to the third node; and a seventh NMOS transistor, whose gate terminal is configured to receive the third input and whose drain terminal is coupled to the third node, wherein the source terminal of each of the sixth NMOS transistor and the seventh NMOS transistor is coupled to the ground terminal, wherein the first OR-NOT logic circuit is configured to generate a third intermediate result at the third node.

[0009] Preferably, the AND-NOR logic circuit includes: an eighth PMOS transistor, whose gate terminal is configured to receive the third intermediate result of the first OR-NOR logic circuit, wherein the source terminal of the eighth PMOS transistor is coupled to the power supply terminal; a ninth PMOS transistor, whose gate terminal is configured to receive the second intermediate result of the OR-NOR logic circuit, whose source terminal is coupled to the drain terminal of the eighth PMOS transistor, and whose drain terminal is coupled to the fourth node; a tenth PMOS transistor, whose gate terminal is configured to receive the third input, whose source terminal is coupled to the drain terminal of the eighth PMOS transistor, and whose drain terminal is coupled to the fourth node; an eighth NMOS transistor, whose gate terminal is configured to receive a third intermediate result of the first NOR logic circuit and whose drain terminal is coupled to a fourth node; a ninth NMOS transistor, whose gate terminal is configured to receive a second intermediate result of the NOR logic circuit and whose drain terminal is coupled to the fourth node; and a tenth NMOS transistor, whose gate terminal is configured to receive a third input and whose drain terminal is coupled to a source terminal of the ninth NMOS transistor, wherein a source terminal of each of the eighth NMOS transistor and the tenth NMOS transistor is coupled to a ground terminal, wherein the NOR logic circuit is configured to generate a first output at the fourth node.

[0010] Preferably, the carry generation circuit includes an inverter and a second NOR logic circuit, the inverter is configured to receive the first intermediate result of the NAND logic circuit and generate a fourth intermediate result, and the second NOR logic circuit is configured to receive the fourth intermediate result of the inverter and the third intermediate result of the first NOR logic circuit and generate a second output.

[0011] Preferably, the inverter includes: an eleventh PMOS transistor, whose gate terminal is configured to receive the first intermediate result of the NAND logic circuit and whose drain terminal is coupled to the fifth node, wherein the source terminal of the eleventh PMOS transistor is coupled to the power supply terminal; and an eleventh NMOS transistor, whose gate terminal is configured to receive the first intermediate result of the NAND logic circuit and whose drain terminal is coupled to the fifth node, wherein the source terminal of the eleventh NMOS transistor is coupled to the ground terminal, wherein the inverter is configured to generate a fourth intermediate result at the fifth node.

[0012] Preferably, the second OR-NO logic circuit includes: a twelfth PMOS transistor, whose gate terminal is configured to receive the fourth intermediate result of the inverter, wherein the source terminal of the twelfth PMOS transistor is coupled to the power supply terminal; a thirteenth PMOS transistor, whose gate terminal is configured to receive the third intermediate result of the first OR-NO logic circuit, whose source terminal is coupled to the drain terminal of the twelfth PMOS transistor, and whose drain terminal is coupled to the sixth node; a twelfth NMOS transistor, whose gate terminal is configured to receive the fourth intermediate result of the inverter and whose drain terminal is coupled to the sixth node; and a thirteenth NMOS transistor, whose gate terminal is configured to receive the output of the OR-NO logic circuit and whose drain terminal is coupled to the sixth node, wherein the source terminal of each of the twelfth NMOS transistor and the thirteenth NMOS transistor is coupled to the ground terminal, wherein the second OR-NO logic circuit is configured to generate a second output at the sixth node.

[0013] According to another aspect of the present invention, there is provided a ripple-carry adder comprising a plurality of cascaded full adders of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] A better understanding of the present invention can be obtained when considering the following detailed description of the embodiments in conjunction with the accompanying drawings. The same or similar reference numerals are used in the various drawings to represent the same or similar parts. The accompanying drawings, together with the following detailed description, are included in this specification and form a part of the specification to illustrate the embodiments of the present invention and to explain the principles and advantages of the present invention.

[0015] Figure 1 The truth table of a full adder is shown.

[0016] Figure 2 The logic diagram of a full adder is shown.

[0017] Figure 3A and Figure 3B The standard CMOS implementation and multiplex implementation of a full adder are shown respectively.

[0018] Figure 4 The structure of the ripple-carry adder is shown.

[0019] Figure 5 A full adder is shown in which the input sign bit is changed to make the area of ​​the full adder smaller.

[0020] Figure 6 A logic diagram of a full adder according to an embodiment of the present invention is shown.

[0021] Figure 7 The CMOS structure diagram of the full adder according to the embodiment of the present invention is shown.

[0022] Figure 8 A logic diagram of a ripple-carry adder according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0023] The following detailed description of the embodiments presents various details of specific embodiments of the present invention. However, the present invention can be implemented in many different ways as defined and covered by the claims. In this specification, the same reference numerals may represent the same or functionally similar elements.

[0024] Figure 1 The truth table of a full adder is shown in FIG. A full adder is a device that adds three 1-bit numbers, namely, addend A, augend B and a carry Cin from a low bit, to obtain two outputs, namely, a carry Cout and a remainder SUM.

[0025] Figure 2 shows the logic diagram of a full adder. Figure 2 In the above example, the logical relationship between remainder SUM, addend A, augend B, and carry Cin from the lower bit is: The logical relationship between the carry Cout, addend A, augend B and the carry Cin from the lower bit is:

[0026] Figure 3A and Figure 3B The standard CMOS implementation of the full adder and the multiplex implementation are shown respectively. Figure 3A and 3B In the above example, the way to find the remainder SUM is The difference is the way to find the carry Cout. Figure 3A middle, exist Figure 3B middle, That is, when When Cout = Cin; when , Cout = a.

[0027] A ripple carry adder can be easily implemented using a full adder, that is, multiple full adders are cascaded. Figure 4 The structure of the ripple carry adder is shown in FIG. The ripple carry adder is composed of N full adders connected in series. The carry C of the i-th full adder o,i Used to generate the remainder S of the i+1th level i and carry C o,i+1 The ripple-carry adder is characterized by its intuitive and simple structure but slow operation speed.

[0028] For the ripple carry adder, one requirement is that the sign bit of the full adder is self-consistent, that is, the sign of the input Cin of the full adder is consistent with the sign of the output Cout. Only when the sign of the input Cin of the full adder is consistent with the sign of the output Cout, can the transfer be realized.

[0029] However, for a circuit implemented with CMOS, its natural output is inverted. If a positive phase output is to be achieved, an inverter needs to be added behind the natural output. For example, for a full adder implemented with CMOS, if an inverter is not added to the previous full adder, its output is an inverted carry. However, in the prior art, a full adder requires a positive carry input. Therefore, an inverter needs to be added between the previous full adder and the current full adder to make the sign (or phase) of the carry output of the previous full adder consistent with the sign (or phase) of the carry required by the current level. However, adding an extra inverter in each full adder will result in an increase in chip area and power consumption.

[0030] Figure 5 shows a full adder with the input sign bit changed to make the full adder area smaller. However, Figure 5 The sign bits of the odd-numbered full adders and the even-numbered full adders are inconsistent. The odd-numbered full adders require that the input addends and the augends are inverted. In other words, an inverter needs to be added to the input of the odd-numbered full adders to change the signs of the input addends and the augends. In other words, Figure 5 Although the solution in avoids adding inverters to the full adder, it requires adding inverters outside the full adder, which will also increase the area of ​​the overall chip.

[0031] The present invention provides a novel circuit implementation of a full adder, which can reduce the number of transistors of the full adder and thus reduce the chip area.

[0032] Figure 6 A logic diagram of a full adder according to an embodiment of the present invention is shown. Figure 6 The full adder in includes a NAND logic circuit ND2, an OR NAND logic circuit OAI21, a first NOR logic circuit NR2, an AND-OR NAND logic circuit AOI21 and a carry generation circuit NR2B.

[0033] The NAND logic circuit ND2 is configured to receive a first input A and a second input B and generate a first intermediate result The NAND logic circuit OAI21 is configured to receive the first input A, the second input B and the first intermediate result GN1 of the NAND logic circuit, and generate a second intermediate result

[0034] because Therefore, the NAND logic circuit ND2 and the NAND logic circuit OAI21 actually constitute an XNOR logic circuit XNR2.

[0035] The first NOR logic circuit NR2 is configured to receive the second intermediate result TN1 of the NOR logic circuit OAI21 and the third input Cin_n and generate a third intermediate result The AND-NOR logic circuit AOI21 is configured to receive the second intermediate result TN1 of the AND-NOR logic circuit, the third input Cin_n and the third intermediate result GN2 of the first OR-NOR logic circuit, and generate an output

[0036] Further we can get Therefore, the first NOR logic circuit NR2 and the AND-NOR logic circuit AOI21 actually constitute an exclusive OR logic circuit XOR2.

[0037] The carry generating circuit NR2B is configured to receive the first intermediate result GN1 of the NAND logic circuit and the third intermediate result GN2 of the first NOR logic circuit, and generate an inverted carry

[0038] When the first input A is a positive addend, the second input B is a positive augend, and the third input Cin_n is a negative carry from a lower bit, First output That is, the first output SUM is the positive phase remainder.

[0039] Second output That is, the second output Cout_n is an inverted carry.

[0040] It can be seen that the input Cin_n and output Cout_n of the full adder are both inverted, thus achieving the logical self-consistency of the full adder. Although the inputs A and B are both positive, with opposite signs to Cin_n and Cout_n, Cin_n and Cout_n are internal signals and have no effect on the external circuit structure.

[0041] Figure 7 The CMOS structure diagram of the full adder according to the embodiment of the present invention is shown.

[0042] like Figure 7As shown, the NAND logic circuit ND2 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1 and a second NMOS transistor N2. The gate terminal of the first PMOS transistor P1 is configured to receive a first input A and a drain terminal is coupled to the first node J1. The gate terminal of the second PMOS transistor P2 is configured to receive a second input B and a drain terminal thereof is coupled to the first node J1. The source terminal of each of the first PMOS transistor P1 and the second PMOS transistor P2 is coupled to the power supply terminal VDD. The gate terminal of the first NMOS transistor is configured to receive a first input A and a drain terminal thereof is coupled to the first node J1. The gate terminal of the second NMOS transistor is configured to receive a second input B and a drain terminal thereof is coupled to the source terminal of the first NMOS transistor. The source terminal of the second NMOS transistor is coupled to the ground terminal VSS. The NAND logic circuit ND2 is configured to generate a first intermediate result GN1 at the first node J1.

[0043] The NAND logic circuit OAI21 includes a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5. The gate terminal of the third PMOS transistor P3 is configured to receive the first intermediate result GN1 of the NAND logic circuit and its drain terminal is coupled to the second node J2. The gate terminal of the fourth PMOS transistor P4 is configured to receive the first input A. The source terminal of each of the third PMOS transistor and the fourth PMOS transistor is coupled to the power supply terminal VDD. The gate terminal of the fifth PMOS transistor P5 is configured to receive the second input B, the source terminal thereof is coupled to the drain terminal of the fourth PMOS transistor, and the drain terminal thereof is coupled to the second node J2. The gate terminal of the third NMOS transistor N3 is configured to receive the first intermediate result GN1 of the NAND logic circuit, and its drain terminal is coupled to the second node J2. The gate terminal of the fourth NMOS transistor N4 is configured to receive the first input A and its drain terminal is coupled to the source terminal of the third NMOS transistor. The gate terminal of the fifth NMOS transistor N5 is configured to receive the second input B and its drain terminal is coupled to the source terminal of the third NMOS transistor. The source terminal of each of the fourth NMOS transistor and the fifth NMOS transistor is coupled to the ground terminal VSS. The NAND logic circuit OAI21 is configured to generate a second intermediate result TN1 at the second node J2.

[0044] The first NOR logic circuit NR2 includes a sixth PMOS transistor P6, a seventh PMOS transistor P7, a sixth NMOS transistor N6, and a seventh NMOS transistor N7. The gate terminal of the sixth PMOS transistor P6 is configured to receive the second intermediate result TN1 of the NOR logic circuit OAI21. The source terminal of the sixth PMOS transistor is coupled to the power supply terminal VDD. The gate terminal of the seventh PMOS transistor P7 is configured to receive the third input Cin_n, its source terminal is coupled to the drain terminal of the sixth PMOS transistor, and its drain terminal is coupled to the third node J3. The gate terminal of the sixth NMOS transistor N6 is configured to receive the second intermediate result TN1 of the NOR logic circuit OAI21 and its drain terminal is coupled to the third node J3. The gate terminal of the seventh NMOS transistor N7 is configured to receive the third input Cin_n and its drain terminal is coupled to the third node J3. The source terminal of each of the sixth NMOS transistor and the seventh NMOS transistor is coupled to the ground terminal VSS. The first NOR logic circuit NR2 is configured to generate a third intermediate result GN2 at a third node J3.

[0045] The AND-NOR logic circuit AOI21 includes an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eighth NMOS transistor N8, a ninth NMOS transistor N9, and a tenth NMOS transistor N10. The gate terminal of the eighth PMOS transistor P8 is configured to receive the third intermediate result GN2 of the first OR-NOR logic circuit. The source terminal of the eighth PMOS transistor is coupled to the power supply terminal VDD. The gate terminal of the ninth PMOS transistor P9 is configured to receive the second intermediate result TN1 of the OR-NOR logic circuit, the source terminal thereof is coupled to the drain terminal of the eighth PMOS transistor, and the drain terminal thereof is coupled to the fourth node J4. The gate terminal of the tenth PMOS transistor P10 is configured to receive the third input Cin_n, the source terminal thereof is coupled to the drain terminal of the eighth PMOS transistor, and the drain terminal thereof is coupled to the fourth node J4. The gate terminal of the eighth NMOS transistor N8 is configured to receive the third intermediate result GN2 of the first NOR logic circuit and its drain terminal is coupled to the fourth node J4. The gate terminal of the ninth NMOS transistor N9 is configured to receive the second intermediate result TN1 of the NAND logic circuit, and its drain terminal is coupled to the fourth node J4. The gate terminal of the tenth NMOS transistor N10 is configured to receive the third input Cin_n and its drain terminal is coupled to the source terminal of the ninth NMOS transistor. The source terminal of each of the eighth NMOS transistor and the tenth NMOS transistor is coupled to the ground terminal VSS. The NAND logic circuit AOI21 is configured to generate a first output SUM at the fourth node J4.

[0046] The carry generating circuit NR2B includes an inverter INV and a second NOR logic circuit NR2', wherein the inverter INV is configured to receive the first intermediate result GN1 of the NAND logic circuit and generate a fourth intermediate result GN1n. The second NOR logic circuit NR2' is configured to receive the fourth intermediate result GN1n of the inverter and the third intermediate result GN2 of the first NOR logic circuit and generate a second output Cout_n.

[0047] The inverter INV includes an eleventh PMOS transistor P11 and an eleventh NMOS transistor N11. The gate terminal of the eleventh PMOS transistor P11 is configured to receive the first intermediate result GN1 of the NAND logic circuit and its drain terminal is coupled to the fifth node J4. The source terminal of the eleventh PMOS transistor is coupled to the power supply terminal VDD. The gate terminal of the eleventh NMOS transistor N11 is configured to receive the first intermediate result GN1 of the NAND logic circuit and its drain terminal is coupled to the fifth node J5. The source terminal of the eleventh NMOS transistor is coupled to the ground terminal VSS. The inverter INV is configured to generate a fourth intermediate result GN1n at the fifth node.

[0048] The second NOR logic circuit NR2' includes a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a twelfth NMOS transistor N12, and a thirteenth NMOS transistor N13. The gate terminal of the twelfth PMOS transistor P12 is configured to receive the fourth intermediate result GN1n of the inverter. The source terminal of the twelfth PMOS transistor is coupled to the power supply terminal VDD. The gate terminal of the thirteenth PMOS transistor P13 is configured to receive the third intermediate result GN2 of the first NOR logic circuit, the source terminal thereof is coupled to the drain terminal of the twelfth PMOS transistor, and the drain terminal thereof is coupled to the sixth node J6. The gate terminal of the twelfth NMOS transistor N12 is configured to receive the fourth intermediate result GN1n of the inverter and the drain terminal thereof is coupled to the sixth node J6. The gate terminal of the thirteenth NMOS transistor N13 is configured to receive the output GN2 of the NOR logic circuit and the drain terminal thereof is coupled to the sixth node J6. A source terminal of each of the twelfth and thirteenth NMOS transistors is coupled to the ground terminal VSS. The second NOR logic circuit NR2' is configured to generate a second output Cout_n at a sixth node.

[0049] Figure 7 The input Cin and output Cout of the full adder shown are both inverted, that is, the logic is self-consistent, so there is no need to add additional inverters, thereby reducing the use of transistors and reducing the chip area.

[0050] Figure 8FIG. 2 shows a logic diagram of a ripple carry adder of an embodiment of the present invention. The ripple carry adder includes a plurality of cascaded full adders of an embodiment of the present invention. Figure 8 As shown, the input carry Cin and output carry Cout of each full adder are inverted, that is, the logic self-consistency is achieved. Since the output carry Cout of the previous full adder has the same sign as the input carry Cin of the current full adder, there is no need to add additional inverters, thereby reducing the use of transistors and reducing the chip area.

[0051] The full adder and ripple carry adder of the present invention are described above in conjunction with specific embodiments. However, it should be understood that any feature of any embodiment may be combined and / or replaced with any other feature of any other embodiment.

[0052] Aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronic products, components of consumer electronic products, electronic test equipment, cellular communication infrastructure such as base stations, etc. Examples of electronic devices may include, but are not limited to, mobile phones such as smart phones, wearable computing devices such as smart watches or headphones, phones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, portable cameras, cameras such as digital cameras, portable memory chips, washing machines, dryers, washing machines / dryers, peripheral devices, clocks, etc. In addition, electronic devices may include incomplete products.

[0053] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include", "comprises", "contains", "has", etc. should be interpreted in an inclusive sense, rather than an exclusive or exhaustive sense. That is, the meaning is "including but not limited to". As generally used herein, the term "coupled" refers to two or more elements that can be directly connected or connected through one or more intermediate elements. Similarly, as generally used herein, the term "connected" refers to two or more elements that can be directly connected or connected through one or more intermediate elements. In addition, when used in this application, the words "herein", "above", "below", "hereafter", "supra" and words of similar meaning shall refer to the entirety of this application rather than any particular part of this application.

[0054] Furthermore, unless expressly stated otherwise or otherwise understood in the context of use, conditional language used herein, such as "may," "might," "for example," "such as," and the like, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and / or states. Thus, such conditional language is generally not intended to imply that one or more embodiments in any way require features, elements, and / or states, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0055] Although certain embodiments have been described, these embodiments are presented as examples only, and are not intended to limit the scope of the present disclosure. In fact, the novel devices, methods, and systems described herein can be embodied in various other forms. In addition, without departing from the spirit of the present disclosure, various omissions, replacements, and changes can be made to the form of the methods and systems described herein. For example, although blocks are presented in a given arrangement, alternative embodiments can perform similar functions with different components and / or circuit topologies, and some blocks can be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks can be implemented in various different ways. Any suitable combination of the elements and actions of the various embodiments described above can be combined to provide further embodiments. The various features and processes described above can be implemented independently of each other, or can be combined in various ways. All suitable combinations and subcombinations of the features of the present disclosure are intended to fall within the scope of the present disclosure.

Claims

1. A full adder, comprising: A NAND logic circuit (ND2) configured to receive a first input (A) and a second input (B) and generate a first intermediate result (GN1); An NAND logic circuit (OAI 21) configured to receive a first input (A), a second input (B) and a first intermediate result (GN1) of the NAND logic circuit and generate a second intermediate result (TN1); a first NOR logic circuit (NR2), configured to receive the second intermediate result (TN1) of the NOR logic circuit (OAI 21) and a third input (C i n_n), and generate a third intermediate result (GN2); An AND-NOR logic circuit (AOI 21) is configured to receive a second intermediate result (TN1) of the AND-NOR logic circuit, a third input (C i n_n) and a third intermediate result (GN2) of the first OR-NOR logic circuit, and generate a first output (SUM); as well as The carry generation circuit (NR2B) is configured to receive the first intermediate result (GN1) of the NAND logic circuit and the third intermediate result (GN2) of the first NOR logic circuit and generate a second output (Cout_n).

2. The full adder as claimed in claim 1, wherein: When the first input (A) is a positive addend, the second input (B) is a positive augend, and the third input (Cin_n) is a negative carry from a lower bit, the first output (SUM) is a positive remainder and the second output is a negative carry (Cout_n).

3. The full adder as claimed in claim 1, wherein: The NAND logic circuit (ND2) includes: a first PMOS transistor having a gate terminal configured to receive a first input (A) and a drain terminal coupled to a first node; a second PMOS transistor having a gate terminal configured to receive the second input (B) and a drain terminal coupled to the first node, wherein a source terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to a power supply terminal; a first NMOS transistor having a gate terminal configured to receive a first input (A) and a drain terminal coupled to the first node; and a second NMOS transistor having a gate terminal configured to receive the second input (B) and a drain terminal coupled to the source terminal of the first NMOS transistor, wherein the source terminal of the second NMOS transistor is coupled to the ground terminal, The NAND logic circuit (ND2) is configured to generate a first intermediate result (GN1) at the first node.

4. The full adder as claimed in claim 1, wherein: The OR and NAND logic circuit (OAI 21) includes: a third PMOS transistor having a gate terminal configured to receive the first intermediate result ( GN1 ) of the NAND logic circuit and a drain terminal coupled to the second node; a fourth PMOS transistor having a gate terminal configured to receive the first input (A), wherein a source terminal of each of the third PMOS transistor and the fourth PMOS transistor is coupled to a power supply terminal; a fifth PMOS transistor having a gate terminal configured to receive the second input (B), a source terminal coupled to the drain terminal of the fourth PMOS transistor, and a drain terminal coupled to the second node; a third NMOS transistor, whose gate terminal is configured to receive the first intermediate result ( GN1 ) of the NAND logic circuit and whose drain terminal is coupled to the second node; a fourth NMOS transistor having a gate terminal configured to receive the first input (A) and a drain terminal coupled to the source terminal of the third NMOS transistor; and a fifth NMOS transistor having a gate terminal configured to receive the second input (B) and a drain terminal coupled to the source terminal of the third NMOS transistor, wherein a source terminal of each of the fourth NMOS transistor and the fifth NMOS transistor is coupled to a ground terminal, The OR-NAND logic circuit (OAI 21) is configured to generate a second intermediate result (TN1) at the second node.

5. The full adder as claimed in claim 1, wherein: The first NOR logic circuit (NR2) comprises: a sixth PMOS transistor, a gate terminal of which is configured to receive the second intermediate result (TN1) of the NAND logic circuit (OAI 21), wherein a source terminal of the sixth PMOS transistor is coupled to the power supply terminal; a seventh PMOS transistor having a gate terminal configured to receive the third input (Ci n_n), a source terminal coupled to the drain terminal of the sixth PMOS transistor, and a drain terminal coupled to the third node; a sixth NMOS transistor having a gate terminal configured to receive the second intermediate result (TN1) of the NAND logic circuit (OAI 21) and having a drain terminal coupled to the third node; and a seventh NMOS transistor having a gate terminal configured to receive the third input (Ci n_n) and a drain terminal coupled to the third node, wherein a source terminal of each of the sixth NMOS transistor and the seventh NMOS transistor is coupled to the ground terminal, The first NOR logic circuit (NR2) is configured to generate a third intermediate result (GN2) at a third node.

6. The full adder as claimed in claim 1, wherein: The AND-OR-NON logic circuit (AOI 21) includes: an eighth PMOS transistor having a gate terminal configured to receive a third intermediate result (GN2) of the first NOR logic circuit, wherein a source terminal of the eighth PMOS transistor is coupled to the power supply terminal; a ninth PMOS transistor, whose gate terminal is configured to receive the second intermediate result (TN1) of the NAND logic circuit, whose source terminal is coupled to the drain terminal of the eighth PMOS transistor, and whose drain terminal is coupled to the fourth node; a tenth PMOS transistor having a gate terminal configured to receive the third input (Ci n_n), a source terminal coupled to the drain terminal of the eighth PMOS transistor, and a drain terminal coupled to the fourth node; an eighth NMOS transistor having a gate terminal configured to receive a third intermediate result (GN2) of the first NOR logic circuit and a drain terminal coupled to the fourth node; a ninth NMOS transistor, whose gate terminal is configured to receive the second intermediate result (TN1) of the NAND logic circuit and whose drain terminal is coupled to the fourth node; and a tenth NMOS transistor having a gate terminal configured to receive the third input (Ci n_n) and a drain terminal coupled to the source terminal of the ninth NMOS transistor, wherein a source terminal of each of the eighth NMOS transistor and the tenth NMOS transistor is coupled to the ground terminal, The AND-NOR logic circuit (AOI 21) is configured to generate a first output (SUM) at the fourth node.

7. The full adder as claimed in claim 1, wherein: The carry generation circuit (NR2B) includes an inverter (I NV) and a second NOR logic circuit (NR2'), the inverter (I NV) is configured to receive the first intermediate result (GN1) of the NAND logic circuit and generate a fourth intermediate result (GN1 n), and the second NOR logic circuit (NR2') is configured to receive the fourth intermediate result (GN1 n) of the inverter and the third intermediate result (GN2) of the first NOR logic circuit and generate a second output (Cout_n).

8. The full adder as claimed in claim 7, wherein: The inverter (I NV) includes: an eleventh PMOS transistor having a gate terminal configured to receive the first intermediate result (GN1) of the NAND logic circuit and a drain terminal coupled to the fifth node, wherein a source terminal of the eleventh PMOS transistor is coupled to the power supply terminal; and an eleventh NMOS transistor, a gate terminal of which is configured to receive the first intermediate result (GN1) of the NAND logic circuit and a drain terminal of which is coupled to the fifth node, wherein a source terminal of the eleventh NMOS transistor is coupled to the ground terminal, The inverter (I NV) is configured to generate a fourth intermediate result (GN1 n) at the fifth node.

9. The full adder as claimed in claim 7, wherein: The second NOR logic circuit (NR2') comprises: a twelfth PMOS transistor having a gate terminal configured to receive the fourth intermediate result (GN1 n) of the inverter, wherein a source terminal of the twelfth PMOS transistor is coupled to the power supply terminal; a thirteenth PMOS transistor, whose gate terminal is configured to receive the third intermediate result (GN2) of the first NOR logic circuit, whose source terminal is coupled to the drain terminal of the twelfth PMOS transistor, and whose drain terminal is coupled to the sixth node; a twelfth NMOS transistor having a gate terminal configured to receive the fourth intermediate result (GN1 n) of the inverter and a drain terminal coupled to the sixth node; and a thirteenth NMOS transistor whose gate terminal is configured to receive the output (GN2) of the first NOR logic circuit and whose drain terminal is coupled to the sixth node, wherein a source terminal of each of the twelfth NMOS transistor and the thirteenth NMOS transistor is coupled to the ground terminal, The second NOR logic circuit (NR2') is configured to generate a second output (Cout_n) at the sixth node.

10. A ripple-carry adder, comprising a plurality of cascaded full adders according to any one of claims 1 to 9.

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