Display device

Abstract

The present disclosure relates to a display device that minimizes the chance of a diode being disconnected while maximizing a light-emitting area. The display device includes: a substrate; a first transistor including a first active pattern having a first channel region, a first source region, a first drain region, and a first gate electrode; a first insulating layer; a first electrode; a second insulating layer having a first opening disposed on the first electrode; a first contact member; a third insulating layer having a second opening disposed on the first contact member; a pixel electrode disposed on the third insulating layer and electrically connected to the first contact member through the second opening; and an emission layer, wherein the first gate electrode overlaps with the first electrode to form a capacitor, the center of the second opening is not aligned with the center of the first opening when shown in a plan view, and the light-emitting area of the pixel electrode is disposed away from the first contact member when shown in a cross-sectional view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0023730 filed on February 28, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a light emitting diode (LED) display device that minimizes the chance of diode disconnection while maximizing a light emitting area. Background Art

[0004] Compared to liquid crystal displays (LCDs), LED displays have become increasingly popular because they have the ability to emit light independently of a separate light source, and therefore have the ability to have minimal thickness and therefore minimal overall weight. Additional advantages include low power consumption and favorable processing speeds.

[0005] Typically, such an LED display includes pixels, and each pixel includes a transistor and a light-emitting element. The transistor is connected to a respective signal line and transmits a driving current to the light-emitting element. Each transistor may include an active pattern including a channel region and a conductive region.

[0006] The light emitting element may include an anode and a cathode, and the anode may be connected to a transistor of the pixel so as to receive a driving current.

[0007] It will be understood that this background section is intended, to some extent, to provide a useful context for understanding the technology. However, this background section may also include ideas, concepts, or understandings that were not already known or understood as part of the subject matter disclosed herein by one skilled in the relevant art before the corresponding effective filing date. Summary of the Invention

[0008] The embodiments herein are directed to optimizing the pixel structure of an LED display device to maximize the light emitting area while preventing the chance of diode disconnection.

[0009] According to an exemplary embodiment of the present disclosure, a display device includes: a substrate; a first transistor, which is arranged on the substrate and includes a first active pattern having a first channel region, a first source region, a first drain region, and a first gate electrode; a first insulating layer, which is arranged on the first transistor; a first electrode, which is arranged on the first insulating layer and electrically connected to the first drain region; a second insulating layer, which has a first opening arranged on the first electrode; a first contact member, which is arranged on the second insulating layer and electrically connected to the first electrode through the first opening; a third insulating layer, which has a second opening arranged on the first contact member; a pixel electrode, which is arranged on the third insulating layer and electrically connected to the first contact member through the second opening; and an emission layer, which is arranged on the pixel electrode, wherein the first gate electrode overlaps with the first electrode to form a capacitor, when shown in a plan view, the center of the second opening is spaced apart from the center of the first opening, and when shown in a cross-sectional view, the light emitting area of the pixel electrode is arranged away from the first contact member.

[0010] In some exemplary embodiments of the present disclosure, when shown in the plan view, the first contact member does not overlap with the first gate electrode.

[0011] In some exemplary embodiments of the present disclosure, when shown in the plan view, a portion of the second opening overlaps with the first opening.

[0012] In some exemplary embodiments of the present disclosure, the display device further includes: a conductive layer disposed on the substrate, and when shown in a cross-sectional view, the conductive layer overlaps the first channel region.

[0013] In some exemplary embodiments of the present disclosure, when shown in the plan view, the first contact member does not overlap with the first active pattern.

[0014] In some exemplary embodiments of the present disclosure, the display device further includes: a fourth insulating layer having a third opening arranged on the pixel electrode; and a common electrode arranged on the emission layer, wherein, when shown in the plan view, the second opening does not overlap with the third opening, and when shown in the cross-sectional view, a portion of the emission layer is arranged in the third opening, and an edge of the third opening is a light-limiting area of the pixel electrode.

[0015] In some exemplary embodiments of the present disclosure, the first contact member does not overlap with the third opening.

[0016] In some exemplary embodiments of the present disclosure, the display device further includes: a common voltage line, which transmits a common voltage and is arranged between the first insulating layer and the second insulating layer; and a second contact member, which is arranged between the second insulating layer and the third insulating layer, and is arranged in the same layer as the first contact member and contains the same material as the first contact member, wherein the second insulating layer further includes a fourth opening arranged on the common voltage line, the third insulating layer further includes a fifth opening arranged on the second contact member, the common electrode is electrically connected to the second contact member through the fifth opening, and the second contact member is electrically connected to the common voltage line through the fourth opening.

[0017] In some exemplary embodiments of the present disclosure, when shown in a cross-sectional view, at least a portion of the first contact member does not overlap with the first electrode.

[0018] In some exemplary embodiments of the present disclosure, the display device further includes: a second transistor disposed on the substrate and including a second active pattern having a second channel region, a second source region, a second drain region, and a second gate electrode, wherein the second drain region is electrically connected to the first gate electrode.

[0019] According to an exemplary embodiment of the present disclosure, a display device includes: a first transistor including a first gate electrode; a driving gate electrode including the first gate electrode; a capacitor electrode overlapping the driving gate electrode to form a capacitor; a first insulating layer having a first opening overlapping a portion of the capacitor electrode; a contact member electrically connected to the capacitor electrode through the first opening; a second insulating layer having a second opening overlapping the contact member; a pixel electrode electrically connected to the contact member through the second opening; an emission layer disposed on the pixel electrode; and a common electrode disposed on the emission layer, wherein, when shown in a plan view, the center of the second opening and the center of the first opening are spaced apart from each other, and when shown in a cross-sectional view, the light-emitting area of the pixel electrode is disposed away from the contact member.

[0020] According to an exemplary embodiment of the present disclosure, a display device includes: a substrate; a first transistor, which is arranged on the substrate and includes a first active pattern including a first channel region, a first source region, a first drain region, and a first gate electrode; a first insulating layer, which is arranged on the first transistor; a first electrode, which is arranged on the first insulating layer and electrically connected to the first drain region; a second insulating layer, which has a first opening arranged on the first electrode; a contact member, which is arranged on the second insulating layer and electrically connected to the first electrode through the first opening; a third insulating layer, which has a second opening arranged on the contact member; a pixel electrode, which is arranged on the third insulating layer and electrically connected to the contact member through the second opening; and an emission layer, which is arranged on the pixel electrode, wherein, when shown in a plan view, an area of the contact member is smaller than a combined area including the pixel electrode and the first electrode, a center of the second opening is not aligned with a center of the first opening, and when shown in a cross-sectional view, a light-emitting region of the pixel electrode is arranged away from the contact member. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Additional understanding according to embodiments of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0022] Figure 1 is a circuit diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure,

[0023] Figure 2 is a planar layout diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure,

[0024] Figure 3 is a planar layout diagram of a portion of a pixel of a display device according to an exemplary embodiment of the present disclosure,

[0025] Figure 4 It is along Figure 2 The line IVa-IVb intercepts Figure 2 A cross-sectional view of the display device shown,

[0026] Figure 5 It is along Figure 2 The line Va-Vb intercepts Figure 2 A cross-sectional view of the display device shown,

[0027] Figure 6 It is along Figure 2 The line VIa-VIb intercepts Figure 2 A cross-sectional view of the display device shown,

[0028] Figure 7 It is along Figure 2 The line VIa-VIb intercepts Figure 2 Another cross-sectional view of the display device shown,

[0029] Figure 8 It is along Figure 2 The line IVa-IVb intercepts Figure 2 Another cross-sectional view of the display device shown,

[0030] Figure 9 is a planar layout diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure,

[0031] Figure 10 It is along Figure 9 The line Xa-Xb intercepts Figure 9 A cross-sectional view of the display device shown,

[0032] Figure 11 It is along Figure 2 The line IVa-IVb intercepts Figure 2 Another cross-sectional view of the display device shown,

[0033] Figure 12 is a planar layout diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure,

[0034] Figure 13 It is along Figure 12 The line XIIIa-XIIIb is intercepted Figure 12 A cross-sectional view of the display device shown,

[0035] Figure 14 is a planar layout diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure,

[0036] Figure 15 is a planar layout diagram of a pixel electrode layer of a display device according to an exemplary embodiment of the present disclosure, and

[0037] Figure 16 It is along Figure 14 The line XVIa-XVIb intercepts Figure 14 A cross-sectional view of the display device shown. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. Although the present disclosure can be modified in various ways and have additional embodiments, the embodiments are shown in the drawings and will be primarily described in the specification. However, the scope of the present disclosure is not limited to the embodiments shown in the drawings and the specification, and should be interpreted as including all variations, equivalents, and alternatives included in the spirit and scope of the present disclosure.

[0039] The drawings and descriptions are to be considered merely illustrative in nature and therefore do not limit the embodiments described and claimed herein. In order to describe the embodiments of the present disclosure, some parts not related to the description may not be provided, and the same reference numerals refer to the same elements throughout the specification.

[0040] In the drawings, the size and thickness of each element are arbitrarily indicated for better understanding and ease of description, but the present disclosure is not limited thereto. In the drawings, the thickness of layers, films, panels, regions, and other elements may be exaggerated for clarity. In the drawings, the thickness of some layers and regions may be exaggerated for better understanding and ease of description.

[0041] In addition, in the specification, the phrase "in a plan view" refers to when the object portion is observed from above, and the phrase "in a cross-sectional view" refers to when a cross-section taken by vertically cutting the object portion is observed from the side. In addition, the term "overlap" or "overlapping" means that a first object can be above or below a second object, and vice versa. When a layer, film, region, substrate or location is referred to as being "on" another layer, film, region, substrate or location, the layer, film, region, substrate or location can be directly on the other film, region, substrate or location, or an intermediate film, region, substrate or location can be present between them. Conversely, when a layer, film, region, substrate or location is referred to as being "directly" "on" another layer, film, region, substrate or location, there may not be an intermediate layer, film, region, substrate or location between them. In addition, when a layer, film, region, substrate or location is referred to as being "below" another layer, film, region, substrate or location, the layer, film, region, substrate or location may be directly below the other layer, film, region, substrate or location, or an intermediate layer, film, region, substrate or location may be present between them. Conversely, when a layer, film, region, substrate or location is referred to as being "directly below" another layer, film, region, substrate or location, an intermediate layer, film, region, substrate or location may not be present between them. In addition, "above" or "on" may include positioning on or below an object, and does not necessarily imply a direction based on gravity.

[0042] For ease of description, as shown in the figures, spatially relative terms such as "below," "under," "below," "above," or "above" may be used herein to describe the relationship between one element or component and another element or component. It will be understood that in addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. For example, where the device shown in the figures is flipped, a device that is located "below" or "beneath" another device can be placed "above" the other device. Thus, the illustrative term "below" can include both a below position and an above position. Devices can also be oriented in other directions, and therefore, spatially relative terms can be interpreted differently depending on the orientation.

[0043] Throughout this specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to the other element, or “electrically connected” to the other element with one or more intervening elements interposed therebetween. It will be further understood that when the terms “comprises,” “includes,” “contains,” and / or “has” are used in this specification, they or it may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0044] It will be understood that although the terms "first," "second," or "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another or to facilitate description and illustration. For example, when discussing a "first element" in the specification, it may be named a "second element" or a "third element," and similar names may be used for the "second element" and "third element" without departing from the teachings herein.

[0045] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined in the specification, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

[0047] Figure 1 is a circuit diagram of a pixel PX of a display device according to an exemplary embodiment of the present disclosure, although it is contemplated that the display device may include several additional pixels PX.

[0048] like Figure 1 As shown, the pixel PX includes transistors T1, T2, and T3, a capacitor Cst, and at least one light emitting diode (LED) ED.

[0049] The transistors T1, T2 and T3 include a first transistor T1, a second transistor T2 and a third transistor T3. As described below, a source electrode and a drain electrode are two separate electrodes provided on both sides of a channel of each transistor T1, T2 and T3.

[0050] A gate electrode G1 of the first transistor T1 is connected to one terminal of the capacitor Cst, a source electrode S1 of the first transistor T1 is connected to a driving voltage line transmitting a driving voltage ELVDD, and a drain electrode D1 of the first transistor T1 is connected to an anode of a light emitting diode (LED) ED and the other terminal of the capacitor Cst. The first transistor T1 receives a data voltage DAT according to a switching operation of the second transistor T2 and can supply a driving current to the light emitting diode (LED) ED according to a voltage stored in the capacitor Cst.

[0051] A gate electrode G2 of the second transistor T2 is connected to a first scan line transmitting a first scan signal SC, a source electrode S2 of the second transistor T2 is connected to a data line transmitting a data voltage DAT or a reference voltage, and a drain electrode D2 of the second transistor T2 is connected to one terminal of the capacitor Cst and the gate electrode G1 of the first transistor T1. The second transistor T2 can be turned on according to the first scan signal SC to transmit the reference voltage or the data voltage DAT to the gate electrode G1 of the first transistor T1 and one terminal of the capacitor Cst.

[0052] The gate electrode G3 of the third transistor T3 is connected to the second scan line transmitting the second scan signal SS, and the source electrode S3 of the third transistor T3 is connected to the other terminal of the capacitor Cst, the drain electrode D1 of the first transistor T1, and the anode of the light emitting diode (LED) ED. The drain electrode D3 of the third transistor T3 is connected to an initialization voltage line for transmitting an initialization voltage INIT. The third transistor T3 can be turned on in response to the second scan signal SS to transmit the initialization voltage INIT to the anode of the light emitting diode (LED) ED and the other terminal of the capacitor Cst, thereby initializing the voltage of the anode of the light emitting diode (LED) ED.

[0053] One terminal of the capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and the other terminal is connected to the source electrode S3 of the third transistor T3 and the anode of the light emitting diode (LED) ED. The cathode of the light emitting diode (LED) ED is connected to a common voltage line for transmitting a common voltage ELVSS.

[0054] A light emitting diode (LED) ED may emit light according to a driving current formed by the first transistor T1.

[0055] We will now describe Figure 1 An example of the operation of the circuit shown, specifically, an example of the operation during one frame. In this example, transistors T1, T2, and T3 are N-channel transistors, but are not limited thereto.

[0056] When a frame begins, during the initialization period, a high-level first scan signal SC and a high-level second scan signal SS are supplied to turn on the second transistor T2 and the third transistor T3. A reference voltage from the data line is supplied to the gate electrode G1 of the first transistor T1 and one terminal of the capacitor Cst via the turned-on second transistor T2. Furthermore, an initialization voltage INIT is supplied to the drain electrode D1 of the first transistor T1 and the anode of the light-emitting diode (LED) ED via the turned-on third transistor T3. Therefore, during the initialization period, the drain electrode D1 of the first transistor T1 and the anode of the light-emitting diode (LED) ED are initialized by the initialization voltage INIT. At this time, the capacitor Cst stores the voltage difference between the reference voltage and the initialization voltage INIT.

[0057] During the sensing period, if the second scan signal SS goes low while the first scan signal SC remains high, the second transistor T2 remains on and the third transistor T3 is turned off. The gate electrode G1 of the first transistor T1 and one terminal of the capacitor Cst maintain a reference voltage via the turned-on second transistor T2, while the drain electrode D1 of the first transistor T1 and the anode of the light-emitting diode (LED) ED are disconnected from the initialization voltage INIT via the turned-off third transistor T3. Therefore, when current flows from the source electrode S1 to the drain electrode D1, the first transistor T1 is turned off, and the voltage at the drain electrode D1 becomes the "reference voltage Vth," where Vth represents the threshold voltage of the first transistor T1. At this time, the voltage difference between the gate electrode G1 and the drain electrode D1 of the first transistor T1 is stored in the capacitor Cst, thereby completing the sensing of the threshold voltage Vth of the first transistor T1. By generating a data signal compensated by reflecting the sensed characteristic information during the sensing period, characteristic variations of the first transistor T1, which may vary for each pixel, can be externally compensated.

[0058] During the data input period, when a high-level first scan signal SC is supplied and a low-level second scan signal SS is supplied, the second transistor T2 is turned on and the third transistor T3 is turned off. The data voltage DAT from the data line is supplied to one terminal of the capacitor Cst and the gate electrode G1 of the first transistor T1 via the turned-on second transistor T2. In this case, with the first transistor T1 in the off state, the anode of the drain electrode D1 and the light-emitting diode (LED) ED of the first transistor T1 can be substantially maintained at the potential during the sensing period.

[0059] In the light emitting period, the first transistor T1 turned on by the data voltage DAT transmitted to the gate electrode G1 generates a driving current according to the data voltage DAT and may activate a light emitting diode (LED) ED by the driving current.

[0060] Now refer to Figure 1 and Figures 2 to 7 A detailed structure of a display device according to an exemplary embodiment of the present disclosure is described.

[0061] Figure 2 is a planar layout diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure, Figure 3 is a planar layout diagram of a portion of a pixel of a display device according to an exemplary embodiment of the present disclosure, Figure 4 It is along Figure 2 The line IVa-IVb intercepts Figure 2 A cross-sectional view of the display device shown, Figure 5 It is along Figure 2 The line Va-Vb intercepts Figure 2 A cross-sectional view of the display device shown, Figure 6 It is along Figure 2 The line VIa-VIb intercepts Figure 2 A cross-sectional view of the display device is shown, and Figure 7 It is along Figure 2 The line VIa-VIb intercepts Figure 2 Another cross-sectional view of the display device shown.

[0062] The display device according to an exemplary embodiment may include a substrate 110 , which may be flexible and may be formed of an insulating material such as glass or plastic.

[0063] like Figures 2 to 7 As shown, a first conductive layer including a lower pattern 111 may be provided on a substrate 110. The lower pattern 111 may include various conductive metals or semiconductor materials having conductive properties.

[0064] The buffer layer 120 of the insulating layer may be disposed on the first conductive layer.

[0065] An active layer including active patterns 130a, 130b, and 130c may be disposed on the buffer layer 120. The active patterns 130a, 130b, and 130c are disposed in the respective pixels PX1, PX2, and PX3 and may include channel regions 134a, 134b, and 134c connected to the conductive regions to form channels of the aforementioned transistors T1, T2, and T3. The conductive regions of each of the active patterns 130a, 130b, and 130c may include source regions 133a, 133b, and 133c and drain regions 135a, 135b, and 135c of the respective transistors T1, T2, and T3.

[0066] In each of the pixels PX1 , PX2 , and PX3 , the active pattern 130 a and the active pattern 130 c may be connected to each other, or may be spaced apart from each other. Figure 2 An example is shown in which the active pattern 130a and the active pattern 130c are connected to each other. In this case, the drain region 135a of the active pattern 130a may be the source region 133c of the active pattern 130c.

[0067] The active layer may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or may be an oxide semiconductor.

[0068] The insulating pattern 144 of the first insulating layer may be disposed on the active layer. Although the insulating pattern 144 may not substantially overlap with the conductive regions of the active patterns 130a, 130b, and 130c, the insulating pattern 144 may overlap with the channel regions 134a, 134b, and 134c of the active patterns 130a, 130b, and 130c and may be disposed on the channel regions 134a, 134b, and 134c.

[0069] The second conductive layer may be disposed on the insulating pattern 144. The second conductive layer may include a first scan line 151 capable of transmitting the first scan signal SC as described above, a second scan line 152 capable of transmitting the second scan signal SS, a horizontal initialization voltage line 153 capable of transmitting the initialization voltage INIT, a horizontal driving voltage line 172b capable of transmitting the driving voltage ELVDD, a driving gate electrode 155, a second gate electrode 154b, and a third gate electrode 154c. The gate electrodes G1, G2, and G3 in the above circuit diagram may correspond to the first gate electrode 154a, the second gate electrode 154b, and the third gate electrode 154c, respectively. Each of the first gate electrode 154a, the second gate electrode 154b, and the third gate electrode 154c may be included in the driving gate electrode 155.

[0070] The first and second scan lines 151 and 152 , the transverse initialization voltage line 153 , and the transverse driving voltage line 172 b may extend in the first direction DR1 , respectively.

[0071] In the plan view, Figure 2 As shown, the driving gate electrode 155 may be disposed between the first scan line 151 and the second scan line 152 .

[0072] Still refer to Figure 2 , the second gate electrode 154b is shown as being spaced apart from the first scan line 151 and may extend substantially in the second direction DR2. Alternatively, the second gate electrode 154b may be directly connected to the first scan line 151.

[0073] The third gate electrode 154 c is spaced apart from the second scan line 152 and may extend substantially in the second direction DR2 . Alternatively, the third gate electrode 154 c may be directly connected to the second scan line 152 .

[0074] The driving gate electrode 155 disposed at each pixel PX1 , PX2 , and PX3 may include a protrusion 155 a protruding upward and a first gate electrode 154 a protruding downward and extending substantially in the second direction DR2 .

[0075] The first gate electrode 154a intersects the active pattern 130a and overlaps the channel region 134a of the active pattern 130a. The second gate electrode 154b intersects the active pattern 130b and overlaps the channel region 134b of the active pattern 130b. The third gate electrode 154c intersects the active pattern 130c and overlaps the channel region 134c of the active pattern 130c.

[0076] refer to Figure 4 For example, the second insulating layer 160 may be disposed on the second conductive layer. In addition, the buffer layer 120 and / or the second insulating layer 160 may include openings 24 , 26 , 60 , 61 , 62 , 63 , 64 , 65 , 66 , 67 , 68 , and 69 .

[0077] Furthermore, a third conductive layer may be disposed on the second insulating layer 160. The third conductive layer may include data lines 171a, 171b, and 171c, driving voltage lines 172a, 172c, and 172d, a common voltage line 170, an initialization voltage line 173, a capacitor electrode 175, and connection members 174, 176, 177, and 178.

[0078] exist Figure 2 In the illustrated plan view, data lines 171 a , 171 b , and 171 c , driving voltage lines 172 a , 172 c , and 172 d , common voltage line 170 , and initialization voltage line 173 may respectively extend in substantially the second direction DR2 and may intersect the first and second scan lines 151 and 152 .

[0079] For example, and if Figure 2 As shown, the pixels PX1, PX2, and PX3 may be arranged adjacent to each other in the first direction DR1, and may be repeatedly arranged in the first direction DR1 and the second direction DR2. The common voltage line 170 may be respectively arranged on the left and right sides of the pixels PX1, PX2, and PX3. Figure 2 As shown, when one or more repeated pixel groups of pixels PX1, PX2 and PX3 include three pixels PX1, PX2 and PX3, three data lines 171a, 171b and 171c, three driving voltage lines 172a, 172c and 172d and at least one initialization voltage line 173 can be set between two adjacent common voltage lines 170.

[0080] Each of the data lines 171a, 171b, and 171c is electrically connected to the source region 133b of the active pattern 130b through the opening 64 of the second insulating layer 160, wherein Figure 2 As shown, two openings 64 are shown in each of pixels PX1 , PX2 and PX3 to provide such a connection.

[0081] The driving voltage lines 172a, 172c, and 172d may be provided to correspond to the pixels PX1, PX2, and PX3, respectively. The driving voltage lines 172a, 172c, and 172d are electrically connected to the source region 133a of the active pattern 130a through the opening 61 of the second insulating layer 160, where Figure 2 As shown, two openings 61 are shown in pixels PX1 and PX2, and one opening 61 is shown in pixel PX3. The driving voltage lines 172a, 172c, and 172d are electrically connected to the transverse driving voltage line 172b through the opening 60 of the second insulating layer 160. Therefore, the transverse driving voltage line 172b can transmit the driving voltage together with the driving voltage lines 172a, 172c, and 172d, so that the driving voltage across the entire display device is transmitted in a grid shape (i.e., in two directions DR1 and DR2).

[0082] The initialization voltage line 173 is electrically connected to the horizontal initialization voltage line 153 through the opening 69 of the second insulating layer 160. Therefore, the horizontal initialization voltage line 153 can transmit the initialization voltage together with the initialization voltage line 173. For example, even if one initialization voltage line 173 is formed for all three pixels PX1, PX2, and PX3, the initialization voltage can be transmitted to all three pixels PX1, PX2, and PX3 through the horizontal initialization voltage line 153.

[0083] One capacitor electrode 175 may be provided at each pixel PX1, PX2, and PX3. The capacitor electrode 175 may overlap with the corresponding driving gate electrode 155, thereby forming a capacitor Cst. The driving gate electrode 155 may be referred to as a first capacitor electrode, and the capacitor electrode 175 may be referred to as a second capacitor electrode.

[0084] like Figure 2 As shown, the capacitor electrode 175 may include a protrusion 175a extending downward toward the transistor T1. The protrusion 175a is electrically connected to the drain region 135a of the active pattern 130a (or the source region 133c of the active pattern 130c) through the opening 62 of the second insulating layer 160. Figure 2 , two openings 62 are shown at each pixel PX1, PX2, and PX3. In addition, the capacitor electrode 175 is electrically connected to the lower pattern 111 through the opening 68 extending through the second insulating layer 160 and the buffer layer 120.

[0085] Return Reference Figure 2 The connection member 174 may be electrically connected to the second scan line 152 and the third gate electrode 154 c through the opening 24 of the second insulating layer 160 to electrically connect the second scan line 152 and the third gate electrode 154 c.

[0086] In addition, the connection member 176 may be electrically connected to the first scan line 151 and the second gate electrode 154 b through the opening 26 of the second insulating layer 160 to electrically connect the first scan line 151 and the second gate electrode 154 b.

[0087] In each of the pixels PX1, PX2, and PX3, the connection member 177 is electrically connected to the drain region 135c of the active pattern 130c through the opening 63 of the second insulating layer 160. Figure 2 , two openings 63 are shown at each pixel PX1, PX2 and PX3, and the connecting member 177 is also electrically connected to the horizontal initialization voltage line 153 through the opening 67 of the second insulating layer 160, so that the drain region 135c of the active pattern 130c can be electrically connected to the horizontal initialization voltage line 153.

[0088] The horizontal initialization voltage line 153 extends across the three pixels PX1, PX2, and PX3 in the first direction DR1. Alternatively, the horizontal initialization voltage line 153 may be disposed between two adjacent common voltage lines 170 so as not to intersect the two common voltage lines 170. Figure 2 As shown, the transverse initialization voltage line 153 intersects three adjacent data lines 171 a , 171 b , and 171 c and may extend to the initialization voltage line 173 .

[0089] The connection member 178 is electrically connected to the drain region 135b of the active pattern 130b in each of the pixels PX1, PX2, and PX3 through the opening 65, wherein Figure 2 As shown, two openings 65 are provided in each of the pixels PX1, PX2, and PX3, and a connecting member 178 is electrically connected to the protrusion 155a of the driving gate electrode 155 through the opening 66 of the second insulating layer 160 so that the drain region 135b of the active pattern 130b and the protrusion 155a of the driving gate electrode 155 can be electrically connected.

[0090] It will be understood that at least one of the first conductive layer, the second conductive layer, and the third conductive layer may be made of at least one of copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys thereof. Each of the first conductive layer, the second conductive layer, and the third conductive layer may include a single layer or multiple layers. For example, the third conductive layer may have a multilayer structure including a lower layer including titanium and an upper layer including copper.

[0091] refer to Figure 2 and Figure 4 For example, the first transistor T1 includes a channel region 134a, a source region 133a, a drain region 135a, and a first gate electrode 154a. The source region 133a of the first transistor T1 is electrically connected to the driving voltage lines 172a, 172c, and 172d, thereby receiving the driving voltage discussed above.

[0092] The lower pattern 111 corresponds to the first transistor T1 and overlaps the channel region 134a of the first transistor T1 between the channel region 134a and the substrate 110 to prevent external light from reaching the channel region 134a, thereby reducing leakage current and degradation of the first transistor T1. The lower pattern 111 is electrically connected to the drain region 135a of the first transistor T1 via the capacitor electrode 175.

[0093] The second transistor T2 includes a channel region 134b, a source region 133b, a drain region 135b, and a second gate electrode 154b. The source region 133b of the second transistor T2 is electrically connected to the data lines 171a, 171b, and 171c to receive a data voltage or a reference voltage. The drain region 135b of the second transistor T2 can be electrically connected to the first gate electrode 154a via the driving gate electrode 155.

[0094] The third transistor T3 includes a channel region 134 c , a source region 133 c , a drain region 135 c , and a third gate electrode 154 c . The drain region 135 c of the third transistor T3 may receive an initialization voltage from the lateral initialization voltage line 153 .

[0095] The third insulating layer 181 may be disposed on the second insulating layer 160 and the third conductive layer. Figure 2 and Figures 5 and 6 , the third insulating layer 181 may include an opening 83a provided on the capacitor electrode 175 and an opening 81 provided on the common voltage line 170. For example, Figure 2 As shown in the plan view of , the opening 83 a may be provided at a position overlapping with the upper end of the capacitor electrode 175 .

[0096] A fourth conductive layer including contact members 190 a , 190 b , 190 c , and 190 d may be disposed on the third insulating layer 181 .

[0097] Each of contact members 190a, 190b, and 190c is provided in each of pixels PX1, PX2, and PX3 and can contact capacitor electrode 175 through opening 83a for electrical connection. Contact members 190a, 190b, and 190c can also overlap an upper end of capacitor electrode 175 and opening 83a.

[0098] In addition, if Figure 2 As shown, each of the contact members 190a, 190b, and 190c may include a portion that does not overlap with the capacitor electrode 175. Specifically, each of the contact members 190a, 190b, and 190c may include a portion that does not overlap with the upper end of the capacitor electrode 175. In addition, each of the contact members 190a, 190b, and 190c may not overlap with the driving gate electrode 155.

[0099] The contact member 190 d may be electrically connected to the common voltage line 170 via the opening 81 .

[0100] The contact members 190a, 190b, 190c, and 190d can improve the adhesion of the capacitor electrode 175 and the common voltage line 170 of the third conductive layer and other conductive layers by contacting the capacitor electrode 175 and the common voltage line 170 of the third conductive layer and other conductive layers, and can prevent oxidation of at least the third conductive layer. This is particularly true if the upper layer of the third conductive layer contains copper. To this end, the fourth conductive layer can include a conductive material that can prevent corrosion of the upper layer of the third conductive layer by overlapping with such an upper layer. For example, the fourth conductive layer can include a conductive material such as a metal oxide, such as ITO or IZO.

[0101] The fourth insulating layer 182 may be disposed on the third insulating layer 181 and the fourth conductive layer. Figure 2 and Figure 5, the fourth insulating layer 182 may include an opening 83b provided on each of the contact members 190a, 190b, and 190c.

[0102] refer to Figure 2 、 Figure 3 and Figure 5 , when viewed in both a plan view and a cross-sectional view, the center CTa of the opening 83a of the third insulating layer 181 is not aligned with the center CTb of the opening 83b of the fourth insulating layer 182. That is, in a plan view, the center CTa of the opening 83a and the center CTb of the opening 83b are spaced apart from each other, so that the opening 83a and the opening 83b may be aligned as shown in the plan view. Figure 2 As shown, they do not overlap with each other, or they can be Figure 3 are shown partially overlapping each other.

[0103] As also shown in the figures referenced above, both openings 83a and 83b overlap with corresponding contact members 190a, 190b, and 190c of each of pixels PX1, PX2, and PX3. However, in a plan view, opening 83b may overlap with capacitor electrode 175, or may not overlap with capacitor electrode 175. For example, Figure 2 As shown, the opening 83b may include a portion that does not overlap with the capacitor electrode 175. That is, the opening 83b does not need to overlap with the capacitor electrode 175, so that the opening 83b can be provided in the entire fourth insulating layer 182 without being aligned with the capacitor electrode 175. That is, since the electrical connection between the capacitor electrode 175 and the contact members 190a, 190b and / or 190c is maintained via the provision of at least one of those members in the opening 83a and the opening 83b, it is not necessary to align each opening. Depending on the position of the opening 83b, the shape of the contact members 190a, 190b and 190c can be changed. Therefore, the design of the entire pixel structure can be advantageously adjusted based on the corresponding number of conductive layers, insulating layers and openings provided, without being limited to aligning such openings to pass electrical connections within the pixel.

[0104] For example, Figure 2 As shown in the plan view of , in each of the pixels PX1 , PX2 , and PX3 , the openings 83 a and 83 b and the first transistor T1 may be disposed opposite to each other about a substantially transverse center line of the capacitor electrode 175 .

[0105] At least one of the buffer layer 120, the second insulating layer 160, the third insulating layer 181, and the fourth insulating layer 182 includes silicon nitride (SiN x ), silicon oxide (SiO x) and silicon oxynitride (SiON) and / or an organic insulating material. Specifically, the fourth insulating layer 182 may include an inorganic insulating material and / or an organic insulating material such as polyimide, an acryl-based polymer, or a siloxane-based polymer, and the fourth insulating layer 182 may have a substantially flat upper surface.

[0106] On the fourth insulating layer 182, a pixel electrode layer including pixel electrodes 191a, 191b, and 191c may be provided as a fifth conductive layer. Figure 2 As shown, each of the pixel electrodes 191a, 191b, and 191c may be provided corresponding to each of the pixels PX1, PX2, and PX3. The sizes and shapes of the pixel electrodes 191a, 191b, and 191c provided on the three pixels PX1, PX2, and PX3 may be different in plan view and are not limited to the sizes and shapes shown. Pixel PX2 represents green, pixel PX1 represents red, and pixel PX3 represents blue, but is not limited thereto.

[0107] Each of the pixel electrodes 191a, 191b, and 191c may make contact with the corresponding contact members 190a, 190b, and 190c through the opening 83b of the fourth insulating layer 182 and may be electrically connected to the capacitor electrode 175 through the contact members 190a, 190b, and 190c. Therefore, each of the pixel electrodes 191a, 191b, and 191c may be electrically connected to the drain region 135a of the first transistor T1 to receive a voltage from the first transistor T1.

[0108] The pixel electrode layer may include a semi-transmissive and semi-reflective conductive material or a reflective conductive material.

[0109] refer to Figures 4 to 7 , a fifth insulating layer 350 may be disposed on the fourth insulating layer 182. The fifth insulating layer 350 has an opening 355 disposed on the pixel electrodes 191a, 191b, and 191c. The fifth insulating layer 350 may include an organic insulating material such as a polyacryl-based resin or a polyimide resin.

[0110] The emission layer 370 is disposed on the fifth insulating layer 350 and the pixel electrode layer 191a. The emission layer 370 may include a portion disposed in the opening 355 of the fifth insulating layer 350 and may include an organic light-emitting material or an inorganic light-emitting material. Alternatively, at least a portion of the fifth insulating layer 350 may not be covered by the emission layer 370.

[0111] refer to Figure 6, the fifth insulating layer 350 and the emission layer 370 may include an opening 82 provided on the contact member 190d.

[0112] The common electrode 270 is disposed above the emission layer 370. The common electrode 270 may be continuously formed above the pixels PX1, PX2, and PX3. Figure 6 , also refer to Figure 2 , the common electrode 270 may be electrically connected to the common voltage line 170 to receive the common voltage by contacting the contact member 190d through the opening 82. The common electrode 270 may include a conductive transparent material.

[0113] When also referring to Figure 7 When the fourth insulating layer 182 includes an opening 81a disposed on the contact member 190d, the pixel electrode layer may further include a contact member 191d that contacts the contact member 190d through the opening 81a. In this case, the fifth insulating layer 350 and the emission layer 370 may include an opening 82a disposed on the contact member 191d. Thus, the common electrode 270 is positioned to contact the contact member 191d through the opening 82a to be electrically connected to the contact member 190d and the common voltage line 170 to receive the common voltage ELVSS through the common voltage line 170.

[0114] As will be understood, the pixel electrodes 191a, 191b, and 191c of each of the pixels PX1, PX2, and PX3, the emission layer 370, and the common electrode 270 together form a light emitting diode (LED) ED, and one of the pixel electrodes 191a, 191b, and 191c and the common electrode 270 becomes a cathode, while the other becomes an anode. In the above, the pixel electrodes 191a, 191b, and 191c become anodes.

[0115] exist Figure 2 In a plan view of , a region where the opening 355 of the fifth insulating layer 350 is provided may define a light emitting region of each of the pixels PX1 , PX2 , and PX3 .

[0116] The edge of the opening 355 of the fifth insulating layer 350 that defines the light-emitting region of each of the pixels PX1, PX2, and PX3 can be spaced apart from the opening 83b and does not overlap with the opening 83b. In this way, the contact members 190a, 190b, or 190c provided in the opening 83b do not overlap with the opening 355. Therefore, the disconnection of the emission layer 370 caused by the step near the edge of the light-emitting region can be prevented, thereby preventing the shortening of the light-emitting period of the light-emitting diode (LED) ED. That is, the emission layer 370 can continue to operate to emit light, because the emission layer 370 does not overlap at the edge of the opening 355, so that the edge of the opening 355 is set away from the contact members 190a, 190b, or 190c. Therefore, the design of the entire pixel structure can be advantageously adjusted based on the corresponding number of conductive layers, insulating layers, and openings provided, without being limited to aligning such openings to pass electrical connections within the pixel and emit light according to the pixel.

[0117] For example, when the above continuous operations of the emission layer 370 are completed, each of the contact members 190a, 190b, and 190c may not overlap with the opening 355 of the fifth insulating layer 350. That is, referring to Figure 5 In each of the pixels PX1 , PX2 , and PX3 , the entire region of each of the contact members 190 a , 190 b , and 190 c may additionally overlap with a region where the opening 355 of the fifth insulating layer 350 is not provided.

[0118] refer to Figure 2 and Figure 4 , the contact members 190 a , 190 b , and 190 c may not overlap with the active pattern 130 a of the first transistor T1 .

[0119] In addition, the lower pattern 111a is electrically connected to the pixel electrodes 191a, 191b, and 191c via the capacitor electrode 175 and also overlaps with the channel region 134a of the first transistor T1. As a result, the current change rate is reduced in the saturation region of the voltage-current characteristic curve of the first transistor T1, thereby increasing the range of the region in which the output current of the first transistor T1 is constant. Therefore, even if the source-drain voltage Vds of the first transistor T1 changes, the output current of the first transistor T1 remains constant, thereby improving the characteristic output saturation. Therefore, the brightness deviation between pixels caused by the output current of the first transistor T1 is reduced, thereby improving the resulting image quality.

[0120] refer to Figure 2 and Figure 8 A display device according to an exemplary embodiment of the present disclosure is described. Figure 8, the display device according to the exemplary embodiment is different from the embodiments discussed above in that the sixth insulating layer 180 is disposed between the third conductive layer and the third insulating layer 181 , and the sixth conductive layer is disposed between the sixth insulating layer 180 and the third insulating layer 181 .

[0121] exist Figure 2 In the plan view shown, the sixth conductive layer may include a conductive pattern extending substantially parallel to the conductive pattern of the third conductive layer, the third conductive layer including the data lines 171a, 171b, and 171c, the driving voltage lines 172a, 172c, and 172d, the common voltage line 170, and the initialization voltage line 173, and the sixth conductive layer is electrically connected to the conductive pattern extending substantially parallel to the conductive pattern of the third conductive layer. For example, referring to Figure 8 , the sixth conductive layer may include a conductive pattern 183. Figure 2 As shown, the conductive pattern 183 may have a planar shape substantially similar to that of the conductive pattern of the third conductive layer.

[0122] In a plan view, the conductive pattern of the third conductive layer and the conductive pattern 183 of the sixth conductive layer may correspond to and overlap each other, and the overlapping area may be greater than about 90% of the area of each conductive pattern. However, the ratio of the overlapping area is not limited to such a precise amount.

[0123] Each conductive pattern 183 may be electrically connected to a corresponding conductive pattern of the third conductive layer through the opening 80 of the sixth insulating layer 180. The conductive pattern 183 may reduce resistance by transmitting the same voltage as that of the connected conductive pattern of the third conductive layer.

[0124] According to another exemplary embodiment, some of the data lines 171a, 171b and 171c, the driving voltage lines 172a, 172c and 172d, the common voltage line 170, the initialization voltage line 173, the capacitor electrode 175 and the connection members 174, 176, 177 and 178 may be disposed in the sixth conductive layer.

[0125] refer to Figures 9 and 10 A display device according to an exemplary embodiment of the present disclosure is described.

[0126] in this regard, Figure 9 is a planar layout diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure, and Figure 10 It is taken along the line Xa-Xb Figure 9 A cross-sectional view of the display device shown.

[0127] Despite Figure 8The illustrated exemplary embodiments are similar, but the embodiments differ in that the configurations of the capacitor electrode 175 of the third conductive layer and the conductive pattern of the sixth conductive layer overlapping with the capacitor electrode 175 may be changed.

[0128] For example, the conductive pattern 183 of the sixth conductive layer electrically connected to the capacitor electrode 175 may include a protrusion 185 such as a contact member that does not overlap with the capacitor electrode 175. Figure 9 When shown in plan view, most of the conductive pattern 183, except for the protrusion 185 of each conductive pattern 183, can overlap with the capacitor electrode 175, wherein the overlapping area can be greater than about 90% of the area of the conductive pattern 183, but is not limited to such a precise amount.

[0129] like Figure 9 and Figure 10 As shown, the sixth insulating layer 180 includes an opening 80 a provided on the capacitor electrode 175 , and the conductive pattern 183 of the sixth conductive layer overlapping the capacitor electrode 175 may be electrically connected to the capacitor electrode 175 through the opening 80 a .

[0130] The third insulating layer 181 may include an opening 83 d disposed above the protrusion 185 of the conductive pattern 183 of the sixth conductive layer.

[0131] exist Figure 9 Floor plan and Figure 10 In the cross-sectional view of FIG, the center of the opening 83d is not aligned with the center of the opening 80a of the sixth insulating layer 180 and is spaced apart. Figure 9 As shown, the opening 80a and the opening 83d may be spaced apart, non-overlapping, or partially overlapping in plan view.

[0132] like Figure 9 and Figure 10 As shown, both opening 80a and opening 83d overlap with the conductive pattern 183 of the corresponding sixth conductive layer of each of pixels PX1, PX2, and PX3. Opening 83d may or may not overlap with capacitor electrode 175 in a plan view. That is, opening 83d does not need to overlap with capacitor electrode 175, and the position of opening 83d can be formed regardless of the position of capacitor electrode 175. The shape of protrusion 185 of conductive pattern 183 of the sixth conductive layer can be changed according to the position of opening 83d.

[0133] The edge of the opening 355 of the fifth insulating layer 350 that defines the light-emitting region of each of the pixels PX1, PX2, and PX3 can be spaced apart from the opening 83d without overlapping with the opening 83d. Therefore, the disconnection of the emission layer 370 due to the step near the edge of the light-emitting region can be prevented, thereby preventing the shortening of the light-emitting period of the light-emitting diode (LED) ED. That is, the emission layer 370 can continue to operate to emit light, because the emission layer 370 does not overlap at the edge of the opening 355, so that the edge of the opening 355 is set away from the protrusion 185 and the contact member 190a, 190b, or 190c. Therefore, the design of the entire pixel structure can be advantageously adjusted based on the corresponding number of conductive layers, insulating layers, and openings provided, without being limited to aligning such openings to pass electrical connections within the pixel and emit light according to the pixel.

[0134] according to Figures 8 to 10 The display device of the exemplary embodiment shown may or may not include Figures 2 to 7 The display device of the exemplary embodiment shown includes a fourth conductive layer and a fourth insulating layer 182 . Figure 8 An exemplary embodiment including a fourth conductive layer and a fourth insulating layer 182 is shown, and Figure 10 An exemplary embodiment without the fourth conductive layer and the fourth insulating layer 182 is shown.

[0135] refer to Figure 11 A display device according to an exemplary embodiment of the present disclosure is described.

[0136] in this regard, Figure 11 Indicates along Figure 2 The line IVa-IVb intercepts Figure 9 Another cross-sectional view of the display device shown.

[0137] refer to Figure 11 , the display device according to the exemplary embodiment may be similar to Figures 2 to 7 The above exemplary embodiment, however, the seventh insulating layer 122 is disposed on the second conductive layer, and the seventh conductive layer is disposed between the seventh insulating layer 122 and the second insulating layer 160 .

[0138] The seventh insulating layer 122 may contact the top surfaces of the conductive regions of the active patterns 130a, 130b, and 130c. The seventh insulating layer 122 may include an opening 61a provided on the source region 133a of the active pattern 130a and an opening 62a provided on the drain region 135a of the active pattern 130a. The seventh insulating layer 122 and the buffer layer 120 may include an opening 68a provided on the lower pattern 111.

[0139] Embodiments may include a capacitor electrode 157 disposed in the seventh conductive layer instead of the capacitor electrode 175. The capacitor electrode 157 may be electrically connected to the lower pattern 111 through the opening 68a and to the drain region 135a of the active pattern 130a through the opening 62a.

[0140] The capacitor electrode 157 may have a planar shape similar to the above-described capacitor electrode 175. The capacitor electrode 157 overlaps with the corresponding driving gate electrode 155 via the seventh insulating layer 122 therebetween to form a capacitor Cst.

[0141] The seventh conductive layer may further include a connection pattern 163. For example, the seventh conductive layer may include the connection pattern 163 contacting the source region 133a of the active pattern 130a through the opening 61a, and the driving voltage line 172a may contact the connection pattern 163 through the opening 61b of the second insulating layer 160 to be electrically connected, so that the driving voltage line 172a may be electrically connected to the source region 133a of the active pattern 130a.

[0142] refer to Figures 12 to 13 A display device according to an exemplary embodiment of the present disclosure is described.

[0143] in this regard, Figure 12 is a planar layout diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure, and Figure 13 It is along Figure 12 A cross-sectional view of the display device taken along line XIIIa-XIIIb.

[0144] Although similar to Figure 11 The display device of the exemplary embodiment shown, however, the configurations of the capacitor electrode 157 of the seventh conductive layer and the third conductive layer may be changed.

[0145] For example, the third conductive layer may include a contact member 179 electrically connected to the conductive pattern of the capacitor electrode 157 , and include a portion that does not overlap with the capacitor electrode 157 .

[0146] The second insulating layer 160 may include an opening 80 b provided on the capacitor electrode 157 , and the contact member 179 of the third conductive layer may be electrically connected to the capacitor electrode 157 through the opening 80 b .

[0147] The third insulating layer 181 may include an opening 83 e provided on the contact member 179 of the third conductive layer.

[0148] In both the plan view and the cross-sectional view, the center of the opening 83e is not aligned with the center of the opening 80b of the second insulating layer 160, and they are spaced apart from each other. Figure 12As shown in the plan view of , the opening 80b and the opening 83e may be spaced apart from each other and not overlap with each other, or they may partially overlap with each other.

[0149] refer to Figure 12 and Figure 13 , both the opening 80b and the opening 83e overlap with the contact member 179 of the corresponding third conductive layer of each of the pixels PX1, PX2, and PX3. The opening 83e may or may not overlap with the capacitor electrode 157 in a plan view. That is, the opening 83e does not need to overlap with the capacitor electrode 157, and the position of the opening 83e can be formed independently of the position of the capacitor electrode 157. The shape of the contact member 179 of the third conductive layer can be changed according to the position of the opening 83e.

[0150] The edge of the opening 355 of the fifth insulating layer 350 that defines the light-emitting region of each of the pixels PX1, PX2, and PX3 can be spaced apart from the opening 83e without overlapping with the opening 83e. Therefore, the disconnection of the emission layer 370 due to the step near the edge of the light-emitting region can be prevented, thereby preventing the shortening of the light-emitting period of the light-emitting diode (LED) ED. That is, the emission layer 370 can continue to operate to emit light because the emission layer 370 does not overlap at the edge of the opening 355, so that the edge of the opening 355 is set away from the contact member 179. Therefore, the design of the entire pixel structure can be advantageously adjusted based on the corresponding number of conductive layers, insulating layers, and openings provided, without being limited to aligning such openings to pass electrical connections within the pixel and emit light according to the pixel.

[0151] according to Figures 11 to 13 The display device of the exemplary embodiment shown may include or may not include the display device according to the above Figures 2 to 7 The display device of the exemplary embodiment shown includes a fourth conductive layer and a fourth insulating layer 182 . Figure 11 An exemplary embodiment including a fourth conductive layer and a fourth insulating layer 182 is shown, and Figure 13 An exemplary embodiment without the fourth conductive layer and the fourth insulating layer 182 is shown.

[0152] refer to Figures 14 to 16 A display device according to an exemplary embodiment of the present disclosure is described.

[0153] Figure 14 is a planar layout diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure, Figure 15 is a planar layout diagram of a pixel electrode layer of a display device according to an exemplary embodiment of the present disclosure, and Figure 16 It is along Figure 14 A cross-sectional view of the display device taken along line XVIa-XVIb.

[0154] Although the display device according to the exemplary embodiment is similar to the display device according to the above-described exemplary embodiment in terms of the described connections and illustrated structures of the constituent elements, the shape of each element and the manner in which they are connected may be changed.

[0155] refer to Figure 14 , the pixels PX4, PX5 and PX6 of a repeated pixel group may be arranged substantially in the second direction DR2, while when referring to Figure 15 , pixel electrodes 191a, 191b, and 191c corresponding to pixels PX4, PX5, and PX6, respectively, may be arranged substantially in the first direction DR1. However, various other configurations of the structures of pixels PX4, PX5, and PX6 and pixel electrodes 191a, 191b, and 191c are possible and within the spirit and scope of the present disclosure.

[0156] refer to Figure 14 , the data lines 171 a , 171 b , and 171 c , the driving voltage line 172 , and the initialization voltage line 173 may be disposed between two adjacent common voltage lines 170 .

[0157] The first scan line 151 and the second scan line 152 may be disposed below and above the pixels PX4 , PX5 , and PX6 of one pixel group, respectively.

[0158] The first conductive layer may include lower patterns 111a, and each lower pattern 111a may be provided in each of the pixels PX4, PX5, and PX6. The first conductive layer may further include a transverse common voltage line 170a extending substantially in the first direction DR1.

[0159] Active patterns 130g, 130h, and 130j may be disposed in the active layer and may include channel regions 134a, 134b, and 134c, source regions 133a, 133b, and 133c, and drain regions 135a, 135b, and 135c. In each of pixels PX4, PX5, and PX6, the active patterns 130g, 130h, and 130j may be separated from each other.

[0160] The second conductive layer may include a first scan line 151, a second scan line 152, a driving gate electrode 155, a second gate electrode 154b, and a third gate electrode 154c. The first scan line 151 and the second scan line 152 may extend in the first direction DR1, respectively. Each driving gate electrode 155 may be provided corresponding to each of the pixels PX4, PX5, and PX6.

[0161] The second gate electrodes 154 b corresponding to the pixels PX4 , PX5 , and PX6 are connected to each other and entirely extend in the second direction DR2 toward the second scan line 152 .

[0162] The third gate electrodes 154 c corresponding to the pixels PX4 , PX5 , and PX6 are connected to each other and entirely extend in the second direction DR2 toward the first scan line 151 .

[0163] The driving gate electrode 155 provided in each of the pixels PX4, PX5, and PX6 may include a first gate electrode 154a protruding upward or downward. The first gate electrode 154a intersects the active pattern 130g and overlaps the channel region 134a of the active pattern 130g. The second gate electrode 154b intersects the active pattern 130h and overlaps the channel region 134b of the active pattern 130h. The third gate electrode 154c intersects the active pattern 130j and overlaps the channel region 134c of the active pattern 130j.

[0164] The third conductive layer may include data lines 171 a , 171 b , and 171 c , a driving voltage line 172 , a common voltage line 170 , an initialization voltage line 173 , a capacitor electrode 175 , and a connecting member 178 .

[0165] The data lines 171 a , 171 b , and 171 c , the driving voltage line 172 , the common voltage line 170 , and the initialization voltage line 173 may respectively extend in the substantially second direction DR2 to intersect the first and second scan lines 151 and 152 .

[0166] Each of the data lines 171a, 171b, and 171c is electrically connected to the source region 133b of the active pattern 130h through the opening 64. The driving voltage line 172 is electrically connected to the source region 133a of the active pattern 130g through the opening 61. The initialization voltage line 173 is electrically connected to the drain region 135c of the active pattern 130j via the opening 63a. The openings 61, 63a, and 64 may be formed in the second insulating layer 160.

[0167] The capacitor electrode 175 may be provided in each of the pixels PX4, PX5, and PX6 and may be provided between the driving voltage line 172 and the data line 171c in a plan view. The capacitor electrode 175 may overlap with the corresponding driving gate electrode 155 via the second insulating layer 160 therebetween to form a capacitor Cst.

[0168] Capacitor electrode 175 is electrically connected to drain region 135a of active pattern 130g through opening 62 of second insulating layer 160, and is electrically connected to source region 133c of active pattern 130j through opening 63b of second insulating layer 160 and first insulating layer 121. Furthermore, capacitor electrode 175 is electrically connected to lower pattern 111a through opening 68 of second insulating layer 160, first insulating layer 121, and buffer layer 120. Drive gate electrode 155 includes opening 55a that overlaps with opening 62, providing contact between capacitor electrode 175 and drain region 135a of active pattern 130g. Thus, drive gate electrode 155 surrounds the periphery of opening 62.

[0169] In each of the pixels PX4, PX5, and PX6, the connection member 178 is electrically connected to the drain region 135b of the active pattern 130h through the opening 65, and is electrically connected to the protrusion 155a of the driving gate electrode 155 through the opening 66, so that the drain region 135b of the active pattern 130h and the protrusion 155a of the driving gate electrode 155 can be electrically connected to each other.

[0170] Similar to the above description Figures 8 to 10 In the illustrated exemplary embodiment, the display device according to the present exemplary embodiment may include a sixth insulating layer 180 and a sixth conductive layer disposed between the third conductive layer and the third insulating layer 181 .

[0171] The sixth conductive layer may include conductive patterns having shapes similar to the conductive patterns of the third conductive layer, such as data lines 171a, 171b and 171c, a driving voltage line 172, a common voltage line 170, an initialization voltage line 173 and a capacitor electrode 175 provided in the third conductive layer below, and may be electrically connected to the corresponding conductive patterns of the third conductive layer.

[0172] For example, each of the data lines 171a, 171b and 171c can be electrically connected to the corresponding conductive pattern set in the sixth conductive layer through each of the openings 74a, 75a and 76a, the driving voltage line 172 can be electrically connected to the corresponding conductive pattern 183a set in the sixth conductive layer through the opening 71a, the common voltage line 170 can be electrically connected to the corresponding conductive pattern set in the sixth conductive layer through the opening 72a, the initialization voltage line 173 can be electrically connected to the corresponding conductive pattern set in the sixth conductive layer through the opening 73a, and the capacitor electrode 175 can be electrically connected to the corresponding conductive pattern 183b set in the sixth conductive layer through the opening 77a.

[0173] The conductive pattern of the sixth conductive layer transmits the same voltage as that of the connected third conductive layer, thereby reducing the resistance value.

[0174] The third insulating layer 181 may include an opening 80 c on the conductive pattern 183 b .

[0175] As described above, the display device according to the present exemplary embodiment may include the fourth conductive layer and the fourth insulating layer 182 .

[0176] The fourth conductive layer may include contact members 190g, 190f, and 190e, each of which has an island shape and is disposed in each of pixels PX4, PX5, and PX6. Each of contact members 190g, 190f, and 190e may contact a corresponding conductive pattern 183b through an opening 80c to be electrically connected. Thus, each of contact members 190g, 190f, and 190e may be electrically connected to capacitor electrode 175, which in turn is electrically connected to conductive pattern 183b. When shown in plan view, each of contact members 190g, 190f, and 190e may overlap with capacitor electrode 175, conductive pattern 183b, and opening 80c in each of pixels PX4, PX5, and PX6.

[0177] like Figure 14 As shown, in each of the pixels PX4, PX5, and PX6, the contact members 190g, 190f, and 190e may overlap or not overlap with the capacitor electrode 175 and the conductive pattern 183b.

[0178] The fourth insulating layer 182 may include an opening 83f provided on each of the contact members 190g, 190f, and 190e.

[0179] like Figures 14 to 16 As shown, the center of opening 83f is not aligned with the center of opening 80c, and they are spaced apart from each other. Figure 14 As shown, the opening 83f and the opening 80c may be spaced apart from each other and may not overlap with each other, or may partially overlap with each other.

[0180] Both opening 83f and opening 80c overlap with corresponding contact members 190g, 190f, and 190e of each of pixels PX4, PX5, and PX6. When shown in plan view, opening 83f may or may not overlap with capacitor electrode 175 and conductive pattern 183b. That is, opening 83f does not need to overlap with capacitor electrode 175 and conductive pattern 183b, and the position of opening 83f can be formed independently of the position of capacitor electrode 175 and conductive pattern 183b. The shapes of contact members 190g, 190f, and 190e can be changed according to the position of opening 83f.

[0181] refer to Figures 14 to 16, the edge of the opening 355 of the fifth insulating layer 350 that defines the light-emitting area of each of the pixels PX4, PX5, and PX6 does not overlap with the opening 83f and can be spaced apart from the opening 83f. Therefore, the disconnection of the emission layer 370 due to the step near the edge of the light-emitting area can be prevented, thereby preventing the shortening of the light-emitting period of the light-emitting diode (LED) ED. That is, the emission layer 370 can continue to operate to emit light because the emission layer 370 does not overlap at the edge of the opening 355, so that the edge of the opening 355 is set away from the contact member 190g, 190f, or 190e. Therefore, the design of the entire pixel structure can be advantageously adjusted based on the corresponding number of conductive layers, insulating layers, and openings provided, without being limited to aligning such openings to pass electrical connections within the pixel and emit light according to the pixel.

[0182] The third insulating layer 181 may further include an opening 81 d disposed on the conductive pattern of the sixth conductive layer connected to the common voltage line 170 .

[0183] refer to Figure 14 and Figure 15 , pixel electrodes 191a, 191b, and 191c disposed in the pixel electrode layer of the fifth conductive layer and corresponding to each of the pixels PX4, PX5, and PX6 may be electrically connected to contact members 190g, 190f, and 190e, which are electrically connected to the capacitor electrode 175 through an opening 83f included in the fourth insulating layer 182. Each of the pixel electrodes 191a, 191b, and 191c is electrically connected to the drain region 135a of the first transistor T1 via the capacitor electrode 175, thereby receiving a voltage from the first transistor T1.

[0184] The pixel electrode layer 191a may further include a contact member 191d or the contact member 190d connected to the common voltage line 170. The common electrode 270 is electrically connected to the contact member 191d through the opening 82d included in the fifth insulating layer 350 and the emission layer 370, thereby receiving a common voltage from the common voltage line 170.

[0185] The common voltage line 170 may be electrically connected to the transverse common voltage line 170 a through the opening 70 .

[0186] The second conductive layer may include a conductive pattern 150a overlapping the common voltage line 170 and conductive patterns 150b and 150c overlapping the driving voltage line 172. In this case, the conductive pattern 150a is electrically connected to the common voltage line 170 through the opening 60a of the second insulating layer 160, thereby reducing the resistance value. The conductive patterns 150b and 150c are electrically connected to the driving voltage line 172 through the openings 60b and 60c of the second insulating layer 160. However, the conductive patterns 150a, 150b, and 150c may be omitted.

[0187] Here, constituent elements provided in the same conductive layer may each include the same material, and constituent elements provided in the same insulating layer may each include the same material.

[0188] While the present disclosure has been shown and described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the disclosure.

Claims

1. A display device, wherein: The display device includes: substrate; a first transistor disposed on the substrate and comprising a first active pattern having a first channel region, a first source region, a first drain region, and a first gate electrode; a first insulating layer, disposed on the first transistor; a first electrode disposed on the first insulating layer and electrically connected to the first drain region; a second insulating layer having a first opening provided on the first electrode; a first contact member disposed on the second insulating layer and electrically connected to the first electrode through the first opening; a third insulating layer having a second opening disposed on the first contact member; a pixel electrode disposed on the third insulating layer and electrically connected to the first contact member through the second opening; a fourth insulating layer having a third opening disposed on the pixel electrode; and an emission layer, disposed on the pixel electrode, in, The first gate electrode overlaps with the first electrode to form a capacitor, When shown in plan view, a center of the second opening is spaced from a center of the first opening, and When shown in a cross-sectional view, the light emitting region of the pixel electrode is disposed away from the first contact member, the first contact member does not overlap with the third opening, A region where the first gate electrode and the first electrode overlap each other in the plan view is spaced apart from the first contact member, In the plan view, the first contact member and the first transistor are opposite to each other with respect to the first electrode of the capacitor.

2. The display device according to claim 1, wherein: When shown in the plan view, the first contact member does not overlap with the first gate electrode.

3. The display device according to claim 1, wherein: When shown in the plan view, a portion of the second opening overlaps the first opening.

4. The display device according to claim 1, wherein The display device further includes: A conductive layer is disposed on the substrate and, when shown in cross-section, overlaps the first channel region.

5. The display device according to claim 1, wherein: When shown in the plan view, the first contact member does not overlap with the first active pattern. The display device according to claim 1 , wherein: The display device further includes: A common electrode is provided on the emission layer. in, When shown in the plan view, the second opening does not overlap with the third opening, and When shown in a cross-sectional view, a portion of the emission layer is disposed in the third opening, and an edge of the third opening is a light-defining region of the pixel electrode.

7. The display device according to claim 6, wherein: The display device further includes: a common voltage line transmitting a common voltage, and the common voltage line is disposed between the first insulating layer and the second insulating layer; and a second contact member disposed between the second insulating layer and the third insulating layer and disposed in the same layer as the first contact member and comprising the same material as the first contact member, in, The second insulating layer further includes a fourth opening provided on the common voltage line, The third insulating layer further includes a fifth opening provided on the second contact member, The common electrode is electrically connected to the second contact member through the fifth opening, and The second contact member is electrically connected to the common voltage line through the fourth opening.

8. The display device according to claim 1, wherein: When shown in cross-section, at least a portion of the first contact member does not overlap with the first electrode.

9. The display device according to claim 1, wherein The display device further includes: The second transistor is disposed on the substrate and includes a second active pattern having a second channel region, a second source region, a second drain region, and a second gate electrode, wherein the second drain region is electrically connected to the first gate electrode.

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