A clock phase alignment method and circuit for high-speed serial transceiver

Abstract

A clock phase alignment method and circuit for high-speed serial transceivers. The method comprises step 1: sampling the parallel clock signal of a channel to be processed within N reference clock signal cycles to obtain N sampling results, the sampling results being a first value or a second value, N>1; step 2: determining the counting result according to the number of the first value in the N sampling results; step 3: adjusting the phase of the parallel clock signal multiple times, and repeating step 1 and step 2 after each adjustment to obtain multiple counting results with values ​​from 0 to N; step 4: drawing a relationship curve between the delay time and the corresponding counting result; step 5: adjusting the phase of the parallel clock signal according to the delay time corresponding to the rising edge or the falling edge of the relationship curve; step 6: repeating steps 1 to 5 for other channels to be processed. The solution provided by the present invention consumes less resources and has high precision, and each channel can still flexibly adjust the delay as needed after the alignment is completed.

Description

Technical Field

[0001] The present invention relates to the field of high-speed serial transceivers, and in particular to a clock phase alignment method and circuit for high-speed serial transceivers. Background Art

[0002] FPGA is a master of digital circuits. It can generate a variety of digital pulses through its large number of general-purpose input and output pins. However, due to the limitation of the global clock speed of FPGA, the clock speed of this direct pulse generation method has long been limited to below 400MHz to 500MHz. As the application fields of high-speed pulses with clock speeds exceeding 1GHz become more and more extensive, in order to generate such high-speed pulses, people have set their sights on high-speed serial transceivers integrated with FPGAs.

[0003] refer to Figure 1 The figure shows a schematic diagram of the structure of a multi-channel high-speed serial transceiver. The high-speed serial transceiver sends the parallel data serially bit by bit at a higher clock speed at the sender, and converts it into parallel data after receiving it bit by bit at the receiver, which greatly improves the communication rate. At present, the speed and number of channels of high-speed serial transceivers integrated in FPGA chips have been greatly improved. Taking the products of Xilinx as an example, its high-end FPGA chips, such as the ultrascale series, can already provide more than 100 channels of GTY transceivers with a line rate of 32.75Gb / s, and multi-channel GTX transceivers exceeding 10G / s have also been popularized in many of its lower-end products. In addition, current high-speed serial transceivers are integrated with phase interpolation, which can achieve picosecond adjustment accuracy. The characteristics of high speed and multi-channel, combined with the high adaptability of FPGA, allow high-speed serial transceivers integrated in FPGA to be applied in more and more fields besides data communication.

[0004] The core part of the data transmission end of the high-speed serial transceiver is the high-speed parallel-to-serial converter, which serializes the encoded parallel data and sends it out. The parallel-to-serial converter is divided into a parallel input side and a serial output side, and the clocks on both sides are the parallel clock signal (XCLK) and the serial clock signal (SCLK). SCLK is generally obtained by multiplying the low-frequency clock signal (REFCLK) through a phase-locked loop (PLL). Since SCLK generally has a very high frequency, it cannot be shared between multiple high-speed serial transceivers, but is used independently. XCLK is generally a frequency division of SCLK, and there is a certain phase relationship between them. In addition to SCLK and XCLK, each high-speed serial transceiver usually has a clock signal (TXUSRCLK2), which is also generated by REFCLK through a clock management unit similar to PLL, which is used to transmit parallel data to the high-speed serial transceiver. Because there are multiple PLLs, and each PLL is not locked at the same time, and the frequency dividers in it do not start working at the same time, there will be random phase differences between the XCLKs of different channels when powered on.

[0005] For ordinary serial communications, each channel can work independently, and the above-mentioned random phase difference is not a problem. However, in the field of high-speed pulse generation, it is usually necessary to superimpose the pulses of multiple channels in some form, which requires solving the phase alignment problem between multiple channels so that the time deviation between each channel meets very strict restrictions. For example, in high-speed quantum key distribution experiments, multiple high-speed serial transceivers are needed to generate high-speed pulse patterns for multiple channels, drive multiple lasers or electro-optical modulators respectively, and then combine them to obtain multi-amplitude and multi-phase modulated optical signals, or synthesize the high-speed pulse signals generated by multiple high-speed serial transceivers into a multi-amplitude electrical pulse signal, and then drive a laser or electro-optical modulator. In a quantum key distribution system with a repetition frequency exceeding 1GHz, the time deviation between each participating serial transceiver channel cannot exceed 10ps.

[0006] However, the existing phase alignment methods still have some defects. For example, Xilinx provides a built-in multi-channel automatic alignment function for its FPGAs. This function forces the XCLK of all channels to align with the rising edge, but its alignment accuracy is poor and it is not possible to flexibly adjust the phase difference between the channels as needed. HB Xie et al. proposed a solution to achieve multi-channel alignment using a time to digital converter (TDC). This solution first uses the logic resources in the FPGA to build a high-precision TDC, then uses this TDC to measure the time difference between each channel and the main channel, and then uses the phase interpolator to move the phase of each channel to compensate for this time difference. This solution has high accuracy, but it requires the implementation of a high-precision TDC in the FPGA, which is more complex to implement and occupies more resources.

[0007] It can be seen that how to provide a phase alignment circuit with low resource consumption, high precision, simple deployment, and the ability to flexibly adjust the delay of each channel as needed after the alignment is completed has become a technical problem that needs to be solved urgently in this field. Summary of the invention

[0008] The purpose of the present invention is to provide a clock phase alignment method and circuit for a high-speed serial transceiver, so as to reduce resource consumption, improve alignment accuracy, reduce deployment difficulty, and enable each channel to flexibly adjust the delay as needed after the alignment is completed.

[0009] To achieve the above object, the present invention provides a clock phase alignment method for a high-speed serial transceiver, comprising:

[0010] Step 1: within N reference clock signal cycles, sampling the parallel clock signal of one of the to-be-processed channels of the high-speed serial transceiver to obtain N sampling results, wherein the sampling result is a first value or a second value, the reference clock signal and the parallel clock signal are homologous clock signals, and the reference clock signal cycle is an integer multiple of the parallel clock signal cycle, and N>1;

[0011] Step 2: Determine a counting result according to the number of first values ​​in the N sampling results;

[0012] Step 3: adjusting the phase of the parallel clock signal multiple times, thereby adding different delay times to the parallel clock signal, and repeating steps 1 and 2 after each adjustment to obtain multiple counting results with values ​​ranging from 0 to N, each adjustment corresponding to a different delay time;

[0013] Step 4: Draw a relationship curve between the delay time and the corresponding counting result;

[0014] Step 5: According to the delay time corresponding to the rising edge or the falling edge of the relationship curve, the parallel clock signal is phase-adjusted so that the rising edge of the parallel clock signal of the channel is aligned with the rising edge of the reference clock signal;

[0015] Step 6: Repeat steps 1 to 5 for other channels to be processed to align the rising edges of the parallel clock signals of each channel.

[0016] In one embodiment, before step 1, the method further comprises:

[0017] Determining whether there is a buffer between the parallel clock signal of the channel and the clock signal of the data encoding circuit in the high-speed serial transceiver;

[0018] When a buffer zone exists, the phase of the parallel clock signal is adjusted until the value of the half-full indication bit of the buffer zone changes from 0 to 1 for the first time.

[0019] In one implementation, the delay time corresponding to the midpoint of the rising edge or the falling edge of the relationship curve is selected to perform phase adjustment on the parallel clock signal.

[0020] In one implementation, the delay time corresponding to the rising edge or the falling edge of the relationship curve is determined by linear fitting or spline fitting.

[0021] In one embodiment, after each step 2 is completed, the counting result is cleared to zero.

[0022] In another embodiment, after step 6, the method further includes:

[0023] Determine a fixed delay time difference between each channel, and perform phase adjustment on the parallel clock signal of each channel according to the fixed delay time difference each time power is turned on to remove the fixed delay time difference;

[0024] Alternatively, steps 1 to 5 are repeated for the output pulse signals of each channel to remove the fixed delay time difference.

[0025] The present invention also provides a clock phase alignment circuit for a high-speed serial transceiver, comprising:

[0026] A first D flip-flop, used for sampling a parallel clock signal of one of the to-be-processed channels of the high-speed serial transceiver under the drive of a reference clock signal, and outputting a sampling result, and for eliminating a metastable state, wherein the sampling result is a first value or a second value, the reference clock signal and the parallel clock signal are homologous clock signals, and a period of the reference clock signal is an integer multiple of a period of the parallel clock signal;

[0027] a counter, electrically connected to the first D flip-flop, configured to receive N sampling results obtained by the first D flip-flop within N reference clock signal cycles, determine the number of first values ​​in the N sampling results, and output a counting result;

[0028] A phase shifter is used to adjust the phase of the parallel clock signal multiple times, thereby adding different delay times to the parallel clock signal, so that the counter outputs multiple counting results with values ​​ranging from 0 to N, and is used to adjust the phase of the parallel clock signal according to the delay time corresponding to the rising edge or falling edge of the relationship curve after obtaining the relationship curve between the delay time and the corresponding counting result, so that the rising edge of the parallel clock signal of the channel is aligned with the rising edge of the reference clock signal.

[0029] In one implementation, between the first D flip-flop and the counter, further includes:

[0030] The second D flip-flop is used to eliminate the metastable state.

[0031] In one embodiment, it further comprises:

[0032] The controller electrically connected to the counter is used to control the counter to clear the counting result every N reference clock signal cycles.

[0033] In another embodiment, when it is necessary to superimpose signals of multiple channels to synthesize one signal, the first D trigger is also used to sample the output pulse signal of each channel separately, and the phase shifter is also used to adjust the phase of the output pulse signal of each channel to eliminate the fixed delay time difference between the channels.

[0034] It can be seen from the technical solution provided by the present invention that the present invention adopts a statistical counting rate method to find the alignment position, so that the alignment accuracy is high, and the alignment error can be much lower than the setup and hold time of the FPGA used and the random jitter of the clock involved. Compared with the existing method of using FPGA built-in alignment circuit, the solution provided by the present invention retains the ability of each channel to continue to adjust the delay as needed. In addition, compared with the existing solution of using TDC for phase alignment, the phase alignment circuit structure provided by the present invention is simpler and consumes less resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 It is a schematic diagram of the structure of a multi-channel high-speed serial transceiver;

[0037] Figure 2 is a flow chart of a clock phase alignment method provided by an embodiment of the present invention;

[0038] Figure 3 is a circuit structure diagram of a clock phase alignment circuit provided by an embodiment of the present invention;

[0039] Figure 4 It is a schematic diagram for controlling phase alignment according to counting results using a computer;

[0040] Figure 5It is a curve showing the relationship between the delay time and the counting result obtained in a specific embodiment. DETAILED DESCRIPTION

[0041] The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and specific implementation methods. It should be understood that these implementation methods are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to the present invention.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0043] refer to Figure 2 As shown, a clock phase alignment method for a high-speed serial transceiver is provided, comprising:

[0044] Step 1: Within N reference clock signal cycles, sample the parallel clock signal of one of the channels to be processed of the high-speed serial transceiver to obtain N sampling results, wherein the sampling result is a first value or a second value, the reference clock signal and the parallel clock signal are homologous clock signals, and the reference clock signal cycle is an integer multiple of the parallel clock signal cycle, and N>1.

[0045] Specifically, the parallel clock signal of the channel can be sampled by a D flip-flop, and the value of the sampling result is 0 or 1. For example, when the rising edge of the reference clock signal (TXUSRCLK2) is aligned with the low level of the parallel clock signal (XCLK), each sampling result is 0; when the rising edge of TXUSRCLK2 is aligned with the high level of XCLK, each sampling result is 1; when the rising edge of TXUSRCLK2 is close to the edge of XCLK, the sampling result is a random number between 0 and 1.

[0046] Step 2: Determine a counting result according to the number of first values ​​in the N sampling results.

[0047] Specifically, the number of values ​​1 in the N sampling results may be counted to obtain a counting result.

[0048] In addition, after completing step 2, the counting result is also cleared.

[0049] Step 3: Adjust the phase of the parallel clock signal multiple times to add different delay times to the parallel clock signal, and repeat steps 1 and 2 after each adjustment to obtain multiple counting results with values ​​from 0 to N, each adjustment corresponding to a different delay time.

[0050] Specifically, since the parallel clock signal (XCLK) is obtained by dividing the serial clock signal (SCLK), the phase of XCLK will change with the change of the SCLK phase. Therefore, the phase of SCLK can be changed by the phase interpolator in the FPGA, thereby adjusting the phase of XCLK. Of course, the adjustment of the XCLK phase can also be achieved by an independent phase interpolator or phase shifter.

[0051] Step 4: Draw a relationship curve between the delay time and the corresponding counting result.

[0052] Specifically, after obtaining a plurality of counting results with values ​​ranging from 0 to N, a relationship curve between the delay time and the corresponding counting results is obtained by linear fitting or spline fitting.

[0053] Step 5: According to the delay time corresponding to the rising edge or falling edge of the relationship curve, the parallel clock signal is phase-adjusted to align the rising edge of the parallel clock signal of the channel with the rising edge of the reference clock signal.

[0054] Specifically, the midpoint of the rising edge or the falling edge of the relationship curve, that is, the delay time corresponding to the counting result of 0.5N, may be selected to perform phase adjustment on the parallel clock signal.

[0055] Step 6: Repeat steps 1 to 5 for other channels to be processed, so that the parallel clock signals of each channel are aligned with the rising edge of the same reference clock signal, thereby aligning the rising edges of the parallel clock signals of each channel.

[0056] It can be seen that this solution can determine whether the edges of XCLK and TXUSRCLK2 are aligned by whether the D flip-flop samples 0 or 1. There are two factors that affect the alignment accuracy: the first factor is the random jitter of the clock signal; the second factor is the setup and hold time of the D flip-flop, which will also make the sampling result uncertain when the two clock edges are close. This solution can average out these uncertain factors by counting multiple counting results, thereby greatly improving the time accuracy of the alignment.

[0057] In addition, before step 1, the following steps may also be included:

[0058] It is determined whether there is a buffer zone between the parallel clock signal of the channel and the clock signal of the data encoding circuit in the high-speed serial transceiver.

[0059] When a buffer zone exists, the phase of the parallel clock signal is adjusted until the value of the half-full indication bit of the buffer zone changes from 0 to 1 for the first time.

[0060] Furthermore, after the above processing steps, there may still be a time difference between the data output by each channel. This time difference comes from the wiring differences between each channel and the routing differences within the FPGA. However, this time difference is fixed and will not change with system restart. In order to remove this fixed delay time difference, after step 6, the following steps may also be included:

[0061] The fixed delay time difference between the channels is determined by measuring with a high-performance oscilloscope, and each time the power is turned on, the parallel clock signals of the channels are phase-adjusted according to the fixed delay time difference to remove the fixed delay time difference.

[0062] In another embodiment, when it is necessary to superimpose the signals of multiple channels to synthesize one signal, the synthesized signal can be led back to the FPGA, and the previously sampled XCLK can be replaced by the led back signal. Each time the signal of one channel is turned on and the signals of other channels are set to a low level (0), and then the same alignment steps such as scan count as before are implemented to align the edge of the returned signal to the rising edge of TXUSRCLK2. After completing these steps for all channels in sequence, the superimposed signal will complete the phase alignment function. This process not only eliminates the random phase difference each time the power is turned on, but also eliminates the fixed time delay difference between the channels, and it is no longer necessary to measure the fixed delay time difference through a high-performance oscilloscope.

[0063] The present invention also provides a clock phase alignment circuit for a high-speed serial transceiver, the circuit comprising:

[0064] A first D flip-flop is used to sample the parallel clock signal of one of the channels to be processed of the high-speed serial transceiver under the drive of a reference clock signal, and output the sampling result, and to eliminate metastable states, wherein the sampling result is a first value or a second value, the reference clock signal and the parallel clock signal are homologous clock signals, and the period of the reference clock signal is an integer multiple of the period of the parallel clock signal.

[0065] The counter is electrically connected to the first D flip-flop, and is used to receive N sampling results obtained by the first D flip-flop within N reference clock signal cycles, determine the number of first values ​​in the N sampling results, and output a counting result.

[0066] A phase shifter is used to adjust the phase of the parallel clock signal multiple times, thereby adding different delay times to the parallel clock signal, so that the counter outputs multiple counting results with values ​​ranging from 0 to N, and is used to adjust the phase of the parallel clock signal according to the delay time corresponding to the rising edge or falling edge of the relationship curve after obtaining the relationship curve between the delay time and the corresponding counting result, so that the rising edge of the parallel clock signal of the channel is aligned with the rising edge of the reference clock signal.

[0067] Specifically, the phase shifter can be implemented using an independent phase interpolator, the counter can be implemented using an independent counter chip, and the D flip-flop can be implemented using an independent D flip-flop.

[0068] In addition, reference Figure 3 The circuit structure diagram shown in FIG. 1 may further include a second D flip-flop between the first D flip-flop and the counter for eliminating metastable state, and may further include a controller connected to the counter, the controller being used to control the counter to clear the counting result every N reference clock signal cycles. Figure 3 The phase-locked loop and frequency divider in the circuit can be realized by devices integrated in high-speed serial transceivers.

[0069] refer to Figure 4 As shown, the counting result is output to a computer to determine the phase value for adjusting the parallel clock signal. After the phase value is determined, the phase value is output so that the phase shifter adjusts the parallel clock signal according to the phase value.

[0070] In one embodiment, it further comprises:

[0071] An oscilloscope is used to measure the fixed delay time difference of each channel to be processed.

[0072] In one embodiment, it further comprises:

[0073] The data fitting module is used to determine the delay time corresponding to the rising edge or the falling edge of the relationship curve by fitting the relationship curve.

[0074] In another embodiment, when it is necessary to superimpose signals from different channels to synthesize a signal, the synthesized signal can be led back to the FPGA with the help of the circuit in the previous implementation method, and the XCLK sampled in the previous circuit can be replaced by the led back signal. Each time the signal of a channel is turned on and the signals of other channels are set to a low level (0), the output pulse signal of the turned-on channel is sampled by the first D flip-flop, and the phase of the output pulse signal of the channel is adjusted by the phase shifter, so as to implement the same alignment steps such as scan count as before, and align the returned signal edge to the rising edge of TXUSRCLK2. After completing the above processing for all channels in turn, the signal obtained after superposition will complete the phase alignment function. This process not only eliminates the random phase difference of each power-on, but also eliminates the fixed time delay difference between each channel, and it is no longer necessary to measure the fixed delay time difference through an oscilloscope.

[0075] An embodiment of the present invention further provides a high-speed serial transceiver, wherein the high-speed serial transceiver includes the above-mentioned clock phase alignment circuit.

[0076] An embodiment of the present invention further provides an FPGA, wherein the FPGA includes the above-mentioned clock phase alignment circuit.

[0077] An embodiment of the present invention further provides an FPGA, wherein the FPGA includes the high-speed serial transceiver.

[0078] In a specific embodiment, the serial clock signal SCLK is 5 GHz, the parallel clock signal XCLK is 312.5 MHz, and the adjustment step of the phase shifter is 1.5625 picoseconds (ps). The relationship curve between the delay time and the counting result obtained by the phase alignment circuit provided by the present invention is as follows: Figure 5 As shown, from Figure 5 It can be seen that the point corresponding to the count result of 0.5N in the curve is (565.8809, 500000), so the phase of the parallel clock signal is adjusted according to the delay time of 565.8809 picoseconds.

[0079] The above-mentioned various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments.

[0080] The above are only several embodiments of the present invention. Although the embodiments disclosed by the present invention are as above, the above contents are only embodiments adopted for facilitating understanding of the technical solution of the present invention, and are not used to limit the present invention. Any technician in the technical field to which the present invention belongs can make any modification and change in the form and details of the embodiments without departing from the spirit and scope disclosed by the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined by the attached claims.

Claims

1. A clock phase alignment method for a high-speed serial transceiver, characterized in that: include: Step 1: within N reference clock signal cycles, sampling the parallel clock signal of one of the to-be-processed channels of the high-speed serial transceiver to obtain N sampling results, wherein the sampling result is a first value or a second value, the reference clock signal and the parallel clock signal are homologous clock signals, and the reference clock signal cycle is an integer multiple of the parallel clock signal cycle, and N>1; Step 2: Determine a counting result according to the number of first values ​​in the N sampling results; Step 3: adjusting the phase of the parallel clock signal multiple times, thereby adding different delay times to the parallel clock signal, and repeating steps 1 and 2 after each adjustment to obtain multiple counting results with values ​​ranging from 0 to N, each adjustment corresponding to a different delay time; Step 4: Draw a relationship curve between the delay time and the corresponding counting result; Step 5: According to the delay time corresponding to the rising edge or the falling edge of the relationship curve, the parallel clock signal is phase-adjusted so that the rising edge of the parallel clock signal of the channel is aligned with the rising edge of the reference clock signal; Step 6: Repeat steps 1 to 5 for other channels to be processed to align the rising edges of the parallel clock signals of each channel.

2. The method according to claim 1, characterized in that: Before step 1, also include: Determining whether there is a buffer between the parallel clock signal of the channel and the clock signal of the data encoding circuit in the high-speed serial transceiver; When a buffer zone exists, the phase of the parallel clock signal is adjusted until the value of the half-full indication bit of the buffer zone changes from 0 to 1 for the first time.

3. The method according to claim 1, characterized in that After step 6, it also includes: Determine a fixed delay time difference between each channel, and perform phase adjustment on the parallel clock signal of each channel according to the fixed delay time difference each time power is turned on to remove the fixed delay time difference; Alternatively, steps 1 to 5 are repeated for the output pulse signals of each channel to remove the fixed delay time difference.

4. The method according to claim 1, characterized in that: The delay time corresponding to the midpoint of the rising edge or the falling edge of the relationship curve is selected to perform phase adjustment on the parallel clock signal.

5. The method according to claim 1, characterized in that The delay time corresponding to the rising edge or falling edge of the relationship curve is determined by linear fitting or spline fitting.

6. The method according to claim 1, characterized in that After each step 2 is completed, the counting result is cleared to zero.

7. A clock phase alignment circuit for a high-speed serial transceiver, characterized in that: include: A first D flip-flop, used for sampling a parallel clock signal of one of the to-be-processed channels of the high-speed serial transceiver under the drive of a reference clock signal, and outputting a sampling result, and for eliminating a metastable state, wherein the sampling result is a first value or a second value, the reference clock signal and the parallel clock signal are homologous clock signals, and a period of the reference clock signal is an integer multiple of a period of the parallel clock signal; a counter, electrically connected to the first D flip-flop, configured to receive N sampling results obtained by the first D flip-flop within N reference clock signal cycles, determine the number of first values ​​in the N sampling results, and output a counting result; a phase shifter, for adjusting the phase of the parallel clock signal multiple times, thereby adding different delay times to the parallel clock signal, so that the counter outputs multiple counting results with values ​​ranging from 0 to N, and for, after obtaining a relationship curve between the delay time and the corresponding counting result, adjusting the phase of the parallel clock signal according to the delay time corresponding to the rising edge or the falling edge of the relationship curve, so that the rising edge of the parallel clock signal of the channel is aligned with the rising edge of the reference clock signal; An oscilloscope, used to measure the fixed delay time difference of each channel to be processed; The data fitting module is used to determine the delay time corresponding to the rising edge or the falling edge of the relationship curve by fitting the relationship curve.

8. The circuit according to claim 7, characterized in that Between the first D flip-flop and the counter, it also includes: The second D flip-flop is used to eliminate the metastable state.

9. The circuit according to claim 7, characterized in that Also includes: The controller electrically connected to the counter is used to control the counter to clear the counting result every N reference clock signal cycles.

10. The circuit according to claim 7, characterized in that When it is necessary to superimpose signals from multiple channels to synthesize one signal, the first D trigger is also used to sample the output pulse signal of each channel separately, and the phase shifter is also used to adjust the phase of the output pulse signal of each channel to eliminate the fixed delay time difference between the channels.

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