Current-controlled MDAC for time-interleaved ADCs and related methods

Abstract

A current-controlled multiplying digital-to-analog converter (MDAC) and related methods for a time-interleaved analog-to-digital converter (ADC) are disclosed. In one embodiment, a circuit includes an MDAC having an amplifier that converts a voltage into an output current, a variable load that controls the output current from the amplifier based on a digital value, and a comparator array that receives the voltage and outputs the digital value to the variable load. The digital value represents at least a portion of the digital conversion of the voltage. Additionally, the circuit may include a phase-controlled current generator that receives the output current and generates time-interleaved currents, wherein each time-interleaved current is a sampled copy of the output current.

Description

Technical Field

[0001] The technical field relates to analog-to-digital conversion and related circuitry. Background Art

[0002] High-speed and high-accuracy analog-to-digital converters (ADCs) are used in many electronic architectures and solutions. For example, high-speed, high-accuracy ADCs are used in digitally modulated radar systems, communications systems, and other environments. The design of such ADCs is challenging due to the speed and accuracy requirements, particularly for low-power solutions. Furthermore, the design complexity of such ADCs increases significantly with semiconductor processing at 40 nanometer (nm) and below.

[0003] Typical high-speed (e.g., sampling rates of 1 gigahertz (GHz) and above) designs use time-interleaved stages to achieve a combined sampling rate that achieves the desired speed and throughput. However, the use of these time-interleaved stages is susceptible to errors in the sampling process, requiring tightly controlled clock skew between the time-interleaved stages and often requiring tuning delays between interleaved paths. In addition to skew, gain and offset errors in the time-interleaved state can also introduce spurious, unwanted noise. Sampling process errors and gain / offset errors can degrade the output spectrum of these previous time-interleaved ADC solutions. As a result, the digital conversion provided by these previous time-interleaved ADC solutions can suffer from decreased accuracy, thereby reducing overall system performance. Summary of the Invention

[0004] According to one aspect of the present invention, there is provided a circuit for analog-to-digital conversion, comprising:

[0005] A multiplying digital-to-analog converter (MDAC), the multiplying digital-to-analog converter comprising:

[0006] an amplifier coupled to convert a voltage received as an input into an output current;

[0007] a variable load coupled to the amplifier to control the output current, the variable load being dependent on a digital value; and

[0008] a comparator array coupled to receive the voltage as input and to have the digital value as output;

[0009] wherein the digital value represents at least a portion of a digital conversion of the voltage.

[0010] According to one or more embodiments, further comprising a phase-controlled current generator coupled to receive the output current and having as output a plurality of time-interleaved currents, each time-interleaved current being a sampled copy of the output current.

[0011] According to one or more embodiments, the phase-controlled current generator includes:

[0012] a plurality of current mirror circuits coupled to mirror the output current and output the time-staggered current;

[0013] a plurality of switches coupled to enable or disable the plurality of current mirror circuits; and

[0014] A plurality of phase-controlled clock pulses are coupled to control the switch.

[0015] According to one or more embodiments, each of the current mirror circuits includes a transistor coupled to mirror the output current and controlled by one of the plurality of phase-controlled clock pulses.

[0016] According to one or more embodiments, the amplifier includes an NMOS transistor having a gate coupled to the voltage through a differential amplifier, a drain coupled to the variable load, and a source coupled to provide the output current.

[0017] According to one or more embodiments, the variable load includes a variable resistance circuit having a plurality of selectable resistors.

[0018] According to one or more embodiments, the plurality of selectable resistors includes a plurality of resistors coupled to the amplifier through switches controlled by the digital value.

[0019] According to one or more embodiments, the comparator array has a plurality of trip voltages as inputs.

[0020] According to one or more embodiments, further included is a resistor tree coupled between two reference voltages and having as output the plurality of trip voltages from intervening nodes.

[0021] In accordance with one or more embodiments, each comparator provides a thermometer bit for the digital value based on at least one of the trip voltages.

[0022] According to another aspect of the present invention, there is provided a method for analog-to-digital conversion, comprising:

[0023] converting a voltage received by the amplifier into an output current;

[0024] controlling the output current with a variable load coupled to the amplifier, the variable load being dependent on a digital value; and

[0025] generating the digital value with a comparator array coupled to receive the voltage as an input;

[0026] wherein said converting, controlling and generating provides a multiplying digital-to-analog converter (MDAC); and

[0027] wherein the digital value represents at least a portion of a digital conversion of the voltage.

[0028] According to one or more embodiments, the method further includes generating a plurality of time-staggered currents based on the output current.

[0029] According to one or more embodiments, generating the plurality of time-staggered currents comprises:

[0030] generating a plurality of currents mirroring the output current using a plurality of current mirror circuits;

[0031] controlling the plurality of current mirror circuits using a plurality of switches to output the plurality of currents; and

[0032] A plurality of phase-controlled clock pulses are applied to control the switches.

[0033] According to one or more embodiments, each of the current mirror circuits includes a transistor coupled to mirror the output current controlled by one of the plurality of phase-controlled clock pulses.

[0034] According to one or more embodiments, the amplifier includes an NMOS transistor having a drain coupled to the variable load, and the method further includes applying the voltage to the gate of the NMOS transistor through a differential amplifier and providing the output current from the source of the NMOS transistor.

[0035] According to one or more embodiments, the controlling includes adjusting a variable resistance circuit having a plurality of selectable resistors to provide the variable load.

[0036] According to one or more embodiments, the adjusting includes applying a digital value to control a switch that selects which of the plurality of selectable resistors is included within the variable load.

[0037] According to one or more embodiments, further comprising providing a plurality of trip voltages as inputs to the comparator array.

[0038] According to one or more embodiments, further comprising generating the plurality of trip voltages from intervening nodes within a resistor tree, the resistor tree coupled between two reference voltages.

[0039] In accordance with one or more embodiments, each comparator provides a thermometer bit for the digital value based on at least one of the trip voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] It is noted that the drawings depict only example embodiments and are therefore not to be considered limiting of the scope of the invention. Elements in the drawings are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0041] Figure 1 is a block diagram of an example embodiment of an analog-to-digital converter (ADC) having a front-end multiplying digital-to-analog converter (MDAC) and an array of time-interleaved current-controlled ring oscillators (ICRO) sub-ADCs.

[0042] Figure 2 yes Figure 1 The global sampling rate (f S ) operation.

[0043] Figure 3 yes Figure 1 A circuit diagram of an example embodiment of a voltage-current multiplying digital-to-analog converter (VIMDAC) that generates a residual output current and an N-bit digital value as part of an overall digital conversion output.

[0044] Figure 4 yes Figure 1 A phase-controlled current generator based on residual current output time-staggered current and Figure 1 A circuit diagram of an example embodiment of a time-interleaved ADC circuit that generates an M-bit digital value as part of an overall digital conversion output.

[0045] Figure 5A -B provides an example embodiment of a Robertson plot implemented by an example implementation of a VIMDAC.

[0046] Figure 6 yes Figure 1 and Figure 3 Circuit diagram of an example differential embodiment of a current-controlled MDAC (VIMDAC).

[0047] Figure 7 Yes Receive Figure 6 Circuit diagram of an example differential embodiment of a comparator array with different trip voltages of an embodiment.

[0048] Figure 8 Is receiving from Figure 6 Circuit diagram of an example differential embodiment of a phase-controlled current generator for the differential residual current of a current-controlled MDAC (VIMDAC).

[0049] Figure 9A is a timing diagram of an example embodiment of a phase-controlled clock pulse that may be generated and output to Figure 8 The phase-controlled current generator shown.

[0050] Figure 9B A timing diagram is provided for an example embodiment of the operation of a phase-controlled current generator to generate time-staggered currents.

[0051] Figure 10A is a flow chart of an example embodiment of a calibration process that may be performed by calibration logic of the multi-stage analog-to-digital converter embodiments described herein.

[0052] Figure 10B Is implemented Figure 10A A block diagram of an example embodiment of calibration logic for a calibration process.

[0053] Figure 11A -B is a representative plot of the ADC output relative to the ADC input before and after applying the calibration process of Figure 10. DETAILED DESCRIPTION

[0054] Disclosed are systems and related methods for a time-interleaved analog-to-digital converter (ADC) based on an MDAC and related methods. In one embodiment, a multiplying digital-to-analog converter (MDAC) is used to convert an input voltage into a current and generate an N-bit digital value that provides the most significant bit (MSB) portion of the digital conversion. This initial conversion reduces the resolution required for additional analog-to-digital conversion circuitry. The current from the MDAC is then sampled to generate a time-interleaved current, which is provided to an array of current-controlled ring oscillators (ICROs) that provide additional M-bit digital values. This multi-stage conversion architecture offers efficiency and accuracy advantages over previous solutions that are subject to skew, gain, and offset errors. In other embodiments, efficient calibration techniques are provided that rely on an M-bit digital value and an operating region determined by the N-bit digital value to generate calibration correction values. These calibration techniques provide additional efficiency improvements. The embodiments described herein can be used in a wide range of environments, including digitally modulated radar systems, vehicle networking, or other environments. When utilizing the techniques described herein, various features and variations can be implemented.

[0055] For the disclosed embodiments, the time-interleaved ADC is based on a time-interleaved current-controlled ring oscillator (ICRO) sub-ADC with a front-end MDAC stage. The front-end MDAC stage provides a portion of the digital conversion (e.g., N bits), while the time-interleaved ICRO sub-ADC array provides the remaining portion of the digital conversion (e.g., M bits). In part, the disclosed embodiments provide one or more of the following features or advantages:

[0056] Current-mode solutions provide improved isolation;

[0057] The current range is divided into smaller parts, and each of the multiple ICRO sub-ADCs operates on these smaller parts, thereby improving linearity;

[0058] The initial N-bit conversion is provided by the MDAC (e.g., 2.5 bits), which reduces the N-bit linearity requirement on the ICRO sub-ADC array.

[0059] Front-end MDAC allows easy calibration of nonlinearities;

[0060] Averaging the outputs of the ICRO sub-ADCs to provide scalability and an easily achievable performance vs. throughput tradeoff among the sub-ADCs;

[0061] Pseudo-differential embodiments may be implemented to provide additional improvements in resolution; and

[0062] Other features and advantages.

[0063] For one embodiment, the ADC circuitry can be implemented using a fin field effect transistor (FinFET) process and a complementary metal oxide semiconductor (CMOS) design. Low power operation can be achieved at core voltages of 0.8 volts and below. Additionally, integrated circuits implementing these time-interleaved ADCs can be fabricated using 16 nm FinFET technology. For one example embodiment, a time-interleaved ADC is disclosed that operates at a frequency of four (4) gigahertz (GHz) or greater while providing ten (10) bits or greater of digital conversion. Additional or different features and variations may also be implemented.

[0064] The disclosed embodiments will now be described in more detail with reference to the accompanying drawings. Figure 1-4 A diagram of an example embodiment of a time-interleaved ADC is provided. Figure 5A -B provides an example embodiment of a Robertson diagram that can be implemented by the MDAC described herein. Figure 6-8 9A-B provide more detailed circuit diagrams and timing diagrams for the MDAC and the generation of time-interleaved currents applied to the ICRO sub-ADC array. Figure 10A 11A-B and 11A-B provide more detailed diagrams of efficient calibration techniques for multi-stage analog-to-digital converters.Additional or different embodiments may also be implemented.

[0065] See first Figure 1, provides a block diagram of an example embodiment of an ADC 100 having a front-end MDAC 108, a phase-controlled current generator 114, and a time-interleaved ICRO sub-ADC array 120. The ADC 100 receives an input signal (V IN ) 102, and outputs a digitally converted output 132 having N+M bits. For one embodiment, the input signal 102 is a high frequency signal including one or more frequency components of 1 GHz or above, and the converted digital output 132 is 10 bits or higher. Variations may be implemented.

[0066] The input signal 102 is received by a sample-and-hold (S / H) circuit 104. The S / H circuit 104 uses a global sampling rate (f S ) sampling clock 105 to sample the input signal 102. For one embodiment, an S / H circuit is implemented with capacitors coupled to switches for switched capacitor operation. The S / H circuit 104 helps prevent errors caused by skew because only one sampling clock 105 is used to sample the input signal 102, as opposed to multiple sampling clocks in previous solutions. Therefore, subsequent time interleaving of the embodiment 100 is not affected by the skew of this sampling clock 105 because the input signal 102 has already been sampled. Figure 2 As further shown in FIG, the sample-and-hold output voltage (V) 106 may also be buffered before being routed to the input of a linear voltage-current multiplying digital-to-analog converter (VIMDAC) 108.

[0067] The VIMDAC 108 provides the output current (I) 112 and the first N bits of the digitally converted output 132 provided by the ADC 100. Figure 3 In more detail, the VIMDAC 108 first converts the output voltage (V) 106 from the S / H circuit 104 into the current domain and then converts this current into a residual output current (I) 112 that is provided to the phase-controlled current generator 114. The voltage-current relationship of the residual current 112 is determined by the bit and full-scale input range of the time-interleaved ADC circuit 116 triggered within the VIMDAC 108. The N-bit digital value 110 from the VIMDAC 108 provides the first N bits of the overall digital conversion output 132 to the ADC 100.

[0068] The phase-controlled current generator 114 receives the output current (I) 112 from the VIMDAC 108 and outputs a time-interleaved current 115 to the ICRO sub-ADC array 120 within the time-interleaved ADC circuit 116. Figure 4 As described in more detail in , current 112 is effectively sampled and maintained using an array of phase-controlled clock pulses and switched current circuits to generate a time-interleaved current 115 .

[0069] Phase-controlled copies of current 112 are provided as time-interleaved current 115 to ICRO sub-ADC array 120. Figure 4 As shown in more detail in , the individual ICRO sub-ADCs within the array 120 receive these phased copies of the current 112 in a time-interleaved manner based on phased clock pulses. The digital output values ​​of each of the sub-ADCs are then averaged. The averaged digital output values ​​are then combined together to form an M-bit digital value 130. This combined M-bit digital value 130 is then combined with the N-bit digital value 110 from the VIMDAC 108 to form an N+M-bit digital conversion output 132 of the ADC 100. As further described herein, nonlinearities and gain errors present within the ADC signal path can be estimated and corrected in the digital domain by a calibration routine using a calibration sub-ADC 128 and calibration logic 140. The calibration sub-ADC 128 generates a calibration value 129 based on the current 112. The calibration logic 140 then generates a correction value 141 for the combiner 124 based on this calibration value 129 and the N-bit digital value 110. Additionally, as described with reference to Figure 10A As described in greater detail, calibration logic 140 may also operate without calibration sub-ADC 128 to generate correction value 141 based on M-bit digital value 130 and N-bit digital value 110. Other variations may also be implemented while still utilizing the techniques described herein.

[0070] Figure 2 is a circuit diagram of an example embodiment of the S / H circuit 104. The input signal (V IN ) 102 is coupled to a transmission gate 202 controlled by a sampling clock 105 so as to transmit the data at the global sampling rate (f S ) samples the input signal 102. For example, the transmission gate 202 may be a CMOS transmission gate that includes a p-channel metal oxide semiconductor (PMOS) transistor and a p-channel metal oxide semiconductor (NMOS) transistor controlled by the sampling clock 105 and an inverted version of the sampling clock 105. The gate of the NMOS transistor may be coupled to the sampling clock 105, while the gate of the PMOS transistor may be countered to the inverted version of the sampling clock 105. When the sampling clock 105 is at a high logic level, the input signal 102 is transmitted by the transmission gate 202 to the node 204. When the sampling clock 105 is at a low logic level, the input signal 102 is isolated from the node 204 by the transmission gate 202. A capacitor 206 coupled between the node 204 and ground stores a voltage proportional to the amplitude of the input signal 102. This stored voltage is buffered by a buffer 208, which may be a CMOS buffer, and the output voltage (V) 106 is output at a global sampling rate (f) based on the sampling clock 105. S ) provides sampling voltage.

[0071] Figure 3 1 is a circuit diagram of an example embodiment of a VIMDAC 108. The VIMDAC 108 receives an output voltage (V) 106 and generates a current (I) 112 and an N-bit digital value 110. For the illustrated embodiment, the output voltage 106 is received by an array 314 of different comparators 315, 316, 317, ..., 318, which compare the voltage 106 to different trip voltages 330. The trip voltage 330 includes trip voltage levels 325, 326, 327, ..., 328 coupled to the comparators 315, 316, 317, ..., 318, respectively. The outputs of these comparators 315, 316, 317, ..., 318 provide a thermometer-coded output representing the N-bit digital value 110. For example, the following embodiment (N=3 and six (6) comparators) is used to achieve 2.5-bit resolution. The output of the comparator represents a thermometer coded value, which in turn represents binary values ​​of 000 to 110. The following table provides an example embodiment of the relationship between these values ​​to achieve 2.5 bits of resolution.

[0072] Table - Thermometer Coded to Binary Relationship (2.5 Bit Resolution)

[0073]

[0074] Replay Figure 3 , comparator 315 compares voltage 106 to transition voltage level 325 and provides a most significant thermometer coded value. Comparator 316 compares voltage 106 to transition voltage level 326 and provides a second most significant thermometer coded value. Comparator 317 compares voltage 106 to transition voltage level 327 and provides a second most significant thermometer coded value. This continues depending on the number of bits selected for N and the resolution achieved. The last comparator 318 compares voltage 106 to transition voltage level 328 and provides a least significant thermometer coded value. N-bit digital value 110 is a binary value based on the thermometer coded values ​​generated by the outputs of comparators 315, 316, 317, ..., 318. N-bit digital value 110 provides the first N bits of the digital converted output 132 provided by ADC 100.

[0075] For example, the N-bit digital value 110, as represented by the thermometer-coded values ​​output by the comparators 315, 316, 317, ..., 318, is also used as a control word applied to the variable resistance circuit 312. For example, the variable resistance circuit 312 can be implemented as a resistor load array, where the resistor load array is enabled or disabled using switches controlled by the N-bit digital value 110. The variable resistance circuit 312 is coupled between the drain of the NMOS transistor 310 and ground. The source of the NMOS transistor 310 is connected to the ground. Figure 1 Phase-controlled current generator 114 is shown providing current 112. The gate of NMOS transistor 310 is controlled by differential amplifier 308. Differential amplifier 308 receives a common-mode (CM) reference voltage 306 and a voltage input 304 from variable tuning resistor 302. Variable tuning resistor 302 receives voltage 106 and provides voltage input 304 to differential amplifier 308. Variable tuning resistor 302 can be implemented as a plurality of selectable resistors controlled by a digital input. The drain of NMOS transistor 310 is also coupled to voltage input 304 of differential amplifier 308.

[0076] In operation, the output current 112 depends on the variable resistance circuit 312 and the voltage 106, which in turn depends on the amplitude of the input signal 102. The output current 112 also depends on the N-bit digital value 110 that controls the variable resistance circuit 312 (e.g., as represented by the thermometer-coded values ​​output by the comparators 315, 316, 317, ..., 318). As described in more detail below, the resistance of the variable resistance circuit 312 is determined by the outputs from the comparators 315, 316, 317, ..., 318, and this variable resistance generates a current 112 that follows the voltage / current (V / I) equation for each region of the Robertson diagram described below. The outputs from the comparators 315, 316, 317, ..., 318 effectively determine which region of the Robertson diagram is used, and the resistance is set based on the voltage-current (V / I) relationship of the region indicated by the comparator output word. Different regions of the Robertson diagram represent different values ​​of the N-bit digital value 110.

[0077] Figure 4 yes Figure 11 is a circuit diagram of an example embodiment of a phase-controlled current generator 114 and a time-interleaved ADC circuit 116. The output current (I) 112 is received by the phase-controlled current generator 114, and the phase-controlled current generator 114 provides time-interleaved currents 420, 422, ..., 424 that are copies of the current 112 to the time-interleaved ADC circuit 116. The time-interleaved ADC circuit 116 includes an ICRO sub-ADC array 120 that receives the time-interleaved currents 420, 422, ..., 424. The time-interleaved ADC circuit 116 outputs an M-bit digital value 130. Note that the output current 112 is implemented using PMOS transistors. Figure 4 0047] An example embodiment of the phase current generator 114 in FIG. The phase current generator 114 may also be implemented using NMOS transistors or a combination of PMOS and NMOS transistors. Other variations may also be implemented.

[0078] Referring to the phase-controlled current generator 114 in more detail, the current 112 is coupled to a node 402. The node 402 is coupled to the drain and gate of a PMOS transistor 404, such that the PMOS transistor 404 operates as a diode-connected device within a current mirror. The source of the PMOS transistor 404 is coupled to a node 412, which is coupled to a supply voltage (V 电源). The sources of PMOS transistors 405, 406, ..., 407, 408 are also coupled to node 412 and the power supply voltage. The drains of PMOS transistors 405, 406, ..., 407, 408 are coupled to provide time-interleaved currents 420, 422, ..., 424 to the time-interleaved ADC circuit 116. The gates of PMOS transistors 405, 406, ..., 407, 408 are coupled to node 402 via switches 415, 416, ..., 417, 418. These switches 415, 416, ..., 417, 418 are controlled by time-interleaved phase-controlled clock pulses θ1, θ2, ..., θX, θCal. When turned "on," these switches 415, 416, ..., 417, 418 connect their gates to node 402, thereby turning on PMOS transistors 405, 406, ..., 407, 408. When turned "on," PMOS transistors 405, 406, ..., 407, 408 operate as current mirrors relative to PMOS transistor 404 and generate copies of current 112 on their respective drains. In this manner, PMOS transistors 405, 406, ..., 407 and time-interleaved phase-controlled clock pulses θ1, θ2, ..., θX (i.e., X different phase-controlled clock pulses) are used to provide copies of current 112 as time-interleaved currents 420, 422, ..., 424 to ICRO sub-ADC array 120. PMOS transistor 408 and phase-controlled clock pulse θCal are used in calibration mode to provide current 418 to calibration sub-ADC 128.

[0079] Referring to the time-interleaved ADC circuit 116, ICRO sub-ADCs 430, 432, ..., 434 receive phase-controlled clock pulses θ1, θ2, ..., θX as phase-sampled versions of the residual output current (I) 112 from the VIMDAC 108. In effect, each of these sub-ADCs 430, 432, ..., 434 uses a sample-and-hold and current-converted version of the input signal 102 that has a different phase relationship than the original signal. The digital values ​​output from the sub-ADCs 430, 432, ..., 434 are then provided to averaging circuits 436, 438, ..., 440, respectively. For example, the averaging circuits 436, 438, ..., 440 may include logic circuits and registers that accumulate the digital values ​​from the sub-ADCs 430, 432, ..., 434 and average them over a selected time period to provide averaged digital output values ​​437, 439, ..., 441 to the combiner 124. This time period depends on the global ADC sampling rate (f S), the sampling rate selected for the sub-ADC, and the number of channels in the time-interleaved sub-ADC array 120 (i.e., X different sub-ADCs). Each of the averaged digital output values ​​437, 439, ..., 441 may provide, for example, M / X bits of the combined M-bit digital value 130 output by the combiner 124.

[0080] The operation of sub-ADCs 436, 438, ..., 440 can be calibrated using calibration sub-ADC 128. During calibration mode, a copy of current 112 is provided as calibration current 418 to ICRO sub-ADC 452 within calibration sub-ADC 128 via PMOS transistor 408. Averaging circuit 454 receives the digital value output from ICRO sub-ADC 452 and provides an averaged digital value 455 to adder 456. Digital calibration value 129 is then output to calibration (CAL) logic 140. Calibration logic 140 may also receive N-bit digital value 110 and M-bit digital value 130. During calibration mode, calibration logic 140 compares this digital calibration value 129 to a desired value and generates a digital correction value 141. Digital correction value 141 is provided to combiner 124 so that calibration adjustments can be made.

[0081] The calibration logic 140 logic can also operate without the calibration sub-ADC 128 to generate calibration correction values ​​141, as shown in FIG. Figure 10A -B is described in more detail. For this calibration embodiment, calibration logic 140 determines calibration correction values ​​141 for different operating regions of VIMDAC 108. As described in more detail below, calibration logic 140 determines the operating regions based on N-bit digital values ​​110 and then tracks the maximum and minimum values ​​of M-bit digital values ​​130 within these different regions. Calibration correction values ​​141 are then generated for each operating region based on the difference between these maximum and minimum values.

[0082] Also like Figure 4As shown, nonlinearity correction can be used to adjust the operation of the time-interleaved ADC circuit 116 via adders 442, 444, ..., 446, 456 coupled between the averaging circuits 436, 438, ..., 440, 454 and the combiner 124. Bus 448 can provide the outputs from the ICRO sub-ADCs 436, 438, ..., 440, 452 to a nonlinearity correction controller 450. Controller 450 processes the outputs, for example, by comparing them to desired operating parameters, and generates corrections to be applied as correction factors. These corrections can be applied to adders 442, 444, ..., 446, 456 via bus 449 to adjust the averaged digital values ​​437, 439, ..., 441, 455 before they are provided to the combiner 124. The correction can be, for example, a positive or negative digital value added to the average digital values ​​437, 439, ..., 441, 455. A different correction can also be generated and provided to each of the adders 442, 444, ..., 446, 456. Calibration adjustments (such as those made by calibrating the correction value 141) can also be applied through operation of the nonlinearity correction controller 450. In this way, the average digital values ​​437, 439, ..., 441, 455 are adjusted to correct for nonlinearities and gain errors present along the signal conversion path.

[0083] ICRO sub-ADCs 430, 432, ..., 434, 452 may be implemented as current-starved ring oscillators that operate as first-order sigma-delta ADCs and operate at a global sampling rate (f S ) is sampled at a rate of . U.S. Patent No. 8,542,138 provides an example embodiment of a current controlled ring oscillator (ICRO) and related circuitry that can be used in the high speed ADC architecture of the disclosed embodiments. The operating principle of the ICRO ADC described therein is that the frequency of the ring oscillator can be directly related to the input voltage of the signal being converted. A digital representation of the applied input voltage is obtained by decoding the various phases of the ring oscillator into an equivalent digital code that relates the input voltage to the output decoded phase. This phase is then digitally differentiated to obtain a representation of the ICRO frequency. The ring oscillator is a current driven, current hungry oscillator, and therefore the correlation with the input is achieved using a signal running through a transconductance operation. U.S. Patent No. 8,542,138 is incorporated herein by reference in its entirety.

[0084] For one embodiment, the sampling rate of ICRO sub-ADCs 430, 432, ..., 434, 452 is 1 GHz or greater. For another embodiment, the sampling rate is 4 GHz or greater. Different sampling rates, including low frequency sampling rates, may also be used. Note that the sampling rate of sub-ADCs 430, 432, ..., 434, 452 is preferably greater than the global sampling rate (f) of ADC 100 based on global sampling clock 105. S ), as this allows for adjustment of the selected time period for averaging. For example, increased averaging within averaging circuits 436, 438, ..., 440, 454 can be implemented by increasing the selected time period. This increased averaging of each time-interleaved current 420, 422, ..., 424 provides additional accuracy in the digital implementation of the average value. This adjustment of the sampling rate can be achieved in part, for example, by reducing the number of ring oscillator stages used within ICRO sub-ADCs 430, 432, ..., 434, 452. For one embodiment, a 62-stage ring oscillator operating at a sampling rate of 1 GHz is used for each of ICRO sub-ADCs 430, 432, ..., 434, 452. For another embodiment, a sampling rate of 4 GHz is achieved using 14 stages (i.e., a 4x reduction). One advantage of this reduction in the number of stages is a 4x reduction in digital overhead in terms of die area and complexity. One disadvantage of this reduction in the number of stages is that the digital logic must now operate at the higher 4 GHz rate, which is more difficult to implement. However, these sampling rates of 4 GHz or above can be achieved using 16 nm FinFET processes or other advanced semiconductor processing.

[0085] During operation, the ICRO sub-ADCs 430, 432, ..., 434 are less susceptible to timing skew and inaccuracies in the time-interleaved channels provided by the ICRO sub-ADCs 430, 432, ..., 434 because the global sample-and-hold provided by the S / H circuit 104 eliminates the need to sample at each of the ICRO sub-ADCs 430, 432, ..., 434. Figure 3 Using a redundant signed digital topology in the illustrated VIMDAC 108, a simple calibration algorithm can be implemented in the digital domain to correct for nonlinearity and gain errors. Other advantages can also be realized.

[0086] like Figure 3 As further shown in FIG. 1 , the sample-and-hold output voltage (V) 106 is converted to a current by a resistor-based linear VIMDAC circuit 108. The resulting residual current (I) 112 from the VIMDAC 108 is then measured using Figure 4The array of switch circuits 415, 416, ..., 417 shown samples and holds. For one embodiment, this sampling by phase-controlled clock pulses θ1, θ2, ..., θX is performed in The update rate occurs, where f S For another embodiment, the global sampling rate (f S ) is 4 GHz, and sixteen (16) sub-ADCs are used in the array 120. Note again that the number of interleaved sub-ADCs, as well as the sampling rates of the sub-ADCs, is completely flexible. Thus, the update rate of the time-interleaved residual currents 420, 422, ..., 424 is not limited to a particular value and will vary based on the selected sampling rate and the accuracy desired for the ADC 100. Furthermore, in the case of averaging the converted digital values ​​437, 439, ..., 441 from the sub-ADCs 430, 432, ..., 434 to generate the averaged digital values ​​437, 439, ..., 441, there is considerable flexibility in increasing the averaging to further improve the accuracy of the sub-ADCs 430, 432, ..., 434 at the expense of reduced throughput. Additional variations are possible while still utilizing the techniques described herein.

[0087] Figure 5A An example embodiment 500 of a Robertson diagram implemented by an example embodiment of the VIMDAC 108 is provided. A Robertson diagram is a diagram used to represent a redundant signed digital topology commonly found in switch-capacitor Nyquist ADCs. For the example 500, relative to Figure 3 The vertical axis 502 represents the residual output current (I) 112 and the horizontal axis represents the sample-and-hold voltage output (V) 106. A nominal reference voltage (Vref) is used to generate the reference voltage for Figure 3 The different trip voltage levels 325, 326, 327, ..., 328 of the comparators 315, 316, 317, ..., 318 of the array 114 are shown. Specifically, six (6) different trip voltage levels 325, 326, 327, ..., 328 are provided:

[0088] -5Vref / 8, -3Vref / 8, -Vref / 8, Vref / 8, 3Vref / 8, and 5Vref / 8. The medium voltage (VMID) is set to Vref. As shown in the figure, these transition voltage levels provide different output regions for the output current 112. Specifically, the first region 506 represents a 3-bit binary (b) output of 000. The next region 508 represents a binary output of 001. The next region 510 represents a binary output of 010. The next region 512 represents a binary output of 011. The next region 514 represents a binary output of 100. The next region 516 represents a binary output of 101. The last region 518 represents a binary output of 110. Note that for this embodiment, the different trip voltage levels 325, 326, 327, ..., 328 are referenced to Vref such that their values ​​referenced to ground are Vref-5Vref / 8, Vref-3Vref / 8, Vref-Vref / 8, Vref+Vref / 8, Vref+3Vref / 8, and Vref+5Vref / 8.

[0089] For one embodiment, a fully differential solution is implemented using embodiment 500. For two pseudo differential paths, the resulting output current range enables one or more subsequent ICRO sub-ADCs to be within 0.5*f S to 1.5*f S oscillates within a frequency range of 1 / 4. This is achieved, in part, by providing a two-fold (2X) gain in the VIMDAC 108 using the differential amplifier 308. While this gain increase would ideally translate into a 6 dB improvement in signal-to-noise ratio, this improvement is reduced in cases where the individual ICRO sub-ADCs have uncorrelated quantization noise. For example, in the case of two individual ICRO sub-ADCs, this improvement translates to only a 3 dB improvement for the 2X gain of the VIMDAC 108.

[0090] Figure 5B An additional example embodiment 550 of a Robertson diagram implemented by another embodiment of a VIMDAC is provided. For embodiment 550, relative to Figure 3 The vertical axis 502 represents the residual output current (I) 112 and the horizontal axis represents the sample-and-hold voltage output (V) 106 of the VIMDAC 108. Again, the nominal reference voltage (Vref) is used to generate the output voltage for Figure 3, 318 of the array 114. Specifically, six (6) different trip voltage levels 325, 326, 327, ..., 328 are provided: -5 Vref / 8, -3 Vref / 8, -Vref / 8, Vref / 8, 3 Vref / 8, and 5 Vref / 8. The medium voltage (VMID) is set to -4 Vref / 8. As shown, these trip voltage levels provide different output regions for the output current 112. Specifically, the first region 556 represents a 3-bit binary (b) output of 000. The next region 558 represents a binary output of 001. The next region 560 represents a binary output of 010. The next region 562 represents a binary output of 011. The next region 564 represents a binary output of 100. The next region 566 represents a binary output of 101. The last region 568 represents the binary output 110. Note that for this embodiment, the different trip voltage levels 325, 326, 327, ..., 328 are referenced to Vref such that their values ​​referenced to ground are Vref-5Vref / 8, Vref-3Vref / 8, Vref-Vref / 8, Vref+Vref / 8, Vref+3Vref / 8, and Vref+5Vref / 8.

[0091] Regarding current levels, the current range in region 556 is from current level 570 to current level 574. The current range in regions 558, 560, 562, 564, and 566 is from current level 572 to current level 574. The current range in region 568 is from current level 572 to current level 576. For one embodiment associated with the equations derived below, current level 570 is represented by the following equation: Ires = Ic + Ic / 2. Current level 572 is represented by the following equation: Ires = Ic + Ic / 4. Current level 574 is represented by the following equation: Ires = -(Ic + Ic / 4). Current level 576 is represented by the following equation: Ires = -(Ic + Ic / 2). When the N-bit digital value 110 in operating region 556 is "000," the output current is represented by the following equation: Ires = (3*Ic / 2) - (M*Vin). When the N-bit digital value 110 in the operating region 558 is "001," the output current is represented by the following equation: Ires = (4*Ic / 2) - (M*Vin). When the N-bit digital value 110 in the operating region 560 is "010," the output current is represented by the following equation: Ires = (5*Ic / 2) - (M*Vin). When the N-bit digital value 110 in the operating region 562 is "011," the output current is represented by the following equation: Ires = (6*Ic / 2) - (M*Vin). When the N-bit digital value 110 in the operating region 564 is "100," the output current is represented by the following equation: Ires = (7*Ic / 2) - (M*Vin). When the N-bit digital value 110 in the operating region 566 is "101," the output current is represented by the following equation: Ires = (8*Ic / 2) - (M*Vin). When the N-bit digital value 110 in the operating region 568 is "110," the output current is represented by the following equation: Ires = (9*Ic / 2) - (M*Vin). Note that the vertical axis 502 is positioned at Vin = -4*Vref / 8, while the horizontal axis 504 is positioned at Ires = Ic. Also, note that "M" represents the slope of the line, while "Ic" represents the center current of the ICRO sub-ADCs 430, 432, ..., 434. For one embodiment, the slope is four (e.g., M = 4). Other variations and Robertson diagrams may also be implemented while still utilizing the techniques described herein.

[0092] Now see Figure 6 、 7, 8, and 9A-B, the circuit diagrams and timing diagrams provide an example differential embodiment of the VIMDAC 108 and the phase-controlled current generator 114. This example embodiment can be used in implementations operating at high frequencies (e.g., 4 GHz) and providing 10-bit resolution using a core supply voltage of one volt or less. This example embodiment can be expanded to higher bit resolutions as the number of comparators used increases. In addition, the accuracy of the comparators can be adjusted based on the number of comparators used and the associated trip points for different operating regions.

[0093] As described in further detail below, an exemplary embodiment provides a 2.5-bit VIMDAC comprising six (6) comparators operating at a sampling rate of 4 GHz. A resistor array controlled by switches coupled to the comparator outputs is implemented for a variable resistance circuit 312 and sets the residual current 112. The operation of this switched resistor array as a variable resistance circuit 312 thereby sets the center current of the sub-ADC array 120 to the residual current 112 based on the digital value 110, which for this exemplary embodiment is 6 bits. The variable resistance circuit 312 essentially operates as a digital-to-analog converter (DAC). An internal transistor amplifier 310 provides a summing point for the resistor array, sums the currents from the resistor array, and provides the residual current 112 to a phase-controlled current generator 114. A sample-and-hold switched current mirror circuit is used as the phase-controlled current generator 114 to create a phase-controlled sample-and-hold copy (θ1, θ2, ..., θX) of the residual current 112, which is sent to a time-interleaved ADC circuit 116.

[0094] The goal of this differential embodiment is to provide a method for implementing Figure 5B The VIMDAC of the current mode implementation of the modified Robertson diagram is shown. In this way, the scaled version and the sample-and-hold phase-controlled version of the residual current 112 are output to the time-interleaved sub-ADC array 120. Figures 5A-5B In the example, the output current is the dependent variable and the input voltage is the independent variable. A set of input voltage dependent residual current replicas 115 are generated, which enable the subsequent ICRO sub-ADC to obtain the current from 0.5*F S Change to 1.5*F S. This current change translates to 0.5*Ic to 1.5*Ic (i.e., Ic±Ic / 2), where Ic is the center current of the ICRO sub-ADC. The center current is the input current that allows the ring oscillator within the ICRO sub-ADC to oscillate at the same frequency as the sampling frequency of the ICRO sub-ADC. A differential solution is shown, and the voltage 106 received by the VIMDAC 108 is converted to a residual current 112 to create the required sample-and-hold replica 115 of the residual current 112 in order to control the ICRO sub-ADC array 120. It should also be noted that additional features and variations can also be implemented while still utilizing the techniques described herein.

[0095] Now see Figure 6 , provides a circuit diagram of an example differential embodiment of a VIMDAC 108. The VIMDAC 108 receives a voltage (V) 106 as a positive input voltage (VIN_P) 106A and a negative input voltage (VIN_N) 106B. The VIMDAC 108 generates an output residual current (I) 112 as differential outputs 112A and 112B. An N-bit digital value 110 from a comparator array 314 is used as a control word for a variable resistor circuit 312. For this embodiment, the N-bit digital value 110 is a 6-bit digital value provided to the variable resistor circuit 312 as thermometer bits (T1-T6) and inverted versions of these thermometer bits (bT1-bT6). The variable resistor circuit 312 is implemented as an array of resistor loads (R1-R6) and uses switches controlled by the thermometer bits (T1-T6) and inverted thermometer bits (bT1-bT6) to enable or disable the resistor loads (R1-R6). The positive resistor (RP) and the negative resistor (RN) are always enabled within the resistor array. The variable resistor circuit 312 has a positive output 604A and a negative output 604B. The resistor load (R1-R6) array is coupled between ground and outputs 604A / 604B based on the switching state, as controlled by the thermometer bits (T1-T6) and the inverted thermometer bits (bT1-bT6). Thus, a variable resistive load is provided based on the digital value 110.

[0096] The drain of positive-side NMOS transistor 310A is coupled to positive-side output 604A from variable resistor circuit 312. The source of NMOS transistor 310A provides positive-side residual current 112A, which is output to phase-controlled current generator 114. The gate of NMOS transistor 310A is controlled by positive-side differential amplifier 308A. Positive-side differential amplifier 308A receives common-mode (CM) reference voltage 306A and positive-side voltage 106A via variable tuning resistor 302A. Variable tuning resistor 302A can be implemented as a plurality of selectable resistors controlled by a digital input, or as a fixed input resistor, if desired. The drain of transistor 310A is also coupled to output 304A of variable tuning resistor 302A and an input of positive-side differential amplifier 308A.

[0097] The drain of the negative-side NMOS transistor 310B is coupled to the negative-side output 604B from the variable resistor circuit 312. The source of the NMOS transistor 310B provides the negative-side residual current 112B output to the phase-controlled current generator 114. The gate of the NMOS transistor 310B is controlled by the negative-side differential amplifier 308B. The negative-side differential amplifier 308B receives the common-mode (CM) reference voltage 306B and the negative-side voltage 106B via the variable tuning resistor 302B. The variable tuning resistor 302B can be implemented as a plurality of selectable resistors controlled by a digital input, or as a fixed input resistor if desired. The drain of the transistor 310B is also coupled to the output 304B of the variable tuning resistor 302B and the input of the negative-side differential amplifier 308B.

[0098] For the depicted example embodiment, trip voltages 330 are generated within resistor tree 602. Resistor tree 602 includes a plurality of resistors coupled in series between a positive reference voltage (VREFP) and a negative reference voltage (VREFN). For this example embodiment, six (6) trip voltages 330 are generated from intervening nodes 610, 612, 614, 616, 618, and 620. Furthermore, for this example embodiment, two resistors (R) are coupled between each of these nodes, while three resistors (R) are coupled between nodes 610 / 620 and the reference voltages (VREFP and VREFN), respectively. Node 610 provides a high trip voltage, VH_3. Node 612 provides a high trip voltage, VH_2. Node 614 provides a high trip voltage, VH_1. Node 616 provides a low trip voltage, VH_3. Node 618 provides a low trip voltage, VH_2. Node 620 provides a low trip voltage, VH_1. The different trip voltages 330 are coupled to a comparator array 314 that also receives the voltages 106A / 106B. The comparator array 314 outputs the thermometer bits (T1-T6) and the inverted thermometer bits (bT1-bT6) as digital values ​​110.

[0099] Figure 7Yes Receive Figure 6 1 . A circuit diagram of an example differential embodiment of a comparator array 314 for different trip voltages 330 of an embodiment of the present invention is shown. A difference voltage based on the positive side voltage (VIN_P) 106A and the negative side voltage (VIN_N) 106B is coupled to the positive inputs (+) of comparators 315, 316, 317, 702, 704, and 318. For comparator 315, a difference voltage based on trip voltage (VH_3) 610 and trip voltage (VL_1) 620 is coupled to the negative input (-) of comparator 315. For comparator 316, a difference voltage based on trip voltage (VH_2) 612 and trip voltage (VL_2) 618 is coupled to the negative input (-) of comparator 316. For comparator 317, a difference voltage based on trip voltage (VH_1) 614 and trip voltage (VL_3) 616 is coupled to the negative input (-) of comparator 317. For comparator 702, a difference voltage based on trip voltage (VL_3) 616 and trip voltage (VH_1) 614 is coupled to the negative input (-) of comparator 702. For comparator 704, a difference voltage based on trip voltage (VL_2) 618 and trip voltage (VH_1) 614 is coupled to the negative input (-) of comparator 704. For comparator 318, a difference voltage based on trip voltage (VL_1) 620 and trip voltage (VH_3) 610 is coupled to the negative input (-) of comparator 315.

[0100] Comparators 315, 316, 317, 702, 704, and 318 generate thermometer bits (T6, T5, T4, T3, T2, T1) and the inverses of these bits (bT6, bT5, bT4, bT3, bT2, bT1). These thermometer bits represent the N-bit digital value 110 as described above. When the positive input (+) exceeds the negative input (-), the thermometer bit will be a high logic level, otherwise it will be a low logic level. The digital value 110 in the form of the thermometer bits (T6, T5, T4, T3, T2, T1) and the inverse thermometer bits (bT6, bT5, bT4, bT3, bT2, bT1) controls the operation of the N-bit digital value 110. Figure 6 312. Additionally, digital value 110 is used to form a Figure 1 An N-bit value of a portion of the converted digital output 132 is provided as shown.

[0101] Figure 8 Is receiving from Figure 6 A circuit diagram of an example differential embodiment of a phase-controlled current generator 114 for the differential residual current 112A / 112B of the VIMDAC 108. For this differential embodiment, there are corresponding Figure 4The PMOS transistors 415, 416, ..., 417 in FIG. 4 include sixteen (16) positive-side PMOS transistors 804A and sixteen (16) negative-side PMOS transistors 804B.

[0102] Positive side current 112A is coupled to node 402A. Node 402A is coupled to the drain and gate of PMOS transistor 404A, causing PMOS transistor 404A to operate as a diode-connected device within a current mirror. The source of PMOS transistor 404A is coupled to node 412, which is coupled to the power supply voltage (V 电源 ). The source of PMOS transistor 804A is also coupled to node 412 and the supply voltage. The drain of PMOS transistor 804A is coupled to generate time-interleaved current 115A. The gate of PMOS transistor 804A is coupled to node 402A via switches. These switches are controlled by time-interleaved phase-controlled clock pulses (θ1-θ16) 806. When "on," these switches connect their gates to node 402A, allowing PMOS transistor 804A to mirror the current in PMOS transistor 404A. In this manner, PMOS transistor 804A and time-interleaved phase-controlled clock pulses (θ1-θ16) 806 provide a copy of current 112A as time-interleaved current 115A to ICRO sub-ADC array 120.

[0103] Negative side current 112B is coupled to node 402B. Node 402B is coupled to the drain and gate of PMOS transistor 404B, causing PMOS transistor 804B to operate as a diode-connected device within a current mirror. The source of PMOS transistor 804B is coupled to node 412, which is coupled to the power supply voltage (V 电源 ). The source of PMOS transistor 804B is also coupled to node 412 and the supply voltage. The drain of PMOS transistor 804B is coupled to generate time-interleaved current 115B. The gate of PMOS transistor 804B is coupled to node 402B via switches. These switches are controlled by time-interleaved phase-controlled clock pulses (θ1-θ16) 806. When "on," these switches connect their gates to node 402B, allowing PMOS transistor 804B to mirror the current in PMOS transistor 804B. In this manner, PMOS transistor 804B and time-interleaved phase-controlled clock pulses (θ1-θ16) 806 provide a copy of current 112B as time-interleaved current 115B to ICRO sub-ADC array 120.

[0104] Figure 9A is a timing diagram of an example embodiment 900 of a phase-controlled clock pulse (θ1-θ16) 806 that may be generated and output to Figure 8The embodiment of the phase-controlled current generator 114 is shown. The sampling clock 105 is used as the main clock. The sub-ADC clock 902 is based on the sampling clock 105 and is used to Figure 4 The sub-ADC array 120 is shown to be clocked. For the example embodiment 900, the sub-ADC clock 902 has a global frequency (f S ) is one-quarter frequency (f S / 4). Each of the phase-controlled clock pulses (θ1-θ16) 806 has a pulse that lasts for one period of the sampling clock 105, and the pulse repeats every sixteen (16) periods of the sampling clock 105. As such, the pulses of the phase-controlled clock pulses (θ1-θ16) 806 do not overlap. As described above, the phase-controlled clock pulses (θ1-θ16) 806 are used to deliver the time-interleaved currents 115A / 115B to the ICRO sub-ADC array 120. More generally, it should be noted that each of the phase-controlled clock pulses (θ1-θ16) 806 is pulsed to generate a current signal that is proportional to the current flow rate of the ICRO sub-ADC array 120. S / X given time period to update the input of its corresponding sub-ADC, where X represents the number of different pulses. For example, in the example embodiment 900, there are sixteen (16) different phases and the frequency of the sampling clock (f S ) is 4 gigahertz (GHz), each of the phased clock pulses (θ1-θ16) 806 is pulsed at a frequency of 250 megahertz (MHz), which is 4 GHz / 16 = 250 MHz. It should also be noted that the sub-ADC clock 902 can be implemented with different frequencies, including slower or faster frequencies than those shown in the embodiment 900. For example, the sub-ADC clock 902 can have a higher frequency than the global frequency (f S ) frequency, as in the case where averaging is used. Other variations can also be implemented.

[0105] Figure 9B A timing diagram of an example embodiment of the operation of the phase-controlled current generator 114 to generate the time-staggered current 115 is provided. Figure 9B In this example embodiment shown at 950 in FIG. 1 , it is assumed that the input voltage (V) 106 ramps through different operating regions of the VIMDAC 108, as indicated by Figure 3 is determined by the comparator array 314 shown. Figure 9B 952 in the figure represents the voltage applied to the switch circuit 417 to control the Figure 4 An example phase-controlled clock pulse θX is shown for sampling the residual current (I) 112. Although one example phase-controlled clock pulse θX is shown, it should be understood that each of the switching circuits 415, 416, ..., 417 will receive phase-controlled clock pulses θ1, θ2, ..., θX. Figure 9B 954 shows the residual current (I) 112 and the resulting time-interleaved currents 420 / 422 / 424 resulting from sampling caused by phase-controlled clock pulses θ1, θ2, ..., θX applied to one of the switching circuits 415, 416, ..., 417. Although a single sampled current (I 采样 ), but it should be noted that each of the switch circuits 415, 416, ..., 417 will time-interleave the currents 420, 422, ..., 424 as in reference Figure 4 These time-staggered currents 115 are provided together to the Figure 4 An array 120 of ICRO sub-ADCs is shown.

[0106] Replay Figure 5B It should be noted that equations for the operating current regions associated with the residual current 112 and different trip voltages 330 can be derived. However, before deriving the equations for the various operating regions, Vref is defined relative to Vrefp-Vrefn. The relationship is therefore Figure 5B The introduction of Figure 6-8 Each of the reference voltages serving as the different trip voltages 330 in the circuit diagram of FIG. 1 may be given as:

[0107]

[0108] Now that the comparator trip voltage 330 is established, the next step is to derive the various regions of operation equation for the residual current. The first step is to derive the required current for the simplest region of operation and apply this learning to the other regions of operation.

[0109] See also Figure 5B In the general diagram, the residual current And when Vin=V mid In the case of , the current is defined to be equal to the center current of the ICRO sub-ADC. The topology specific operating point on the modified Robertson diagram is not Figure 5B The middle of the Robertson diagram of , but allows the circuit to operate without having to source and sink current in the voltage-to-current circuit. Figure 6-8 The implementation of the circuit block diagram shown achieves the full operating range of the ICRO sub-ADC. Once this condition is established, the current in each region can be derived. Note that the following equations represent a single-ended embodiment; however, the differential embodiment equations can be derived similarly.

[0110] As mentioned above, the residual current And in this case, where Vin=V midI1=0. In this case and see Figure 5B , according to and Confirm I res =I x If R x = Rin, and plug this back into L res In the equation, the following results are obtained:

[0111] in

[0112] Now according to Figure 5B In the Robertson plot, the transconductance slope is And the only place where this equation holds true is This residual current equation applies to the operating region compared to the established comparator trip point This leads to The slope is given by

[0113] The next obvious area to derive operational equations is the area In this region, Vin=0 (or -Vref) is set. For the case of Vin=0 or as shown in the figure of the differential operation Vin=-Vref, the residual current is required to be equal to So the equation for this region is

[0114] The next region is the upper operating region of the full-scale input. In this operating region, in View mode, a set of operating equations for each operating area is as follows:

[0115] for

[0116] for

[0117] for

[0118] for

[0119] for

[0120] for

[0121] for

[0122] Among them I c It is the center current of ICRO sub-ADC.

[0123] for Figure 6 The required resistors for the VIMDAC topology example shown are calculated by looking at the defined resistors The region of R x = Rin, which is applicable to exist In this area, in

[0124] For other operating regions, you can define the Rx for each region. and in And if the constraints given this region are used Rx can be defined. If Vin = 0 is used, Rx can be easily solved. And in addition, And by combining these two equivalent values, Rx can be found. The given Rin and Provided

[0125] For the region Provided by setting Vin=Vref=Vrefp-Vrefm can be easily solved again Looking at the patterns again, the resistance Rx of each section is nothing more than a set of parallel resistors controlled by the comparator trip points for each region of operation.

[0126] Now see Figure 10A 11A-B and 11A-B provide example embodiments for calibrating multi-stage analog-to-digital converters, including the multi-stage ADC embodiments described above. Due to circuit implementation non-idealities (e.g., component mismatches, finite amplifier gain and bandwidth, etc.), missing output digital values ​​or codes may be present in the digital conversion output 132 at the conversion region of an initial ADC (e.g., the N-bit VIMDAC 108 used in the multi-stage ADC 100). These missing digital values ​​may occur due to various non-idealities of the VIMDAC 108 itself, as well as any non-idealities in subsequent analog-to-digital conversion circuitry, such as the time-interleaved ADC 116. For example, even with an ideal N-bit VIMDAC 108, missing digital values ​​at the conversion points may become apparent if the subsequent ADC circuitry exhibits a nonlinear transfer function.

[0127] As described herein, calibration circuits and methods can be implemented to correct for these circuit non-idealities in multi-stage ADCs. The disclosed calibration embodiments implement efficient digital routines to approximate and correct these missing digital values. The calibration embodiments can also be implemented as background operations. Furthermore, the disclosed calibration embodiments can be implemented using digital logic without requiring additional analog calibration circuitry or specialized, predefined calibration input sequences. Other advantages can also be realized.

[0128] For the above reference Figure 1 In one embodiment, the calibration logic 140 generates calibration correction values ​​141 by tracking the maximum / minimum values ​​of the M-bit digital value 130 within different operating regions of the VIMDAC 108. In addition to the M-bit digital value 130, the calibration logic 140 also receives the N-bit digital value 110 from the VIMDAC 108 and uses this N-bit digital value 110 to determine the current operating region of the VIMDAC 108. The calibration logic 140 executes one or more calibration algorithms to generate calibration correction values ​​141, such as digital correction values, for adjusting and correcting the digital conversion output 132. For example, the digital correction values ​​141 can provide correction values ​​for each operating region of the VIMDAC 108, and these correction values ​​141 can be applied by the combiner 124 to adjust the current operating region of the VIMDAC 108. Figure 4 , 437, 439, ..., 441 received from the sub-ADC array 120, as shown in greater detail in FIG. In operation, these digital correction values ​​141 effectively correct linearity errors within the N-bit digital values ​​110 generated by the MIMDAC 108, within the M-bit digital values ​​130 generated by the additional analog-to-digital converter 116, or both. In this manner, non-idealities within both the MDAC 108 and the additional analog-to-digital converter 116 are compensated for by the calibration embodiments described herein.

[0129] Figure 10A1 is a flow chart for an example embodiment 1000 of a calibration process that can be performed by calibration logic 140 of a multi-level ADC 100 based on the operation of an N-bit initial ADC, such as a VIMDAC 108, having multiple operating regions (e.g., Z regions), followed by an M-bit additional ADC. As shown in example embodiment 1000, a calibration method keeps track of the minimum and maximum values ​​of the M-bit digital values ​​130 for each of the Z operating regions of the N-bit initial ADC. The calibration method uses these minimum and maximum values ​​to generate correction values ​​141 for the different regions determined by the N-bit digital values ​​110. The correction values ​​141, which can be digital values, are then applied to correct the N-bit digital values ​​110 output by the VIMDAC 108, the M-bit digital values ​​130 output by the additional ADC 116, or the N+M-bit digital conversion output 132 of the multi-level ADC 100. Furthermore, as described above, the calibration method can operate in the background during normal operation of the ADC 100.

[0130] For more details, see Figure 10AThe calibration process begins at block 1002. At block 1004, a new result (RESULT) of the M-bit digital value 130 is obtained based on the residual current 112 from the VIMDAC 108 of the example embodiment described above. At block 1006, a region (Z) of the residual current 112 is determined based on the N-bit digital value 110. At block 1008, a determination is made as to whether the result is the first result for region (Z). If "no," block 1012 is reached. If "yes," block 1010 is reached, where the maximum value for this region (REGION_MAX[Z]) is set to zero and the minimum value for this region (REGION_MIN[Z]) is set to 1000. Block 1012 is then reached. At block 1012, a determination is made as to whether the result is greater than the current value stored for the maximum value. If "no," block 1016 is reached. If "yes", block 1014 is reached, where the maximum value for this region (REGION_MAX[Z]) is set to the current result, which is the current value of the M-bit digital value 130. Block 1016 is then reached. In block 1016, a determination is made as to whether the result is less than the current value stored for the minimum value. If "no", block 1020 is reached. If "yes", block 1018 is reached, where the minimum value for this region (REGION_MIN[Z]) is set to the current result, which is the current value of the M-bit digital value 130. Block 1020 is then reached. In block 1020, the correction value for the region (CORRECTION[Z]) is set to the expected range value for the region (EXPECTED[Z]) minus the difference between the maximum value (REGION_MAX[Z]) and the minimum value (REGION_MIN[Z]). Flow then returns to block 1004. Note that the expected range value (EXPECTED[Z]) is an ideal value that depends on the number of bits (N) converted by the MDAC front end and the number of bits (M) converted by the additional ADC 116. It should also be noted that the difference between the maximum value (REGION_MAX[Z]) and the minimum value (REGION_MIN[Z]) represents the approximate actual conversion range for that region. It should also be noted that different or additional steps can also be implemented while still utilizing the techniques described herein.

[0131] Figure 10B Is implemented Figure 10A1. A block diagram of an example embodiment of a calibration logic 140 for a calibration process of FIG. 1. A comparison engine 1052 receives as input an M-bit digital value 130 from an additional ADC (e.g., ADC 116) and an N-bit digital value 110 from an initial ADC (e.g., VIMDAC 108). The maximum value for region 1-Z is stored in a lookup table 1054, while the minimum value for region 1-Z is stored in a lookup table 1056. The expected range value for region 1-Z is stored in a lookup table 1062. The comparison engine 1052 determines the operating region of the initial ADC based on the N-bit digital value 110, accesses the lookup tables 1054 and 1056, and updates the lookup table 1062. Figure 10A The calibration logic 140 stores the values ​​described in Example 1000 in the preceding embodiment. For each zone 1-Z, the calibration engine 1060 compares the desired range value from the lookup table 1062 with the difference between the maximum and minimum values ​​from the lookup tables 1054 / 1056 to generate a correction value stored in table 1064. A controller 1058 is coupled to the comparison logic 1052 and the correction logic 1060 to facilitate control and timing of the internal operations of the calibration logic 140. The calibration correction value 141 stored in table 1064 is then output to the combiner 124 for adjusting the M-bit digital value 130 and thereby correcting for non-idealities in the operation of the initial ADC (e.g., VIMDAC 108), the operation of the additional ADC (e.g., time-interleaved ADC 116), or both. As described herein, the calibration correction value 141 is updated over time as the maximum or minimum values ​​stored in the lookup tables 1054 / 1056 are updated. The desired range value stored in the lookup table 1062 can be a programmable value or can be a fixed value based on the implementation of the multi-level ADC. Note that calibration logic 140 can be implemented using one or more integrated circuits that are programmed to provide the functionality described herein. It should also be noted that tables 1054, 1056, 1062, and 1064 can be implemented as one or more non-transitory computer-readable media. Other circuit systems and variations can also be implemented while still utilizing the calibration techniques described herein.

[0132] Therefore, as stated in this article, Figure 10AThe calibration circuit and method of -B can be implemented as an effective digital routine that approximates and corrects for missing digital values ​​or codes within the conversion region of the front-end VIMDAC 108. The digital routine runs in the background by evaluating each result of the M-bit digital value 130. For each given result, the digital routine determines which region of the N-bit MDAC transfer function the code resides in based on the N-bit digital value 110 from the MDAC 108. After this determination, the routine further determines whether the current result represents the maximum or minimum value of the region in which it resides. The calibration algorithm effectively stores the output value for a given region only if the value represents the minimum or maximum value of all values ​​that have occurred in that region. The difference between the maximum and minimum values ​​represents the actual conversion range implemented by the given region. The difference between the expected range value and this actual conversion range represents the correction value that can be applied to adjust and correct the actual conversion range. Over time, the calibration routine obtains increasingly accurate estimates of the minimum and maximum values ​​for each region. These minimum and maximum values ​​are also compared between adjacent MDAC region conversions to calculate correction values ​​between regions (e.g., code hopping). This correction value is then digitally added or subtracted to ultimately generate a corrected ADC output for the multi-stage ADC 100. Because this occurs continuously, the accuracy of this correction improves over time. After a period of time, the correction value 141 will resolve, and the digital conversion output 132 of the multi-stage ADC 100 will no longer contain missing code errors at the MDAC conversion region.

[0133] Figure 11A -B are representative plots of the ADC output relative to the ADC input before and after applying the calibration process of Figure 10. These ADC transfer curves represent the ADC output after the N bits associated with the VIMDAC 108 are summed to generate the overall digital conversion output 132. For the example embodiment described above, the VIMDAC 108 outputs the three MSBs (000 to 110) for the digital conversion output 132.

[0134] See first Figure 11A , a representative graph of an embodiment 1100 is shown of an ideal ADC transfer curve 1102 and an actual ADC transfer curve 1104. As described herein, the front-end VIMDAC 108 determines the first N bits of the digital conversion output 132 based on the operating region of the residual current 112 based on the voltage input 106. For the above example, the VIMDAC 108 (e.g., a 2.5-bit MDAC) has seven (7) different regions. For embodiment 1100, these different regions are regions 556, 558, 560, 562, 564, 566, and 568 (representing outputs 000, 001, 010, 011, 100, 101, 110, respectively), which are provided to Figure 3The trip voltage 330 of the comparator array 314 is shown determined.

[0135] Now see Figure 11B , shows a representative graph of embodiment 1150 of an ideal ADC transfer curve 1102 and a corrected ADC transfer curve 1154 after correction values ​​are applied. The front-end VIMDAC 108 again determines the first N bits of the digital conversion output 132 based on the operating region of the residual current 112 based on the voltage input 106. However, for embodiment 1150, the correction values ​​generated by the calibration logic 140 have been applied to correct for the digital values ​​or codes that are lost during the region conversion. For the above example, the VIMDAC 108 (e.g., a 2.5-bit MDAC) still has seven (7) different regions. For embodiment 1100, these different regions are regions 556, 558, 560, 562, 564, 566, and 568 (representing outputs 000, 001, 010, 011, 100, 101, 110, respectively), which are provided to Figure 3 The trip voltage 330 of the illustrated comparator array 314 is determined. As shown, the corrected ADC transfer curve 1154 provides significantly improved linearity.

[0136] As described herein, multiple embodiments may be implemented, and different features and variations may be implemented, if desired.

[0137] According to one embodiment, a circuit for analog-to-digital conversion is disclosed, comprising a multiplying digital-to-analog converter (MDAC). The MDAC comprises an amplifier coupled to convert a voltage received as an input into an output current; a variable load coupled to the amplifier to control the output current, wherein the variable load depends on a digital value; and a comparator array coupled to receive the voltage as an input and output the digital value. The digital value represents at least a portion of a digital conversion of the voltage.

[0138] In additional embodiments, the circuit further comprises a phase-controlled current generator coupled to receive the output current and having as output a plurality of time-interleaved currents, each of which is a sampled copy of the output current. In further embodiments, the phase-controlled current generator comprises a plurality of current mirror circuits coupled to mirror the output current and output the time-interleaved currents; a plurality of switches coupled to enable or disable the plurality of current mirror circuits; and a plurality of phase-controlled clock pulses coupled to control the switches. In still further embodiments, each of the current mirror circuits comprises a transistor coupled to mirror the output current and controlled by one of the plurality of phase-controlled clock pulses.

[0139] In an additional embodiment, the amplifier includes an NMOS transistor having a gate coupled to the voltage through a differential amplifier, a drain coupled to the variable load, and a source coupled to provide the output current.

[0140] In additional embodiments, the variable load comprises a variable resistance circuit having a plurality of selectable resistors. In further embodiments, the plurality of selectable resistors comprises a plurality of resistors coupled to the amplifier via switches controlled by the digital value.

[0141] In additional embodiments, the comparator array has a plurality of trip voltages as inputs. In further embodiments, the circuit further comprises a resistor tree coupled between two reference voltages and having a plurality of trip voltages from intervening nodes as outputs. In further embodiments, each comparator provides a thermometer bit for the digital value based on at least one of the trip voltages.

[0142] In one embodiment, a method for analog-to-digital conversion is disclosed, the method comprising: converting a voltage received by an amplifier into an output current; controlling the output current with a variable load coupled to the amplifier, wherein the variable load depends on a digital value; and generating the digital value with a comparator array coupled to receive the voltage as an input. The conversion, control, and generation provide a multiplying digital-to-analog converter (MDAC). Additionally, the digital value represents at least a portion of a digital conversion of the voltage.

[0143] In additional embodiments, the method includes generating a plurality of time-staggered currents based on the output current. In further embodiments, generating the plurality of time-staggered currents includes: generating a plurality of currents that mirror the output current using a plurality of current mirror circuits; controlling the plurality of current mirror circuits using a plurality of switches to output the plurality of currents; and applying a plurality of phase-controlled clock pulses to control the switches. In still further embodiments, each of the current mirror circuits includes a transistor coupled to mirror the output current controlled by one of the plurality of phase-controlled clock pulses.

[0144] In additional embodiments, the amplifier includes an NMOS transistor having a drain coupled to the variable load, and the method further includes applying the voltage to a gate of the NMOS transistor and providing the output current from a source of the NMOS transistor through a differential amplifier.

[0145] In additional embodiments, the controlling includes adjusting a variable resistance circuit having a plurality of selectable resistors to provide the variable load. In further embodiments, the adjusting includes applying a digital value to control a switch that selects which of the plurality of selectable resistors is included in the variable load.

[0146] In additional embodiments, the method further comprises providing a plurality of trip voltages as inputs to the comparator array. In further embodiments, the method further comprises generating the plurality of trip voltages from intervening nodes within a resistor tree, the resistor tree coupled between two reference voltages. In further embodiments, each comparator provides a thermometer bit for the digital value based on at least one of the trip voltages.

[0147] It should also be noted that the functional blocks, components, systems, devices, or circuit systems described herein can be implemented using hardware, software, or a combination of hardware and software. For example, the disclosed embodiments can be implemented using one or more integrated circuits that are programmed to perform the functions, tasks, methods, actions, or other operational features described herein for the disclosed embodiments. The one or more integrated circuits may include, for example, one or more processors or configurable logic devices (CLDs) or a combination thereof. The one or more processors may be, for example, one or more central processing units (CPUs), controllers, microcontrollers, microprocessors, hardware accelerators, application specific integrated circuits (ASICs), or other integrated processing devices. The one or more CLDs may be, for example, one or more complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), reconfigurable logic circuits, or other integrated logic devices. In addition, the integrated circuits (including one or more processors) may be programmed to execute software, firmware, code, or other program instructions that are implemented in one or more non-transitory tangible computer-readable media to perform the functions, tasks, methods, actions, or other operational features described herein for the disclosed embodiments. The integrated circuit (including one or more CLDs) may also be programmed using logic code, logic definitions, hardware description languages, configuration files, or other logic instructions embodied in one or more non-transitory tangible computer-readable media to perform the functions, tasks, methods, actions, or other operational features described herein with respect to the disclosed embodiments. Additionally, the one or more non-transitory tangible computer-readable media may include, for example, one or more data storage devices, memory devices, flash memory, random access memory, read-only memory, programmable memory devices, reprogrammable storage devices, hard drives, floppy disks, DVDs, CD-ROMs, or any other non-transitory tangible computer-readable media. Other variations may also be implemented while still utilizing the techniques described herein.

[0148] Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Therefore, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

[0149] In view of this specification, additional modifications and alternative embodiments of the described systems and methods will be apparent to those skilled in the art. Therefore, it will be appreciated that the described systems and methods are not limited to these example arrangements. It should be understood that the forms of the systems and methods shown and described herein are to be regarded as example embodiments. Various changes can be made in the embodiments. Therefore, although the present invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention. Therefore, this specification and the accompanying drawings should be regarded as illustrative rather than restrictive, and such modifications are intended to be included within the scope of the present invention. In addition, any benefits, advantages, or problem solutions described herein for specific embodiments are not intended to be interpreted as key, essential, or necessary features or elements of any or all claims.

Claims

1. A circuit for analog-to-digital conversion, characterized in that include: A multiplying digital-to-analog converter (MDAC), the multiplying digital-to-analog converter comprising: an amplifier coupled to convert a voltage received as an input into an output current; a variable load coupled to the amplifier to control the output current, the variable load being dependent on a digital value; and a comparator array coupled to receive the voltage as input and to have the digital value as output; wherein the digital value represents at least a portion of a digital conversion of the voltage; The circuit further includes a phase-controlled current generator coupled to receive the output current and having as output a plurality of time-interleaved currents, each time-interleaved current being a sampled copy of the output current.

2. The circuit according to claim 1, wherein: The phase-controlled current generator comprises: a plurality of current mirror circuits coupled to mirror the output current and output the time-interleaved current; a plurality of switches coupled to enable or disable the plurality of current mirror circuits; and A plurality of phase-controlled clock pulses are coupled to control the switch.

3. The circuit according to claim 2, characterized in that Each of the current mirror circuits includes a transistor coupled to mirror the output current and controlled by one of the plurality of phase-controlled clock pulses.

4. The circuit according to claim 1, wherein: The amplifier includes an NMOS transistor having a gate coupled to the voltage through a differential amplifier, a drain coupled to the variable load, and a source coupled to provide the output current.

5. The circuit according to claim 1, wherein: The variable load includes a variable resistance circuit having a plurality of selectable resistors.

6. The circuit according to claim 5, characterized in that The plurality of selectable resistors includes a plurality of resistors coupled to the amplifier through switches controlled by the digital value.

7. The circuit according to claim 1, wherein: The comparator array has a plurality of trip voltages as inputs.

8. The circuit according to claim 7, characterized in that Further included is a resistor tree coupled between two reference voltages and having as output the plurality of trip voltages from the intervening nodes.

9. A method for analog-to-digital conversion, characterized in that include: converting a voltage received by the amplifier into an output current; controlling the output current with a variable load coupled to the amplifier, the variable load being dependent on a digital value; as well as generating the digital value with a comparator array coupled to receive the voltage as an input; wherein said converting, controlling and generating provides a multiplying digital-to-analog converter (MDAC); and wherein the digital value represents at least a portion of a digital conversion of the voltage; The method further includes generating a plurality of time-staggered currents based on the output current, each time-staggered current being a sampled copy of the output current.

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