Data holding circuit, data processing system and method for writing charging status

Abstract

A nonvolatile data retention circuit includes: a complementary latch configured to generate and store complementary nonvolatile spin states corresponding to an input signal when in a write mode, and to simultaneously generate a first charging current signal and a second charging current signal corresponding to the complementary nonvolatile spin states when in a read mode; and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first charging current signal and the second charging current signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Non-Provisional Patent Application No. 16 / 290,715, filed on March 1, 2019, which is hereby incorporated by reference in its entirety.

[0003] This application is also related to U.S. Patent No. 9,805,795 (“ZERO LEAKAGE, HIGHNOISE MARGIN COUPLED GIANT SPIN HALL BASED”) issued on October 31, 2017 and U.S. Patent No. 9,858,975 (“ZERO TRANSISTOR TRANSVERSECURRENT BI-DIRECTIONAL BITCELL”) issued on January 2, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0004] Aspects of the present invention relate to the field of data holding and processing devices. Background Art

[0005] In recent years, field neuromorphic computing has attempted to use analog, digital, and / or mixed-mode electronics and software systems to mimic the neurobiological architecture of the nervous system, which is responsible for perception, motor control, sensory integration, etc. Neuromorphic chips, which are hardware implementations of neuromorphic computing, include multiple neuromorphic units that mimic synapses in the brain by encoding and transmitting data in a series of electrical pulses (bursts). This is in contrast to existing computers, which typically have a linear architecture for processing data, sending information back and forth between a central processing unit (CPU) and memory chips.

[0006] While neuromorphic chips may not be as powerful or flexible as general-purpose chips, they can be specialized to perform specific tasks faster and more energy-efficiently than general-purpose chips. Neuromorphic chips and their constituent neuromorphic cells are a hot topic of research in the fields of machine learning and artificial intelligence. In a neuromorphic cell, information is learned in the form of weight values ​​stored in one or more memory cells. This information can be stored in a complementary form and read differentially to minimize or reduce noise. However, storing complementary information may increase the area and power consumption of the neuromorphic cell, and therefore increase the area and power consumption of the neuromorphic chip.

[0007] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the Invention

[0008] One aspect of embodiments of the present invention is directed to a compact cell with differential read circuitry that can be used as a neuromorphic weight cell, wherein the compact cell includes a coupled giant spin Hall latch (CGSHL) with two simultaneously programmed resistors Rp and Rn, a current mirror, and a differential amplifier. Some embodiments of the present invention exploit the unique property of giant spin Hall-based devices, wherein the device can be used to write 0 / 1 or 1 / 0 bit pairs simultaneously, thereby automatically creating copies of weight values. Therefore, some embodiments of the present invention save area and power and can be very useful in dense neuromorphic circuit implementations.

[0009] According to some embodiments of the present invention, a nonvolatile data retention circuit is provided, comprising: a complementary latch configured to generate and store complementary nonvolatile spin states corresponding to an input signal when in a write mode, and to simultaneously generate a first charging current signal and a second charging current signal corresponding to the complementary nonvolatile spin states when in a read mode; and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first charging current signal and the second charging current signal.

[0010] In some embodiments, the nonvolatile data retention circuit further includes: a current mirror coupled between the complementary latch and the differential amplifier and configured to receive the second charging current signal and supply a reverse current signal to the differential amplifier, the reverse current signal having a polarity opposite to that of the second charging current signal.

[0011] In some embodiments, the differential amplifier is a current sense amplifier.

[0012] In some embodiments, a complementary latch includes: a giant spin Hall metal configured to pass a charging current signal corresponding to an input signal; a first spin transfer torque (STT) stack located on a first side of the giant spin Hall metal; and a second STT stack located on a second side of the giant spin Hall metal opposite to the first side, wherein the first STT stack and the second STT stack extend in a direction orthogonal to an extension direction of the giant spin Hall metal and are configured to generate and store complementary non-volatile spin states.

[0013] In some embodiments, in response to a charging current signal flowing through a giant spin Hall metal, the first STT stack is configured to exhibit a magnetic moment having a parallel configuration and the second STT stack is configured to exhibit a magnetic moment having an antiparallel configuration, and wherein the first STT stack and the second STT stack are configured to maintain their parallel configuration and antiparallel configuration even when no power is supplied to the non-volatile data retention circuit.

[0014] In some embodiments, the parallel configuration of the first STT stack and the antiparallel configuration of the second STT stack correspond to complementary non-volatile spin states stored in the first STT stack and the second STT stack.

[0015] In some embodiments, the giant spin Hall metal includes beta tantalum, platinum, and / or copper bismuth.

[0016] In some embodiments, each of the first STT stack and the second STT stack includes: a free layer, which includes a magnetic material and is configured to respond to a spin current signal corresponding to a charging current signal flowing through a giant spin Hall metal based on a giant spin Hall effect, and exhibits a free magnetic moment that is substantially orthogonal to the spin current signal in a direction; a fixed layer, which includes a magnetic material and exhibits a fixed magnetic moment that is not affected by a stray field generated from the charging current signal flowing through the giant spin Hall metal; and a non-magnetic layer, between the free layer and the fixed layer, and is configured to magnetically isolate the free magnetic moment of the free layer from the fixed magnetic moment of the fixed layer and maintain any existing directional difference between the free magnetic moment and the fixed magnetic moment.

[0017] In some embodiments, in response to a charging current signal flowing through a giant spin Hall metal, the free layer of the first STT stack is configured to exhibit a first free magnetic moment parallel to the fixed magnetic moment of the fixed layer of the first STT stack, and the free layer of the second STT stack is configured to exhibit a second free magnetic moment antiparallel to the fixed magnetic moment of the fixed layer of the second STT stack.

[0018] In some embodiments, the nonvolatile data retention circuit further includes: a first transistor coupled to the giant spin Hall metal and configured to be activated in response to a first selection signal; and a second transistor coupled to the giant spin Hall metal and configured to be activated in response to a second selection signal, wherein, when in a write mode, the first transistor and the second transistor are configured to be activated in response to the first selection signal and the second selection signal and enable a charging current signal to flow through the giant spin Hall metal, and wherein, when in a read mode, the second transistor is configured to be deactivated, and the first transistor is configured to be activated in response to the first selection signal and enable the first charging current signal to flow through the first STT stack and enable the second charging current signal to flow through the second STT stack.

[0019] In some embodiments, the first transistor and the second transistor are coupled to opposite ends of the giant spin Hall metal, and the second transistor is configured to electrically couple the giant spin Hall metal to the pull-down resistor in response to a second select signal.

[0020] In some embodiments, the differential amplifier includes a first input terminal configured to receive a first charging current signal from a first STT stack and a second input terminal configured to receive a second charging current signal from a second STT stack.

[0021] In some embodiments, the nonvolatile data retention circuit further includes a current mirror coupled between the second STT stack and the differential amplifier and configured to receive the second charging current signal and supply a reverse current signal to the differential amplifier, the reverse current signal having a polarity opposite to that of the second charging current signal.

[0022] In some embodiments, the complementary latch is configured to continue storing the complementary nonvolatile spin states even when no power is provided to the nonvolatile data retention circuit.

[0023] In some embodiments, the differential amplifier is directly coupled to opposite ends of the complementary latch through the first bit line and the second bit line and is configured to receive the first charging current signal and the second charging current signal through the first bit line and the second bit line.

[0024] According to some embodiments of the present invention, a data processing system is provided, comprising: a first complementary latch configured to generate and store a first complementary non-volatile spin state corresponding to a first input signal when in a write mode, and to simultaneously generate a first charging current signal and a second charging current signal corresponding to the first complementary non-volatile spin state when in a read mode; a second complementary latch configured to generate and store a second complementary non-volatile spin state corresponding to the second input signal when in a write mode, and to simultaneously generate a third charging current signal and a fourth charging current signal corresponding to the second complementary non-volatile spin state when in a read mode; and a differential amplifier coupled to the first complementary latch and the second complementary latch and configured to generate an output signal based on the first charging current signal to the fourth charging current signal.

[0025] In some embodiments, the first input of the differential amplifier is configured to receive a sum of the first charging current signal and the third charging current signal from the first complementary latch and the second complementary latch.

[0026] In some embodiments, the data processing system further includes: a current mirror coupled between the first complementary latch and the second complementary latch and the differential amplifier, and configured to receive the second charging current signal and the fourth charging current signal and supply a reverse current signal to the differential amplifier, the reverse current signal having a polarity opposite to that of the second charging current signal and the fourth charging current signal.

[0027] In some embodiments, the reverse current signal corresponds to a sum of the second charging current signal and the fourth charging current signal.

[0028] According to some embodiments of the present invention, a method for writing complementary non-volatile charge states of a data retention circuit is provided, the method comprising: receiving a first selection signal and a second selection signal, the first selection signal and the second selection signal indicating a data write operation; and in response to receiving the first selection signal and the second selection signal: receiving an input signal at an input terminal of the data retention circuit; coupling opposite ends of a giant spin Hall metal of a coupled giant spin Hall latch to the input terminal of the data retention circuit and a pull-down resistor via a first transistor and a second transistor to receive a charge current signal from the input terminal through the giant spin Hall metal; and in response to receiving the charge current signal from the input terminal, generating and storing a complementary non-volatile spin state corresponding to the input signal through the coupled giant spin Hall latch. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings, together with the specification, illustrate exemplary embodiments of the present invention, and, together with the description, serve to explain the principles of the present invention.

[0030] Figure 1 is a schematic diagram of a data processing system utilizing a nonvolatile data retention circuit according to some example embodiments of the present invention.

[0031] Figure 2 is a schematic diagram of a complementary latch of a nonvolatile, high noise tolerance data retention circuit according to some example embodiments of the present invention.

[0032] Figure 3A Schematic diagrams illustrating nonvolatile data retention circuits according to some example embodiments of the present invention are shown.

[0033] Figure 3B Simplified schematic diagrams of non-volatile data retention circuits according to some other example embodiments of the present invention are shown.

[0034] Figure 4 A schematic diagram illustrating a column of data retention circuits in a data processing system according to some example embodiments of the present invention is shown.

[0035] Figure 5is a flowchart illustrating a process of writing complementary data into a data holding circuit according to some example embodiments of the present invention. DETAILED DESCRIPTION

[0036] In the following detailed description, only certain exemplary embodiments of the present invention are shown and described by way of illustration. As will be appreciated by those skilled in the art, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. The description of the features or aspects within each exemplary embodiment should generally be considered to be applicable to other similar features or aspects in other exemplary embodiments. Throughout this specification, identical reference numerals designate identical elements.

[0037] Some example embodiments of the present invention implement efficient, low-noise-tolerance, differential readout for inference based on neuromorphic cells. In some embodiments, this is achieved by storing a bit (e.g., "1") and its complement (e.g., "0") as resistance values ​​in a coupled giant spin Hall latch (CGSHL) and sensing the resistance difference between these stored bits for very low-noise readout.

[0038] Figure 1 is a schematic diagram of a data processing system 10 utilizing a nonvolatile data retention circuit 100 according to some example embodiments of the present invention.

[0039] refer to Figure 1 , data processing system 10 stores and processes data. In some examples, data processing system 10 may be a node (e.g., a neuromorphic unit or "synapse") within an artificial intelligence (AI) system (e.g., a neuromorphic chip). Data processing system 10 multiplies an input signal by a value (also called a weight) to produce an output signal.

[0040] According to some embodiments, a data processing system 10 includes a plurality of nonvolatile data retention circuits 100, each of which acts as a latch for storing complementary states of nonvolatile data. The nonvolatile data retention circuits 100 achieve zero (or near-zero) leakage retention of latched data when idle, i.e., when the latched data is not subject to read or write requests, such as may be the case when the electronic device of which the data processing system 10 is a part is powered down (e.g., shut down or in sleep / hibernation mode). According to some embodiments, the nonvolatile data retention circuits 100 use the giant spin Hall effect to convert an input signal (e.g., an input voltage / current signal) into a complementary spin state corresponding to (e.g., representing) complementary bit data. When the stored complementary state is retrieved (e.g., when an output signal is generated based on the input signal and the latched data), the nonvolatile data retention circuits 100 convert the stored complementary spin state into a complementary charge state for further processing.

[0041] According to some embodiments, each nonvolatile data retention circuit 100 receives a first control signal SELp and a second control signal SELn (also referred to as a selection signal), which control the data write and read operations of the nonvolatile data retention circuit 100. In some embodiments, the first selection signal SELp and the second selection signal SELn are supplied from a cell controller 20 that controls the operation of a plurality of nonvolatile data retention circuits 100, wherein the plurality of nonvolatile data retention circuits 100 are organized in a matrix form along columns and rows. According to some embodiments, the nonvolatile data retention circuits 100 along the j-th column (where j is an integer greater than zero) share a common first selection signal SELp(j) and a second selection signal SELn(j), and their output signals are summed together (e.g., equal to Figure 1 ). In some embodiments, each nonvolatile data retention circuit 100 generates a current signal at its output terminal, and the output signals of the nonvolatile data retention circuits 100 in a particular column are added together by connecting their output terminals together (i.e., electrically connecting). Those nonvolatile data retention circuits 100 arranged along the i-th row (where i is an integer greater than zero) share a common input signal Vin(i). In some examples, the input signal Vin(i) can be the output signal of the previous node (e.g., from a neuromorphic unit of the previous stage).

[0042] As one of ordinary skill in the art will recognize, although Figure 1 Only four data holding circuits 100 are shown in FIG. 1 , but embodiments of the present invention are not limited thereto, and data processing system 10 may include any suitable number of data holding circuits 100. Furthermore, the data holding circuits 100 shown represent weight components W(i,j), W(i,j+1), W(i+1,j), and W(i+1,j+1) of cell values ​​(or node weights), which may or may not have other components.

[0043] Figure 2 is a schematic diagram of a complementary latch 110 of a nonvolatile, high noise tolerance data retention circuit 100 according to some embodiments of the present invention.

[0044] According to some embodiments, a nonvolatile data retention circuit 100 includes a complementary latch (e.g., a coupled giant spin Hall latch) 110 that uses a dual spin transfer torque (STT) stack to store complementary data. The dual STT stack includes a first STT stack 111p and a second STT stack 111n located on opposite sides (e.g., in opposite Z directions) of a giant spin Hall metal (GSH) 130 and adjacent to the GSH metal 130, wherein the GSH metal 130 is a metal such as beta tantalum, platinum, copper bismuth (CuBi), or the like. The two stacks of STT devices 111p and 111n, together with the GSH metal 130, may also be referred to as a coupled giant spin Hall latch (CGSHL). Due to the GSH effect, a charge current passing through the GSH metal 130 causes complementary binary "0" / "1" or "1" / "0" states to be stored simultaneously (e.g., synchronously) in the first STT stack 111p and the second STT stack 111n as complementary nonvolatile spin states.

[0045] According to some embodiments, each of the first STT stack and the second STT stack 111p / 111n includes a free layer 112p / 112n adjacent to the giant spin Hall metal 130, a fixed layer 114p / 114n, and a non-magnetic tunnel barrier layer (which may also be referred to as a non-magnetic layer) 116p / 116n (such as crystalline magnesium oxide (MgO), amorphous aluminum oxide, etc., which separate the free layer 112p / 112n and the fixed layer 114p / 114n).

[0046] The free layers 112p / 112n and the pinned layers 114p / 114n are magnetic. According to some embodiments, the magnetic moments (eg, pinned magnetic moments) of the pinned layers 114p and 114n are collinear and pinned in a particular direction, for example, Figure 2, which is parallel or substantially parallel to the height direction of the first STT stack 111p and the second STT stack 111n. The magnetic moment can be fixed by the exchange bias interaction with the antiferromagnetic (AFM) layer. In some examples, the fixed layer 114p / 114n may include multiple layers. For example, the fixed layer 114p / 114n may include an antiferromagnetic layer 118p / 118n between two fixed ferromagnetic layers 117p / 117n and 119p / 119n. The antiferromagnetic layer 118p / 118n is an intermediate layer that mediates the antiferromagnetic coupling between the fixed ferromagnetic layers 117p / 117n and 119p / 119n. This can help couple the fixed ferromagnetic layer 117p / 117n to 119p / 119n and produce a stronger fixed layer 114p / 114n. In some examples, the antiferromagnetic layers 118p / 118n can include ruthenium (Ru). According to some embodiments, symmetry-breaking layers 120p / 120n are placed on the pinned layers 114p and 114n to enable perpendicular spin torque operation, which is desirable for the scaling region of the STT structure. Capping layers 123p / 123n can cover the symmetry-breaking layers 120p / 120n to protect the layers beneath them, and electrode layers 122p / 122n can be placed on the capping layers 123p / 123n to enable electrical connection between the STT stack 111p / 111n and an external circuit (e.g., a differential amplifier or a current mirror) through the bit lines BLp / BLn.

[0047] When a charge current (e.g., along the X direction) passes through the giant spin Hall metal 130, a spin current is generated in an orthogonal direction (e.g., the + / -Z direction), wherein the spin current provides a torque that flips the magnetic moment in a direction transverse to the direction of the charge current (e.g., the + / -Y direction). Due to the giant spin Hall effect, the generated spin current can then switch the magnetic orientation of the adjacent first free layer 112p and second free layer 112n. The first free layer 112p and the second free layer 112n may include iron (Fe), a cobalt-iron alloy (e.g., CoFe), a cobalt-iron-boron alloy (e.g., CoFeB), etc. Since the first free layer 112p and the second free layer 112n are on opposite sides of the giant spin Hall metal 130, the magnetic orientation of the first free layer 112p can be opposite to the magnetic orientation of the second free layer 112n (e.g., one in the -Z direction and the other in the +Z direction). According to some embodiments, the magnetic orientation of the pinned layers 114p / 114n is fixed, and stray fields generated by the charging current passing through the giant spin Hall metal 130 are ineffective and do not affect (or substantially affect) the magnetic orientation. The nonmagnetic tunnel barrier layers 116p / 116n are used to magnetically isolate the magnetic moment (e.g., free magnetic moment) of the free layers 112p / 112n from the fixed magnetic moment of the pinned layers 114p / 114n and maintain any existing directionality difference between the free magnetic moment and the fixed magnetic moment (i.e., prevent the fixed magnetic moment of the pinned layers 114p / 114n from affecting and changing the directionality of the free magnetic moment of the free layers 112p / 112n). In embodiments where the magnetic moments of the pinned layers 114p and 114n are oriented in the +Z or -Z direction, the charging current passing through the giant spin Hall metal 130 can flip the magnetic moments of the free layers 112p and 112n in the + / -Z and - / +Z directions, respectively. A charge current passing through the giant spin Hall metal 130 in the opposite direction (e.g., along the -X direction) can cause the magnetic moment of the free layer 112p / 112n to flip (e.g., from the + / -Z direction to the - / +Z direction). Here, the fixed layer 114p / 114n has a strong magnetic polarization and serves as a reference point for the magnetic polarization (or magnetic moment).

[0048] According to some embodiments, the first fixed layer 114p and the second fixed layer 114n have magnetic orientations in the same or substantially the same direction (e.g., +Z direction), and the charging current +Jc in the first direction (e.g., +X direction) causes the magnetic orientations of the first free layer 112p and the first fixed layer 114p to be parallel, and the magnetic orientations of the second free layer 112n and the second fixed layer 114n to be antiparallel. Figure 2As shown, the first STT stack 111p exhibits a parallel configuration, while the second STT stack 111n exhibits an antiparallel configuration. According to some examples, the parallel configuration of the first STT stack 111p can represent the storage of a binary "1" state, while the antiparallel configuration of the second STT stack 111n can represent the storage of a binary "0" state. However, embodiments of the present invention are not limited thereto, and the parallel and antiparallel magnetic orientations can represent a binary "0" state and a binary "1" state, respectively. Therefore, the charging current +Jc flowing through the giant spin Hall metal 130 can cause the CGSHL 110 to simultaneously (e.g., synchronously) store complementary states "1" and "0" in the first STT stack 111p and the second STT stack 111n, respectively (or store "0" and "1" if the charging current directions are opposite).

[0049] The antiparallel configuration makes the corresponding stack (e.g. Figure 2 The first STT stack 111p in the parallel configuration has a larger resistance, while the parallel configuration makes the resistance of its corresponding stack (e.g., the second STT stack 111n) smaller. In some embodiments, the data retention circuit 100 utilizes this resistance difference to perform a differential read of the storage bits during a read operation. According to some examples, in an artificial intelligence system (or a neuromorphic system), a read operation can represent an inference phase of operation, during which data stored at a node / unit (e.g., weights / weight components) is used to perform a calculation (e.g., a linear mathematical operation) on the input value from the previous node / unit to generate an output value to be passed to a subsequent node / unit.

[0050] Figure 3A Schematic diagram of a nonvolatile data retention circuit 100 according to some example embodiments of the present invention is shown. Figure 3B A simplified schematic diagram of a nonvolatile data retention circuit 100 - 1 according to some other example embodiments of the present invention is shown.

[0051] refer to Figure 3AAccording to some embodiments, the nonvolatile data retention circuit 100 includes a complementary latch 110, a first select transistor 140 and a second select transistor 142, a differential amplifier (e.g., a current sense amplifier) ​​150, and a current mirror 160. When storing complementary data, the complementary latch 110 exhibits different resistances at its first STT stack 111p and second STT stack 111n. The first select transistor 140 and the second select transistor 142 are coupled to opposite ends of the giant spin Hall metal 130 and are configured to control the operation mode (e.g., idle / read / write mode) of the complementary latch 110 based on a first select signal SELp and a second select signal SELn. A first input terminal of the differential amplifier 150 is electrically connected to the first STT stack 111p of the complementary latch 110, and a second input terminal of the differential amplifier 150 is electrically connected to the current mirror 160, wherein the current mirror 160 is electrically connected between the differential amplifier 150 and the second STT stack 111n of the complementary latch 110. The differential amplifier 150 is configured to sense (e.g., amplify) the difference in charge current flowing through the first STT stack 111p and the second STT stack 111n when in write mode. The current mirror 160 is configured to apply a mirror current (e.g., an inverse current) of the charge current flowing through the second STT stack 111n to a second input of the differential amplifier 150. The first select transistor 140 and the second select transistor 142 receive a first select signal SELp and a second select signal SELn at their gates, respectively.

[0052] When in idle mode, both the select signals SELp and SELn are disabled (e.g., not powered), which deactivates (e.g., turns off) both the first select transistor 140 and the second select transistor 142 and prevents any current from passing through the giant spin Hall metal 130 and the first and second STT stacks 111p and 111n. In idle mode, data cannot be written to or read from the data holding circuit 100.

[0053] In the data write mode, when both the first selection transistor 140 and the second selection transistor 142 are activated (e.g., turned on) due to receiving the first selection signal SELp and the second selection signal SELn at their gates, the first selection transistor 140 and the second selection transistor 142 form a current path from the input terminal of the data holding circuit 100 (where the input signal Vin is received) through the giant spin Hall metal 130 and to the pull-down resistor Rpd. The charging current induces a spin current through the giant spin Hall metal 130, wherein the spin current stores complementary bits in the first STT stack 111p and the second STT stack 111n, and makes the resistance in one STT stack higher than the other. Figure 3AIn the example shown in , the first STT stack 111 p exhibits a lower resistance Rp (ie, has a parallel configuration), and the second STT stack 111 n exhibits a higher resistance Rn (ie, has an anti-parallel configuration).

[0054] In the read mode, the first selection signal SELp is applied to the first selection transistor 140, thereby activating (turning on) the first selection transistor 140, while the second selection transistor 142 is deactivated (disabled or turned off) because the second selection signal SELn is not applied to the second selection transistor 142. Here, the input current to the giant spin Hall metal 130 is divided into a first current Ip passing through the first STT stack 111p and a second current In passing through the second STT stack 111n. The ratio of the first current Ip to the second current In can be inversely proportional to the ratio of the first resistor Rp to the second resistor Rn. Therefore, in Figure 3A In the example of , the first current Ip may have a higher value than the second current In. The current difference is detected by the differential amplifier 150 that generates an output current proportional to the difference. The output current Io of the differential amplifier 150 of the data holding circuit 100 can be expressed by Equation 1:

[0055] Io=(Gp-Gn)×Vin Equation 1

[0056] Here, Gp and Gn represent the conductance (ie, the inverse of the resistance) of the first STT stack 111 p and the second STT stack 111 n , respectively.

[0057] Here, the current mirror 160 is used to change the polarity of the second current In at the input terminal of the differential amplifier 150 (to -In). Figure 3A The example shown in FIG. 1 utilizes a Wilson current mirror, but embodiments of the present invention are not limited thereto, and the current mirror 160 may utilize any suitable current mirror circuit topology (eg, a Wilson current mirror topology). Figure 3A The embodiment of the data holding circuit 100 shown in FIG utilizes the current mirror 160 , but the embodiments of the present invention are not limited thereto. For example, if the reversal of the current polarity occurs internally at either input terminal of the differential amplifier, the current mirror 160 may be eliminated.

[0058] Figure 3B An embodiment of the present invention is shown in which the operation of the current mirror has been integrated into the differential amplifier 150-1, so that the second input terminal of the differential amplifier 150-1 is directly connected to the second STT stack 111n (i.e., without an intermediate current mirror) and receives the second current In during the read mode. For clarity of illustration, components such as the giant spin Hall metal 130, the first and second select transistors 140 and 142, and the corresponding first and second select signals SELp and SELn are not shown in FIG. Figure 3B Shown in.

[0059] Figure 3A and Figure 3B Some embodiments of the present invention are shown where each data holding circuit 100 / 100-1 has its own dedicated differential amplifier 150 / 150-1 (and, in some examples, a dedicated current mirror). However, embodiments of the present invention are not limited thereto.

[0060] Figure 4 FIG1 shows a schematic diagram of a column of data holding circuits 100 in a data processing system 10 according to some example embodiments of the present invention. For clarity of illustration, components such as the giant spin Hall metal 130, the first and second selection transistors 140 and 142, and the corresponding first and second selection signals SELp and SELn are not shown in FIG1 . Figure 4 Shown in.

[0061] refer to Figure 4 In some embodiments, the data holding circuits 100 arranged in a column whose output terminals are electrically coupled to each other share a common differential amplifier 150. In embodiments where the differential amplifier 150 utilizes a current mirror 160 at one of its input terminals, the data holding circuits 100 in the column also share a common current mirror 160. Figure 3B ), the current mirror 160 may be removed, and the second input terminal of the differential amplifier 150 - 1 may be connected (eg, directly connected) to the second STT stack 111 n of the data holding circuit 100 .

[0062] In some embodiments, the corresponding first STT stacks 111p of the column data retention circuit 100 are electrically connected to each other (e.g., by sharing a common first bit line) and to the first input of the differential amplifier 150, and the corresponding second STT stacks 111n thereof are electrically connected to each other (e.g., by sharing a common second bit line) and to the second input of the differential amplifier 150. In this manner, the first input of the differential amplifier 150 receives the sum of the first currents (e.g., Ip(i,j), Ip(i+1,j), etc.) from the first STT stacks of the column data retention circuit 100, and the second input of the differential amplifier 150 receives the sum of the second currents (e.g., In(i,j), In(i+1,j), etc.) from the second STT stacks of the column data retention circuit 100. The output current Io(j) of the differential amplifier 150 of the (j)th column data retention circuit 100 can be expressed by Equation 2:

[0063] Io(j)=∑ k [(Gp(k,j)-Gn(k,j))×Vin(k)] Equation 2

[0064] Wherein Gp(k,j) and Gn(k,j) represent the conductance (ie, the inverse of the resistance) of the first STT stack and the second STT stack of the data retention circuit 100(k,j) of the (k)th row and the (j)th column, respectively.

[0065] Sharing the common differential amplifier 150 (and the common current mirror) can save significant area and power consumption, and reduce overall manufacturing costs.

[0066] Thus, as described above, embodiments of the present invention implement two differential weights (Rp and Rn) in a single unit cell (e.g., of a neuromorphic system), thereby reducing or minimizing the area occupied by the differential weights and providing high noise tolerance differential reading due to paired bit storage. According to some embodiments, the data retention circuit 100 can be stacked in three dimensions, which can enable very large data storage (e.g., in the gigabyte range). Due to the relatively low voltages used, embodiments of the present invention can also be embedded in logic processes. In addition, no external magnetic field is required in this structure, thereby reducing the overhead of creating an external magnetic field.

[0067] Figure 5 is a flowchart illustrating a process S100 of writing complementary data into the data holding circuit 100 according to some example embodiments of the present invention.

[0068] refer to Figure 5 , the data holding circuit 100 may receive a first selection signal SELp and a second selection signal SELn indicating a data write operation (S102). In response to receiving the first selection signal SELp and the second selection signal SELn, the data holding circuit 100 may receive an input signal at its input terminal (S104). The data holding circuit 100 may then couple the opposite ends of the giant spin Hall metal 130 of the coupled giant spin Hall latch 110 to the input terminal of the data holding circuit 100 and the pull-down resistor Rpd via the first selection transistor 140 and the second selection transistor 142 (also referred to as the first transistor and the second transistor) to receive a charging current from the input terminal through the giant spin Hall metal 130 (S106). The data holding circuit 100 may then generate and store a complementary non-volatile spin state corresponding to the input signal through the coupled giant spin Hall latch in response to receiving the charging current from the input terminal (S108).

[0069] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the first element, component, region, layer, or part discussed below may be referred to as a second element, component, region, layer, or part without departing from the spirit and scope of the present invention.

[0070] In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0071] The professional terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present invention concept. As used herein, the singular form "one" is intended to also include the plural form, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of...", when preceding a list of elements, modify the entire list of elements without modifying the individual elements of the list. In addition, when describing an embodiment of the present invention concept, the use of "may" refers to "one or more embodiments of the present invention concept." In addition, the term "exemplary" is intended to refer to an example or illustration.

[0072] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to another element or layer, or one or more intervening elements or layers may be present. When an element or layer is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intervening elements or layers present.

[0073] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not terms of degree, and are intended to account for the inherent variations in measurements or calculations that would be recognized by those having ordinary skill in the art.

[0074] As used herein, the term "use" may be considered synonymous with the term "utilize."

[0075] Although the present invention has been described in detail with particular reference to illustrative embodiments thereof, the embodiments described herein are not intended to be exhaustive or to limit the scope of the invention to the precise forms disclosed. Those skilled in the art and technology to which the present invention pertains will appreciate that modifications and variations in the described structures and methods of assembly and operation may be practiced without meaningfully departing from the principles, spirit, and scope of the invention as set forth in the appended claims and their equivalents.

Claims

1. A non-volatile data retention circuit, comprising: a complementary latch configured to generate and store complementary nonvolatile spin states corresponding to an input signal when in a write mode, and to simultaneously generate a first charging current signal and a second charging current signal corresponding to the complementary nonvolatile spin states when in a read mode; a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first charging current signal and the second charging current signal; as well as A current mirror is coupled between the complementary latch and the differential amplifier and is configured to receive the second charging current signal and supply a reverse current signal having a polarity opposite to that of the second charging current signal to the differential amplifier.

2. The nonvolatile data retention circuit according to claim 1, wherein: The differential amplifier is a current sense amplifier.

3. The nonvolatile data retention circuit according to claim 1, wherein: The complementary latch comprises: a giant spin Hall metal configured to pass a charging current signal corresponding to the input signal; a first spin transfer torque stack located on a first side of the giant spin Hall metal; and a second spin transfer torque stack located on a second side of the giant spin Hall metal opposite to the first side, The first spin transfer torque stack and the second spin transfer torque stack extend along a direction orthogonal to an extension direction of the giant spin Hall metal and are configured to generate and store the complementary non-volatile spin states.

4. The nonvolatile data retention circuit according to claim 3, wherein: In response to the charge current signal flowing through the giant spin Hall metal, the first spin transfer torque stack is configured to exhibit a magnetic moment having a parallel configuration, and the second spin transfer torque stack is configured to exhibit a magnetic moment having an antiparallel configuration, and wherein the first spin transfer torque stack and the second spin transfer torque stack are configured to maintain their parallel configuration and anti-parallel configuration even when no power is supplied to the nonvolatile data retention circuit.

5. The nonvolatile data retention circuit according to claim 4, wherein: The parallel configuration of the first spin-transfer torque stack and the anti-parallel configuration of the second spin-transfer torque stack correspond to the complementary non-volatile spin states stored in the first spin-transfer torque stack and the second spin-transfer torque stack.

6. The nonvolatile data retention circuit according to claim 3, wherein: The giant spin Hall metal includes beta tantalum, platinum and / or copper bismuth.

7. The nonvolatile data retention circuit according to claim 3, wherein: Each of the first spin-transfer torque stack and the second spin-transfer torque stack comprises: a free layer comprising a magnetic material and configured to respond to a spin current signal corresponding to the charge current signal flowing through the giant spin Hall metal based on a giant spin Hall effect and to exhibit a free magnetic moment having a direction substantially orthogonal to the spin current signal; a fixed layer comprising a magnetic material and exhibiting a fixed magnetic moment that is not affected by a stray field generated from the charging current signal flowing through the giant spin Hall metal; and A nonmagnetic layer is between the free layer and the pinned layer and is configured to magnetically isolate a free magnetic moment of the free layer from a pinned magnetic moment of the pinned layer and maintain any existing directional difference between the free magnetic moment and the pinned magnetic moment.

8. The nonvolatile data retention circuit according to claim 7, wherein: In response to the charging current signal flowing through the giant spin Hall metal, the free layer of the first spin-transfer torque stack is configured to exhibit a first free magnetic moment parallel to the fixed magnetic moment of the fixed layer of the first spin-transfer torque stack, and the free layer of the second spin-transfer torque stack is configured to exhibit a second free magnetic moment antiparallel to the fixed magnetic moment of the fixed layer of the second spin-transfer torque stack.

9. The nonvolatile data retention circuit according to claim 3, further comprising: a first transistor coupled to the giant spin Hall metal and configured to be activated in response to a first selection signal; as well as a second transistor coupled to the giant spin Hall metal and configured to be activated in response to a second selection signal, wherein, when in the write mode, the first transistor and the second transistor are configured to be activated in response to the first selection signal and the second selection signal and to enable the charging current signal to flow through the giant spin Hall metal, and Wherein, when in the read mode, the second transistor is configured to be deactivated, and the first transistor is configured to be activated in response to the first selection signal and to enable the first charging current signal to flow through the first spin-transfer torque stack and to enable the second charging current signal to flow through the second spin-transfer torque stack.

10. The nonvolatile data holding circuit according to claim 9, in, The first transistor and the second transistor are coupled to opposite ends of the giant spin Hall metal, and The second transistor is configured to electrically couple the giant spin Hall metal to a pull-down resistor in response to the second selection signal.

11. The nonvolatile data retention circuit according to claim 3, wherein: The differential amplifier includes a first input terminal configured to receive the first charging current signal from the first spin-transfer torque stack, and a second input terminal configured to receive the second charging current signal from the second spin-transfer torque stack.

12. The nonvolatile data retention circuit according to claim 3, wherein: The current mirror is coupled between the second spin-transfer torque stack and the differential amplifier.

13. The nonvolatile data retention circuit according to claim 1, wherein: The complementary latch is configured to continue storing the complementary nonvolatile spin state even when no power is supplied to the nonvolatile data retention circuit.

14. The nonvolatile data retention circuit according to claim 1, wherein: The differential amplifier is directly coupled to opposite ends of the complementary latch through a first bit line and a second bit line, and is configured to receive the first charging current signal and the second charging current signal through the first bit line and the second bit line.

15. A data processing system comprising: a first complementary latch configured to generate and store a first complementary nonvolatile spin state corresponding to a first input signal when in a write mode, and to simultaneously generate a first charging current signal and a second charging current signal corresponding to the first complementary nonvolatile spin state when in a read mode; a second complementary latch configured to generate and store a second complementary nonvolatile spin state corresponding to a second input signal when in a write mode, and to simultaneously generate a third charging current signal and a fourth charging current signal corresponding to the second complementary nonvolatile spin state when in a read mode; a differential amplifier coupled to the first complementary latch and the second complementary latch and configured to generate an output signal based on the first to fourth charging current signals; as well as a current mirror coupled between the first complementary latch, the second complementary latch and the differential amplifier, and configured to receive the second charging current signal and the fourth charging current signal and supply a reverse current signal to the differential amplifier, the reverse current signal having a polarity opposite to that of the second charging current signal and the fourth charging current signal.

16. The data processing system according to claim 15, wherein: A first input terminal of the differential amplifier is configured to receive a sum of the first charging current signal and the third charging current signal from the first complementary latch and the second complementary latch.

17. The data processing system according to claim 15, wherein: The reverse current signal corresponds to the sum of the second charging current signal and the fourth charging current signal.

18. A method of writing complementary nonvolatile charge states to a data retention circuit, the method comprising: receiving a first selection signal and a second selection signal, wherein the first selection signal and the second selection signal indicate a data write operation; as well as In response to receiving the first selection signal and the second selection signal: receiving an input signal at an input terminal of the data holding circuit; coupling a first terminal of a giant spin Hall metal of the coupled giant spin Hall latch to an input terminal of the data holding circuit via a first transistor to receive a charging current signal from the input terminal through the giant spin Hall metal; In response to the second selection signal, coupling a second end of the giant spin Hall metal to a pull-down resistor coupled to ground via a second transistor; as well as In response to receiving the charging current signal from the input terminal, a complementary non-volatile spin state corresponding to the input signal is generated and stored by the coupled giant spin Hall latch.

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