Semiconductor device, contact pad layout thereof, contact pad structure and mask plate combination

Abstract

The present invention provides a semiconductor device, a contact pad layout thereof, a contact pad structure and a mask template combination. By providing a first edge layout area on one side of the main layout area where the main contact pad pattern is located, and the area of each of the first edge contact pad patterns in the first edge layout area is larger than the area of each of the main contact pad patterns, when forming the main contact pads in the core area and the virtual contact pads in the boundary area of the core area or the junction area between the core area and the peripheral area based on this contact pad layout, the top surface area of the virtual contact pads can be made larger than the top surface area of the main contact pads. Furthermore, when connecting electrical structures to the main contact pads and the virtual contact pads, the size of the electrical structures connected to the virtual contact pads can be increased, so as to improve the dense / sparse effect of the circuit patterns between the core area and the peripheral area, and improve the consistency of the electrical structures connected to the main contact pads. At the same time, the problem of abnormal electrical structures connected to the main contact pads at the boundary of the core area can also be avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device, a contact pad layout, a contact pad structure, and a mask combination thereof. Background Art

[0002] Various techniques have been used to integrate more circuit patterns in a limited area of a semiconductor substrate or wafer. Due to different circuit pattern pitches, integrated circuits are generally divided into a device-dense area (Dense), a device-sparse area (ISO), and a device-isolated area. The device-dense area is an area with a relatively high device density (i.e., devices are relatively dense), the device-sparse area is an area with a relatively low device density (i.e., devices are relatively sparse), and the device-isolated area is an area separately set relative to the sparse area and the dense area. As the critical dimension of semiconductor devices continues to decrease, the density of circuit patterns and / or the device height also continue to increase. Affected by the resolution limit of the optical exposure tool and the density difference effect between the device-dense area and the device-sparse area (i.e., the dense / sparse effect of circuit patterns), the difficulty in performing the lithography process and / or the etching process will increase significantly (for example, the process margin decreases), thereby affecting the performance of the manufactured semiconductor device.

[0003] For example, in the case of a dynamic random access memory (DRAM) device, a huge number of memory cells aggregate to form an array memory area, and there is a peripheral circuit area beside the array memory area. The peripheral circuit area contains other transistor elements and contact structures, etc. The array memory area, as the device-dense area of the DRAM, is used to store data, and the peripheral circuit area, as the device-sparse area of the DRAM, is used to provide input / output signals required by the array memory area, etc. Among them, each memory cell in the array memory area can be composed of a metal oxide semiconductor (MOS) transistor and a capacitor structure connected in series. Among them, the capacitor is located in the array memory area. Among them, the capacitor is stacked above the bit line and electrically coupled to the corresponding storage node contact portion of the capacitor, and the storage node contact portion is electrically coupled to the active area below it. With the continuous development of semiconductor technology, the critical dimension of the device is continuously reduced, and the gap between the memory cells of the DRAM device becomes narrower. When forming the storage node contact portion through the Self Aligned Contact (SAC) process, affected by the resolution limit of the optical exposure tool and the density difference effect between the device-dense area and the device-sparse area, the contact holes formed inside the array memory area are inconsistent, and the contact holes at the boundary of the device-dense area are abnormal, which in turn leads to a decrease in the contact area between the capacitor formed above and the contact plug in the contact hole and an increase in the contact impedance, possibly causing some storage bits to fail due to the open or short circuit problem of the contact plug, and, the problem of the capacitor collapse at the boundary of the array memory area. These problems affect and limit the improvement of DRAM performance. Summary of the Invention

[0004] The purpose of the present invention is to provide a semiconductor device, its contact pad layout, contact pad structure and mask plate combination to solve the problems that the electrical structures connected to the contact plugs inside the core area are inconsistent and the electrical structures connected to the contact plugs at the boundary of the core area are abnormal in existing semiconductor devices such as dynamic random access memories due to optical proximity effects and dense / sparse effects of circuit patterns.

[0005] To solve the above technical problems, the present invention provides a contact pad layout of a semiconductor device, and the contact pad layout includes:

[0006] A main layout area, in which a plurality of main contact pad patterns are provided. The shapes and sizes of the main contact pad patterns are similar, and all the main contact pad patterns are arranged in a checkerboard-like staggered manner, and there is a fourth spacing between the main contact pad patterns;

[0007] A first edge layout region is distributed outside one side of the main layout region. At least one first edge contact pad pattern is provided in the first edge layout region, and the area of each first edge contact pad pattern is larger than the area of each main contact pad pattern. There is a first edge spacing between the first edge layout region and the main layout region;

[0008] Wherein, the first edge contact pad pattern is different from the main contact pad pattern, and the first edge spacing is different from the fourth spacing.

[0009] Based on the same inventive concept, the present invention also provides a contact pad structure formed by using the contact pad layout of the semiconductor device of the present invention, including:

[0010] A plurality of main contact pads are arranged in a checkerboard pattern and staggered. The shapes and sizes of the main contact pads are similar, and there is a fourth spacing between the main contact pads;

[0011] At least one first edge contact pad is distributed outside one side of the arrangement area of all the main contact pads, and the top surface area of each first edge contact pad is larger than the top surface area of each main contact pad. There is a first edge spacing between the first edge contact pad adjacent to the main contact pad and the main contact pad;

[0012] Wherein, the size of the first edge contact pad is different from the size of the main contact pad, and the first edge spacing is different from the fourth spacing.

[0013] Based on the same inventive concept, the present invention also provides a semiconductor device, including:

[0014] A semiconductor substrate, the semiconductor substrate has a core region, and a plurality of core components are formed in the core region;

[0015] An interlayer dielectric layer covering the semiconductor substrate;

[0016] The contact pad structure of the semiconductor device as described in the present invention is formed in the interlayer dielectric layer;

[0017] A plurality of contact plugs are formed in the interlayer dielectric layer, and each contact plug is aligned with the corresponding contact pad in the contact pad structure to electrically connect the corresponding contact pad and the active region of the core component.

[0018] Based on the same inventive concept, the present invention also provides a mask set for manufacturing the contact pad structure of the semiconductor device of the present invention, including:

[0019] The first mask plate has multiple parallel first lines. There is a first interval region between two adjacent first lines. The line width of at least one first line on the outermost side of the first mask plate is greater than that of other first lines, and the line width of at least one first interval region on the outermost side of the first mask plate is greater than that of other first interval regions;

[0020] The second mask plate has multiple parallel second stripes that intersect each first line. There is a second interval region between two adjacent second lines. The line width of at least one second line on the outermost side of the second mask plate is greater than that of other second lines, and the line width of at least one second interval region on the outermost side of the second mask plate is greater than that of other second interval regions;

[0021] Wherein, when the first mask plate and the second mask plate are of the same-sex mask plates and the second mask plate and the first mask plate are aligned and overlapped, the overlapping region of the first line and the second line is the region for forming the contact pad; when the first mask plate and the second mask plate are of opposite-sex mask plates and the second mask plate and the first mask plate are aligned and overlapped, the overlapping region of the first line and the second interval region is the region for forming the contact pad.

[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0023] By providing a first edge layout region on one side of the main layout region where the main contact pad pattern is located, and the area of each first edge contact pad pattern in the first edge layout region is greater than the area of each main contact pad pattern. Thus, when forming the main contact pad of the core region based on this contact pad layout, the first edge contact pad pattern can be used to form corresponding virtual contact pads at the boundary of the core region or in the junction region between the core region and the peripheral region, and the top surface area of the virtual contact pad is greater than the top surface area of the main contact pad. Therefore, it is possible to increase the size of the electrical structure connected to the virtual contact pad subsequently, and when connecting the electrical structure to the main contact pad and the virtual contact pad, it can improve the dense / sparse effect of the circuit pattern between the core region and the peripheral region, improve the consistency of the electrical structure connected to the main contact pad inside the core region, and at the same time avoid the problem of abnormal electrical structure connected to the main contact pad at the boundary of the core region, improving the performance of the finally formed semiconductor device. Description of the Drawings

[0024] Figure 1 is a schematic structural diagram of a contact pad layout according to an embodiment of the present invention;

[0025] Figure 2 is a schematic structural diagram of a contact pad layout according to another embodiment of the present invention;

[0026] Figure 3It is a schematic structural diagram of the contact pad layout of another embodiment of the present invention;

[0027] Figure 4A It is a schematic structural diagram of the contact pad structure of an embodiment of the present invention;

[0028] Figure 4B It is a schematic structural diagram of the contact pad structure of another embodiment of the present invention;

[0029] Figure 5A It is a schematic structural diagram of the first mask in the mask combination of an embodiment of the present invention;

[0030] Figure 5B It is a schematic structural diagram of the second mask in the mask combination of an embodiment of the present invention;

[0031] Figure 6 It is a schematic structural diagram of the superposition of two masks when both the first mask and the second mask in the mask combination of an embodiment of the present invention are positive masks;

[0032] Figure 7 It is a schematic structural diagram of the superposition of two masks when the first mask in the mask combination of an embodiment of the present invention is a positive mask and the second mask is a negative mask;

[0033] Figures 8A to 8D It is a schematic structural diagram during the process of transferring the pattern in the first mask or the second mask to the layer to be etched in an embodiment of the present invention;

[0034] Figures 9A to 9D It is a schematic structural diagram during the process of transferring the pattern in the first mask or the second mask to the layer to be etched in another embodiment of the present invention;

[0035] Figure 10A It is a top view structural diagram in the manufacturing method of a semiconductor device according to an embodiment of the present invention;

[0036] Figure 10B 、 Figures 11 to 12 respectively are the cross-sectional structural diagrams along the Figure 9A aa' line in the manufacturing method of a semiconductor device according to an embodiment of the present invention. Detailed Embodiments

[0037] The following further describes in detail the memory and its forming method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0038] Please refer to Figure 1, an embodiment of the present invention provides a contact pad layout of a semiconductor device. The contact pad layout includes a main layout area 10 and a first edge layout area 11. Among them, a plurality of main contact pad patterns 101 are provided in the main layout area 10. The shapes and sizes of the respective main contact pad patterns 101 are similar, and all the main contact pad patterns 101 are arranged in a checkerboard pattern and staggered. There is a fourth pitch D4 between adjacent two rows of the main contact pad patterns 101, and a fifth pitch D5 between adjacent two columns of the main contact pad patterns 101. D4 may be equal to D5, or D4 may not be equal to D5. The first edge layout area 11 is distributed outside one side of the main layout area 10. A plurality of first edge contact pad patterns arranged in two rows along the direction of the one side of the main layout area 10 are provided in the first edge layout area 11. That is, in this embodiment, there is a row of first edge contact pad patterns 111 and a row of first edge contact pad patterns 112 in the first edge layout area 11. There is a sixth pitch D6 between the two rows of first edge contact pad patterns 111 and 112. A row of first edge contact pad patterns 112 is relatively close to the main layout area 10, and the shapes and sizes of the respective first edge contact pad patterns 112 in this row may be the same or may not be completely the same. A row of first edge contact pad patterns 111 is relatively far from the main layout area 10, and the shapes and sizes of the respective first edge contact pad patterns 111 in this row may be the same or may not be completely the same. The respective first edge contact pad patterns 111 and 112 are aligned with the corresponding main contact pad patterns 101 in the main layout area 10 (for example, aligned by column). The pitch between the row of first edge contact pad patterns 112 closest to the main layout area 10 and its nearest row of main contact pad patterns 101 is the first edge pitch D1 (that is, there is a first edge pitch D1 between the first edge layout area 11 and the main layout area 10). The area of each of the first edge contact pad patterns 111 and 112 is larger than the area of each of the main contact pad patterns 101. The first edge contact pad patterns 111 and 112 are all different from the main contact pad patterns 101 (for example, the areas of the respective first edge contact pad patterns 111 and 112 are larger than the area of the main contact pad pattern 101). The first edge pitch D1 is different from the fourth pitch D4, and the sixth pitch D6 is different from the fourth pitch D4 and the first edge pitch D1. For example, D6 is greater than D1, and D1 is greater than D4.

[0039] Optionally, please continue to refer to Figure 1, the contact pad layout of this embodiment further includes a second edge layout area 12, which is distributed outside the adjacent side of the side of the main layout area 10. A plurality of second edge contact pad patterns 121 and / or 122 are provided in the second edge layout area 12, and each of the second edge contact pad patterns 121, 122 is different from the main contact pad pattern 101, and the area of each of the second edge contact pad patterns 121, 122 is larger than the area of each of the main contact pad patterns 101. There is a second edge spacing D2 between the second edge layout area 12 and the main layout area 10. The second edge spacing D2 is different from the fourth spacing D4, different from the fifth spacing D5, and may also be different from the first edge spacing D1. In addition, the second edge contact pad patterns 121, 122 in the second edge layout area 12 are aligned and arranged with the corresponding main contact pad patterns 101 and the first edge contact pad patterns 111, 112 in the main layout area 10. For example, all the second edge contact pad patterns 121, 122 in the second edge layout area 12 are further arranged in two columns along the direction of the adjacent side. The column closer to the main layout area 10 is the second edge contact pad pattern 121, and the column farther from the main layout area 10 is the second edge contact pad pattern 122. The second edge contact pad patterns 121, 122 in each column may not be exactly the same. And the spacing between the column of the second edge contact pad patterns 121 closest to the main layout area 10 and the column of the main contact pad patterns 101 closest to it is the second edge spacing D2. There is a third spacing D3 between the two columns of the second edge contact pad patterns 121, 122. The third spacing D3 is larger than the second edge spacing D2 and also larger than the fifth spacing D5. Optionally, in the second edge layout area 12, the shapes of the second edge contact pad patterns 122 in the column farther from the main layout area 10 include at least two of a long strip shape, a U shape laid down to the left, a U shape laid down to the right, an L shape laid down to the left, an L shape laid down to the right, and a comb shape having at least two comb teeth.

[0040] Please refer to Figure 2, Another embodiment of the present invention provides a contact pad layout of a semiconductor device. The contact pad layout includes a main layout area 10, a first edge layout area 11, and a second edge layout area 12. Among them, a plurality of main contact pad patterns 101 are provided in the main layout area 10. The shapes and sizes of the respective main contact pad patterns 101 are similar, and all the main contact pad patterns 101 are arranged in a checkerboard pattern in a staggered manner. There is a fourth spacing D4 between adjacent rows of the main contact pad patterns 101, and a fifth spacing D5 between adjacent columns of the main contact pad patterns 101. D4 may be equal to D5, or D4 may not be equal to D5. The first edge layout area 11 is distributed outside one side of the main layout area 10. A long strip with a serrated edge is provided in the first edge layout area 11 to serve as the first edge contact pad pattern 111. Optionally, the serrated edge faces the main layout area 10, and each serration 111a in the serrated edge is aligned with a corresponding main contact pad pattern 101 in the main layout area 10 (for example, each serration 111a and the corresponding main contact pad pattern 101 are aligned in columns). The spacing between the serration 111a and the nearest adjacent main contact pad pattern 101 that is aligned is the first edge spacing D1., that is, in this embodiment, only one row of first edge contact pad patterns 111 is provided in the first edge layout area 11, and this row of first edge contact pad patterns 111 is connected as a whole. The shapes and sizes of each serration may be all the same or may not be completely the same, and the spacings of the serrations 111a are not completely the same. The area of each serration may be less than, equal to, or greater than the area of each main contact pad pattern 101, and the first edge spacing D1 is different from the fourth spacing D4. The second edge layout area 12 is distributed outside the adjacent side of the side of the main layout area 10. A plurality of second edge contact pad patterns 121 and / or 122 are provided in the second edge layout area 12, and each of the second edge contact pad patterns 121, 122 is different from the main contact pad pattern 101, and the area of each of the second edge contact pad patterns 121, 122 is greater than the area of each main contact pad pattern 101. There is a second edge spacing D2 between the second edge layout area 12 and the main layout area 10. The second edge spacing D2 is different from the fourth spacing D4, different from the fifth spacing D5, and may also be different from the first edge spacing D1.In addition, the corresponding second edge contact pad patterns 121 and 122 in the second edge layout area 12 are aligned with the corresponding main contact pad patterns 101 in the main layout area 10, and the remaining second edge contact pad patterns 121 and 122 are aligned with the first edge contact pad patterns 111. For example, the corresponding second edge contact pad patterns 121 and 122 in the second edge layout area 12 are further arranged in two columns along the direction of the adjacent side. The column close to the main layout area 10 is the second edge contact pad pattern 121, and the column far from the main layout area 10 is the second edge contact pad pattern 122. The second edge contact pad patterns 121 and 122 in each column may not be exactly the same. The distance between the column of the second edge contact pad pattern 121 closest to the main layout area 10 and the column of the main contact pad pattern 101 closest to it is the second edge distance D2. There is a third distance D3 between the two columns of the second edge contact pad patterns 121 and 122. The third distance D3 is greater than the second edge distance D2 and also greater than the fifth distance D5. In this embodiment, the second edge contact pad pattern 121 is a horizontal long strip structure, and its length extends along the row direction of the main layout area 10. The second edge contact pad pattern 122 is a vertical long strip structure, and its length extends along the column direction of the main layout area 10.

[0041] Please refer to Figure 3 , Another embodiment of the present invention provides a contact pad layout of a semiconductor device. The contact pad layout includes a main layout area 10, a first edge layout area 11, and a second edge layout area 12. The structure in the main layout area 10 in this embodiment can be the same as Figure 1 or Figure 2The structures of the layout regions 10 in the illustrated embodiments are the same and will not be described herein again. The first edge layout region 11 is distributed outside one side of the main layout region 10. There are two rows of structures in the first edge layout region 11. In the row close to the main layout region 10, there are a plurality of first edge contact pad patterns 112. In the row far from the main layout region 10, there is a long strip with a serrated edge as the first edge contact pad pattern 111. Optionally, the serrated edge faces the main layout region 10. Each serration 111a in the serrated edge and the corresponding first edge contact pad pattern 112 are aligned with the corresponding main contact pad pattern 101 in the main layout region 10 (for example, each serration 111a, the first edge contact pad pattern 112, and the corresponding main contact pad pattern 101 are aligned in columns). The distance between the first edge contact pad pattern 112 and the nearest aligned main contact pad pattern 101 is the first edge distance D1 (that is, the row distance between a row of first edge contact pad patterns 112 and its nearest adjacent row of main contact pad patterns 101 is the first edge distance D1). The row distance between a row of first edge contact pad patterns 112 and a row of first edge contact pad patterns 111 with a serrated edge is the sixth distance D6. Among them, the first edge contact pad patterns 111 are connected as a whole. The shapes and sizes of the individual serrations 111a can be the same or not completely the same, and the distances between the serrations 111a can be not completely the same or the same. The area of each serration 111a can be less than, equal to, or greater than the area of each main contact pad pattern 101. The first edge distance D1 is different from the fourth distance D4, and the sixth distance D1 is different from the first edge distance D1. The second edge layout region 12 is distributed outside the adjacent side of the side of the main layout region 10. There are a plurality of second edge contact pad patterns 121 and / or 122 in the second edge layout region 12. And each of the second edge contact pad patterns 121, 122 is different from the main contact pad pattern 101, and the area of each of the second edge contact pad patterns 121, 122 is greater than the area of each main contact pad pattern 101. There is a second edge distance D2 between the second edge layout region 12 and the main layout region 10. The second edge distance D2 is different from the fourth distance D4, different from the fifth distance D5, and can also be different from the first edge distance D1.In addition, the corresponding second edge contact pad patterns 121 and 122 in the second edge layout region 12 are arranged in alignment with the corresponding main contact pad patterns 101 in the main layout region 10, and the remaining second edge contact pad patterns 121 and 122 are arranged in alignment with the first edge contact pad patterns 111. For example, the corresponding second edge contact pad patterns 121 and 122 in the second edge layout region 12 are further arranged in two columns along the direction of the adjacent side. The column closer to the main layout region 10 is the second edge contact pad pattern 121, and the column farther from the main layout region 10 is the second edge contact pad pattern 122. The second edge contact pad patterns 121 and 122 in each column may not be completely the same. The distance between the column of the second edge contact pad patterns 121 closest to the main layout region 10 and the column of the main contact pad patterns 101 closest to it is the second edge distance D2. There is a third distance D3 between the two columns of the second edge contact pad patterns 121 and 122. The third distance D3 is greater than the second edge distance D2 and also greater than the fifth distance D5. In this embodiment, the second edge contact pad patterns 121 are all in the form of horizontal long strips, and their lengths extend along the row direction of the main layout region 10. The shapes of the second edge contact pad patterns 122 include at least two of a long strip shape, a U shape laid down to the left, a U shape laid down to the right, an L shape laid down to the left, an L shape laid down to the right, and a comb shape having at least two comb teeth.

[0042] In the contact pad layout of the semiconductor device according to the embodiments of the present invention, the main layout area corresponds to the effective area of the core area of the semiconductor device or the entire area of the core area of the semiconductor device, and each main contact pad pattern is used to fabricate the main contact pads in the core area of the semiconductor device. The first edge layout area and the second edge layout area respectively correspond to the boundary at the corresponding side of the core area or the junction area between the core area of the semiconductor device and the peripheral area of the semiconductor device on the corresponding side. The first edge contact pad pattern and the second edge contact pad pattern are both used to fabricate the dummy contact pads at the boundary at the corresponding side of the core area of the semiconductor device or in the junction area. Since the area of each of the first edge contact pad patterns in the first edge layout area is larger than the area of each of the main contact pad patterns, and the area of each of the second edge contact pad patterns in the second edge layout area is larger than the area of each of the main contact pad patterns, therefore, when forming the main contact pads in the core area based on the contact pad layout according to the embodiments of the present invention, the first edge contact pad pattern and the second edge contact pad pattern can be used to form the corresponding dummy contact pads, and the top surface area of the formed dummy contact pads is larger than the top surface area of the formed main contact pads. Thus, the size of the electrical structure connected to the dummy contact pads subsequently can be increased, and the dense / sparse effect of the circuit pattern between the core area and the peripheral area can be improved when the electrical structure is connected to the main contact pads and the dummy contact pads, thereby improving the consistency of the electrical structure connected to the main contact pads inside the core area, and at the same time, the problem of abnormal electrical structure connected to the main contact pads at the boundary of the core area can be avoided, and the performance of the finally formed semiconductor device is improved.

[0043] Please refer to Figures 1 to 3 and Figure 4A , based on the same inventive concept, an embodiment of the present invention further provides a contact pad structure formed by using the contact pad layout of the semiconductor device shown in any one of Figures 1 to 3 . The contact pad structure includes: a plurality of main contact pads 101a and at least one first edge contact pad 111b. Each of the main contact pads 101a is fabricated based on the corresponding main contact pad pattern 101 in the main layout area 10, and is located in the core area I of the semiconductor device and is arranged in a checkerboard pattern in a staggered manner. The shapes and sizes of the main contact pads 101a are similar, and there is a fourth spacing D4 between the main contact pads 101a. Each of the main contact pads 101a is used to connect to a capacitor (such as Figure 11Effective electrical structures such as 705b) therein. Each of the first edge contact pads 111b is fabricated based on the first edge contact pad pattern 111 or based on the first edge contact pad patterns 111 and 112, and is distributed on the outer side of one side of all the main contact pad arrangement regions. Moreover, the top surface area of each of the first edge contact pads 111b is larger than the top surface area of each of the main contact pads (furthermore, the cross-sectional area of each of the first edge contact pads 111b is larger than the cross-sectional area of each of the main contact pads). There is a first edge spacing D1 between the first edge contact pad 111b (fabricated based on the first edge contact pad pattern 111) adjacent to the main contact pad 101a and the main contact pad 101a. Among them, the size of the first edge contact pad 111b is different from the size of the main contact pad 101a, and the first edge spacing D1 is different from the fourth spacing D4. In this embodiment, each of the first edge contact pads 111b is distributed at the boundary of the core region I, and electrically connects at least the outermost two source / drain regions S / D1 at the boundary of the core region I together (for example Figure 11 as shown, each of the first edge contact pads 501b straddles the word line at the boundary of the core region I and the two source / drain regions S / D1 on both sides thereof). The first edge contact pad 111b can be used as a dummy contact pad. Since the top surface area of each of the first edge contact pads 111b is larger than the top surface area of each of the main contact pads 101a, it is possible to increase the size of the electrical structure connected to the first edge contact pad 111b relative to the size of the electrical structure connected to the main contact pad 101a (as Figure 11 shown, the size of the capacitor 705b is larger than that of the capacitor 705a), so as to reduce the contact resistance between the first edge contact pad 111b and the electrical structure connected thereto, enhance the device reliability. More importantly, when corresponding electrical structures are respectively connected to the main contact pad 101a and the first edge contact pad 111b, the relatively increased size of the electrical structure connected to the first edge contact pad 111b can be utilized to improve the dense / sparse effect of the circuit pattern between the core region I and the peripheral region II, thereby improving the consistency between the electrical structures connected to all the main contact pads 101a inside the core region I. At the same time, it can also avoid the problem of abnormality of the electrical structure connected to the main contact pad 101a at the boundary of the core region I (i.e., each main contact pad 101a adjacent to each first edge contact pad 111b), and improve the performance of the finally formed semiconductor device.

[0044] Please refer to Figures 1 to 3 and Figure 4B In addition, another embodiment of the present invention also provides a method of using Figures 1 to 3The contact pad structure formed by the contact pad layout of the semiconductor device shown in any one of the following, the contact pad structure includes: a plurality of main contact pads 101a and at least one first edge contact pad 111b. Each main contact pad 101a is made based on the corresponding main contact pad pattern 101 in the main layout area 10, and is located in the core area I of the semiconductor device and arranged in a checkerboard pattern in a staggered manner. The shapes and sizes of the main contact pads 101a are similar, and there is a fourth spacing D4 between the main contact pads 101a. Each main contact pad 101a is used to connect to an effective electrical structure such as a capacitor (such as Figure 11 705b) in. Each first edge contact pad 111b is made based on the first edge contact pad pattern 111 or based on the first edge contact pad patterns 111 and 112, and is distributed outside one side of all the main contact pad arrangement areas. And the top surface area of each first edge contact pad 111b is larger than the top surface area of each main contact pad (furthermore, the cross-sectional area of each first edge contact pad 111b is larger than the cross-sectional area of each main contact pad). The first edge contact pad 111b (made based on the first edge contact pad pattern 111) adjacent to the main contact pad 101a has a first edge spacing D1 from the main contact pad 101a. Among them, the size of the first edge contact pad 111b is different from the size of the main contact pad 101a, and the first edge spacing D1 is different from the fourth spacing D4. In this embodiment, each of the first edge contact pads 111b is distributed on the junction area III between the core area I and the peripheral area II, and is electrically connected to at least one source / drain region S / D1 at the boundary of the core area I (for example Figure 12 As shown, each first edge contact pad 501b extends from the junction area III to the outermost source / drain region S / D1 at the boundary of the core area I, connecting the shallow trench isolation structure STI401a in the junction area III and the source / drain region S / D1 adjacent to the shallow trench isolation structure STI401a). The first edge contact pad 111b can be used as a virtual contact pad. Since the top surface area of each first edge contact pad 111b is larger than the top surface area of each main contact pad 101a, therefore, it can make the size of the electrical structure connected to the first edge contact pad 111b subsequently larger than the size of the electrical structure connected to the main contact pad 101a (such as Figure 11The size of the capacitor 705b shown in the figure is larger than that of the capacitor 705a). Thus, when connecting corresponding electrical structures to the main contact pad 101a and the first edge contact pad 111b respectively, the size of the electrical structure connected to the first edge contact pad 111b can be relatively increased, so as to improve the dense / sparse effect of the circuit pattern between the core region I and the peripheral region II, thereby improving the consistency between the electrical structures connected to all the main contact pads 101a inside the core region I. At the same time, it can also avoid the problem of abnormal electrical structures connected to the main contact pads 101a at the boundary of the core region I (i.e., the main contact pads 101a adjacent to each first edge contact pad 111b), and improve the performance of the finally formed semiconductor device. In addition, it should be noted that in other embodiments of the present invention, all the first edge contact pads 111b can also be entirely located on the junction region III as a whole. In the case where at least a part of each first edge contact pad 111b is formed on the junction region III, on the one hand, the occupied area of the first edge contact pad 111b and the electrical structure connected thereto in the core region I can be minimized, which is beneficial to improving the effective area utilization rate of the core region and further beneficial to improving the device density; on the other hand, the size of the first edge contact pad 111b and the electrical structure connected thereto can be increased as much as possible, so as to have a better effect in improving the consistency between the electrical structures connected to all the main contact pads 101a inside the core region I and other aspects.

[0045] It should be noted that when the contact pad structure in each embodiment of the present invention is made based on Figure 1 the shown contact pad layout, the number of the first edge contact pads 111b is multiple, and they are arranged in two rows along the direction of one side of the arrangement area of the main contact pads 101a (i.e., the area within the boundary of the core region I, which can be called the central region or the internal region of the core region I). Each of the first edge contact pads 111b is aligned with the corresponding main contact pad 101a. The distance between the row of the first edge contact pads 111b closest to the arrangement area of the main contact pads 101a (i.e., the first edge contact pads 111b formed based on the first edge contact pad pattern 112) and the nearest row of the main contact pads 101a is the first edge distance D1. And when the contact pad structure in each embodiment of the present invention is made based on Figure 2 or Figure 3 the shown contact pad layout, the first edge contact pad 111b includes a long strip with a serrated edge (not shown), that is, corresponding to Figure 2 or Figure 3The first edge contact pad pattern 111 therein, optionally, the serrated edge faces the arrangement area of the main contact pad 101a, each serration in the long serrated edge is aligned with the corresponding main contact pad 101a, and the distance between the serration of the long strip and the nearest main contact pad 101a aligned therewith is the first edge distance D1.

[0046] In addition, optionally, please refer to Figures 1 to 3 As shown, the contact pad structure of each embodiment of the present invention may further include a plurality of second edge contact pads (not shown), and the second edge contact pads are formed based on the second edge contact pad patterns 121 and 122 in the second edge layout area 12. The second edge contact pads are distributed outside the adjacent side of the side of all the main contact pad arrangement areas, and the top surface area of each second edge contact pad is larger than the top surface area of each main contact pad (further, the cross-sectional area of each second edge contact pad is larger than the cross-sectional area of each main contact pad). There is a second edge distance D2 between the second edge contact pad (i.e., the second edge contact pad formed based on the second edge contact pad pattern 121) adjacent to the main contact pad and the main contact pad. The shape of the second edge contact pad is different from the shape of the first edge contact pad, and the second edge distance D2 is different from the fourth distance D4. Optionally, each of the second edge contact pads is aligned with the corresponding main contact pad. For example, all the second edge contact pads are arranged in two columns along the direction of the adjacent side, and the distance between the column of the second edge contact pads closest to the main contact pad arrangement area and the column of the main contact pads closest to them is the second edge distance D2. There is a third distance D3 between the two columns of the second edge contact pads, and the third distance D3 is greater than the second edge distance D2. Optionally, among all the second edge contact pads, the cross-sectional shape (or top surface shape) of the second edge contact pads in the column far from the main contact pad arrangement area includes at least two of a long strip shape, a U shape laid down to the left, a U shape laid down to the right, an L shape laid down to the left, an L shape laid down to the right, and a comb shape having at least two comb teeth.

[0047] In addition, please refer to Figure 4A and Figure 4B, in the contact pad structure of the semiconductor device according to the embodiments of the present invention, the main contact pad 101a, the first edge contact pad 101b, and the second edge contact pad can be formed simultaneously with the contact pad 105 in the peripheral region II. The main contact pad 101a is connected to the corresponding active region AA1 (i.e., the corresponding source / drain region S / D1) in the core region I through the corresponding contact plug 103a. The first edge contact pad 101b and the second edge contact pad are connected to the corresponding active region AA1 (i.e., the corresponding source / drain region S / D1) at the boundary of the core region I or connected to the shallow trench isolation structure 100a in the junction region III through the corresponding contact plug 103b. The contact pad 105 is connected to the corresponding source / drain region S / D2 in the peripheral region IT through the contact plug 103c. Among them, each contact pad is formed by the same filling process; and each contact pad and its contacted contact plug can be separately and individually fabricated, or can be formed by the same metal filling process. Among them, when each contact pad and its contacted contact plug are separately and individually fabricated, the interlayer dielectric layer 102 can be first deposited, etched, filled with metal, and planarized to form the contact plugs 103a, 103b, and 103c in one step, and then the interlayer dielectric layer 104 can be deposited, etched, filled with metal, and planarized to form the main contact pad 101a, the first edge contact pad 111b, the second edge contact pad, and the contact pad 105 in one step. When each contact pad and its contacted contact plug are formed by the same metal filling process, a relatively thick interlayer dielectric layer (for example, its thickness is equal to the sum of the thickness of the interlayer dielectric layer 102 and the interlayer dielectric layer 104) can be deposited at one time, and then the channels communicating with each contact pad and its contacted contact plug are formed through corresponding etching processes, etc. After that, the channels are filled with metal and planarized, so as to form the contact plugs 103a, 103b, and 103c, as well as the main contact pad 101a, the first edge contact pad 111b, the second edge contact pad, and the contact pad 105 in one step. At this time, the main contact pad 101a and its contacted contact plug 103a are integrally formed, the first edge contact pad 111b and its contacted contact plug 103b are integrally formed, the second edge contact pad and its contacted contact plug 103b are integrally formed, and the contact pad 105 and its contacted contact plug 103c are integrally formed.

[0048] Please refer to Figures 1 to 3 and Figures 4A to 4B, based on the same inventive concept, an embodiment of the present invention further provides a semiconductor device, including: a semiconductor substrate 100, an interlayer dielectric layer, and a contact pad structure of the semiconductor device as described in the present invention. Among them, the semiconductor substrate has a core region I, a peripheral region II, and a junction region III located between the core region I and the peripheral region II. A plurality of core components are formed in the core region I. Each core component is formed on a corresponding active region AA1, and a shallow trench isolation structure (STI) 100b is formed between adjacent active regions AA1. Each core component can be a MOS transistor, having a buried gate formed in the corresponding active region AA1 and source / drain regions S / D1 located on both sides of the buried gate. The interlayer dielectric layer has an interlayer dielectric layer 102 and an interlayer dielectric layer 104 that sequentially cover the semiconductor substrate 100. A shallow trench isolation structure (STI) 100a for isolating the core region I and the peripheral region II is formed in the junction region III. The contact pad structure is formed in the interlayer dielectric layer 104 and at least includes a main contact pad 101a and a first edge contact 111b, and may further include a second edge contact pad. The semiconductor device further includes contact plugs connected to the bottom of each contact pad and electrical structures (such as capacitors or resistors, etc.) connected to the top of each contact pad. Each contact plug 103a, 103b, 103c is formed in the interlayer dielectric layer 102. Each contact plug 103a is disposed to align with the bottom of the corresponding main contact pad 101a and the active region AA1 (i.e., the corresponding source / drain region S / D1) of the corresponding core component, so as to electrically connect the corresponding main contact pad 101a and the active region AA1 of the core component. The top of each contact plug 103b aligns with the bottom of the corresponding first edge contact pad 111b or the second edge contact pad, and the bottom of each contact plug 103b aligns with the active region AA1 (i.e., the corresponding source / drain region S / D1) at the boundary of the core region I or the STI 100a in the junction region III, so as to connect the corresponding first edge contact pad 111b or the second edge contact pad and the active region AA1 at the boundary of the core region I or the STI 100a in the junction region III.

[0049] Please refer to Figure 5A and Figure 5B, based on the same inventive concept, the present invention also provides a mask plate combination for manufacturing a contact pad structure of the semiconductor device described in the present invention, including: a first mask plate 20 and a second mask plate 30. Among them, the first mask plate 20 has a plurality of parallel first lines 201, and the space between two adjacent first lines 201 is a first interval region 202. And the line width of at least one first line 201 on the outermost side of the first mask plate 20 is greater than that of other first lines 201, and the line width of at least one first interval region 202 on the outermost side of the first mask plate 20 is greater than that of other first interval regions 202. For example, the line widths of the two outermost first lines 201 (i.e., the outermost first line 201a and the second first line 201b) of the first mask plate 20 are both greater than those of other first lines 201, the line width of the first line 201a is greater than the line width of the first line 201b, the line width D6 of the first interval region 202 (i.e., a first interval region 202 on the outermost side of the first mask plate 20) between the first lines 201a and 201b is greater than the line widths of other first interval regions 202, and the line width D1 of the first interval region 202 between the first line 201b and another adjacent first line 201 is different from the line width D4 of other first interval regions 202 except the first interval region 202 between the first lines 201a and 201b. The second mask plate 30 has a plurality of parallel second stripes 301 that are perpendicular to and intersect each first line 201. The space between two adjacent second stripes 301 is a second interval region 302. And the line width of at least one second stripe 301 on the outermost side of the second mask plate 30 is greater than that of other second stripes 301, and the line width of at least one second interval region 302 on the outermost side of the second mask plate 30 is greater than that of other second interval regions 302. For example, the line widths of the two outermost second stripes (i.e., the outermost first second stripe 301a and the second second stripe 301b) of the second mask plate 30 are both greater than those of other second stripes 301, the line width of the second stripe 301a is greater than the line width of the second stripe 301b, the line width of the second interval region 302 (i.e., a second interval region 302 on the outermost side of the second mask plate 30) between the second stripes 301a and 301b is greater than the line widths of other second interval regions 302, and the line width of the second interval region 302 between the second stripe 301b and another adjacent second stripe 301 is different from the line widths of other second interval regions 302 except the second interval region 302 between the second stripes 301a and 301b. Optionally, in the second mask plate 30, the line width of the end 303 of all other second stripes 301 except the first second stripe 301a and the second second stripe 301b is greater than the line width of the middle region of the second stripe 301.

[0050] Among them, please refer to Figure 6, when the first mask 20 and the second mask 30 are of the same-sex mask and the second mask 30 and the first mask 20 are aligned and overlapped, the overlapping area of each first line 201 and each second line 301 is the area for forming the contact pads. Thus, the overlapping area of the first line 201a and each second line 301 except the second lines 301a and 301b defines Figure 1 each first edge contact pad pattern 111 in the first edge layout area 11 in Figure 1 ; the overlapping area of the first line 201b and each second line 301 except the second lines 301a and 301b defines Figure 1 each first edge contact pad pattern 112 in the first edge layout area 11 in Figure 1 ; the overlapping area of the second line 301a and each first line 201 except the first lines 201a and 201b defines Figure 1The main layout area 10 therein and each main contact pad pattern 101 therein. The first spacing region 202 between the first line 201b and the first line 201 adjacent to its inner side defines the first edge spacing D1 between the first edge layout area 11 and the main layout area 10. The line width of the first spacing region 202 between the first line 201b and the first line 201a adjacent to its outer side defines the sixth spacing D6 between two rows of first edge contact pad patterns 111, 112 in the first edge layout area 11. The remaining first spacing regions 202 define the fourth spacing D4 between two rows of main contact pad patterns. The second spacing region 302 between the second line 301b and the second line 301 adjacent to its inner side defines the second edge spacing D2 between the second edge layout area 12 and the main layout area 10. The line width of the second spacing region 302 between the second line 301b and the second line 301a adjacent to its outer side defines the third spacing D3 between two columns of second edge contact pad patterns 121, 122 in the second edge layout area 12. The remaining second spacing regions 302 define the fifth spacing D5 between two columns of main contact pad patterns. Wherein, the meaning that the first mask 20 and the second mask 30 are the same-sex masks is that the pattern development properties of the two masks are the same, and both retain the parts corresponding to their lines or both retain the parts corresponding to their spacing regions. For example, when both masks are negative masks, after lithography using the first mask 20 and the second mask 30 respectively, the parts corresponding to the first spacing region and the second spacing region will be retained correspondingly as the mask structure for etching the underlying film layer. When both masks are positive masks, after lithography using the first mask 20 and the second mask 30 respectively, the parts corresponding to the first line and the second line will be retained correspondingly as the mask structure for etching the underlying film layer.

[0051] Please refer to Figure 7 , when the first mask 20 and the second mask 30 are opposite-sex masks and the second mask 30 and the first mask 20 are aligned and overlapped, the overlapping region of each first line 201 and each second spacing region 302 is the region for forming contact pads. Thus, the overlapping region of the first line 201a and each second spacing region 302 defines Figure 3 each first edge contact pad pattern 111 in the first edge layout area 11 in Figure 3 ; the overlapping region of the first line 201b and each second spacing region 302 defines Figure 3 each first edge contact pad pattern 112 in the first edge layout area 11 in Figure 3The second edge spacing D2 between the second edge layout area 12 and the main layout area 10, the end 203 of each first line 201 exposed outside the second line 301a defines Figure 3 The second edge contact pad patterns 122 in the second edge layout area 12 in the embodiment of the present invention and the exposed portions of the first lines 201 in the second spacing area 302 between the second lines 301a and the second lines 301b define a Figure 3 The second edge contact pad patterns 121 in the second edge layout area 12 in the embodiment of the present invention and the exposed portions of the first lines 201 in the remaining second spacing areas 302 define the Figure 3 The main contact pad patterns 101 in the main layout area 10 in the embodiment of the present invention are as follows: Figure 3 The fifth spacing D5 between two columns of the main contact pad patterns 101 in the main layout area 10 in FIG. 1 is defined by the first lines 201 except the first lines 21b and the first lines 201a. Figure 3 The fourth spacing D4 between two rows of main contact pad patterns 101 in the main layout area 10 in the main layout area 10. The first mask plate 20 and the second mask plate 30 are heterogeneous mask plates, which means that the pattern development properties of the two mask plates are opposite, one retains the portion corresponding to its line, and the other retains the portion corresponding to its spacer. For example, when the first mask plate is a negative mask plate and the second mask plate 30 is a positive mask plate, after photolithography using the first mask plate 20, the portion corresponding to the first spacer will be retained as a mask structure for etching the film layer below, and after photolithography using the second mask plate 30, the portion corresponding to the second line will be retained as a mask structure for etching the film layer below; when the first mask plate 20 is a positive mask plate and the second mask plate 30 is a negative mask plate, after photolithography using the first mask plate 20, the portion corresponding to the first line will be retained as a mask structure for etching the film layer below, and after photolithography using the second mask plate 30, the portion corresponding to the second spacer will be retained as a mask structure for etching the film layer below.

[0052] Please refer to Figure 5A and Figure 7 Optionally, on one side of the first mask 20, ends 203 of at least two first lines 201 are connected together, thereby making the shapes of the outermost column of second edge contact pad patterns in the defined second edge layout area not completely the same and including at least two of a long strip shape, a left-handed U-shape, a right-handed U-shape, a left-handed L-shape, a right-handed L-shape, and a comb shape with at least two comb teeth.

[0053] Please refer to Figure 6 and Figure 7, optionally, when the second mask 30 and the first mask 20 are aligned and overlapped, the ends of all the second lines 301 (including the second second line 301b on the outermost side) except the first second line 301a on the outermost side of the second mask 30 do not extend beyond the first first line 201a on the outermost side of the first mask 20. Please refer to Figure 7 , when the first mask 20 and the second mask 30 are opposite-sex masks and the second mask 30 and the first mask 20 are aligned and overlapped, the first second line 301 on the outermost side of the second mask 30 exposes at least the end 203 of one of the first lines 201.

[0054] It should be noted that in each embodiment of the present invention, the first mask 20 and the second mask 30 may respectively be masks that can transfer the patterns of the first stripe and the first spacer, the second stripe and the second spacer to the layer for forming the contact pad structure through a single lithography process, or may respectively be masks that require a double patterning or multiple patterning process to form the required patterns of the first stripe and the first spacer, the second stripe and the second spacer in some auxiliary layers (such as a hard mask layer on the layer for forming the contact pad structure). At this time, the auxiliary layer with the pattern of the first stripe and the first spacer is the first mask 20, and the auxiliary layer with the pattern of the second stripe and the second spacer is the first mask 30. Of course, in some embodiments of the present invention, the patterns of the first stripe, the first spacer, the second stripe, and the second spacer after alignment and overlap may also be formed in the same auxiliary layer (such as a hard mask layer on the layer for forming the contact pad structure) through a double patterning or multiple patterning process. At this time, this auxiliary layer can be regarded as a mask combination formed after the first mask 20 and the second mask 30 are aligned and overlapped. To more clearly understand how to form the first mask 20 or the second mask 30 through a double patterning or multiple patterning process, the following combination of attached Figures 8A to 8D , attached Figures 9A to 9D will be described in detail.

[0055] Please refer to Figures 8A to 8D , in an embodiment of the present invention, the specific steps for forming the first mask 20 or the second mask 30 through a double patterning process include:

[0056] First, please refer to Figure 8A, a semiconductor substrate 800 is provided, on which an etch stop layer 801 (such as silicon oxide, etc.), an interlayer dielectric layer 802 (a layer for forming contact pads), a hard mask layer 803 (such as silicon nitride, etc.), a first auxiliary layer 804 (such as an organic dielectric layer, etc.), a bottom anti-reflection layer 805, and a photoresist layer 806 are sequentially formed. The photoresist layer 806 can be patterned through a single lithography process to a corresponding pattern;

[0057] Then, please refer to Figure 8B , using the patterned photoresist layer 806 as a mask, etch the bottom anti-reflection layer 805 and the first auxiliary layer 804 to the top surface of the hard mask layer 803 to transfer the pattern in the patterned photoresist layer 806 to the first auxiliary layer 804. The remaining bottom anti-reflection layer 805 and the first auxiliary layer 804 form multiple cores, and then the patterned photoresist layer 806 is removed;

[0058] Next, please refer to Figure 8B and 8C , cover a second auxiliary layer 807 on the bottom anti-reflection layer 805, the first auxiliary layer 804, and the hard mask layer 803, and etch the second auxiliary layer 807 to form sidewalls 807a on the sidewalls of each core (i.e., the bottom anti-reflection layer 805 and the first auxiliary layer 804). Then, remove each core (i.e., the bottom anti-reflection layer 805 and the first auxiliary layer 804). At this time, the plate layer composed of all the sidewalls 807a and their intervals is the first mask 20 or the second mask 30. For example, when it is the first mask 20, the sidewall 807a is the first interval area 202 in the first mask 20, and the interval between adjacent sidewalls 807a is the first line 201 in the first mask 20.

[0059] After that, please refer to Figure 8C and 8D , using the sidewall 807a as a mask, etch the hard mask layer 803 and the interlayer dielectric layer 802 to form grooves extending in the first direction (i.e., corresponding to the first line 201 in the first mask 20) at positions in the interlayer dielectric layer 802 corresponding to the intervals between the sidewalls 807a.

[0060] It should be noted that when both the first mask 20 and the second mask 30 are formed by the Figures 8A to 8D shown method, grooves extending in the first direction (i.e., corresponding to the first line 201 in the first mask 20) and grooves extending in the second direction perpendicular to the first direction (i.e., corresponding to the second line 301 in the second mask 30) will be formed in the interlayer dielectric layer 802. The intersection of the grooves in the two directions is the position for forming contact pads.

[0061] Please refer to Figures 9A to 9D, in another embodiment of the present invention, the specific steps for forming the first mask 20 or the second mask 30 by a double patterning process include:

[0062] First, please refer to Figure 9A , provide a semiconductor substrate 800, on which an etch stop layer 801 (such as silicon oxide, etc.), an interlayer dielectric layer 802 (a layer for forming contact pads), a hard mask layer 803 (such as silicon nitride, etc.), a first auxiliary layer 804 (such as an organic dielectric layer, etc.), a bottom anti-reflection layer 805, and a photoresist layer 806 are sequentially formed. The photoresist layer 806 can be patterned by a single lithography process to a corresponding pattern;

[0063] Then, please refer to Figure 9B , using the patterned photoresist layer 806 as a mask, etch the bottom anti-reflection layer 805 and the first auxiliary layer 804 to the top surface of the hard mask layer 803 to transfer the pattern in the patterned photoresist layer 806 to the first auxiliary layer 804. The remaining bottom anti-reflection layer 805 and the first auxiliary layer 804 form multiple cores, and then the patterned photoresist layer 806 is removed;

[0064] Next, please refer to Figure 9B and 9C , sequentially cover a second auxiliary layer 807 and a third auxiliary layer 809 on the bottom anti-reflection layer 805, the first auxiliary layer 804, and the hard mask layer 803, and planarize the top of the third auxiliary layer 809 until the top surface of the bottom anti-reflection layer 805 is exposed, and etch and remove the second auxiliary layer 807 on the sidewalls of each core (i.e., the bottom anti-reflection layer 805 and the first auxiliary layer 804) to form openings 808. At this time, the plate structure composed of the remaining second auxiliary layer 807, the third auxiliary layer 809, the bottom anti-reflection layer 805, the first auxiliary layer 804, and the openings 808 is the first mask 20 or the second mask 30. For example, when it is the first mask 20, the opening 808 is the first line 201 in the first mask 20, and the stacked structure formed by the second auxiliary layer 807 and the third auxiliary layer 809 on each side of the opening 808 or the stacked structure formed by the bottom anti-reflection layer 805 and the first auxiliary layer 804 film layers is the first spacer 202 in the first mask 20.

[0065] After that, the same method can be used to fabricate the second mask 30 on the already formed first mask 20, or fabricate the first mask 20 on the already formed second mask 30, so as to form the first mask 20 and the second mask 30 that are aligned and overlapped, that is, a mask combination. Then, using this mask combination as a mask, etch the hard mask layer 803 and the interlayer dielectric layer 802 to form trenches for fabricating contact pads in the interlayer dielectric layer 802.

[0066] Taking a semiconductor device as a dynamic random access memory as an example, and combined with Figures 10A to 12 , a method for manufacturing a semiconductor device having a contact pad layout of the present invention will be described in detail.

[0067] First, please refer to Figure 10A and 10B, a semiconductor substrate 400 having multiple core elements (i.e., memory transistors) is provided. The specific process includes: First, a semiconductor substrate 400a is provided, which includes a core region I, a peripheral region II, and a junction region III. In this embodiment, the core region I is a storage region, and the core elements to be formed on the core region I include select elements. Subsequently, a data storage element is connected above the core element. The select element is, for example, a MOS transistor or a diode, and the data storage element is, for example, a capacitor, a variable resistor, etc. A select element and a corresponding data storage element form a memory cell. Peripheral circuits (e.g., NMOS transistors, PMOS transistors, diodes, or resistors) can be formed in the peripheral region II to control the memory cells. A plurality of shallow trench isolation structures 401b are formed in the semiconductor substrate 400a of the core region I, and a shallow trench isolation structure 401a is formed in the semiconductor substrate 400a of the junction region III. The shallow trench isolation structure 401a defines the boundary between the core region I and the peripheral region II in the two-dimensional plane, and the shallow trench isolation structure 401b defines the active regions AA1 corresponding to the respective core elements in the core region I. The active regions AA1 are arranged in a strip shape and extend along the first direction in the two-dimensional plane, and the active regions AA1 may be arranged in a staggered manner on the surface of the semiconductor substrate 400a. Then, a buried word line WL is formed in the semiconductor substrate 400a. The buried word line WL is generally buried at a predetermined depth position in the semiconductor substrate 400a, extends along the second direction (i.e., the row direction), and passes through the shallow trench isolation structure 401b and the active regions AA1. The second direction is not perpendicular to the first direction of the active regions AA1. The buried word line WL serves as a gate to control the switching of the memory cells. Usually, the sidewalls and the bottom of the buried word line WL are surrounded by a gate dielectric layer (not shown), and the top of the buried word line WL is buried by a gate capping layer 402. Since the buried word line WL is not the focus of the present invention, its related manufacturing process can refer to the known technical solutions in the art and will not be elaborated here. In addition, the gate dielectric layer may include silicon oxide or other suitable dielectric materials, the buried word line WL may include aluminum, tungsten, copper, titanium-aluminum alloy, polysilicon, or other suitable conductive materials, and the gate capping layer 402 may include silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable insulating materials. Furthermore, a second type of dopant, such as a P-type or N-type dopant, can be doped into the active regions AA1 on both sides of the buried word line WL to form source and drain regions (collectively defined as S / D1). One of the AA1 on both sides of the buried word line WL is located at the position corresponding to a predetermined bit line contact structure at the center of the AA1, and the other is located at the position of a predetermined memory node contact structure at the end of the active region AA1. The word line WL and S / D1 can constitute or define a plurality of MOS memory transistors formed on the core region I of the semiconductor device.In addition, while forming S / D1, the source and drain regions corresponding to the peripheral transistors (collectively defined as S / D2) can also be formed in the peripheral region II. After forming the S / D1 and S / D2, an etch stop layer 403 can be further formed on the semiconductor substrate 400a, and the etch stop layer 303 covers the S / D1 and S / D2, and its material includes, for example, silicon nitride (SiN) and / or silicon dioxide (SiO2), etc. Then, a plurality of bit line contact plugs (bit line contact, not shown) are formed on the S / D1 serving as the drain region in the core region I, and a bit line BL is located above the bit line contact plugs. The bit line contact plugs can be formed by first etching a groove in the S / D1 between two adjacent WLs formed in an active region AA1, and then forming a metal silicide in the groove. The plurality of bit lines BL are parallel to each other and extend along a third direction (i.e., the column direction) perpendicular to the buried word line WL, and simultaneously span the active region AA1 and the buried word line WL. Each bit line BL includes, for example, a semiconductor layer (such as polysilicon, not shown), a barrier layer (such as including Ti or TiN, etc., not shown), a metal layer (such as tungsten, aluminum, or copper, etc., not shown), and a mask layer (such as including silicon dioxide, silicon nitride, or silicon carbonitride, not shown) stacked in sequence. In addition, at least one gate structure G1 is formed on the peripheral region II of the semiconductor substrate 400a, which includes, for example, a gate dielectric layer (not shown) and a gate layer (not shown) stacked in sequence. In a specific example, the gate layer of the gate structure G1 and the semiconductor layer or metal layer of the bit line BL are formed together. Further, sidewalls 404 surrounding the bit lines BL and the gate structure G1 can be formed by using different processes or the same process. For example, the sidewall manufacturing process of the gate structure G1 can be performed first, so that the sidewall 404 of the gate structure G1 includes silicon dioxide or silicon oxynitride (SiON), and then the sidewall manufacturing process of the bit line BL can be performed, so that the sidewall of the bit line BL can include silicon nitride. In addition, in the sidewall manufacturing process of the gate structure G1, a back-etching manufacturing process can be performed again to make the overall height of the gate structure G1 lower than that of the bit lines BL.

[0068] Then, the contact pad layout shown in the present invention Figures 1 to 3 or the mask plate combination shown Figures 5A to 7 can be used to form the storage node contact structure. The specific process is as follows:

[0069] First, please refer to Figure 11Or 12, after providing a semiconductor substrate 400 having bit lines BL, source regions and drain regions S / D1 of core elements, an interlayer dielectric layer 500 is formed on the semiconductor substrate 400, and its material, for example, includes silicon oxide, silicon nitride or low-K dielectric, etc. Specifically, first, the interlayer dielectric layer 500 is comprehensively covered on the semiconductor substrate 400 through a deposition process, and the interlayer dielectric layer 500 is filled in the space between each bit line BL and the gate structure G1 and its sidewall 404 are buried therein, and then the interlayer dielectric layer 500 is planarized through processes such as chemical mechanical polishing to form an interlayer dielectric layer 500 having a flat top surface as a whole. Among them, the top surface of the planarized interlayer dielectric layer 500 is at least not lower than the top surface of each bit line BL.

[0070] Next, please refer to Figure 11 Or 12, through a series of processes of corresponding auxiliary layer deposition, lithography, and etching, Figure 6 Or Figure 7 The combined mask pattern (not shown) after the first mask 20 and the second mask 30 shown are aligned and overlapped. This combined mask pattern is Figures 1 to 3 Any one of the contact pad layouts in, to define the positions of each storage node contact structure. Then, using the combined mask pattern as an etching mask, the interlayer dielectric layer 500 is anisotropically etched to form contact holes penetrating the interlayer dielectric layer 500 and exposing the corresponding S / D1 serving as the source region below and contact holes exposing the source region S / D2 or the gate G1 in the peripheral region II (not shown). Among them, the contact holes corresponding to the first edge contact pad pattern and the second edge contact pad pattern in the contact pad layout can be formed at the boundary of the core region I (at this time, the tops of the contact holes are connected together and at least span the outermost word line WL at the boundary of the core region I), or at least partially formed on the STI 401a in the junction region III; the contact holes corresponding to the main contact pad pattern in the contact pad layout are formed in the core region I.

[0071] Next, please continue to refer to Figure 11Or 12, after forming the contact holes, an ashing process, a wet cleaning process, or other suitable processes may be performed to remove the film layer above the interlayer dielectric layer 500, and a barrier metal layer (not shown) and a conductive metal layer (not shown) are sequentially filled in each contact hole. The barrier metal layer may cover the inner wall of the contact hole and the top surface of the interlayer dielectric layer 500 with a uniform thickness. The barrier metal layer can reduce or prevent the metal material disposed in the contact hole from diffusing into the interlayer dielectric layer 500. It may be formed of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or any combination thereof, and may be formed by processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (e.g., sputtering). The conductive metal layer may be formed of (one or more) refractory metals (e.g., cobalt, iron, nickel, tungsten, and / or molybdenum). Additionally, a deposition process with good step coverage properties may be used to form the conductive metal layer, e.g., using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (e.g., sputtering). The formed conductive metal layer also covers the surface of the interlayer dielectric layer 500 around the contact hole. Thereafter, a chemical mechanical polishing (CMP) process may be employed to chemically mechanically polish the top surface of the deposited conductive metal layer until the top surface of the interlayer dielectric layer 500 is exposed to form the main contact pad 501a, the peripheral contact pads 501d and 501e, and the first edge contact pad (or second edge contact pad) 501b located in the interlayer dielectric layer 500. The main contact pad 501a serves as a storage node contact structure in the core region I and is used to connect to a capacitor structure formed subsequently above the core region I. The first edge contact pad (or second edge contact pad) 501b is formed by at least two top-connected contact plugs at the boundary of the core region I (as shown in Figure 11 ), or is formed by connecting the contact plug in the junction region III and the contact plug at the boundary of the core region I at the top (as shown in Figure 12shown), or formed by a relatively larger contact structure in the boundary region III (not shown), as a virtual storage node contact structure at the boundary of the core region I or in the boundary region III, for connection to a capacitor structure subsequently formed at the boundary of the core region I or above the boundary region III. The first edge contact pad (or the second edge contact pad) 501b is aligned and parallel to the bit line BL. The cross-sectional structure of the first edge contact pad (or the second edge contact pad) 501b is, for example, an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure. The peripheral contact pad 501d serves as a contact structure for the gate structure G1 of the peripheral region II, for leading the gate structure G1 outwards, and the peripheral contact pad 501e serves as a contact structure for the source region or drain region S / D2 of the peripheral region II, for leading the source region or drain region S / D2 of the peripheral region II outwards. The main contact pad 501a, the peripheral contact pads 501d and 501e, and the first edge contact pad (or the second edge contact pad) 501b can each be an integrally formed structure, or can be composed of a pad and a contact plug connected thereunder.

[0072] After that, please continue to refer to Figure 11Or 12, the corresponding capacitor structure can be fabricated on the core region I by using the conventional fabrication method of capacitor structures in the art, and the specific process will not be elaborated here. Each main contact pad 501a in the core region I is connected to a capacitor 705a, and the first edge contact pad or the second edge contact pad 501b at the boundary of the core region I and / or in the junction region III is connected to a capacitor 705b. Each capacitor includes a lower electrode layer 701, a capacitive dielectric layer 702, and an upper electrode layer 703. There are lateral supports and spaced-apart stacked bottom support layer 600, intermediate support layer 601, and top support layer 602 between the capacitors. The bottom support layer 600 is used for bottom-supporting the subsequently formed lower electrode layer on one hand, and for isolating the internal components of the semiconductor substrate 400 from the upper components such as capacitors on the other hand. The formation process of the bottom support layer 600 can also be a thermal oxidation process. The materials of the bottom support layer 600, intermediate support layer 601, and top support layer 602 include but are not limited to silicon nitride. In other embodiments of the present invention, in order to better support the lower electrode layer, more than two intermediate support layers 601 can be stacked between the bottom support layer 600 and the top support layer 602. The capacitor 705b has a first width W1, and the capacitor 705a has a second width W2. Optionally, W1 is greater than W2, for example, W1 = 1.3*W2 to 2.3*W2. Optionally, all the capacitors can be arranged in a hexagonal close-packed arrangement. Further, the lower electrode layer 701 has a cylindrical structure and can be a polysilicon electrode or a metal electrode. When the lower electrode layer 701 is a metal electrode, a stacked structure of titanium nitride (TiN) and Ti can also be used. When the lower electrode layer 701 is a polysilicon electrode, it can be formed of undoped and / or doped polysilicon material. The capacitive dielectric layer 702 covers the inner surface and the outer surface of the cylindrical structure of the lower electrode layer 701 to fully utilize the two opposite surfaces of the lower electrode layer 701 to form a capacitor with a larger electrode surface area. Preferably, the capacitive dielectric layer 702 can be a high-K dielectric layer such as a metal oxide. Further, the capacitive dielectric layer 702 is a multi-layer structure, for example, a two-layer structure of hafnium oxide-zirconium oxide. The upper electrode layer 703 can be a single-layer structure or a multi-layer structure. When the upper electrode layer 703 is a single-layer structure, for example, it can be a polysilicon electrode or a metal electrode. When the upper electrode layer 703 is a metal electrode, for example, it can be formed of titanium nitride (TiN). The upper electrode layer 703 can form a capacitor with the capacitive dielectric layer 702 and the lower electrode layer 701 both inside and outside the corresponding cylindrical structure.In addition, on the edge region of the core region I (i.e., the boundary region of the capacitor hole array), due to the presence of the lateral support layers (i.e., the intermediate support layer 601 and the top support layer 602), the sidewall structures of the capacitor dielectric layer 702 and the upper electrode layer 703 both have uneven morphologies. The sidewall structures with uneven morphologies correspond to the intermediate support layer 601 and the top support layer 602 outside the cylindrical structure of the lower electrode layer 701. As a result, the part of the upper electrode layer 703 on the edge region of the core region I (i.e., the boundary region of the capacitor hole array) bulges away from the lower electrode layer 701 corresponding to the intermediate support layer 601 and the top support layer 602, making the boundary of the capacitor array in the core region I uneven. In addition, in this embodiment, the capacitor dielectric layer 702 and the upper electrode layer 703 also sequentially extend and cover the surface of the bottom support layer 600 reserved on the peripheral region II.

[0073] Please refer to Figure 11 or Figure 12 As shown, a upper electrode filling layer 704 can be first formed on the surface of the upper electrode layer 703 by chemical vapor deposition. The upper electrode filling layer 704 fills the gaps between the upper electrode layers 703. That is to say, the upper electrode filling layer 704 fills the gaps between adjacent cylindrical structures and covers the above-formed structures. Preferably, the material of the upper electrode filling layer 704 includes undoped or boron-doped polysilicon. Thus, the fabrication of the capacitor array is completed.

[0074] It can be understood that since the top surface areas of the first edge contact pad and the second edge contact pad 501b are relatively large, sufficient process margin can be provided for the fabrication of the capacitor 705b, and the width of the capacitor hole corresponding to the capacitor 705b is relatively large, avoiding abnormal deformation or collapse of the capacitor hole corresponding to the capacitor 705b. At the same time, the capacitor 705b and the corresponding first edge contact pad or second edge contact pad 501b have a relatively large contact area, thereby reducing the contact impedance, which is beneficial to improving the electrical performance of the device. In addition, because the width of the capacitor hole corresponding to the capacitor 705b is relatively large, it can buffer the density difference of the circuit patterns in the peripheral region II and the core region I, so as to improve the optical proximity effect when performing the photolithography process and / or etching process of the capacitor hole, reduce the sparse / dense load effect of the circuit patterns in the peripheral region II and the core region I, protect the capacitor holes in the core region I, ensure the consistency of the capacitor holes within the core region boundary and the capacitors filled in the capacitor holes in the core region, and prevent the problem that the capacitor holes above the main contact pad in the core region are abnormal and cause the failure of the subsequent formed capacitor structure.

[0075] It should be noted that the embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts among the embodiments can be referred to each other. In addition, the above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure fall within the scope of protection required by the technical solution of the present invention.

[0076] In addition, it should be noted that unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

Claims

1. A contact pad layout of a semiconductor device, characterized in that, The contact pad layout includes: A main layout area, in which a plurality of main contact pad patterns are provided. The shapes and sizes of the respective main contact pad patterns are similar, and all the main contact pad patterns are arranged in a checkerboard pattern and staggered. There is a fourth spacing between adjacent rows of the main contact pad patterns, and a fifth spacing between adjacent columns of the main contact pad patterns; A first edge layout area, distributed on the outer side of one side of the main layout area. At least one first edge contact pad pattern is provided in the first edge layout area, and the area of each first edge contact pad pattern is larger than the area of each main contact pad pattern. There is a first edge spacing between the first edge layout area and the main layout area; Wherein, the first edge contact pad pattern is different from the main contact pad pattern, and the first edge spacing is different from the fourth spacing; Further, the first edge contact pad patterns in the first edge layout area are arranged in one row or two rows. One row of the first edge contact pad patterns is only a long strip with a serrated edge, or the numbers of the two rows of the first edge contact pad patterns are respectively multiple; And the serrated edge is provided on the side of the long strip facing the main layout area, the other side of the long strip opposite to the serrated edge is a straight edge, and each serration in the serrated edge is aligned with the corresponding main contact pad pattern in the main layout area.

2. The contact pad layout according to claim 1, characterized in that, There are a plurality of first edge contact pad patterns arranged in two rows along the direction of the one side of the main layout area in the first edge layout area, and each first edge contact pad pattern is aligned with the corresponding main contact pad pattern in the main layout area. The spacing between the row of the first edge contact pad patterns closest to the main layout area and the nearest row of the main contact pad patterns is the first edge spacing.

3. The contact pad layout according to claim 1, characterized in that, The contact pad layout further includes a second edge layout area, which is distributed on the outer side of the adjacent side of the one side of the main layout area. A plurality of second edge contact pad patterns are provided in the second edge layout area, and the area of each second edge contact pad pattern is larger than the area of each main contact pad pattern. There is a second edge spacing between the second edge layout area and the main layout area; Wherein, the second edge contact pad pattern is different from the first edge contact pad pattern, and the second edge spacing is different from the fourth spacing.

4. The contact pad layout according to claim 3, characterized in that, The second edge spacing is different from the first edge spacing.

5. The contact pad layout according to claim 3, characterized in that, The respective second edge contact pad patterns in the second edge layout area are not completely the same.

6. The contact pad layout according to claim 3, characterized in that, The respective second edge contact pad patterns in the second edge layout area are aligned with the corresponding main contact pad patterns in the main layout area.

7. The contact pad layout according to claim 6, characterized in that, The second edge layout area includes second edge contact pad patterns arranged in two columns along the direction of the adjacent side, and the spacing between the column of the second edge contact pad patterns closest to the main layout area and the nearest column of the main contact pad patterns is the second edge spacing. There is a third spacing between the two columns of the second edge contact pad patterns, and the third spacing is larger than the second edge spacing.

8. The contact pad layout according to claim 7, characterized in that, In the second edge layout region, the shapes of the second edge contact pad patterns in a column far from the main layout region include at least two of a strip shape, a U shape lying on its left side, a U shape lying on its right side, an L shape lying on its left side, an L shape lying on its right side, and a comb shape having at least two comb teeth.

9. A contact pad structure formed by using the contact pad layout of the semiconductor device according to any one of claims 1 to 8, characterized in that, Comprising: a plurality of main contact pads arranged in a checkerboard pattern and staggered, the shapes and sizes of the main contact pads being similar, and a fourth spacing being provided between the main contact pads; at least one first edge contact pad distributed outside one side of the arrangement region of all the main contact pads, the top surface area of each first edge contact pad being larger than the top surface area of each main contact pad, and a first edge spacing being provided between the first edge contact pad adjacent to the main contact pad and the main contact pad; wherein, the size of the first edge contact pad is different from the size of the main contact pad, and the first edge spacing is different from the fourth spacing.

10. The contact pad structure according to claim 9, characterized in that, The first edge contact pad is a strip having a serrated edge.

11. The contact pad structure according to claim 10, characterized in that, The serrated edge is arranged facing the main contact pad, and each serration in the serrated edge is aligned with a corresponding main contact pad.

12. The contact pad structure according to claim 9, characterized in that, The number of the first edge contact pads is multiple, and they are arranged in two rows along the direction of the one side of the arrangement region of the main contact pads, each first edge contact pad being aligned with a corresponding main contact pad, and the spacing between the row of first edge contact pads closest to the arrangement region of the main contact pads and the nearest row of main contact pads being the first edge spacing.

13. The contact pad structure according to claim 10, characterized in that, The contact pad structure further includes: a plurality of second edge contact pads distributed outside the adjacent side of the one side of the arrangement region of all the main contact pads, the top surface area of each second edge contact pad being larger than the top surface area of each main contact pad, and a second edge spacing being provided between the second edge contact pad adjacent to the main contact pad and the main contact pad; wherein, the shape of the second edge contact pad is different from the shape of the first edge contact pad, and the second edge spacing is different from the fourth spacing.

14. The contact pad structure according to claim 13, characterized in that, Each of the second edge contact pads is aligned with a corresponding main contact pad.

15. The contact pad structure according to claim 14, wherein, All the second edge contact pads are arranged in two columns along the direction of the adjacent side, and the spacing between the column of second edge contact pads closest to the arrangement region of the main contact pads and the nearest column of main contact pads is the second edge spacing, and a third spacing is provided between the two columns of second edge contact pads, and the third spacing is larger than the second edge spacing.

16. The contact pad structure according to claim 15, wherein, Among all the second edge contact pads, the cross-sectional shapes of the second edge contact pads in the column far from the arrangement region of the main contact pads include at least two of a strip shape, a U shape lying on its left side, a U shape lying on its right side, an L shape lying on its left side, an L shape lying on its right side, and a comb shape having at least two comb teeth.

17. A semiconductor device, wherein, Comprising: a semiconductor substrate having a core region in which a plurality of core elements are formed; an interlayer dielectric layer covering the semiconductor substrate; the contact pad structure of the semiconductor device according to any one of claims 9 to 16, formed in the interlayer dielectric layer; A plurality of contact plugs are formed in the interlayer dielectric layer, and each contact plug is disposed to align with a corresponding contact pad in the contact pad structure to electrically connect the corresponding contact pad and the active region of the core component.

18. A mask set for manufacturing the contact pad structure of the semiconductor device according to any one of claims 9 to 16, wherein, Comprising: A first mask, having a plurality of parallel first lines, a first spacer region between two adjacent first lines, and the line width of at least one first line on the outermost side of the first mask being greater than that of other first lines, and the line width of at least one first spacer region on the outermost side of the first mask being greater than that of other first spacer regions; A second mask, having a plurality of parallel second lines intersecting each first line, a second spacer region between two adjacent second lines, and the line width of at least one second line on the outermost side of the second mask being greater than that of other second lines, and the line width of at least one second spacer region on the outermost side of the second mask being greater than that of other second spacer regions; Wherein, when the first mask and the second mask are of the same type of mask and the second mask and the first mask are aligned and overlapped, the overlapping region of the first line and the second line is the region for forming the contact pad; when the first mask and the second mask are of different types of masks and the second mask and the first mask are aligned and overlapped, the overlapping region of the first line and the second spacer region is the region for forming the contact pad.

19. The mask set according to claim 18, wherein, At one side of the first mask, the ends of at least two first lines are connected together.

20. The mask set according to claim 18, wherein, When the second mask and the first mask are aligned and overlapped, the ends of all second lines except the first second line on the outermost side of the second mask do not extend beyond the first first line on the outermost side of the first mask; the first second line on the outermost side of the second mask exposes the ends of at least one first line.

21. The mask set according to claim 18, wherein, In the second mask, the line width of the ends of the other second lines is greater than the line width of the middle region of the other second lines.

Images